MPC92433

Freescale Semiconductor Technical Data MPC92433 Rev 2, 06/2005 1428 MHz Dual Output LVPECL Clock Synthesizer The MPC92433 is a 3.3 V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 42.50 MHz to 1428 MHz and the support of two differential PECL output signals, the device meets the needs of the most demanding clock applications. Features • • • • • • • • • • • • • • 42.50 MHz to 1428 MHz synthesized clock output signal Two differential, LVPECL-compatible high-frequency outputs Output frequency programmable through 2-wire I2C bus or parallel interface On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock input Synchronous clock stop functionality for both outputs LOCK indicator output (LVCMOS) LVCMOS compatible control inputs Fully integrated PLL 3.3 V power supply 48-lead LQFP 48-lead Pb-free package available SiGe Technology Ambient temperature range: –40°C to +85°C MPC92433 1428 MHz LOW VOLTAGE CLOCK SYNTHESIZER FA SUFFIX(1) 48-LEAD LQFP PACKAGE CASE 932-03 AE SUFFIX(2) 48-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 932-03 Typical Applications • • • Programmable clock source for server, computing, and telecommunication systems Frequency margining Oscillator replacement The MPC92433 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a highfrequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can be changed on the fly for frequency margining purposes. The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2856 MHz. Its output is scaled by a divider that is configured by either the I2C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL post-divider N is configured through either the I2C or the parallel interfaces, and can provide one of seven division ratios (2, 4, 6, 8, 12, 16, 32). This divider extends the performance of the part while providing a 50 Ω duty cycle. The highfrequency outputs, QA and QB, are differential and are capable of driving a pair of transmission lines terminated 50 Ω to VCC – 2.0 V. The second high-frequency output, QB, can be configured to run at either 1x or 1/2x of the clock frequency or the first output (QA). The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: I2C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB, and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I2C interface. The serial interface is I2C compatible and provides read and write access to the internal PLL configuration registers. The lock state of the PLL is indicated by the LVCMOS-compatible LOCK output. 1. FA suffix: leaded terminations. 2. AE suffix: lead-free, EPP and RoHS-compliant. © Freescale Semiconductor, Inc., 2005. All rights reserved. REF_CLK XTAL1 XTAL2 REF_SEL TEST_EN SDA SCL ADR[1:0] PLOAD M[9:0] NA[2:0] NB P CLK_STOPx BYPASS MR XTAL fREF ÷P PLL fVCO ÷NA fQA QA fQB ÷NB QB ÷M PLL Configuration Registers I2C Control LOCK Figure 1. MPC92433–Generic Logic Diagram TEST_EN 25 24 23 22 21 20 36 35 34 33 32 31 30 29 28 27 GND NA2 NA1 NA0 PLOAD VCC MR SDA SCL ADR1 ADR0 P LOCK 26 GND GND VCC VCC VCC QA QA QB QB NB 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 M9 M8 M7 M6 M5 GND M4 M3 M2 M1 M0 VCC MPC92433 19 18 17 16 15 14 13 CLK_STOPB Figure 2. 48-Lead Package Pinout (Top View) MPC92433 2 Advanced Clock Drivers Devices Freescale Semiconductor CLK_STOPA It is recommended to use an external RC filter for the analog VCC_PLL supply pin. Please see the application section for details. BYPASS VCC_PLL XTAL1 REF_SEL REF_CLK XTAL2 GND GND VCC VCC Table 1. Signal Configuration Pin XTAL1, XTAL2 REF_CLK REF_SEL QA QB LOCK M[9:0] NA[2:0] NB P P_LOAD SDA SCL ADR[1:0] BYPASS TEST_EN CLK_STOPx MR GND VCC_PLL VCC I/O Input Input Input Output Output Output Input Input Input Input Input I/O Input Input Input Input Input Input Supply Supply Supply Analog LVCMOS LVCMOS Differential LVPECL Differential LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC Type Crystal oscillator interface PLL external reference input Selects the reference clock input High frequency clock output High frequency clock output PLL lock indicator PLL feedback divider configuration PLL post-divider configuration for output QA PLL post-divider configuration for output QB PLL pre-divider configuration Selects the programming interface I2C data I2C clock Selectable two bits of the I2C slave address Selects the static circuit bypass mode Factory test mode enable. This input must be set to logic low level in all applications of the device. Output Qx disable in logic low state Device master reset Negative power supply Positive power supply for the PLL (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Positive power supply for I/O and core Function MPC92433 Advanced Clock Drivers Devices Freescale Semiconductor 3 Table 2. Function Table Control Inputs REF_SEL M[9:0] NA[2:0] NB P PLOAD 1 01 1111 0100b(2) 010 0 1 0 Selects REF_CLK input as PLL reference clock Selects the XTAL interface as PLL reference clock Default(1) 0 1 PLL feedback divider (10-bit) parallel programming interface PLL post-divider parallel programming interface. See Table 9 PLL post-divider parallel programming interface. See Table 9 PLL pre-divider parallel programming interface. See Table 8 Selects the parallel programming interface. The internal PLL divider settings (M, NA, NB and P) are equal to the setting of the hardware pins. Leaving the M, NA, NB and P pins open (floating) results in a default PLL configuration with fOUT = 250 MHz. See application/programming section. Address bit = 0 See Programming the MPC92433 Selects the serial (I2C) programming interface. The internal PLL divider settings (M, NA, NB and P) are set and read through the serial interface. ADR[1:0] SDA, SCL BYPASS 00 Address bit = 1 1 PLL function bypassed fQA=fREF÷ NA and fQB=fREF÷ (NA· NB) Application mode. Test mode disabled. Output Qx is disabled in logic low state. Synchronous disable is only guaranteed if NB = 0. The device is reset. The output frequency is zero and the outputs are asynchronously forced to logic low state. After releasing reset (upon the rising edge of MR and independent on the state of PLOAD), the MPC92433 reads the parallel interface (M, NA, NB and P) to acquire a valid startup frequency configuration. See application/programming section. PLL function enabled fQA = (fREF÷ P) · M ÷ NA and fQB = (fREF ÷ P) · M ÷ (NA · NB) Factory test mode is enabled Output Qx is synchronously enabled The PLL attempts to lock to the reference signal. The tLOCK specification applies. TEST_EN CLK_STOPx MR 0 1 Outputs LOCK PLL is not locked PLL is frequency locked 1. Default states are set by internal input pull-up or pull-down resistors of 75 kΩ. 2. If fREF = 16 MHz, the default configuration will result in an output frequency of 250 MHz. MPC92433 4 Advanced Clock Drivers Devices Freescale Semiconductor Table 3. General Specifications Symbol VTT MM HBM LU CIN θJA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Input Capacitance LQFP 48 Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 200 2000 200 4.0 69 64 53 50 TBD TBD Min Typ VCC – 2 Max Unit V V V mA pF °C/W °C/W °C/W °C/W °C/W Inputs Natural convection 200 ft/min Natural convection 200 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board θJC LQFP 48 Thermal Resistance Junction to Case Table 4. Absolute Maximum Ratings(1) Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage(2) DC Output Voltage DC Input Current DC Output Current Storage Temperature –65 Characteristics Min –0.3 –0.3 –0.3 Max 3.9 VCC + 0.3 VCC + 0.3 ±20 ±50 125 Unit V V V mA mA °C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2. All input pins including SDA and SCL pins. MPC92433 Advanced Clock Drivers Devices Freescale Semiconductor 5 Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TJ = –40°C to +85°C) Symbol Characteristics Min Typ Max Unit Condition LVCMOS Control Inputs (M[9:0], N[2:0], ADDR[1:0], NB, P, CLK_STOPx, BYPASS, MR, REF_SEL, TEST_EN, PLOAD) VIH VIL IIN Input High Voltage Input Low Voltage Input Current(1) 2.0 — — — — — VCC + 0.3 0.8 ±200 V V µA LVCMOS LVCMOS VIN = VCC or GND I2C Inputs (SCL, SDA) VIH VIL IIN Input High Voltage Input Low Voltage Input Current 2.0 — — — — — VCC + 0.3 0.8 ±10 V V µA LVCMOS LVCMOS LVCMOS Output (LOCK) VOH VOL Output High Voltage Output Low Voltage 2.4 — — — — 0.4 V V IOH = –4 mA IOL = 4 mA I2C Open-Drain Output (SDA) VOL Input Low Voltage — — 0.4 V IOL = 4 mA Differential Clock Output QA, QB(2) VOH VOL VO(P-P) Output High Voltage Output Low Voltage Output Peak-to-Peak Voltage VCC – 1.05 VCC – 1.95 0.5 — — 0.6 VCC – 0.74 VCC – 1.60 1.0 V V V LVPECL LVPECL Supply current ICC_PLL ICC Maximum PLL Supply Current Maximum Supply Current — — — — 10 150 mA mA VCC_PLL Pins All VCC Pins 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 Ω to VTT = VCC – 2 V. MPC92433 6 Advanced Clock Drivers Devices Freescale Semiconductor Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TJ = –40°C to +85°C(1) (2) Symbol fXTAL fREF fVCO fMAX Characteristics Crystal Interface Frequency Range FREF_EXT Reference Frequency Range VCO Frequency Range Output Frequency (4) (3) Min 15 15 1360 N= ÷2 N= ÷4 N= ÷6 N= ÷8 N= ÷12 N= ÷16 N= ÷32 680 340 226.67 170 113.30 178.50 42.50 0 (P_LOAD) 50 45 Typ 16 Max 20 20 2856 1428 714 476 357 238 178.50 89.25 0.4 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns Condition fSCL tP,MIN DC tSK(O) tr, tf tr, tf tP_EN tP_DIS tJIT(CC) Serial Interface (I2C) Clock Frequency Minimum Pulse Width Output Duty Cycle Output-to-Output Skew NB=0 (fQA = fQB) NB=1 (fQA = 2· fQB) 50 55 38 96 % ps ps ns ns 20% to 80% CL = 400 pF TQx = Output period TQx = Output period ps ps ps ps ps ps ps ps ps ps Output Rise/Fall Time (QA, QB) Output Rise/Fall Time (SDA) Output Enable Time (CLKSTOPx to QA, QB) Output Disable Time (CLKSTOPx to QA, QB) Cycle-to-Cycle Jitter (RMS) (5) 0.05 0.3 250 0 0 2 · TQx 1.5 · TQx 15 20 30 8 10 12 13 17 23 29 N= ÷2, ÷4, ÷6, ÷8 N= ÷12 N= ÷16, ÷32 N= ÷2 N= ÷4 N= ÷6 N= ÷8 N= ÷12 N= ÷16 N= ÷32 2 tJIT(PER) Period Jitter (RMS)(6) NREF(UNLOCK) tLOCK Number of missing reference clock cycles to declare an out of LOCK condition(7) Maximum PLL Lock Time 10 ms 1. AC specifications are subject to change. 2. AC characteristics apply for parallel output termination of 50 Ω to VTT. 3. The input frequency fXTAL, the PLL divider M and P must match the VCO frequency range: fVCO = fXTAL · M ÷ P. The feedback divider M is limited to 170