PC3S12P128J0MLH

MC9S12P128 Reference Manual Covers also MC9S12P-Family MC9S12P96 MC9S12P64 MC9S12P32 S12 Microcontrollers MC9S12P128RMV1 Rev. 1.12 16 October 2009 freescale.com To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices. The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual. Revision History Date April 2008 July 2008 December 2008 March 2009 Revision Level 1.07 1.08 1.09 1.10 PRELIMINARY Minor Corrections Added typ. IDD values Completed Electricals Minor Corrections Final Electricals Corrected section 1.11.3.4 Memory Corrected 1.7.3.16 - 1.7.3.19 SPI pin description Removed reference to MMCCTL1 register from Table 13-5 Removed item 4b from Table A-6 and A-7 Changed Version ID in Table 1-5 from $FF to $00 Added Register Summary Appendix D Updated FTMRC Blockguide . See Revision History Chapter 13 Updated CPMU Blockguide . See Revision History Chapter 7 Description June 2009 1.11 October 2009 1.12 Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Device Overview MC9S12P-Family . . . . . . . . . . . . . . . . . . . . . . 17 Port Integration Module (S12PPIMV1) . . . . . . . . . . . . . . . . . . . 49 S12P Memory Map Control (S12PMMCV1). . . . . . . . . . . . . . . 107 Interrupt Module (S12SINTV1). . . . . . . . . . . . . . . . . . . . . . . . . 123 Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . . 131 S12S Debug Module (S12SDBGV2) . . . . . . . . . . . . . . . . . . . . 155 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description197 Chapter 8 249 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3). Analog-to-Digital Converter (ADC12B10CRev 00.05) . . . . . .303 Pulse-Width Modulator (PWM8B6CV1) Block Description . . 327 Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . . 361 Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . 397 128 KByte Flash Module (S12FTMRC128K1V1). . . . . . . . . . . 423 Timer Module (TIM16B8CV2) Block Description . . . . . . . . . . 471 Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 Appendix B Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 Appendix D Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . 543 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 3 S12P-Family Reference Manual, Rev. 1.12 4 Freescale Semiconductor Chapter 1Device Overview MC9S12P-Family 1.1 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.1 MC9S12P Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.2.2 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3.1 S12 16-Bit Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3.2 On-Chip Flash with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3.3 On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.4 Main External Oscillator (XOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.5 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.6 Internal Phase-Locked Loop (IPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.7 System Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.8 Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.9 Pulse Width Modulation Module (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.10 Controller Area Network Module (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.11 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.13 Analog-to-Digital Converter Module (ATD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.14 On-Chip Voltage Regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.15 Background Debug (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.16 Debugger (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.7.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.7.2 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.7.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.9.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.9.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ATD External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 5 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 S12CPMU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Chapter 2 Port Integration Module (S12PPIMV1) 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.3 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.4 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.5 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.6 Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.7 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.8 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.9 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.3.10 Ports A, B, E, BKGD pin Pull-up Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . 67 2.3.11 Ports A, B, E Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.12 ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.13 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.14 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.3.15 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.3.16 Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.17 Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.18 Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.3.19 Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.3.20 Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.3.21 Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.3.22 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.3.23 Port T Routing Register (PTTRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.3.24 Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.3.25 Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.3.26 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.3.27 Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.3.28 Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.3.29 Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.30 Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.31 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.3.32 Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.3.33 Port M Input Register (PTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.3.34 Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.35 Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.3.36 Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 S12P-Family Reference Manual, Rev. 1.12 6 Freescale Semiconductor 2.2 2.3 2.4 2.5 2.3.37 Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.3.38 Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.39 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.40 Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.41 Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.42 Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.43 Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.3.44 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.3.45 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.3.46 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.3.47 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.3.48 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.3.49 Port J Data Register (PTJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.3.50 Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.3.51 Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.3.52 Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.3.53 Port J Pull Device Enable Register (PERJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.3.54 Port J Polarity Select Register (PPSJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.3.55 Port J Interrupt Enable Register (PIEJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.3.56 Port J Interrupt Flag Register (PIFJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 2.3.57 Port AD Data Register (PT0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 2.3.58 Port AD Data Register (PT1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.3.59 Port AD Data Direction Register (DDR0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.3.60 Port AD Data Direction Register (DDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.3.61 Port AD Reduced Drive Register (RDR0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.3.62 Port AD Reduced Drive Register (RDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.3.63 Port AD Pull Up Enable Register (PER0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.3.64 Port AD Pull Up Enable Register (PER1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.3.65 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 2.4.4 Pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Chapter 3S12P Memory Map Control (S12PMMCV1) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 7 3.2 3.3 3.4 3.5 3.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.4.1 MCU Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Implemented Memory in the System Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3.5.1 Implemented Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3.5.2 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.6.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Chapter 4 Interrupt Module (S12SINTV1) 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.4.1 S12S Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.4.3 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.4.4 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.2 4.3 4.4 4.5 Chapter 5 Background Debug Module (S12SBDMV1) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.2 5.3 S12P-Family Reference Manual, Rev. 1.12 8 Freescale Semiconductor 5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Chapter 6 S12S Debug Module (S12SDBGV2) 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.4.1 S12SDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.4.3 Match Modes (Forced or Tagged) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.5.1 State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.5.2 Scenario 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.5.3 Scenario 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.5.4 Scenario 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.5.5 Scenario 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.5.6 Scenario 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 6.5.7 Scenario 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 6.5.8 Scenario 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 6.5.9 Scenario 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.5.10 Scenario 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 6.5.11 Scenario 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 9 6.2 6.3 6.4 6.5 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.2.3 TEMPSENSE — temperature sensor output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.2.4 VDDR — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.2.5 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.2.6 VSS, VSSPLL— Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.2.7 VDDX, VSSX— Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.2.8 API_EXTCLK — API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 7.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 7.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.4.3 Stop Mode using PLL Clock as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 7.4.4 Full Stop Mode using Oscillator Clock as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 234 7.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 7.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 7.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 7.5.3 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.5.4 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 7.2 7.3 7.4 7.5 7.6 7.7 Chapter 8 Freescale’s Scalable Controller Area Network (S12MSCANV3) 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 8.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 8.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 8.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 8.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 8.2 S12P-Family Reference Manual, Rev. 1.12 10 Freescale Semiconductor 8.3 8.4 8.5 8.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 8.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 8.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 8.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 8.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 8.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 8.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 8.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 8.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 8.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 8.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Chapter 9 Analog-to-Digital Converter (ADC12B10CRev 00.05) Block Description 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 9.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 9.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 9.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 9.2 9.3 9.4 9.5 9.6 Chapter 10 Pulse-Width Modulator (PWM8B6CV1) Block Description 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 10.2.1 PWM5 — Pulse Width Modulator Channel 5 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 10.2.2 PWM4 — Pulse Width Modulator Channel 4 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 11 10.3 10.4 10.5 10.6 10.2.3 PWM3 — Pulse Width Modulator Channel 3 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 10.2.4 PWM2 — Pulse Width Modulator Channel 2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 10.2.5 PWM1 — Pulse Width Modulator Channel 1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 10.2.6 PWM0 — Pulse Width Modulator Channel 0 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 10.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 10.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 Chapter 11 Serial Communication Interface (S12SCIV5) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 11.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 11.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 11.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 11.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 11.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 11.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 11.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 11.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 11.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 11.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 11.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 11.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 11.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 11.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 11.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 11.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 11.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 S12P-Family Reference Manual, Rev. 1.12 12 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV5) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 12.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 12.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 12.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 12.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 12.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 12.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 12.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 12.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 12.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 12.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 12.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 12.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 12.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Chapter 13 128 KByte Flash Module (S12FTMRC128K1V1) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 13.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 13.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 13.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 13.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 13.4.3 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 13.4.4 Allowed Simultaneous P-Flash and D-Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . 453 13.4.5 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 13.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 13.4.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 13.4.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 13.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 13 13.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 13.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 469 13.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 470 13.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 Chapter 14 Timer Module (TIM16B8CV2) Block Description 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 14.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 14.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 475 14.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 475 14.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 475 14.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 475 14.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 475 14.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 475 14.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 476 14.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 476 14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 14.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 14.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 14.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 14.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 14.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 14.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 14.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 14.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 14.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 14.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 Appendix A Electrical Characteristics A.1 General A.1.1 A.1.2 A.1.3 A.1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 S12P-Family Reference Manual, Rev. 1.12 14 Freescale Semiconductor A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 A.3.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 A.4.1 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 A.4.2 Electrical Characteristics for the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Electrical Characteristics for the IRC1M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Electrical Characteristics for the Oscillator (OSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 Electrical Specification for Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 A.11.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 A.11.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Appendix B Ordering Information Appendix C Package Information C.1 80 QFP Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 C.2 48 QFN Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 C.3 64 LQFP Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Appendix D Detailed Register Address Map D.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 15 S12P-Family Reference Manual, Rev. 1.12 16 Freescale Semiconductor Chapter 1 Device Overview MC9S12P-Family 1.1 Introduction The MC9S12P family is an optimized, automotive, 16-bit microcontroller product line focused on lowcost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS family. The MC9S12P family is targeted at generic automotive applications requiring CAN or LIN/J2602 communication. Typical examples of these applications include body controllers, occupant detection, door modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes. The MC9S12P family uses many of the same features found on the MC9S12XS family, including error correction code (ECC) on flash memory, a separate data-flash module for diagnostic or data storage, a fast analog-to-digital converter (ATD) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance. The MC9S12P family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12XS family, the MC9S12P family run 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12P family is available in 80-pin QFP, 64-pin LQFP, and 48-pin QFN package options and aims to maximize pin compatibility with the MC9S12XS family. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. 1.2 Features This section describes the key features of the MC9S12P family. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 17 Device Overview MC9S12P-Family 1.2.1 MC9S12P Family Comparison Table 1 provides a summary of different members of the MC9S12P family and their proposed features. This information is intended to provide an understanding of the range of functionality offered by this microcontroller family. Table 1. MC9S12P Family Feature CPU Flash memory (ECC) Data flash (ECC) RAM MSCAN SCI SPI Timer PWM ADC Frequency modulated PLL External oscillator (4 – 16 MHz Pierce with loop control) Internal 1 MHz RC oscillator Supply voltage Execution speed 2 Kbytes 4 Kbytes 1 1 1 8 ch x 16-bit 6 ch x 8-bit 10 ch x 12-bit Yes Yes 32 Kbytes 64 Kbytes 4 Kbytes 6 Kbytes MC9S12P32 MC9S12P64 CPU12-V1 96 Kbytes 128 Kbytes MC9S12P96 MC9S12P128 Yes 3.15 V – 5.5 V Static(1) – 32 MHz Package 80 QFP, 64 LQFP, 48 QFN 1. P or D Flash erasing or programming requires a minimum bus frequency of 1MHz 1.2.2 Chip-Level Features On-chip modules available within the family include the following features: • S12 CPU core • Up to 128 Kbyte on-chip flash with ECC • 4 Kbyte data flash with ECC • Up to 6 Kbyte on-chip SRAM • Phase locked loop (IPLL) frequency multiplier with internal filter • 4–16 MHz amplitude controlled Pierce oscillator • 1 MHz internal RC oscillator • Timer module (TIM) supporting input/output channels that provide a range of 16-bit input capture, output compare, counter, and pulse accumulator functions S12P-Family Reference Manual, Rev. 1.12 18 Freescale Semiconductor Device Overview MC9S12P-Family • • • • • • • Pulse width modulation (PWM) module with 6 x 8-bit channels 10-channel, 12-bit resolution successive approximation analog-to-digital converter (ATD) One serial peripheral interface (SPI) module One serial communication interface (SCI) module supporting LIN communications One multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B) On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages Autonomous periodic interrupt (API) 1.3 Module Features The following sections provide more details of the modules implemented on the MC9S12P family. 1.3.1 S12 16-Bit Central Processor Unit (CPU) S12 CPU is a high-speed 16-bit processing unit: • Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution • Includes many single-byte instructions. This allows much more efficient use of ROM space. • Extensive set of indexed addressing capabilities, including: — Using the stack pointer as an indexing register in all indexed operations — Using the program counter as an indexing register in all but auto increment/decrement mode — Accumulator offsets using A, B, or D accumulators — Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8) 1.3.2 On-Chip Flash with ECC On-chip flash memory on the MC9S12P features the following: • Up to 128 Kbyte of program flash memory — 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection — Erase sector size 512 bytes — Automated program and erase algorithm — User margin level setting for reads — Protection scheme to prevent accidental program or erase • 4 Kbyte data flash space — 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection — Erase sector size 256 bytes — Automated program and erase algorithm — User margin level setting for reads S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 19 Device Overview MC9S12P-Family 1.3.3 • On-Chip SRAM Up to 6 Kbytes of general-purpose RAM 1.3.4 • Main External Oscillator (XOSC) Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals 1.3.5 • Internal RC Oscillator (IRC) Trimmable internal reference clock. — Frequency: 1 MHz — Trimmed accuracy over –40˚C to +125˚C ambient temperature range: ±1.5% 1.3.6 • Internal Phase-Locked Loop (IPLL) Phase-locked-loop clock frequency multiplier — No external components required — Reference divider and multiplier allow large variety of clock rates — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – External 4–16 MHz resonator/crystal (XOSC) – Internal 1 MHz RC oscillator (IRC) 1.3.7 • • • • • • System Integrity Support Power-on reset (POR) System reset generation Illegal address detection with reset Low-voltage detection with interrupt or reset Real time interrupt (RTI) Computer operating properly (COP) watchdog — Configurable as window COP for enhanced failure detection S12P-Family Reference Manual, Rev. 1.12 20 Freescale Semiconductor Device Overview MC9S12P-Family • — Initialized out of reset using option bits located in flash memory Clock monitor supervising the correct function of the oscillator 1.3.8 • • • Timer (TIM) 8 x 16-bit channels for input capture or output compare 16-bit free-running counter with 7-bit precision prescaler 1 x 16-bit pulse accumulator 1.3.9 • Pulse Width Modulation Module (PWM) 6 channel x 8-bit or 3 channel x 16-bit pulse width modulator — Programmable period and duty cycle per channel — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies 1.3.10 • Controller Area Network Module (MSCAN) • • • • • • • • 1 Mbit per second, CAN 2.0 A, B software compatible — Standard and extended data frames — 0–8 bytes data length — Programmable bit rate up to 1 Mbps Five receive buffers with FIFO storage scheme Three transmit buffers with internal prioritization Flexible identifier acceptance filter programmable as: — 2 x 32-bit — 4 x 16-bit — 8 x 8-bit Wakeup with integrated low pass filter option Loop back for self test Listen-only mode to monitor CAN bus Bus-off recovery by software intervention or automatically 16-bit time stamp of transmitted/received messages 1.3.11 • • • • Serial Communication Interface Module (SCI) Full-duplex or single-wire operation Standard mark/space non-return-to-zero (NRZ) format Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths 13-bit baud rate selection S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 21 Device Overview MC9S12P-Family • • • • Programmable character length Programmable polarity for transmitter and receiver Active edge receive wakeup Break detect and transmit collision detect supporting LIN 1.3.12 • • • • • • Serial Peripheral Interface Module (SPI) Configurable 8- or 16-bit data size Full-duplex or single-wire bidirectional Double-buffered transmit and receive Master or slave mode MSB-first or LSB-first shifting Serial clock phase and polarity options 1.3.13 • Analog-to-Digital Converter Module (ATD) • 10-channel, 12-bit analog-to-digital converter — 3 us single conversion time — 8-/10-/12-bit resolution — Left or right justified result data — Internal oscillator for conversion in stop modes — Wakeup from low power modes on analog comparison > or CompB_Addr) In the Outside Range comparator mode, comparator pair A and B can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary is valid only if the aligned address is outside the range. Outside range mode in combination with tagging can be used to detect if the opcode fetches are from an unexpected range. In forced match mode the outside range match would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $3FFFF or lower range limit to $00000 respectively. 6.4.3 Match Modes (Forced or Tagged) Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register TAG bits select the match mode. The modes are described in the following sections. 6.4.3.1 Forced Match When configured for forced matching, a comparator channel match can immediately initiate a transition to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the current state determines the next state. Forced matches are typically generated 2-3 bus cycles after the final matching address bus cycle, independent of comparator RWE/RW settings. Furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an opcode address typically precedes a tagged match at the same address. 6.4.3.2 Tagged Match If a CPU taghit occurs a transition to another state sequencer state is initiated and the corresponding DBGSR flags are set. For a comparator related taghit to occur, the DBG must first attach tags to instructions as they are fetched from memory. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition. 6.4.3.3 Immediate Trigger Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the session and issues a forced breakpoint request to the CPU. It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of the current state of ARM. 6.4.3.4 Channel Priorities In case of simultaneous matches the priority is resolved according to Table 6-36. The lower priority is suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher priority. The priorities described in Table 6-36 dictate that in the case of simultaneous matches, the match pointing to final state has highest priority followed by the lower channel number (0,1,2). S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 179 S12S Debug Module (S12SDBGV2) Table 6-36. Channel Priorities Priority Highest Source TRIG Channel pointing to Final State Match0 (force or tag hit) Match1 (force or tag hit) Lowest Match2 (force or tag hit) Action Enter Final State Transition to next state as defined by state control registers Transition to next state as defined by state control registers Transition to next state as defined by state control registers Transition to next state as defined by state control registers 6.4.4 State Sequence Control ARM = 0 State 0 (Disarmed) ARM = 1 State1 ARM = 0 Session Complete (Disarm) Final State ARM = 0 State3 State2 Figure 6-24. State Sequencer Diagram The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and channel matches. From Final State the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of comparator matches. Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If a debug session is ended by a match on a channel the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. 6.4.4.1 Final State On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control as defined by the TALIGN bit (see 6.3.2.3”). If the TSOURCE bit in DBGTCR is clear then the trace buffer S12P-Family Reference Manual, Rev. 1.12 180 Freescale Semiconductor S12S Debug Module (S12SDBGV2) is disabled and the transition to Final State can only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed. 6.4.5 Trace Buffer Operation The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information in the RAM array in a circular buffer format. The system accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 20-bit trace buffer line is read, an internal pointer into the RAM increments so that the next read receives fresh information. Data is stored in the format shown in Table 6-37 and Table 6-40. After each store the counter register DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented. 6.4.5.1 Trace Trigger Alignment Using the TALIGN bit (see 6.3.2.3) it is possible to align the trigger with the end or the beginning of a tracing session. If end alignment is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the transition to Final State signals the end of the tracing session. Tracing with Begin-Trigger starts at the opcode of the trigger. Using end alignment or when the tracing is initiated by writing to the TRIG bit whilst configured for begin alignment, tracing starts in the second cycle after the DBGC1 write cycle. 6.4.5.1.1 Storing with Begin Trigger Alignment Storing with begin alignment, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the DBG module remains armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with the trigger is stored in the Trace Buffer. Using begin alignment together with tagging, if the tagged instruction is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 6.4.5.1.2 Storing with End Trigger Alignment Storing with end alignment, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module becomes disarmed and no more data is stored. If the trigger is at the address of a change of flow instruction, the trigger event is not stored in the Trace Buffer. If all trace buffer lines have been used before a trigger event occurrs then the trace continues at the first line, overwriting the oldest entries. 6.4.5.2 Trace Modes Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using the TSOURCE bit in the DBGTCR register. The modes are described in the following subsections. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 181 S12S Debug Module (S12SDBGV2) 6.4.5.2.1 Normal Mode In Normal Mode, change of flow (COF) program counter (PC) addresses are stored. COF addresses are defined as follows: • Source address of taken conditional branches (long, short, bit-conditional, and loop primitives) • Destination address of indexed JMP, JSR, and CALL instruction • Destination address of RTI, RTS, and RTC instructions • Vector address of interrupts, except for BDM vectors LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are not stored in the trace buffer. Stored information includes the full 18-bit address bus and information bits, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. NOTE When a COF instruction with destination address is executed, the destination address is stored to the trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. The instruction at the destination address of the original program flow gets executed after the interrupt service routine. In the following example an IRQ interrupt occurs during execution of the indexed JMP at address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ service routine but the destination address is entered into the trace buffer to indicate that the indexed JMP COF has taken place. MARK1 MARK2 SUB_1 LDX JMP NOP BRN NOP DBNE LDAB STAB RTI #SUB_1 0,X ; IRQ interrupt occurs during execution of this ; ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 ; ; Source address TRACE BUFFER ENTRY 4 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 ; * ADDR1 IRQ_ISR A,PART5 #$F0 VAR_C1 The execution flow taking into account the IRQ is as follows MARK1 IRQ_ISR LDX JMP LDAB STAB RTI BRN NOP DBNE #SUB_1 0,X #$F0 VAR_C1 * A,PART5 ; ; ; ; ; SUB_1 ADDR1 S12P-Family Reference Manual, Rev. 1.12 182 Freescale Semiconductor S12S Debug Module (S12SDBGV2) 6.4.5.2.2 Loop1 Mode Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the DBG module writes this value into a background register. This prevents consecutive duplicate address entries in the Trace Buffer resulting from repeated branches. Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help find. 6.4.5.2.3 Detail Mode In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information bit storage to the trace buffer, for each address byte storage. The information bits indicate the size of access (word or byte) and the type of access (read or write). When tracing in Detail Mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle. 6.4.5.2.4 Compressed Pure PC Mode In Compressed Pure PC Mode, the PC addresses of all executed opcodes, including illegal opcodes are stored. A compressed storage format is used to increase the effective depth of the trace buffer. This is achieved by storing the lower order bits each time and using 2 information bits to indicate if a 64 byte boundary has been crossed, in which case the full PC is stored. Each Trace Buffer row consists of 2 information bits and 18 PC address bits NOTE: When tracing is terminated using forced breakpoints, latency in breakpoint generation means that opcodes following the opcode causing the breakpoint can be stored to the trace buffer. The number of opcodes is dependent on program flow. This can be avoided by using tagged breakpoints. 6.4.5.3 Trace Buffer Organization (Normal, Loop1, Detail modes) ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix refers to the tracing count. The information format for Loop1 and Normal modes is identical. In Detail mode, the address and data for each entry are stored on consecutive lines, thus the maximum number of entries is 32. In this case DBGCNT bits are incremented twice, once for the address line and once for the data line, on S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 183 S12S Debug Module (S12SDBGV2) each trace buffer entry. In Detail mode CINF comprises of R/W and size access information (CRW and CSZ respectively). Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte1 and the byte at the higher address is stored to byte0. Table 6-37. Trace Buffer Organization (Normal,Loop1,Detail modes) Mode Entry Number 4-bits Field 2 CINF1,ADRH1 0 CINF2,ADRH2 0 PCH1 PCH2 8-bits Field 1 ADRM1 DATAH1 ADRM2 DATAH2 PCM1 PCM2 8-bits Field 0 ADRL1 DATAL1 ADRL2 DATAL2 PCL1 PCL2 Entry 1 Detail Mode Entry 2 Normal/Loop1 Modes Entry 1 Entry 2 6.4.5.3.1 Information Bit Organization The format of the bits is dependent upon the active trace mode as described below. Field2 Bits in Detail Mode Bit 3 CSZ Bit 2 CRW Bit 1 Bit 0 ADDR[17] ADDR[16] Figure 6-25. Field2 Bits in Detail Mode In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU. Table 6-38. Field Descriptions Bit 3 CSZ 2 CRW Description Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail Mode 0 Word Access 1 Byte Access Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access when tracing in Detail Mode. 0 Write Access 1 Read Access Address Bus bit 17— Corresponds to system address bus bit 17. Address Bus bit 16— Corresponds to system address bus bit 16. 1 ADDR[17] 0 ADDR[16] S12P-Family Reference Manual, Rev. 1.12 184 Freescale Semiconductor S12S Debug Module (S12SDBGV2) Field2 Bits in Normal and Loop1 Modes Bit 3 CSD Bit 2 CVA Bit 1 PC17 Bit 0 PC16 Figure 6-26. Information Bits PCH Table 6-39. PCH Field Descriptions Bit 3 CSD Description Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a source or destination address. This bit has no meaning in Compressed Pure PC mode. 0 Source Address 1 Destination Address Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This bit has no meaning in Compressed Pure PC mode. 0 Non-Vector Destination Address 1 Vector Destination Address Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17. Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16. 2 CVA 1 PC17 0 PC16 6.4.5.4 Trace Buffer Organization (Compressed Pure PC mode) Table 6-40. Trace Buffer Organization Example (Compressed PurePC mode) 2-bits Line Number Field 3 Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 00 11 01 00 10 00 0 PC4 0 6-bits Field 2 6-bits Field 1 PC1 (Initial 18-bit PC Base Address) PC3 0 PC6 (New 18-bit PC Base Address) PC8 PC9 (New 18-bit PC Base Address) PC7 PC2 PC5 6-bits Field 0 Mode Compressed Pure PC Mode NOTE Configured for end aligned triggering in compressed PurePC mode, then after rollover it is possible that the oldest base address is overwritten. In this case all entries between the pointer and the next base address have lost their base address following rollover. For example in Table 6-40 if one line of rollover has occurred, Line 1, PC1, is overwritten with a new entry. Thus the entries on Lines 2 and 3 have lost their base address. For reconstruction of program flow the first base address following the pointer must be used, in the example, Line 4. The pointer points to the oldest entry, Line 2. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 185 S12S Debug Module (S12SDBGV2) Field3 Bits in Compressed Pure PC Modes Table 6-41. Compressed Pure PC Mode Field 3 Information Bit Encoding INF1 0 0 1 1 INF0 0 1 0 1 TRACE BUFFER ROW CONTENT Base PC address TB[17:0] contains a full PC[17:0] value Trace Buffer[5:0] contain incremental PC relative to base address zero value Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value Each time that PC[17:6] differs from the previous base PC[17:6], then a new base address is stored. The base address zero value is the lowest address in the 64 address range The first line of the trace buffer always gets a base PC address, this applies also on rollover. 6.4.5.5 Reading Data from Trace Buffer The data stored in the Trace Buffer can be read provided the DBG module is not armed, is configured for tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed. The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid lines can be determined. DBGCNT does not decrement as data is read. Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no rollover has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. In compressed Pure PC mode on rollover the line with the oldest data entry may also contain newer data entries in fields 0 and 1. Thus if rollover is indicated by the TBF bit, the line status must be decoded using the INF bits in field3 of that line. If both INF bits are clear then the line contains only entries from before the last rollover. If INF0=1 then field 0 contains post rollover data but fields 1 and 2 contain pre rollover data. If INF1=1 then fields 0 and 1 contain post rollover data but field 2 contains pre rollover data. The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. The least significant word of line is read out first. This corresponds to the fields 1 and 0 of Table 6-37. The next word read returns field 2 in the least significant bits [3:0] and “0” for bits [15:4]. Reading the Trace Buffer while the DBG module is armed returns invalid data and no shifting of the RAM pointer occurs. 6.4.5.6 Trace Buffer Reset State The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out and the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current S12P-Family Reference Manual, Rev. 1.12 186 Freescale Semiconductor S12S Debug Module (S12SDBGV2) trace buffer address is initialized by unlocking the trace buffer and points to the oldest valid data even if a reset occurred during the tracing session. To read the trace buffer after a reset, TSOURCE must be set, otherwise the trace buffer reads as all zeroes. Generally debugging occurrences of system resets is best handled using end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. The Trace Buffer contents and DBGCNT bits are undefined following a POR. NOTE An external pin RESET that occurs simultaneous to a trace buffer entry can, in very seldom cases, lead to either that entry being corrupted or the first entry of the session being corrupted. In such cases the other contents of the trace buffer still contain valid tracing information. The case occurs when the reset assertion coincides with the trace buffer entry clock edge. 6.4.6 Tagging A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and can initiate a state sequencer transition. Each comparator control register features a TAG bit, which controls whether the comparator match causes a state sequencer transition immediately or tags the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address. Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is generated immediately, before the tagged instruction is carried out. R/W monitoring, access size (SZ) monitoring and data bus monitoring are not useful if tagging is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the type of access. Thus these bits are ignored if tagging is selected. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. Tagging is disabled when the BDM becomes active. 6.4.7 Breakpoints It is possible to generate breakpoints from channel transitions to final state or using software to write to the TRIG bit in the DBGC1 register. 6.4.7.1 Breakpoints From Comparator Channels Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 187 S12S Debug Module (S12SDBGV2) If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 6-42). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing trigger alignment. Table 6-42. Breakpoint Setup For CPU Breakpoints BRK 0 0 0 0 1 1 TALIGN 0 0 1 1 x x DBGBRK 0 1 0 1 1 0 Breakpoint Alignment Fill Trace Buffer until trigger then disarm (no breakpoints) Fill Trace Buffer until trigger, then breakpoint request occurs Start Trace Buffer at trigger (no breakpoints) Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full Terminate tracing and generate breakpoint immediately on trigger Terminate tracing immediately on trigger 6.4.7.2 Breakpoints Generated Via The TRIG Bit If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the TALIGN bit. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 6-42). If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible with a single write to DBGC1, setting ARM and TRIG simultaneously. 6.4.7.3 Breakpoint Priorities If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator channel match, it has no effect, since tracing has already started. If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is activated by the BGND and the breakpoint to SWI is suppressed. 6.4.7.3.1 DBG Breakpoint Priorities And BDM Interfacing Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU is executing out of BDM firmware, thus comparator matches and associated breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the breakpoint gives priority to BDM requests over SWI requests if the breakpoint happens to coincide with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed. S12P-Family Reference Manual, Rev. 1.12 188 Freescale Semiconductor S12S Debug Module (S12SDBGV2) Table 6-43. Breakpoint Mapping Summary DBGBRK 0 1 X 1 1 BDM Bit (DBGC1[4]) X 0 X 1 1 BDM Enabled X X 1 0 1 BDM Active X 0 1 X 0 Breakpoint Mapping No Breakpoint Breakpoint to SWI No Breakpoint Breakpoint to SWI Breakpoint to BDM BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code, checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow. If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code could coincide with a DBG breakpoint. The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid a repeated breakpoint at the same address. Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes. NOTE When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it returns to the instruction whose tag generated the breakpoint. To avoid a repeated breakpoint at the same location reconfigure the DBG module in the SWI routine, if configured for an SWI breakpoint, or over the BDM interface by executing a TRACE command before the GO to increment the program flow past the tagged instruction. 6.5 6.5.1 Application Information State Machine scenarios Defining the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2 respectively. SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR register. Thus the existing encoding for SCRx[2:0] is not changed. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 189 S12S Debug Module (S12SDBGV2) 6.5.2 Scenario 1 Figure 6-27. Scenario 1 A trigger is generated if a given sequence of 3 code events is executed. SCR1=0011 State1 M1 SCR2=0010 State2 M2 SCR3=0111 State3 M0 Final State Scenario 1 is possible with S12SDBGV1 SCR encoding 6.5.3 Scenario 2 Figure 6-28. Scenario 2a A trigger is generated if a given sequence of 2 code events is executed. SCR1=0011 State1 M1 SCR2=0101 State2 M2 Final State A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes. Figure 6-29. Scenario 2b SCR1=0111 State1 M01 SCR2=0101 State2 M2 Final State A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry into a range (COMPA,COMPB configured for range mode) Figure 6-30. Scenario 2c SCR1=0010 State1 M2 SCR2=0011 State2 M0 Final State All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding S12P-Family Reference Manual, Rev. 1.12 190 Freescale Semiconductor S12S Debug Module (S12SDBGV2) 6.5.4 Scenario 3 Figure 6-31. Scenario 3 A trigger is generated immediately when one of up to 3 given events occurs SCR1=0000 State1 M012 Final State Scenario 3 is possible with S12SDBGV1 SCR encoding 6.5.5 Scenario 4 Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A cause a trigger. This is possible by using CompA and CompC to match on the same address as shown. Figure 6-32. Scenario 4a SCR1=0100 State1 M1 M0 M2 M1 State2 M0 SCR2=0011 SCR3=0001 State 3 M1 Final State This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2 comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown. Figure 6-33. Scenario 4b (with 2 comparators) SCR1=0110 State1 M2 M0 M0 M2 State2 M01 SCR2=1100 M1 disabled in range mode Final State SCR3=1110 State 3 M2 The advantage of using only 2 channels is that now range comparisons can be included (channel0) S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 191 S12S Debug Module (S12SDBGV2) This however violates the S12SDBGV1 specification, which states that a match leading to final state always has priority in case of a simultaneous match, whilst priority is also given to the lowest channel number. For S12SDBG the corresponding CPU priority decoder is removed to support this, such that on simultaneous taghits, taghits pointing to final state have highest priority. If no taghit points to final state then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG would break on a simultaneous M0/M2. 6.5.6 Scenario 5 Figure 6-34. Scenario 5 Trigger if following event A, event C precedes event B. i.e. the expected execution flow is A->B->C. SCR1=0011 State1 M1 M2 SCR2=0110 State2 M0 Final State Scenario 5 is possible with the S12SDBGV1 SCR encoding 6.5.7 Scenario 6 Trigger if event A occurs twice in succession before any of 2 other events (BC) occurs. This scenario is not possible using the S12SDBGV1 SCR encoding. S12SDBGV2 includes additions shown in red. The change in SCR1 encoding also has the advantage that a State1->State3 transition using M0 is now possible. This is advantageous because range and data bus comparisons use channel0 only. Figure 6-35. Scenario 6 SCR1=1001 State1 M0 M12 SCR3=1010 State3 M0 Final State 6.5.8 Scenario 7 Trigger when a series of 3 events is executed out of order. Specifying the event order as M1,M2,M0 to run in loops (120120120). Any deviation from that order should trigger. This scenario is not possible using the S12P-Family Reference Manual, Rev. 1.12 192 Freescale Semiconductor S12S Debug Module (S12SDBGV2) S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding OR forks as shown in red this scenario is possible. Figure 6-36. Scenario 7 M01 SCR1=1101 State1 M1 SCR2=1100 State2 M2 SCR3=1101 State3 M12 Final State M0 M02 On simultaneous matches the lowest channel number has priority so with this configuration the forking from State1 has the peculiar effect that a simultaneous match0/match1 transitions to final state but a simultaneous match2/match1transitions to state2. 6.5.9 Scenario 8 Figure 6-37. Scenario 8a Trigger when a routine/event at M2 follows either M1 or M0. SCR1=0111 State1 M01 SCR2=0101 State2 M2 Final State Trigger when an event M2 is followed by either event M0 or event M1 Figure 6-38. Scenario 8b SCR1=0010 State1 M2 SCR2=0111 State2 M01 Final State Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 193 S12S Debug Module (S12SDBGV2) 6.5.10 Scenario 9 Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed again. This cannot be realized with theS12SDBGV1 SCR encoding due to OR limitations. By changing the SCR2 encoding as shown in red this scenario becomes possible. Figure 6-39. Scenario 9 SCR1=0111 State1 M01 M2 SCR2=1111 State2 M01 Final State 6.5.11 Scenario 10 Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1. As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger is generated. Configuring CompA and CompC the same, it is possible to generate a breakpoint on the third consecutive occurrence of event M0 without a reset M1. Figure 6-40. Scenario 10a M1 SCR1=0010 State1 M2 SCR2=0100 State2 M2 SCR3=0010 State3 M0 Final State M1 Figure 6-41. Scenario 10b M0 SCR1=0010 State1 M2 SCR2=0011 State2 M1 SCR3=0000 State3 Final State M0 Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before M1 then a trigger is generated. S12P-Family Reference Manual, Rev. 1.12 194 Freescale Semiconductor S12S Debug Module (S12SDBGV2) S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 195 S12S Debug Module (S12SDBGV2) S12P-Family Reference Manual, Rev. 1.12 196 Freescale Semiconductor Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description Revision History Version Revision Effective Number Date Date V01.00 V01.01 V01.02 V01.03 16 Jan.07 9 July 08 7 Oct. 08 16 Jan. 07 9 July 08 7 Oct. 08 Author Initial release Description of Changes added IRCLK to Block Diagram clarified and detailed oscillator filter functionality added note, that startup time of external Oscillator tUPOSC must be considered, especially when entering Pseudo Stop Mode Modified reset phase descriptions to reference fVCORST instead of fPLLRST and correct typo of RESET pin sample point from 64 to 256 cycles in section: Description of Reset Operation 11 Dec. 08 11 Dec. 08 V01.04 17 Jun. 09 17 Jun. 09 7.1 Introduction This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU). • The optional Pierce oscillator (OSCLCP) provides a robust, low-noise and low-power external clock source. It is designed for optimal start-up margin with typical crystal oscillators. • The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required chip internal voltages and voltage monitors. • The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter. • The Internal Reference Clock (IRC1M) provides a stable 1MHz internal clock. 7.1.1 Features The optional Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity. • For crystals or resonators from 4MHz to 16MHz. • High noise immunity due to input hysteresis and spike filtering. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 197 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description • • • • • Low RF emissions with peak-to-peak swing limited dynamically Transconductance (gm) sized for optimum start-up margin for typical crystals Dynamic gain control eliminates the need for external current limiting resistor Integrated resistor eliminates the need for external bias resistor. Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits power The Voltage Regulator (IVREG) has the following features: • Input voltage range form 3.13V to 5.5V • Low-voltage detect (LVD) with low-voltage interrupt (LVI) • Power-on reset (POR) • Low-voltage reset (LVR) The Phase Locked Loop (PLL) has the following features: • highly accurate and phase locked frequency multiplier • Configurable internal filter for best stability and lock time. • Frequency modulation for defined jitter and reduced emission • Automatic frequency lock detector • Interrupt request on entry or exit from locked condition • Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based. • PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock The Internal Reference Clock (IRC1M) has the following features: • Trimmable in frequency • Factory trimmed value for 1MHz in Flash Memory, can be overwritten by application if required Other features of the S12CPMU include • Clock monitor to detect loss of crystal • Autonomous periodical interrupt (API) • Bus Clock Generator — Clock switch to select either PLL Clock or external crystal/resonator based Bus Clock — PLL Clock divider to adjust system speed • System Reset generation from the following possible sources: — Power-on reset (POR) — Low-voltage reset (LVR) — Illegal address access — COP time out — Loss of oscillation (clock monitor fail) — External pin RESET S12P-Family Reference Manual, Rev. 1.12 198 Freescale Semiconductor S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description 7.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the S12CPMU. 7.1.2.1 Run Mode The voltage regulator is in full performance mode (FPM). The Phase Locked Loop (PLL) is on. The Internal Reference Clock (IRC1M) is on. The API is available. • PLL Engaged Internal (PEI) — This is the default mode after System Reset and Power-On Reset. — The Bus Clock is based on the PLL Clock. — After reset the PLL is configured for 64MHz VCOCLK operation Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 16MHz and Bus Clock is 8MHz. The PLL can be re-configured for other bus frequencies. — The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M • PLL Engaged External (PEE) — The Bus Clock is based on the PLL Clock. — This mode can be entered from default mode PEI by performing the following steps: – Configure the PLL for desired bus frequency. – Program the reference divider (REFDIV[3:0] bits) to divide down Oscillator frequency if necessary. – Enable the external Oscillator (OSCE bit) • PLL Bypassed External (PBE) — The Bus Clock is based on the Oscillator Clock. — This mode can be entered from default mode PEI by performing the following steps: – Enable the external Oscillator (OSCE bit) – Wait for Oscillator to start up (UPOSC=1) – Select the Oscillator Clock as Bus Clock (PLLSEL=0). — The PLL Clock is still on for spike filtering on Oscillator Clock. 7.1.2.2 Wait Mode For S12CPMU Wait Mode is the same as Run Mode. 7.1.2.3 Stop Mode This mode is entered by executing the CPU STOP instruction. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 199 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description The voltage regulator is in reduced power mode (RPM). The API is available. The Phase Locked Loop (PLL) is off. The Internal Reference Clock (IRC1M) is off. Core Clock, Bus Clock and BDM Clock are stopped. Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1). • Full Stop Mode The oscillator (OSCLCP) is disabled. After wake from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL=0, RTIOSCSEL=0). • Pseudo Stop Mode The oscillator (OSCLCP) continues torun. If the respective enable bits are set the COP and RTI will continue to run. The clock configuration bits PLLSEL, COPOSCSEL, RTIOSCSEL are unchanged. NOTE When starting up the external Oscillator (either by programming OSCEN bit to 1 or on exit from full stop mode with OSCEN bit is already 1) the software must wait for a minimum time equivalent to the startup-time of the external Oscillator tUPOSC before entering Pseudo Stop Mode. 7.1.3 Block Diagram Figure 7-1 shows a block diagram of the S12CPMU. S12P-Family Reference Manual, Rev. 1.12 200 Freescale Semiconductor S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description MMC VDDR VSSPLL VSS VDDX VSSX VDDA VSSA RESET Clock Monitor Voltage Regulator 3.13 to 5.5V Illegal Address Access VDD, VDDPLL, VDDF (core supplies) Low Voltage Detect VDDA Low Voltage Detect VDDX Power-On Detect LVRF PORF Reset Generator UPOSC=0 sets PLLSEL bit COP time out ILAF LVDS LVIE Low Voltage Interrupt S12CPMU Power-On Reset System Reset Oscillator status Interrupt OSCIE monitor fail UPOSC adaptive spike filter IRCTRIM[9:0] Internal Reference Clock (IRC1M) Loop EXTAL Controlled Pierce Oscillator XTAL (OSCLCP) 4MHz-16MHz REFDIV[3:0] Reference Divider OSCCLK OSCFILT[4:0] & PLLSEL CAN_OSCCLK (to MSCAN) POSTDIV[4:0] Post Divider 1,2,..32 divide by 4 Core Clock PLLCLK divide Bus Clock by 2 IRCCLK (to LCD) divide by 8 HTDS HTIE BDM Clock PSTP OSCE VCOFRQ[1:0] VCOCLK Lock detect REFCLK FBCLK Phase locked Loop with internal Filter (PLL) REFFRQ[1:0] LOCK Divide by 2*(SYNDIV+1) SYNDIV[5:0] Bus Clock RC ACLK Osc. APICLK HT Interrupt High Temperature Sense LOCKIE PLL Lock Interrupt Autonomous API_EXTCLK Periodic Interrupt (API) APIE RTIE API Interrupt RTI Interrupt UPOSC UPOSC=0 clears IRCCLK COPCLK COP OSCCLK COP time out to Reset Generator IRCCLK Watchdog RTICLK OSCCLK Real Time Interrupt (RTI) PRE CPMURTI COPOSCSEL PCE CPMUCOP RTIOSCSEL Figure 7-1. Block diagram of S12CPMU S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 201 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description Figure 7-2 shows a block diagram of the OSCLCP. OSCCLK Peak Detector Gain Control VDDPLL = 1.8 V VSSPLL Rf EXTAL XTAL Figure 7-2. OSCLCP Block Diagram 7.2 Signal Description This section lists and describes the signals that connect off chip. 7.2.1 RESET RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered. 7.2.2 EXTAL and XTAL These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal OSCCLK is derived from the EXTAL input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 kΩ and the XTAL pin is pulled down by an internal resistor of approximately 700 kΩ. S12P-Family Reference Manual, Rev. 1.12 202 Freescale Semiconductor S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals. 7.2.3 TEMPSENSE — temperature sensor output voltage Depending on the VSEL value either the voltage level generated by the temperature sensor or the VREG bandgap voltage is driven to a special channel of the ATD Converter. See device level specification for connectivity. 7.2.4 VDDR — Regulator Power Input Pin VDDR is the power input of IVREG. All currents sourced into the regulator loads flow through this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSS can smooth ripple on VDDR. 7.2.5 VDDA, VSSA — Regulator Reference Supply Pins VDDA/VSSA, which are relatively quiet, are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply. 7.2.6 VSS, VSSPLL— Ground Pins VSS and VSSPLL must be grounded. 7.2.7 VDDX, VSSX— Pad Supply Pins This supply domain is monitored by the Low Voltage Reset circuit. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can further improve the quality of this supply. 7.2.8 API_EXTCLK — API external clock output pin This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification to which pin it connects. 7.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the S12CPMU. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 203 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description 7.3.1 Module Memory Map The S12CPMU registers are shown in Figure 7-3. Addres s 0x0034 0x0035 0x0036 0x0037 0x0038 Name CPMU SYNR CPMU REFDIV CPMU POSTDIV CPMUFLG CPMUINT R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 Bit 0 VCOFRQ[1:0] REFFRQ[1:0] 0 0 0 0 0 SYNDIV[5:0] REFDIV[3:0] POSTDIV[4:0] LOCKIF LOCKIE 0 LOCK 0 ILAF 0 OSCIF OSCIE RTI OSCSEL 0 UPOSC 0 RTIF RTIE PLLSEL 0 PORF 0 LVRF 0 0 0x0039 CPMUCLKS 0x003A 0x003B CPMUPLL CPMURTI PSTP 0 PRE 0 PCE 0 COP OSCSEL 0 FM1 RTR5 0 WRTMASK 0 0 0 Bit 5 VSEL 0 0 FM0 RTR4 0 0 0 0 Bit 4 0 0 RTDEC WCOP 0 0 0 Bit 7 0 0 RTR6 RSBCK 0 0 0 Bit 6 0 0 0 RTR3 0 0 0 0 Bit 3 HTE 0 RTR2 CR2 0 0 0 Bit 2 HTDS LVDS RTR1 CR1 0 0 0 Bit 1 HTIE LVIE APIE 0 RTR0 CR0 0 0 0 Bit 0 HTIF LVIF APIF 0 0x003C CPMUCOP 0x003D 0x003E 0x003F 0x02F0 0x02F1 0x02F2 RESERVED R CPMUTEST0 W RESERVED R CPMUTEST1 W CPMU ARMCOP CPMU HTCTL CPMU LVCTL CPMU APICTL R W R W R W R W R W R W APICLK APITR5 APIR15 APIES APITR2 APIR12 APIEA APITR1 APIR11 APIFE APITR0 APIR10 0x02F3 CPMUAPITR 0x02F4 CPMUAPIRH APITR4 APIR14 APITR3 APIR13 APIR9 APIR8 = Unimplemented or Reserved Figure 7-3. CPMU Register Summary S12P-Family Reference Manual, Rev. 1.12 204 Freescale Semiconductor S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description Addres s Name R W Bit 7 APIR7 0 6 APIR6 0 0 5 APIR5 0 0 4 APIR4 0 0 3 APIR3 0 2 APIR2 0 1 APIR1 0 Bit 0 APIR0 0 0x02F5 CPMUAPIRL 0x02F6 RESERVED R CPMUTEST3 W R W R W R W R W R W 0x02F7 CPMUHTTR 0x02F8 0x02F9 0x02FA CPMU IRCTRIMH CPMU IRCTRIML CPMUOSC HTOE HTTR3 0 HTTR2 0 HTTR1 HTTR0 TCTRIM[3:0] IRCTRIM[9:8] IRCTRIM[7:0] OSCE 0 0 OSCBW 0 0 0 0 0 0 0 0 0 OSCFILT[4:0] 0 0 0 0 PROT 0 0x02FB CPMUPROT 0x02FC RESERVED R CPMUTEST2 W = Unimplemented or Reserved Figure 7-3. CPMU Register Summary 7.3.2 Register Descriptions This section describes all the S12CPMU registers and their individual bits. Address order is as listed in Figure 7-3. 7.3.2.1 S12CPMU Synthesizer Register (CPMUSYNR) The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range. 0x0034 7 6 5 4 3 2 1 0 R VCOFRQ[1:0] W Reset 0 1 0 1 1 1 1 1 SYNDIV[5:0] Figure 7-4. S12CPMU Synthesizer Register (CPMUSYNR) Read: Anytime S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 205 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime. Else write has no effect. NOTE Writing to this register clears the LOCK and UPOSC status bits. If PLL has locked (LOCK=1) f VCO = 2 × f REF × ( SYNDIV + 1 ) NOTE fVCO must be within the specified VCO frequency lock range. Bus frequency fbus must not exceed the specified maximum. The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK frequency as shown in Table 7-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). Table 7-1. VCO Clock Frequency Selection VCOCLK Frequency Ranges 32MHz VDD35) is greater than IDD35, the injection current may flow out of VDD35 and could result in external power supply going out of regulation. Ensure external VDD35 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS35 or VDD35). S12P-Family Reference Manual, Rev. 1.12 500 Freescale Semiconductor Electrical Characteristics Table A-1. Absolute Maximum Ratings(1) Num 1 2 3 4 5 6 7 8 Rating I/O, regulator and analog supply voltage Voltage difference VDDX to VDDA Voltage difference VSSX to VSSA Digital I/O input voltage Analog reference EXTAL, XTAL Instantaneous maximum current Single pin limit for all digital I/O pins(2) Instantaneous maximum current Single pin limit for EXTAL, XTAL Symbol VDD35 ∆VDDX ∆VSSX VIN VRH, VRL VILV I I D Min –0.3 –6.0 –0.3 –0.3 –0.3 –0.3 –25 –25 –65 Max 6.0 0.3 0.3 6.0 6.0 2.16 +25 +25 155 Unit V V V V V V mA mA °C DL 9 Storage temperature range Tstg 1. Beyond absolute maximum ratings device might be damaged. 2. All digital I/O pins are internally clamped to VSSX and VDDX, or VSSA and VDDA. A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 501 Electrical Characteristics Table A-2. ESD and Latch-up Test Conditions Model Human Body Series resistance Storage capacitance Number of pulse per pin Positive Negative Latch-up Minimum input voltage limit Maximum input voltage limit Description Symbol R1 C — — — — Value 1500 100 3 3 –2.5 7.5 V V Unit Ohm pF Table A-3. ESD and Latch-Up Protection Characteristics Num 1 2 3 C C C C Rating Human Body Model (HBM) Charge Device Model (CDM) Latch-up current at TA = 125°C Positive Negative Latch-up current at TA = 27°C Positive Negative Symbol VHBM VCDM ILAT +100 –100 ILAT +200 –200 — — — — mA Min 2000 500 Max — — Unit V V mA 4 C A.1.7 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”. Table A-4. Operating Conditions Rating I/O, regulator and analog supply voltage Voltage difference VDDX to VDDA Voltage difference VDDR to VDDX Voltage difference VSSX to VSSA Voltage difference VSS3 , VSSPLL to VSSX Digital logic supply voltage Symbol VDD35 ∆VDDX ∆VDDR ∆VSSX ∆VSS VDD -0.1 1.72 -0.1 Min 3.13 Typ 5 Max 5.5 Unit V refer to Table A-14 0 0.1 V refer to Table A-14 0 1.8 0.1 1.98 V V S12P-Family Reference Manual, Rev. 1.12 502 Freescale Semiconductor Electrical Characteristics Table A-4. Operating Conditions Oscillator Bus frequency Temperature Option C Operating junction temperature range Operating ambient temperature range(1) Temperature Option V Operating junction temperature range Operating ambient temperature range1 fosc fbus TJ TA TJ TA 4 0.5 –40 –40 –40 –40 — — — 27 — 27 16 32 105 85 °C 125 105 MHz MHz °C Temperature Option M °C Operating junction temperature range TJ –40 — 150 Operating ambient temperature range1 TA –40 27 125 1. Please refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” for more details about the relation between ambient temperature TA and device junction temperature TJ. NOTE Operation is guaranteed when powering down until low voltage reset assertion. A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be obtained from: T T T J A D = Junction Temperature, [ ° C ] = Ambient Temperature, [ ° C ] = Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ ° C/W] J = T + (P • Θ ) A D JA P Θ JA The total power dissipation can be calculated from: P P D =P INT +P IO INT = Chip Internal Power Dissipation, [W] 2 P = R ⋅I IO DSON IO i i ∑ S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 503 Electrical Characteristics PIO is the sum of all output currents on I/O ports associated with VDDX, whereby R V OL = ----------- ;for outputs driven low DSON I OL R V –V DD 35 OH = -------------------------------------- ;for outputs driven high DSON I OH P INT =I DDR ⋅V DDR +I DDA ⋅V DDA Table A-5. Thermal Package Characteristics(1) Num C Rating QFN 48 1 2 3 4 5 D D D D D Thermal resistance QFN 48, single sided PCB(2) Thermal resistance QFN 48, double sided PCB with 2 internal planes(3) Junction to Board QFN 48 Junction to Case QFN 48 4 Symbol Min Typ Max Unit θJA θJA θJB θJC ΨJT — — — — — — — — — — 82 28 11 1.4 4 °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Junction to Case (Bottom) QFN 485 QFP 80 6 7 8 9 10 D D D D D Thermal resistance QFP 80, single sided PCB 2 θJA θJA θJB θJC ΨJT — — — — — — — — — — 56 43 28 19 5 Thermal resistance QFP 80, double sided PCB with 2 internal planes3 Junction to Board QFP 80 Junction to Case QFP 80(4) Junction to Package Top QFP 80(5) LQFP 64 11 12 13 14 D D D D Thermal resistance LQFP 64, single sided PCB2 Thermal resistance LQFP 64, double sided PCB with 2 internal planes3 Junction to Board LQFP 64 Junction to Case LQFP 64(6) (7) θJA θJA θJB θJC — — — — — — — — 70 52 35 17 ΨJT — — 3 °C/W 15 D Junction to Package Top LQFP 64 1. The values for thermal resistance are achieved by package simulations 2. Junction to ambient thermal resistance, θJA was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. 3. Junction to ambient thermal resistance, θJA was simulated to be equivalent to the JEDEC specification JESD51-7 in a horizontal configuration in natural convection. S12P-Family Reference Manual, Rev. 1.12 504 Freescale Semiconductor Electrical Characteristics 4. Junction to case thermal resistance was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the “case” temperature. This basic cold plate measurement technique is described by MILSTD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 5. Thermal characterization parameter ΨJT is the “resistance” from junction to reference point thermocouple on top center of the case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in a steady state customer enviroment. 6. Junction to case thermal resistance was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the “case” temperature. This basic cold plate measurement technique is described by MILSTD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 7. Thermal characterization parameter ΨJT is the “resistance” from junction to reference point thermocouple on top center of the case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in a steady state customer enviroment. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 505 Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. Table A-6. 3.3-V I/O Characteristics ALL 3.3V RANGE I/O PARAMETERS ARE SUBJECT TO CHANGE FOLLOWING CHARACTERIZATION Conditions are 3.15 V < VDD35 < 3.6 V junction temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C 1 P Input high voltage T Input high voltage 2 P Input low voltage T Input low voltage 3 4 C Input hysteresis Input leakage current (pins in high impedance input mode)(1) Vin = VDD35 or VSS35 P M temperature range –40°C to +150°C C V temperature range –40°C to +125°C C C temperature range –40°C to +105°C C Output high voltage (pins in output mode) Partial drive IOH = –0.75 mA P Output high voltage (pins in output mode) Full drive IOH = –4 mA C Output low voltage (pins in output mode) Partial Drive IOL = +0.9 mA P Output low voltage (pins in output mode) Full Drive IOL = +4.75 mA P Internal pull up resistance VIH min > input voltage > VIL max P Internal pull down resistance VIH min > input voltage > VIL max D Input capacitance T Injection current Single pin limit Total device limit, sum of all injected currents P Port J, P interrupt input pulse filtered (STOP)(3) P Port J, P interrupt input pulse passed (STOP) D Port J, P interrupt input pulse filtered (STOP) D Port J, P interrupt input pulse passed (STOP) 3 (2) Rating Symbol VIH VIH VIL VIL VHYS I in Min 0.65*VDD35 — — VSS35 – 0.3 Typ — — — — 250 Max — VDD35 + 0.3 0.35*VDD35 — Unit V V V V mV µA –1.00 -0.75 -0.50 V OH — — — — — — — — — 6 — 1.00 0.75 0.50 — — 0.4 0.4 50 50 — 2.5 25 V V V V KΩ KΩ pF mA 5 6 7 8 9 10 11 12 VDD35 – 0.4 VDD35 – 0.4 — — 25 25 — –2.5 –25 — 10 — 4 VOH VOL V OL RPUL RPDH Cin IICS IICP tPULSE tPULSE tPULSE tPULSE 13 14 15 16 — — — — 3 — 3 — µs µs tcyc tcyc PWIRQ 1 — — tcyc 17 D IRQ pulse width, edge-sensitive mode (STOP) 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8°C to 12 C in the temperature range from 50°C to 125°C. ° 2. Refer to Section A.1.4, “Current Injection” for more details 3. Parameter only applies in stop or pseudo stop mode. S12P-Family Reference Manual, Rev. 1.12 506 Freescale Semiconductor Electrical Characteristics Table A-7. 5-V I/O Characteristics Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C 1 P Input high voltage T Input high voltage 2 P Input low voltage T Input low voltage 3 4 C Input hysteresis Input leakage current (pins in high impedance input mode)(1) Vin = VDD35 or VSS35 P M temperature range –40°C to +150°C C V temperature range –40°C to +125°C C C temperature range –40°C to +105°C C Output high voltage (pins in output mode) Partial drive IOH = –2 mA P Output high voltage (pins in output mode) Full drive IOH = –10 mA C Output low voltage (pins in output mode) Partial drive IOL = +2 mA P Output low voltage (pins in output mode) Full drive IOL = +10 mA P Internal pull up resistance VIH min > input voltage > VIL max P Internal pull down resistance VIH min > input voltage > VIL max D Input capacitance T Injection current Single pin limit Total device Limit, sum of all injected currents P Port J, P interrupt input pulse filtered (STOP)(3) P Port J, P interrupt input pulse passed (STOP) D Port J, P interrupt input pulse filtered (STOP) D Port J, P interrupt input pulse passed (STOP) 3 (2) Rating Symbol V IH Min 0.65*VDD35 — — VSS35 – 0.3 Typ — — — — 250 Max — VDD35 + 0.3 0.35*VDD35 — — Unit V V V V mV µA VIH VIL VIL VHYS I in –1.00 -0.75 -0.50 V OH — — — — — — — — — 6 — 1.00 0.75 0.50 — — 0.8 0.8 50 50 — 2.5 25 V V V V KΩ KΩ pF mA 5 6 7 8 9 10 11 12 VDD35 – 0.8 VDD35 – 0.8 — — 25 25 — –2.5 –25 — 10 — 4 VOH VOL V OL RPUL RPDH Cin IICS IICP tPULSE tPULSE tPULSE tPULSE 13 14 15 16 — — — — 3 — 3 — µs µs tcyc tcyc PWIRQ 1 — — tcyc 17 D IRQ pulse width, edge-sensitive mode (STOP) 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8°C to 12 C in the temperature range from 50°C to 125°C. ° 2. Refer to Section A.1.4, “Current Injection” for more details 3. Parameter only applies in stop or pseudo stop mode. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 507 Electrical Characteristics A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions Run current is measured on VDDR pin. It does not include the current to drive external loads. Unless otherwise noted the currents are measured in special single chip mode and the CPU code is executed from RAM. For Run and Wait current measurements PLL is on and the reference clock is the IRC1M trimmed to 1MHz. The bus frequency is 32MHz and the CPU frequency is 64MHz. Table A-8., Table A-9. and Table A-10. show the configuration of the CPMU module and the peripherals for Run, Wait and Stop current measurement. Table A-8. CPMU Configuration for Pseudo Stop Current Measurement CPMU REGISTER CPMUCLKS CPMUOSC CPMURTI CPMUCOP Bit settings/Conditions PLLSEL=0, PSTP=1, PRE=PCE=RTIOSCSEL=COPOSCSEL=1 OSCE=1, External Square wave on EXTAL fEXTAL=16MHz, VIH= 1.8V, VIL=0V RTDEC=0, RTR[6:4]=111, RTR[3:0]=1111; WCOP=1, CR[2:0]=111 Table A-9. CPUM Configuration for Run/Wait and Full Stop Current Measurement CPMU REGISTER CPMUSYNR CPMUPOSTDIV CPMUCLKS CPMUOSC Bit settings/Conditions VCOFRQ[1:0]=01,SYNDIV[5:0] = 32 POSTDIV[4:0]=0, PLLSEL=1 OSCE=0, Reference clock for PLL is fref=firc1m trimmed to 1MHz API settings for STOP current measurement CPMUAPICTL CPMUAPITR CPMUAPIRH/RL APIEA=0, APIFE=1, APIE=0 trimmed to 10Khz set to $FFFF S12P-Family Reference Manual, Rev. 1.12 508 Freescale Semiconductor Electrical Characteristics Table A-10. Peripheral Configurations for Run & Wait Current Measurement Peripheral MSCAN SPI SCI PWM ATD Configuration configured to loop-back mode using a bit rate of 1Mbit/s configured to master mode, continously transmit data (0x55 or 0xAA) at 1Mbit/s configured into loop mode, continously transmit data (0x55) at speed of 57600 baud configured to toggle its pins at the rate of 40kHz the peripheral is configured to operate at its maximum specified frequency and to continuously convert voltages on all input channels in sequence. the module is enabled and the comparators are configured to trigger in outside range.The range covers all the code executed by the core. the peripheral shall be configured to output compare mode, pulse accumulator and modulus counter enabled. enabled DBG TIM COP & RTI Table A-11. Run and Wait Current Characteristics Conditions are: VDDR=5.5V, TA=125°C, see Table A-9. and Table A-10. Num 1 2 C P P IDD Run Current IDD Wait Current Rating Symbol IDDR IDDW Min Typ 18 11 Max 20 12 Unit mA mA Table A-12. Full Stop Current Characteristics Conditions are: VDDR=5.5V, API see Table A-9. Num C 150°C -40°C 25°C, 150°C, -40°C 25°C Rating Symbol Stop Current API disabled 1 2 3 4 5 6 P P P C C C IDDS IDDS IDDS Stop Current API enabled IDDS IDDS IDDS 270 20 40 µA µA µA 250 15 25 1100 35 50 µA µA µA Min Typ Max Unit S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 509 Electrical Characteristics Table A-13. Pseudo Stop Current Characteristics Conditions are: VDDR=5.5V, RTI and COP and API enabled, see Table A-8. Num 1 2 3 C C C C 150°C -40°C 25°C Rating Symbol IDDPS IDDPS IDDPS Min Typ 450 175 200 Max Unit µA µA µA A.2 ATD Characteristics This section describes the characteristics of the analog-to-digital converter. A.2.1 ATD Operating Characteristics The Table A-14 and Table A-15 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-14. ATD Operating Characteristics Conditions are shown in Table A-4 unless otherwise noted, supply voltage 3.13 V < VDDA < 5.5 V Num C 1 D Reference potential Low High D Voltage difference VDDX to VDDA D Voltage difference VSSX to VSSA C Differential reference voltage (1) Rating Symbol VRL VRH ∆VDDX ∆VSSX VRH-VRL fATDCLk Min VSSA VDDA/2 –2.35 –0.1 3.13 0.25 0.6 Typ — — 0 0 5.0 Max VDDA/2 VDDA 0.1 0.1 5.5 8.0 Unit V V V V V MHz MHz us 2 3 4 5 6 7 C ATD Clock Frequency (derived from bus clock via the prescaler bus) P ATD Clock Frequency in Stop mode (internal generated temperature and voltage dependent clock, ICLK) D ADC conversion in stop, recovery time(2) ATD Conversion Period(3) 12 bit resolution: D 10 bit resolution: 8 bit resolution: 1 — 1.7 1.5 tATDSTPRC V — 8 NCONV12 NCONV10 NCONV8 20 19 17 42 41 39 ATD clock Cycles 1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V 2. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time. 3. The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles. S12P-Family Reference Manual, Rev. 1.12 510 Freescale Semiconductor Electrical Characteristics A.2.2 Factors Influencing Accuracy Source resistance, source capacitance and current injection have an influence on the accuracy of the ATD. A further factor is that PortAD pins that are configured as output drivers switching. A.2.2.1 Port AD Output Drivers Switching PortAD output drivers switching can adversely affect the ATD accuracy whilst converting the analog voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply pins. Although internal design measures are implemented to minimize the affect of output driver noise, it is recommended to configure PortAD pins as outputs only for low frequency, low load outputs. The impact on ATD accuracy is load dependent and not specified. The values specified are valid under condition that no PortAD output drivers switch during conversion. A.2.2.2 Source Resistance Due to the input pin leakage current as specified in Table A-6 and Table A-7 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error (10-bit resolution) of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance of up to 10Kohm are allowed. A.2.2.3 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB (10-bit resilution), then the external filter capacitor, Cf ≥ 1024 * (CINS–CINN). A.2.2.4 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF (in 10-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as: VERR = K * RS * IINJ with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 511 Electrical Characteristics Table A-15. ATD Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 5 Rating Symbol RS CINN CINS RINA INA Kp Min — — — -2.5 — — Typ — — — 5 — — — Max 1 10 16 15 2.5 1E-4 5E-3 Unit KΩ pF kΩ mA A/A A/A C Max input source resistance(1) D Total input capacitance Non sampling Total input capacitance Sampling D Input internal Resistance C Disruptive analog input current C Coupling ratio positive current injection 6 C Coupling ratio negative current injection Kn 1. 1 Refer to A.2.2.2 for further information concerning source resistance A.2.3 ATD Accuracy Table A-16. and Table A-17. specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. S12P-Family Reference Manual, Rev. 1.12 512 Freescale Semiconductor Electrical Characteristics A.2.3.1 ATD Accuracy Definitions For the following definitions see also Figure A-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps. V –V i i–1 DNL ( i ) = -------------------------- – 1 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: INL ( n ) = i=1 ∑ n V –V n 0 DNL ( i ) = -------------------- – n 1LSB S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 513 Electrical Characteristics DNL Vi-1 $3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 10-Bit Resolution $3F3 LSB 10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary $FF $FE $FD 8-Bit Resolution Vin mV 9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 45 55 60 Ideal Transfer Curve 2 10-Bit Transfer Curve 1 8-Bit Transfer Curve 65 70 75 80 85 90 95 100 105 110 115 120 5000 + Figure A-1. ATD Accuracy Definitions NOTE Figure A-1 shows only definitions, for specification values refer to Table A16 and Table A-17. S12P-Family Reference Manual, Rev. 1.12 514 Freescale Semiconductor Electrical Characteristics Table A-16. ATD Conversion Performance 5V range Conditions are shown in Table A-4. unless otherwise noted. VREF = VRH - VRL = 5.12V. fATDCLK = 8.0MHz The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions. Num C 1 2 3 4 5 6 7 8 9 10 11 P Resolution P Differential Nonlinearity P Integral Nonlinearity P Absolute Error C Resolution C Differential Nonlinearity C Integral Nonlinearity C Absolute Error2. C Resolution C Differential Nonlinearity C Integral Nonlinearity (2) Rating(1) 12-Bit 12-Bit 12-Bit 12-Bit 10-Bit 10-Bit 10-Bit 10-Bit 8-Bit 8-Bit 8-Bit Symbol LSB DNL INL AE LSB DNL INL AE LSB DNL INL Min Typ 1.25 Max Unit mV -4 -5 -7 ±2 ±2.5 ±4 5 4 5 7 counts counts counts mV -1 -2 -3 ±0.5 ±1 ±2 20 ±0.3 ±0.5 1 2 3 counts counts counts mV -0.5 -1 0.5 1 counts counts 8-Bit AE -1.5 ±1 1.5 counts 12 C Absolute Error2. 1. The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode. 2. These values include the quantization error which is inherently 1/2 count for any A/D converter. Table A-17. ATD Conversion Performance 3.3V range Conditions are shown in Table A-4. unless otherwise noted. VREF = VRH - VRL = 3.3V. fATDCLK = 8.0MHz The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions. Num C 1 2 3 4 5 6 7 8 9 10 11 P Resolution P Differential Nonlinearity P Integral Nonlinearity P Absolute Error C Resolution C Differential Nonlinearity C Integral Nonlinearity C Absolute Error C Resolution C Differential Nonlinearity C Integral Nonlinearity 2. 2. (2) Rating(1) 12-Bit 12-Bit 12-Bit 12-Bit 10-Bit 10-Bit 10-Bit 10-Bit 8-Bit 8-Bit 8-Bit Symbol LSB DNL INL AE LSB DNL INL AE LSB DNL INL Min Typ 0.80 Max Unit mV -6 -7 -8 ±3 ±3 ±4 3.22 ±1 ±1 ±2 12.89 ±0.3 ±0.5 6 7 8 counts counts counts mV -1.5 -2 -3 1.5 2 3 counts counts counts mV -0.5 -1 0.5 1 counts counts 8-Bit AE -1.5 ±1 1.5 counts 12 C Absolute Error 1. The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode. 2. These values include the quantization error which is inherently 1/2 count for any A/D converter. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 515 Electrical Characteristics A.3 A.3.1 NVM Timing Parameters The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV register. The frequency of this derived clock must be set within the limits specified as fNVMOP. The NVM module does not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. When attempting to program or erase the NVM module at a lower frequency, a full program or erase transition is not assured. The following sections provide equations which can be used to determine the time required to execute specific flash commands. All timing parameters are a function of the bus clock frequency, fNVMBUS. All program and erase times are also a function of the NVM operating frequency, fNVMOP. A summary of key timing parameters can be found in Table A-18. A.3.1.1 Erase Verify All Blocks (Blank Check) (FCMD=0x01) The time required to perform a blank check on all blocks is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming that no non-blank location is found, then the time to erase verify all blocks is given by: 1 t check = 35500 ⋅ -------------------f NVMBUS A.3.1.2 Erase Verify Block (Blank Check) (FCMD=0x02) The time required to perform a blank check is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by: 1 t pcheck = 33500 ⋅ -------------------f NVMBUS Assuming that no non-blank location is found, then the time to erase verify a D-Flash block is given by: 1 t dcheck = 2800 ⋅ -------------------f NVMBUS S12P-Family Reference Manual, Rev. 1.12 516 Freescale Semiconductor Electrical Characteristics A.3.1.3 Erase Verify P-Flash Section (FCMD=0x03) The maximum time to erase verify a section of P-Flash depends on the number of phrases being verified (NVP) and is given by: 1 t ≈ ( 450 + N VP ) ⋅ -------------------f NVMBUS A.3.1.4 Read Once (FCMD=0x04) The maximum read once time is given by: 1 t = 400 ⋅ -------------------f NVMBUS A.3.1.5 Program P-Flash (FCMD=0x06) The programming time for a single phrase of four P-Flash words and the two seven-bit ECC fields is dependent on the bus frequency, fNVMBUS, as well as on the NVM operating frequency, fNVMOP. The typical phrase programming time is given by: 1 1 t ppgm ≈ 164 ⋅ ------------------ + 2000 ⋅ -------------------f NVMBUS f NVMOP The maximum phrase programming time is given by: 1 1 t ppgm ≈ 164 ⋅ ------------------ + 2500 ⋅ -------------------f NVMBUS f NVMOP A.3.1.6 Program Once (FCMD=0x07) The maximum time required to program a P-Flash Program Once field is given by: 1 1 t ≈ 164 ⋅ ------------------ + 2150 ⋅ -------------------f NVMBUS f NVMOP A.3.1.7 Erase All Blocks (FCMD=0x08) The time required to erase all blocks is given by: 1 1 t mass ≈ 100100 ⋅ ------------------ + 70000 ⋅ -------------------f NVMBUS f NVMOP S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 517 Electrical Characteristics A.3.1.8 Erase P-Flash Block (FCMD=0x09) The time required to erase the P-Flash block is given by: 1 1 t pmass ≈ 100100 ⋅ ------------------ + 67000 ⋅ -------------------f NVMBUS f NVMOP A.3.1.9 Erase P-Flash Sector (FCMD=0x0A) The typical time to erase a 512-byte P-Flash sector is given by: 1 1 t pera ≈ 20020 ⋅ ------------------ + 700 ⋅ -------------------f NVMBUS f NVMOP The maximum time to erase a 512-byte P-Flash sector is given by: 1 1 t pera ≈ 20020 ⋅ ------------------ + 1400 ⋅ -------------------f NVMOP f NVMBUS A.3.1.10 Unsecure Flash (FCMD=0x0B) The maximum time required to erase and unsecure the Flash is given by: for 128 Kbyte P-Flash and 4 Kbyte D-Flash 1 1 t uns ≈ 100100 ⋅ ------------------ + 70000 ⋅ -------------------f NVMBUS f NVMOP A.3.1.11 Verify Backdoor Access Key (FCMD=0x0C) The maximum verify backdoor access key time is given by: 1 t = 400 ⋅ -------------------f NVMBUS A.3.1.12 Set User Margin Level (FCMD=0x0D) The maximum set user margin level time is given by: 1 t = 350 ⋅ -------------------f NVMBUS S12P-Family Reference Manual, Rev. 1.12 518 Freescale Semiconductor Electrical Characteristics A.3.1.13 Set Field Margin Level (FCMD=0x0E) The maximum set field margin level time is given by: 1 t = 350 ⋅ -------------------f NVMBUS A.3.1.14 Erase Verify D-Flash Section (FCMD=0x10) The time required to Erase Verify D-Flash for a given number of words NW is given by: 1 t dcheck ≈ ( 450 + N W ) ⋅ -------------------f NVMBUS A.3.1.15 Program D-Flash (FCMD=0x11) D-Flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary since programming across a row boundary requires extra steps. The DFlash programming time is specified for different cases: 1,2,3,4 words and 4 words across a row boundary. The typical D-Flash programming time is given by the following equation, where NW denotes the number of words; BC=0 if no row boundary is crossed and BC=1 if a row boundary is crossed: 1 1 t dpgm ≈ ⎛ ( 14 + ( 54 ⋅ N W ) + ( 14 ⋅ BC ) ) ⋅ ------------------ ⎞ + ⎛ ( 500 + ( 525 ⋅ N W ) + ( 100 ⋅ BC ) ) ⋅ -------------------- ⎞ ⎝ f NVMOP ⎠ ⎝ f NVMBUS ⎠ The maximum D-Flash programming time is given by: 1 1 t dpgm ≈ ⎛ ( 14 + ( 54 ⋅ N W ) + ( 14 ⋅ BC ) ) ⋅ ------------------ ⎞ + ⎛ ( 500 + ( 750 ⋅ N W ) + ( 100 ⋅ BC ) ) ⋅ -------------------- ⎞ ⎝ f NVMOP ⎠ ⎝ f NVMBUS ⎠ A.3.1.16 Erase D-Flash Sector (FCMD=0x12) Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given by: 1 1 t dera ≈ 5025 ⋅ ------------------ + 700 ⋅ -------------------f NVMBUS f NVMOP Maximum D-Flash sector erase times is given by: 1 1 t dera ≈ 20100 ⋅ ------------------ + 3400 ⋅ -------------------f NVMBUS f NVMOP S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 519 Electrical Characteristics The D-Flash sector erase time is ~5ms on a new device and can extend to ~20ms as the flash is cycled. Table A-18. NVM Timing Characteristics (FTMRC) Num C 1 2 3 4 5 6 7 8 9 10 11 12a 12b 12c 12d 12e Bus frequency Operating frequency Rating Symbol fNVMBUS fNVMOP tmass tcheck tuns tpmass tpcheck tpera tppgm tdera tdcheck tdpgm1 tdpgm2 tdpgm3 tdpgm4 Min 1 0.8 — — — — — — — — — — — — — Typ(1) — 1.0 100 — 100 100 — 20 226 5 (4) Max(2) 32 1.05 130 35500 130 130 33500 26 285 26 2800 107 185 262 339 357 Unit(3) MHz MHz ms tcyc ms ms tcyc ms µs ms tcyc µs µs µs µs µs D Erase all blocks (mass erase) time D Erase verify all blocks (blank check) time D Unsecure Flash time D P-Flash block erase time D P-Flash erase verify (blank check) time D P-Flash sector erase time D P-Flash phrase programming time D D-Flash sector erase time D D-Flash erase verify (blank check) time D D-Flash one word programming time D D-Flash two word programming time D D-Flash three word programming time D D-Flash four word programming time — 100 170 241 311 328 — D D-Flash four word programming time crossing row tdpgm4c boundary 1. Typical program and erase times are based on typical fNVMOP and maximum fNVMBUS 2. Maximum program and erase times are based on minimum fNVMOP and maximum fNVMBUS 3. tcyc = 1 / fNVMBUS 4. Typical value for a new device A.3.2 NVM Reliability Parameters The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The data retention and program/erase cycling failure rates are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. S12P-Family Reference Manual, Rev. 1.12 520 Freescale Semiconductor Electrical Characteristics NOTE All values shown in Table A-19 are preliminary and subject to further characterization. Table A-19. NVM Reliability Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Program Flash Arrays 1 2 C Data retention at an average junction temperature of TJavg = 85°C(1) after up to 10,000 program/erase cycles C Program Flash number of program/erase cycles (-40°C ≤ tj ≤ 150°C) Data Flash Array 3 4 5 C Data retention at an average junction temperature of TJavg = 85°C1 after up to 50,000 program/erase cycles C Data retention at an average junction temperature of TJavg = 85°C1 after up to 10,000 program/erase cycles C Data retention at an average junction temperature of TJavg = 85°C1 after less than 100 program/erase cycles tNVMRET tNVMRET tNVMRET 5 10 20 1002 1002 1002 — — — Years Years Years tNVMRET nFLPE 20 10K 100(2) 100K(3) — — Years Cycles Symbol Min Typ Max Unit 6 C Data Flash number of program/erase cycles (-40°C ≤ tj ≤ 150°C) nFLPE 50K 500K3 — Cycles 1. TJavg does not exceed 85°C in a typical temperature profile over the lifetime of a consumer, industrial or automotive application. 2. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618 3. Spec table quotes typical endurance evaluated at 25°C for this product family. For additional information on how Freescale defines Typical Endurance, please refer to Engineering Bulletin EB619. A.4 A.4.1 Phase Locked Loop Jitter Definitions With each transition of the feedback clock, the deviation from the reference clock is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the VCOCLK frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-2. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 521 Electrical Characteristics 0 1 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Figure A-2. Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as: t (N) t (N) ⎞ ⎛ max min J ( N ) = max ⎜ 1 – ---------------------- , 1 – ---------------------- ⎟ N⋅t N⋅t ⎝ nom nom ⎠ For N < 100, the following equation is a good fit for the maximum jitter: j 1 J ( N ) = ------N J(N) 1 5 10 20 N Figure A-3. Maximum Bus Clock Jitter Approximation NOTE On timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent. S12P-Family Reference Manual, Rev. 1.12 522 Freescale Semiconductor Electrical Characteristics A.4.2 Electrical Characteristics for the PLL Table A-20. PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 6 7 Rating Symbol fVCORST fVCO fREF |∆Lock| |∆unl| tlock Min 8 32 1 0 0.5 1.5 2.5 150 + 256/fREF Typ Max 32 64 Unit MHz MHz MHz %(1) %1 µs D VCO frequency during system reset C VCO locking range C Reference Clock D Lock Detection D Un-Lock Detection C Time to lock j1 8 C Jitter fit parameter 1(2) 1.4 % 1. % deviation from target frequency 2. fREF = 4MHz oscillator, fBUS = 32MHz equivalent fPLL = 64MHz, CPMUREFDIV=$40, CPMUSYNR=$47, CPMUPOSTDIV=$00 A.5 Electrical Characteristics for the IRC1M Table A-21. IRC1M Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 Rating Symbol fIRC1M_TRIM Min 0.985 Typ 1 Max 1.015 Unit MHz P Junction Temperature -40°C to 150°C Internal Reference Frequency, factory trimmed S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 523 Electrical Characteristics A.6 Electrical Characteristics for the Oscillator (OSCLCP) Table A-22. OSCLCP Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3a 3b 3c 4 5 6 7 Rating Symbol fOSC iOSC tUPOSC tUPOSC tUPOSC fCMFA CIN VHYS,EXTAL Min 4.0 100 — — — 200 Typ Max 16 Unit MHz µA C Crystal oscillator range P Startup Current C Oscillator start-up time (LCP, 4MHz)(1) C Oscillator start-up time (LCP, 8MHz)1 C Oscillator start-up time (LCP, 16MHz)1 P Clock Monitor Failure Assert Frequency D Input Capacitance (EXTAL, XTAL pins) C EXTAL Pin Input Hysteresis C 2 1.6 1 400 7 10 8 5 1000 ms ms ms KHz pF — 180 — mV EXTAL Pin oscillation amplitude (loop — — VPP,EXTAL 0.9 V controlled Pierce) 1. These values apply for carefully designed PCB layouts with capacitors that match the crystal/resonator requirements. A.7 Reset Characteristics Table A-23. Reset and Stop & Startup Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 Rating Symbol PWRSTL nRST tSTP_REC Min 2 768 50 Typ Max Unit tVCORS T C Reset input pulse width, minimum input time C Startup from Reset C STOP recovery time tVCORS T µs S12P-Family Reference Manual, Rev. 1.12 524 Freescale Semiconductor Electrical Characteristics A.8 Electrical Specification for Voltage Regulator Table A-24. IVREG Characteristics Num 1 2 3 4 5 C P P P T C Characteristic Input Voltages VDDA Low Voltage Interrupt Assert Level (1) VDDA Low Voltage Interrupt Deassert Level VDDX Low Voltage Reset Deassert (2) (3) API ACLK frequency (APITR[5:0] = %000000) Trimmed API internal clock(4) ∆f / fnominal The first period after enabling the counter by APIFE might be reduced by API start up delay Temperature Sensor Slope Symbol VVDDR,A VLVIA VLVID VLVRXD fACLK dfACLK tsdel Min 3.13 4.04 4.19 — — - 5% Typical — 4.23 4.38 — 10 — Max 5.5 4.40 4.49 3.13 — + 5% Unit V V V V KHz — 6 D — — 100 us mV/ oC 7 T dVTS 4.0 5.5 6.5 High Temperature Interrupt Assert THTIA 125 oC (CPMUHTTR=$88)(5) 105 8 T THTID High Temperature Interrupt Deassert (CPMUHTTR=$88) 1. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply voltage. 2. Device functionality is guaranteed on power down to the LVR assert level 3. Monitors VDDX, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure A-4) 4. The API Trimming APITR[5:0] bits must be set so that fACLK=10KHz. 5. A hysteresis is guaranteed by design NOTE The LVR monitors the voltages VDD, VDDF and VDDX. As soon as voltage drops on these supplies which would prohibit the correct function of the microcontroller, the LVR is triggering a reset. A.9 Chip Power-up and Voltage Drops LVI (low voltage interrupt), POR (power-on reset) and LVRs (low voltage reset) handle chip power-up or drops of the supply voltage. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 525 Electrical Characteristics Figure A-4. MC9S12P-Family - Chip Power-up and Voltage Drops (not scaled) V VLVID VLVIA VLVRD VLVRA VDDA/VDDX VDD VPORD t LVI LVI enabled POR LVI disabled due to LVR LVR S12P-Family Reference Manual, Rev. 1.12 526 Freescale Semiconductor Electrical Characteristics A.10 MSCAN Table A-25. MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol tWUP tWUP Min — 5 Typ — — Max 1.5 — Unit µs µs P MSCAN wakeup dominant pulse filtered P MSCAN wakeup dominant pulse pass A.11 SPI Timing This section provides electrical parametrics and ratings for the SPI. In Table A-26 the measurement conditions are listed. Table A-26. Measurement Conditions Description Drive mode Load capacitance CLOAD(1), on all outputs Thresholds for delay measurement points 1. Timing specified for equal load on all SPI output pins. Avoid asymmetric load. Value Full drive mode 50 (20% / 80%) VDDX Unit — pF V A.11.1 Master Mode In Figure A-5 the timing diagram for master mode with transmission format CPHA = 0 is depicted. SS (Output) 2 SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 5 MISO (Input) 6 Bit MSB-1. . . 1 9 Bit MSB-1. . . 1 LSB OUT LSB IN 11 1 4 4 12 13 12 13 3 MSB IN2 10 MOSI (Output) MSB OUT2 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB. Figure A-5. SPI Master Timing (CPHA = 0) S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 527 Electrical Characteristics In Figure A-6 the timing diagram for master mode with transmission format CPHA=1 is depicted. SS (Output) 1 2 SCK (CPOL = 0) (Output) 4 SCK (CPOL = 1) (Output) 5 MISO (Input) 9 MOSI (Output) Port Data Master MSB OUT2 6 Bit MSB-1. . . 1 11 Bit MSB-1. . . 1 Master LSB OUT Port Data LSB IN MSB IN2 4 12 13 12 13 3 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB. Figure A-6. SPI Master Timing (CPHA = 1) S12P-Family Reference Manual, Rev. 1.12 528 Freescale Semiconductor Electrical Characteristics In Table A-27 the timing characteristics for master mode are listed. Table A-27. SPI Master Mode Timing Characteristics Num 1 1 2 3 4 5 6 9 10 11 12 13 C D D D D D D D D D D D D SCK period Enable lead time Enable lag time Clock (SCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid after SCK edge Data valid after SS fall (CPHA = 0) Data hold time (outputs) Rise and fall time inputs Rise and fall time outputs Characteristic SCK frequency Symbol fsck tsck tlead tlag twsck tsu thi tvsck tvss tho trfi trfo Min 1/2048 2 — — — 8 8 — — 20 — — Typ — — 1/2 1/2 1/2 — — — — — — — Max 1/2 2048 — — — — — 29 15 — 8 8 Unit fbus tbus tsck tsck tsck ns ns ns ns ns ns ns A.11.2 Slave Mode In Figure A-7 the timing diagram for slave mode with transmission format CPHA = 0 is depicted. SS (Input) 1 SCK (CPOL = 0) (Input) 2 SCK (CPOL = 1) (Input) 10 7 MISO (Output) See Note 5 MOSI (Input) NOTE: Not defined MSB IN Slave MSB 6 Bit MSB-1. . . 1 LSB IN 9 Bit MSB-1 . . . 1 4 4 12 13 8 11 11 See Note 12 13 3 Slave LSB OUT Figure A-7. SPI Slave Timing (CPHA = 0) S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 529 Electrical Characteristics In Figure A-8 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. SS (Input) 1 2 SCK (CPOL = 0) (Input) 4 SCK (CPOL = 1) (Input) 9 MISO (Output) See Note 7 MOSI (Input) NOTE: Not defined Slave 5 MSB OUT 6 MSB IN Bit MSB-1 . . . 1 LSB IN 4 12 13 12 13 3 11 Bit MSB-1 . . . 1 Slave LSB OUT 8 Figure A-8. SPI Slave Timing (CPHA = 1) In Table A-28 the timing characteristics for slave mode are listed. Table A-28. SPI Slave Mode Timing Characteristics Num 1 1 2 3 4 5 6 7 8 9 10 11 12 C D D D D D D D D D D D D D Characteristic SCK frequency SCK period Enable lead time Enable lag time Clock (SCK) high or low time Data setup time (inputs) Data hold time (inputs) Slave access time (time to data active) Slave MISO disable time Data valid after SCK edge Data valid after SS fall Data hold time (outputs) Rise and fall time inputs Symbol fsck tsck tlead tlag twsck tsu thi ta tdis tvsck tvss tho trfi trfo Min DC 4 4 4 4 8 8 — — — — 20 — — Typ — — — — — — — — — — — — — — Max 1/4 ∞ — — — — — 20 22 29 + 0.5 ⋅ tbus(1) tbus1 Unit fbus tbus tbus tbus tbus ns ns ns ns ns ns ns ns ns 29 + 0.5 ⋅ — 8 8 13 D Rise and fall time outputs 1. 0.5 tbus added due to internal synchronization delay S12P-Family Reference Manual, Rev. 1.12 530 Freescale Semiconductor Ordering Information Appendix B Ordering Information The following figure provides an ordering partnumber example for the devices covered by this data book. There are two options when ordering a device. Customers must choose between ordering either the maskspecific partnumber or the generic / mask-independent partnumber. Ordering the mask-specific partnumber enables the customer to specify which particular maskset they will receive whereas ordering the generic maskset means that FSL will ship the currently preferred maskset (which may change over time). In either case, the marking on the device will always show the generic / mask-independent partnumber and the mask set number. NOTE The mask identifier suffix and the Tape & Reel suffix are always both omitted from the partnumber which is actually marked on the device. For specific partnumbers to order, please contact your local sales office. The below figure illustrates the structure of a typical mask-specific ordering number for the MC9S12P-Family devices S 9 S12 P128 J0 M FT R Tape & Reel: R = Tape & Reel No R = No Tape & Reel Package Option: FT = 48 QFN LH = 64 LQFP QK = 80 QFP Temperature Option: C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C Maskset identifier Suffix: First digit usually references wafer fab Second digit usually differentiates mask rev (This suffix is omitted in generic partnumbers) Device Title Controller Family Main Memory Type: 9 = Flash 3 = ROM (if available) Status / Partnumber type: S or SC = Maskset specific partnumber MC = Generic / mask-independent partnumber P or PC = prototype status (pre qualification) S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 531 Ordering Information S12P-Family Reference Manual, Rev. 1.12 532 Freescale Semiconductor Package Information Appendix C Package Information This section provides the physical dimensions of the MC9S12P-Family packages. NOTE The exposed pad of the 48 QFN package should be attached to Vss ground plane. S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 533 Package Information C.1 80 QFP Package Mechanical Outline S12P-Family Reference Manual, Rev. 1.12 534 Freescale Semiconductor Package Information S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 535 Package Information S12P-Family Reference Manual, Rev. 1.12 536 Freescale Semiconductor Package Information C.2 48 QFN Package Mechanical Outline S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 537 Package Information S12P-Family Reference Manual, Rev. 1.12 538 Freescale Semiconductor Package Information S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 539 Package Information C.3 64 LQFP Package Mechanical Outline S12P-Family Reference Manual, Rev. 1.12 540 Freescale Semiconductor Package Information S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 541 Package Information S12P-Family Reference Manual, Rev. 1.12 542 Freescale Semiconductor Detailed Register Address Map Appendix D Detailed Register Address Map D.1 Detailed Register Map The following tables show the detailed register map of the MC9S12P-Family. 0x0000-0x0009 Port Integration Module (PIM) Map 1 of 4 Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE R W R W R W R W R W R W R W R W R W R W Bit 7 PA7 PB7 DDRA7 DDRB7 0 0 0 0 Bit 6 PA6 PB6 DDRA6 DDRB6 0 0 0 0 Bit 5 PA5 PB5 DDRA5 DDRB5 0 0 0 0 Bit 4 PA4 PB4 DDRA4 DDRB4 0 0 0 0 Bit 3 PA3 PB3 DDRA3 DDRB3 0 0 0 0 Bit 2 PA2 PB2 DDRA2 DDRB2 0 0 0 0 Bit 1 PA1 PB1 DDRA1 DDRB1 0 0 0 0 PE1 0 Bit 0 PA0 PB0 DDRA0 DDRB0 0 0 0 0 PE0 0 PE7 DDRE7 PE6 DDRE6 PE5 DDRE5 PE4 DDRE4 PE3 DDRE3 PE2 DDRE2 0x000A-0x000B Module Mapping Conrol (MMC) Map 1 of 2 Address 0x000A 0x000B Name Reserved MODE R W R W Bit 7 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 MODC S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 543 Detailed Register Address Map 0x000C-0x000D Port Integration Module (PIM) Map 2 of 4 Address 0x000C 0x000D Name PUCR RDRIV R W R W Bit 7 0 0 Bit 6 BKPUE 0 Bit 5 0 0 Bit 4 PUPEE RDPE Bit 3 0 0 Bit 2 0 0 Bit 1 PUPBE RDPB Bit 0 PUPAE RDPA 0x000E-0x000F Reserved Address 0x000E 0x000F Name Reserved Reserved R W R W Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 0x0010-0x0017 Module Mapping Control (MMC) Map 2 of 2 Address 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 Name Reserved DIRECT Reserved Reserved Reserved PPAGE Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 DP15 0 0 0 DP14 0 0 0 DP13 0 0 0 DP12 0 0 0 DP11 0 0 0 DP10 0 0 0 DP9 0 0 0 DP8 0 0 0 PIX7 0 0 PIX6 0 0 PIX5 0 0 PIX4 0 0 PIX3 0 0 PIX2 0 0 PIX1 0 0 PIX0 0 0 0x0018-0x0019 Reserved Address 0x0018 0x0019 Name Reserved Reserved R W R W Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 S12P-Family Reference Manual, Rev. 1.12 544 Freescale Semiconductor Detailed Register Address Map 0x001A-0x001B Part ID Registers Address 0x001A 0x001B Name PARTIDH PARTIDL R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PARTIDH PARTIDL 0x001C-0x001F Port Intergartion Module (PIM) Map 3 of 4 Address 0x001C 0x001D Name ECLKCTL Reserved R W R W R W R W Bit 7 NECLK 0 Bit 6 NCLKX2 0 Bit 5 DIV16 0 0 0 Bit 4 EDIV4 0 0 0 Bit 3 EDIV3 0 0 0 Bit 2 EDIV2 0 0 0 Bit 1 EDIV1 0 0 0 Bit 0 EDIV0 0 0 0 0x001E 0x001F IRQCR Reserved IRQE 0 IRQEN 0 0x0020-0x002F Debug Module (S12SDBG) Map Address 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0027 0x0028 (1) Name DBGC1 DBGSR DBGTCR DBGC2 DBGTBH DBGTBL DBGCNT DBGSCRX DBGMFR DBGACTL DBGBCTL R W R W R W R W R W R W R W R W R W R W R W Bit 7 ARM TBF 0 0 Bit 15 Bit 7 TBF 0 0 Bit 6 0 TRIG 0 Bit 5 0 0 0 0 Bit 13 Bit 5 Bit 4 BDM 0 0 0 Bit 12 Bit 4 Bit 3 DBGBRK 0 Bit 2 0 SSF2 Bit 1 Bit 0 COMRV SSF1 0 SSF0 TSOURCE 0 Bit 14 Bit 6 0 0 0 TRCMOD 0 Bit 11 Bit 3 CNT 0 Bit 10 Bit 2 TALIGN ABCM Bit 9 Bit 1 Bit 8 Bit 0 0 0 0 0 SC3 0 SC2 MC2 SC1 MC1 0 0 SC0 MC0 SZE SZE SZ SZ TAG TAG BRK BRK RW RW RWE RWE COMPE COMPE 0x0028 (2) S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 545 Detailed Register Address Map 0x0020-0x002F Debug Module (S12SDBG) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 Bit 0 COMPE Bit 16 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 R 0 0 0x0028 DBGCCTL TAG BRK RW RWE (3) W R 0 0 0 0 0 0 0x0029 DBGXAH W R 0x002A DBGXAM Bit 15 14 13 12 11 10 W R 0x002B DBGXAL Bit 7 6 5 4 3 2 W R 0x002C DBGADH Bit 15 14 13 12 11 10 W R 0x002D DBGADL Bit 7 6 5 4 3 2 W R 0x002E DBGADHM Bit 15 14 13 12 11 10 W R 0x002F DBGADLM Bit 7 6 5 4 3 2 W 1. This represents the contents if the Comparator A or C control register is blended into this address 2. This represents the contents if the Comparator B or D control register is blended into this address 3. This represents the contents if the Comparator B or D control register is blended into this address 17 9 1 9 1 9 1 0x0030-0x0033 Reserved Address 0x0030 0x0031 0x0032 0x0033 Name Reserved Reserved Reserved Reserved R W R W R W R W Bit 7 0 0 0 0 Bit 6 0 0 0 0 Bit 5 0 0 0 0 Bit 4 0 0 0 0 Bit 3 0 0 0 0 Bit 2 0 0 0 0 Bit 1 0 0 0 0 Bit 0 0 0 0 0 0x0034-0x003F Clock Reset and Power Management (CPMU) Map Address 0x0034 Name CPMUSYNR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W R 0x0035 CPMUREFDIV W CPMUPOSTDI R 0x0036 V W R 0x0037 CPMUFLG W VCOFRQ[1:0] REFFRQ[1:0] 0 0 0 0 0 SYNDIV[5:0] REFDIV[3:0] POSTDIV[4:0] LOCKIF LOCK ILAF OSCIF UPOSC RTIF PORF LVRF S12P-Family Reference Manual, Rev. 1.12 546 Freescale Semiconductor Detailed Register Address Map 0x0034-0x003F Clock Reset and Power Management (CPMU) Map Address 0x0038 0x0039 0x003A 0x003B Name CPMUINT CPMUCLKS CPMUPLL CPMURTI Bit 7 R RTIE W R PLLSEL W R 0 W R W R W R W R W R W RTDEC Bit 6 0 Bit 5 0 0 Bit 4 LOCKIE 0 Bit 3 0 Bit 2 0 Bit 1 OSCIE RTIOSCS EL 0 Bit 0 0 COPOSC SEL 0 PSTP 0 PRE 0 PCE 0 FM1 RTR5 0 WRTMAS K 0 0 0 5 FM0 RTR4 0 RTR6 RTR3 0 RTR2 RTR1 RTR0 0x003C CPMUCOP WCOP 0 0 0 Bit 7 RSBCK 0 0 0 6 CR2 0 0 Reserved For Factory Test 0 Reserved For Factory Test 0 0 4 3 0 0 0 2 CR1 0 0 0 1 CR0 0 0 0 Bit 0 0x003D 0x003E 0x003F Reserved Reserved CPMU ARMCOP 0x0040-0x006F Timer Module (TIM) Map Address 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B Name TIOS CFORC OC7M OC7D TCNTH TCNTL TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 IOS7 0 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 0 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 0 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0 TEN TOV7 OM7 OM3 EDG7B EDG3B TSWAI TOV6 OL7 OL3 EDG7A EDG3A TSFRZ TOV5 OM6 OM2 EDG6B EDG2B TFFCA TOV4 OL6 OL2 EDG6A EDG2A PRNT TOV3 OM5 OM1 EDG5B EDG1B TOV2 OL5 OL1 EDG5A EDG1A TOV1 OM4 OM0 EDG4B EDG0B TOV0 OL4 OL0 EDG4A EDG0A S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 547 Detailed Register Address Map 0x0040-0x006F Timer Module (TIM) Map Address 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F 0x0060 0x0061 0x0062 Name TIE TSCR2 TFLG1 TFLG2 TC0H TC0L TC1H TC1L TC2H TC2L TC3H TC3L TC4H TC4L TC5H TC5L TC6H TC6L TC7H TC7L PACTL PAFLG PACNTH Bit 7 R C7I W R TOI W R C7F W R TOF W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R 0 W R 0 W R PACNT15 W Bit 6 C6I 0 Bit 5 C5I 0 Bit 4 C4I 0 Bit 3 C3I TCRE C3F 0 Bit 2 C2I PR2 C2F 0 Bit 1 C1I PR1 C1F 0 Bit 0 C0I PR0 C0F 0 C6F 0 C5F 0 C4F 0 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 PAEN 0 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 PAMOD 0 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 PEDGE 0 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CLK1 0 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 CLK0 0 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 PAOVI PAOVF PACNT9 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF PACNT8 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 S12P-Family Reference Manual, Rev. 1.12 548 Freescale Semiconductor Detailed Register Address Map 0x0040-0x006F Timer Module (TIM) Map Address 0x0063 0x0064– 0x006B 0x006C 0x006D 0x006E 0x006F Name PACNTL Reserved OCPD Reserved PTPSR Reserved Bit 7 R PACNT7 W R 0 W R OCPD7 W R W R PTPS7 W R 0 W Bit 6 PACNT6 0 Bit 5 PACNT5 0 Bit 4 PACNT4 0 Bit 3 PACNT3 0 Bit 2 PACNT2 0 Bit 1 PACNT1 0 Bit 0 PACNT0 0 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 PTPS6 0 PTPS5 0 PTPS4 0 PTPS3 0 PTPS2 0 PTPS1 0 PTPS0 0 0x0070-0x009F Analog to Digital Converter 12-Bit 10-Channel (ATD) Map Address 0x0070 0x0071 0x0072 0x0073 0x0074 0x0075 0x0076 0x0077 0x0078 0x0079 0x007A 0x007B 0x007C 0x007D Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Reserved ATDCMPEH ATDCMPEL ATDSTAT2H ATDSTAT2L ATDDIENH ATDDIENL R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 ETRIG SEL 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 WRAP3 ETRIG CH3 ETRIGP S1C PRS3 CD CC3 0 0 Bit 2 WRAP2 ETRIG CH2 ETRIGE FIFO PRS2 CC CC2 0 0 Bit 1 WRAP1 ETRIG CH1 ASCIE FRZ1 PRS1 CB CC1 0 Bit 0 WRAP0 ETRIG CH0 ACMPIE FRZ0 PRS0 CA CC0 0 SRES1 AFFC S8C SMP1 SC 0 0 0 SRES0 ICLKSTP S4C SMP0 SCAN ETORF 0 0 SMP_DIS ETRIGLE S2C PRS4 MULT FIFOR 0 0 DJM SMP2 0 SCF 0 0 CMPE[9:8] CMPE[7:0] CCF[9:8] CCF[7:0] 0 0 0 0 0 0 IEN[9:8] IEN[7:0] S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 549 Detailed Register Address Map 0x0070-0x009F Analog to Digital Converter 12-Bit 10-Channel (ATD) Map Address 0x007E 0x007F 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x090 0x091 0x092 0x093 0x094 Name R ATDCMPHTH W R ATDCMPHTL W R ATDDR0H W R ATDDR0L W R ATDDR1H W R ATDDR1L W R ATDDR2H W R ATDDR2L W R ATDDR3H W R ATDDR3L W R ATDDR4H W R ATDDR4L W R ATDDR5H W R ATDDR5L W R ATDDR6H W R ATDDR6L W R ATDDR7H W R ATDDR7L W R ATDDR8H W R ATDDR8L W R ATDDR9H W R ATDDR9L W R ATDDR10H W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 CMPHT[9:8] CMPHT[7:0] Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 S12P-Family Reference Manual, Rev. 1.12 550 Freescale Semiconductor Detailed Register Address Map 0x0070-0x009F Analog to Digital Converter 12-Bit 10-Channel (ATD) Map Address 0x095 0x096 0x097 0x098 0x099 0x09A 0x09B 0x09C 0x09D 0x09E 0x009F Name ATDDR10L ATDDR11H ATDDR11L ATDDR12H ATDDR12L ATDDR13H ATDDR13L ATDDR14H ATDDR14L ATDDR15H ATDDR15L R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 0 13 0 13 0 13 0 13 0 13 0 Bit 4 0 12 0 12 0 12 0 12 0 12 0 Bit 3 0 11 0 11 0 11 0 11 0 11 0 Bit 2 0 10 0 10 0 10 0 10 0 10 0 Bit 1 0 9 0 9 0 9 0 9 0 9 0 Bit 0 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 0x00A0-0x00C7 Pulse Width Modulator 6-Channels (PWM) Map Address 0x00A0 0x00A1 0x00A2 0x00A3 0x00A4 0x00A5 0x00A6 0x00A7 0x00A8 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC PWMSCLA R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 Bit 7 0 Bit 6 0 0 0 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 Bit 3 PWME3 PPOL3 PCLK3 0 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 PCKB2 0 CAE3 PSWAI 0 0 CON45 0 0 Bit 7 6 5 4 3 2 1 Bit 0 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 551 Detailed Register Address Map 0x00A0-0x00C7 Pulse Width Modulator 6-Channels (PWM) Map Address 0x00A9 0x00AA 0x00AB 0x00AC 0x00AD 0x00AE 0x00AF 0x00B0 0x00B1 0x00B2 0x00B3 0x00B4 0x00B5 0x00B6 0x00B7 0x00B8 0x00B9 0x00BA 0x00BB 0x00BC 0x00BD 0x00BE 0x00BF0x00C7 Name R PWMSCLB W R PWMSCNTA W R PWMSCNTB W R PWMCNT0 W R PWMCNT1 W R PWMCNT2 W R PWMCNT3 W R PWMCNT4 W R PWMCNT5 W R PWMPER0 W R PWMPER1 W R PWMPER2 W R PWMPER3 W R PWMPER4 W R PWMPER5 W R PWMDTY0 W R PWMDTY1 W R PWMDTY2 W R PWMDTY3 W R PWMDTY4 W R PWMDTY5 W R PWMSDN W R Reserved W Bit 7 Bit 7 0 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 PWMIF 0 Bit 6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 6 6 6 6 6 6 6 PWMIE 0 Bit 5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 0 0 Bit 2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 2 2 2 2 2 2 2 PWM5IN 0 Bit 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 PWM5INL 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 PWM5 ENA 0 0 PWMLVL PWRSTRT 0 0 S12P-Family Reference Manual, Rev. 1.12 552 Freescale Semiconductor Detailed Register Address Map 0x00C8-0x00CF Serial Communication Interface (SCI) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE BERRM0 RWU FE Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF RAF 0 R0 T0 R 0x00C8 SCIBDH(1) IREN TNP1 TNP0 SBR12 SBR11 W R SBR7 SBR6 SBR5 SBR4 SBR3 0x00C9 SCIBDL1 W R LOOPS SCISWAI RSRC M WAKE 0x00CA SCICR11 W R 0 0 0 0 RXEDGIF 0x00C8 SCIASR1(2) W R 0 0 0 0 RXEDGIE 0x00C9 SCIACR12 W R 0 0 0 0 0 0x00CA SCIACR22 W R 0x00CB SCICR2 TIE TCIE RIE ILIE TE W R TDRE TC RDRF IDLE OR 0x00CC SCISR1 W R 0 0 0x00CD SCISR2 AMAP TXPOL RXPOL W R R8 0 0 0 0x00CE SCIDRH T8 W R R7 R6 R5 R4 R3 0x00CF SCIDRL W T7 T6 T5 T4 T3 1. Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero 2. Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one BERRM1 RE NF BRK13 0 R2 T2 TXDIR 0 R1 T1 0x00D0-0x00D7 Reserved Address 0x00D00x00D7 Name Reseved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x00D8-0x00DF Serial Peripheral Interface (SPI) Map Address 0x00D8 0x00D9 0x00DA 0x00DB Name SPICR1 SPICR2 SPIBR SPISR R W R W R W R W Bit 7 SPIE 0 0 SPIF Bit 6 SPE XFRW SPPR2 0 Bit 5 SPTIE 0 Bit 4 MSTR MODFEN SPPR0 MODF Bit 3 CPOL BIDIROE 0 0 Bit 2 CPHA 0 Bit 1 SSOE SPISWAI SPR1 0 Bit 0 LSBFE SPC0 SPR0 0 SPPR1 SPTEF SPR2 0 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 553 Detailed Register Address Map 0x00D8-0x00DF Serial Peripheral Interface (SPI) Map Address 0x00DC 0x00DD 0x00DE 0x00DF Name SPIDRH SPI0DRL Reserved Reserved R W R W R W R W Bit 7 R15 T15 R7 T7 0 0 Bit 6 R14 T14 R6 T6 0 0 Bit 5 R13 T13 R5 T5 0 0 Bit 4 R12 T12 R4 T4 0 0 Bit 3 R11 T11 R3 T3 0 0 Bit 2 R10 T10 R2 T2 0 0 Bit 1 R9 T9 R1 T1 0 0 Bit 0 R8 T8 R0 T0 0 0 0x00E0-0x00FF Reserved Address 0x00E00x00FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0100-0x0113 NVM Contol Register (FTMRC) Map Address 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010A 0x010B 0x010C Name FCLKDIV FSEC FCCOBIX FRSV0 FCNFG FERCNFG FSTAT FERSTAT FPROT DFPROT FCCOBHI FCCOBLO FRSV1 R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 FDIVLD KEYEN1 0 0 Bit 6 FDIV6 KEYEN0 0 0 0 0 0 0 RNV6 0 Bit 5 FDIV5 RNV5 0 0 0 0 Bit 4 FDIV4 RNV4 0 0 Bit 3 FDIV3 RNV3 0 0 0 0 MGBUSY 0 Bit 2 FDIV2 RNV2 Bit 1 FDIV1 SEC1 Bit 0 FDIV0 SEC0 CCOBIX2 0 0 0 RSVD 0 CCOBIX1 0 CCOBIX0 0 CCIE 0 IGNSF 0 FDFD DFDIE FSFD SFDIE CCIF 0 ACCERR 0 FPVIOL 0 MGSTAT1 MGSTAT0 DFDIF FPLS1 DPS1 CCOB9 CCOB1 0 SFDIF FPLS0 DPS0 CCOB8 CCOB0 0 FPOPEN DPOPEN CCOB15 CCOB7 0 FPHDIS 0 FPHS1 0 FPHS0 DPS3 CCOB11 CCOB3 0 FPLDIS DPS2 CCOB10 CCOB2 0 CCOB14 CCOB6 0 CCOB13 CCOB5 0 CCOB12 CCOB4 0 S12P-Family Reference Manual, Rev. 1.12 554 Freescale Semiconductor Detailed Register Address Map 0x0100-0x0113 NVM Contol Register (FTMRC) Map Address 0x010D 0x010E 0x010F 0x0110 0x0111 0x0112 0x0113 Name FRSV2 FRSC3 FRSV4 FOPT FRSV5 FRSV6 FRSV7 R W R W R W R W R W R W R W Bit 7 0 0 0 NV7 0 0 0 Bit 6 0 0 0 NV6 0 0 0 Bit 5 0 0 0 NV5 0 0 0 Bit 4 0 0 0 NV4 0 0 0 Bit 3 0 0 0 NV3 0 0 0 Bit 2 0 0 0 NV2 0 0 0 Bit 1 0 0 0 NV1 0 0 0 Bit 0 0 0 0 NV0 0 0 0 0x0114-0x011F Reserved Address 0x01140x011F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0120 Interrupt Vector Base Register Address 0x0120 Name IVBR R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IVB_ADDR[7:0] 0x0121-0x013F Reserved Address 0x01140x011F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0140-0x017F MSCAN Map Address 0x0140 0x0141 0x0142 Name CAN0CTL0 CAN0CTL1 CAN0BTR0 Bit 7 R RXFRM W R CANE W R SJW1 W Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 Bit 4 SYNCH Bit 3 TIME BORM BRP3 Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK CLKSRC SJW0 LISTEN BRP4 BRP1 BRP0 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 555 Detailed Register Address Map 0x0140-0x017F MSCAN Map Address 0x0143 0x0144 0x0145 0x0146 0x0147 0x0148 0x0149 0x014A 0x014B 0x014C 0x014D 0x014E 0x014F 0x01500x0153 Name CAN0BTR1 CAN0RFLG CAN0RIER CAN0TFLG CAN0TIER CAN0TARQ CAN0TAAK CAN0TBSEL CAN0IDAC Reserved CAN0MISC CAN0RXERR CAN0TXERR CAN0IDAR0CAN0IDAR3 Bit 7 R SAMP W R WUPIF W R WUPIE W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R RXERR7 W R TXERR7 W R AC7 W R AM7 W R AC7 W R AM7 W R W R W Bit 6 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0 0 RXERR6 TXERR6 Bit 5 TSEG21 RSTAT1 Bit 4 TSEG20 RSTAT0 Bit 3 TSEG13 TSTAT1 Bit 2 TSEG12 TSTAT0 Bit 1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 Bit 0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0 RSTATE1 0 0 0 0 0 RSTATE0 0 0 0 0 0 TSTATE1 0 0 0 0 0 0 0 0 RXERR3 TXERR3 TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2 TX2 IDHIT2 0 0 RXERR2 TXERR2 TX1 IDHIT1 0 0 RXERR1 TXERR1 TX0 IDHIT0 0 IDAM1 0 0 RXERR5 TXERR5 IDAM0 0 0 RXERR4 TXERR4 BOHOLD RXERR0 TXERR0 AC6 AM6 AC6 AM6 AC5 AM5 AC5 AM5 AC4 AM4 AC4 AM4 AC3 AM3 AC3 AM3 AC2 AM2 AC2 AM2 AC1 AM1 AC1 AM1 AC0 AM0 AC0 AM0 0x0154- CAN0IDMR00x0157 CAN0IDMR3 0x01580x015B CAN0IDAR4CAN0IDAR7 0x015C- CAN0IDMR40x015F CAN0IDMR7 0x01600x016F 0x01700x017F CAN0RXFG FOREGROUND RECEIVE BUFFER (SeeTable ) FOREGROUND TRANSMIT BUFFER (SeeTable ) CAN0TXFG S12P-Family Reference Manual, Rev. 1.12 556 Freescale Semiconductor Detailed Register Address Map MSCAN Foreground Receive and Transmit Buffer Layout Address 0xXXX0 Name Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 R R W R R W R R W R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15 0xXXX1 ID9 ID8 ID7 0xXXX2 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR 0xXXX3 0xXXX4- CANxRDSR00xXXXB CANxRDSR7 0xXXXC 0xXXXD CANRxDLR Reserved DB7 DB6 DB5 DB4 DB3 DLC3 DB2 DLC2 DB1 DLC1 DB0 DLC0 0xXXXE CANxRTSRH 0xXXXF CANxRTSRL Extended ID CANxTIDR0 Standard ID Extended ID CANxTIDR1 Standard ID Extended ID CANxTIDR2 Standard ID Extended ID CANxTIDR3 Standard ID TSR15 TSR7 TSR14 TSR6 TSR13 TSR5 TSR12 TSR4 TSR11 TSR3 TSR10 TSR2 TSR9 TSR1 TSR8 TSR0 ID28 ID10 ID20 ID2 ID14 ID27 ID9 ID19 ID1 ID13 ID26 ID8 ID18 ID0 ID12 ID25 ID7 SRR=1 RTR ID11 ID24 ID6 IDE=1 IDE=0 ID10 ID23 ID5 ID17 ID22 ID4 ID16 ID21 ID3 ID15 0xXX10 0xXX0x XX10 ID9 ID8 ID7 0xXX12 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR 0xXX13 0xXX14- CANxTDSR0– 0xXX1B CANxTDSR7 0xXX1C 0xXX1D CANxTDLR CANxTTBPR DB7 DB6 DB5 DB4 DB3 DLC3 DB2 DLC2 PRIO2 DB1 DLC1 PRIO1 DB0 DLC0 PRIO0 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 557 Detailed Register Address Map MSCAN Foreground Receive and Transmit Buffer Layout Address 0xXX1E 0xXX1F Name R CANxTTSRH W R CANxTTSRL W Bit 7 TSR15 TSR7 Bit 6 TSR14 TSR6 Bit 5 TSR13 TSR5 Bit 4 TSR12 TSR4 Bit 3 TSR11 TSR3 Bit 2 TSR10 TSR2 Bit 1 TSR9 TSR1 Bit 0 TSR8 TSR0 0x0180-023F Reserved Address 0x01800x023F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4 Address 0x0240 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 0x0247 Name PTT PTIT DDRT RDRT PERT PPST Reserved PTTRR Bit 7 R PTT7 W R PTIT7 W R DDRT7 W R RDRT7 W R PERT7 W R PPST7 W R 0 W R PTTRR7 W Bit 6 PTT6 PTIT6 Bit 5 PTT5 PTIT5 Bit 4 PTT4 PTIT4 Bit 3 PTT3 PTIT3 Bit 2 PTT2 PTIT2 Bit 1 PTT1 PTIT1 Bit 0 PTT0 PTIT0 DDRT6 RDRT6 PERT6 PPST6 0 DDRT5 RDRT5 PERT5 PPST5 0 DDRT4 RDRT4 PERT4 PPST4 0 DDRT3 RDRT3 PERT3 PPST3 0 0 DDRT2 RDRT2 PERT2 PPST2 0 DDRT1 RDRT1 PERT1 PPST1 0 DDRT0 RDRT0 PERT0 PPST0 0 PTTRR6 PTTRR5 PTTRR4 PTTRR2 PTTRR1 PTTRR0 S12P-Family Reference Manual, Rev. 1.12 558 Freescale Semiconductor Detailed Register Address Map 0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4 Address 0x0248 0x0249 0x024A 0x024B 0x024C 0x024D 0x024E 0x024F 0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C 0x025D 0x025E 0x025F Name PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM WOMM MODRR PTP PTIP DDRP RDRP PERP PPSP PIEP PIFP R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 PTS7 PTIS7 Bit 6 PTS6 PTIS6 Bit 5 PTS5 PTIS5 Bit 4 PTS4 PTIS4 Bit 3 PTS3 PTIS3 Bit 2 PTS2 PTIS2 Bit 1 PTS1 PTIS1 Bit 0 PTS0 PTIS0 DDRS7 RDRS7 PERS7 PPSS7 WOMS7 0 DDRS6 RDRS6 PERS6 PPSS6 WOMS6 0 DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0 DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM7 PTIM7 PTM6 PTIM6 PTM5 PTIM5 PTM4 PTIM4 PTM3 PTIM3 PTM2 PTIM2 PTM1 PTIM1 PTM0 PTIM0 DDRM7 RDRM7 PERM7 PPSM7 WOMM7 MODRR7 PTP7 PTIP7 DDRM6 RDRM6 PERM6 PPSM6 WOMM6 MODRR6 PTP6 PTIP6 DDRM5 RDRM5 PERM5 PPSM5 WOMM5 0 DDRM4 RDRM4 PERM4 PPSM4 WOMM4 MODRR4 PTP4 PTIP4 DDRM3 RDRM3 PERM3 PPSM3 WOMM3 0 DDRM2 RDRM2 PERM2 PPSM2 WOMM2 0 DDRM1 RDRM1 PERM1 PPSM1 WOMM1 0 DDRM0 RDRM0 PERM0 PPSM0 WOMM0 0 PTP5 PTIP5 PTP3 PTIP3 PTP2 PTIP2 PTP1 PTIP1 PTP0 PTIP0 DDRP7 RDRP7 PERP7 PPSP7 PIEP7 PIFP7 DDRP6 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 559 Detailed Register Address Map 0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4 Address 0x0260 0x0261 0x0262 0x0263 0x0264 0x0265 0x0266 0x0267 0x0268 0x0269 0x026A 0x026B 0x026C 0x026D 0x026E 0x026f 0x0270 0x0271 0x0272 0x0273 0x0274 0x0275 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ PT0AD0 PT1AD0 DDR0AD0 DDR1AD0 RDR0AD0 RDR1AD0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 0 0 0 0 0 0 0 Bit 6 0 00 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PT0AD0 5 PT1AD0 5 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PT0AD0 4 PT1AD0 4 Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PT0AD0 3 PT1AD0 3 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0 PTJ7 PTIJ7 PTJ6 PTIJ6 PTJ2 PTIJ12 PTJ1 PTIJ1 PTJ0 PTIJ0 DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7 PT0AD0 7 PT1AD0 7 DDRJ6 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6 PT0AD0 6 PT1AD0 6 DDRJ2 RDRJ2 PERJ2 PPSJ2 PIEJ2 PIFJ2 PT0AD0 2 PT1AD0 2 DDRJ1 RDRJ1 PERJ1 PPSJ1 PIEJ1 PIFJ1 PT0AD0 1 PT1AD0 1 DDRJ0 RDRJ0 PERJ0 PPSJ0 PIEJ0 PIFJ0 PT0AD0 0 PT1AD0 0 DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0 7 6 5 4 3 2 1 0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 7 6 5 4 3 2 1 0 RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0 7 6 5 4 3 2 1 0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 7 6 5 4 3 2 1 0 S12P-Family Reference Manual, Rev. 1.12 560 Freescale Semiconductor Detailed Register Address Map 0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4 Address 0x0276 0x0277 0x02780x027F Name PER0AD0 PER1AD0 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 7 6 5 4 3 2 1 0 W R PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 7 6 5 4 3 2 1 0 W R 0 0 0 0 0 0 0 0 W 0x0280-0x02EF Reserved Address 0x02800x02EF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x02F0-0x02FF Clock and Power Management Unit (CPMU) Map 2 of 2 Address 0x02F0 0x02F1 Name CPMUHTCL CPMULVCTL Bit 7 R 0 W R 0 W R APICLK W R APITR5 W R APIR15 W R APIR7 W R 0 W R HTOEN W R W R W R OSCE W R 0 W R 0 W Bit 6 0 0 0 Bit 5 VSEL 0 0 Bit 4 0 0 Bit 3 HTEN 0 Bit 2 HTDS LVDS Bit 1 HTIE LVIE APIE 0 Bit 0 HTIF LVIF APIF 0 0x02F2 CPMUAPICTL 0x02F3 0x02F4 0x02F5 0x02F6 0x02F7 0x02F8 0x02F9 0x02FA 0x02FB 0x02FC VREGAPITR CPMUAPIRH CPMUAPIRL Reserved CPMUHTTR CPMU IRCTRIMH CPMU IRCTRIML CPMUOSC CPMUPROT Reserved APIFES APITR2 APIR12 APIR4 0 0 APIEA APITR1 APIR11 APIR3 0 APIFE APITR0 APIR10 APIR2 0 APITR4 APIR14 APIR6 0 0 APITR3 APIR13 APIR5 0 0 APIR9 APIR1 0 APIR8 APIR0 0 HTTR3 0 HTTR2 0 HTTR1 HTTR0 TCTRIM[3:0] IRCTRIM[9:8] IRCTRIM[7:0] OSCBW 0 0 0 0 0 0 0 0 0 OSCFILT[4:0] 0 0 0 0 PROT 0 S12P-Family Reference Manual, Rev. 1.12 Freescale Semiconductor 561 Detailed Register Address Map 0x0300-0x03FF Reserved Address 0x03000x03FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 S12P-Family Reference Manual, Rev. 1.12 562 Freescale Semiconductor How to Reach Us: USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 Japan: Freescale Semiconductor Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor H.K. Ltd. 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong 852-26668334 Learn More: For more information about Freescale Semiconductor products, please visit http://www.freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009