SPMCM16Z3RMFC16

Freescale Semiconductor Freescale Semiconductor, Inc... M68HC16Z Series User’s Manual © Freescale Sem iconductor, Inc., 2004. All rights reserved. NON-DISCLOSURE MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 MC68HC16Z3 MC68HC16Z4 MC68CK16Z4 AGREEMENT HC16 REQUIRED Order this document by MC68HC16ZUM/AD Freescale Semiconductor, Inc. User’s Manual REQUIRED How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. 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TABLE OF CONTENTS Paragraph Title SECTION 1 INTRODUCTION SECTION 2 NOMENCLATURE 2.1 2.2 2.3 2.4 Symbols and Operators .............................................................................2-1 CPU16 Register Mnemonics .....................................................................2-2 Register Mnemonics ..................................................................................2-3 Conventions ..............................................................................................2-6 SECTION 3 OVERVIEW 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.2 3.3 3.4 3.5 3.6 3.7 M68HC16 Z-Series MCU Features ...........................................................3-1 Central Processor Unit (CPU16/CPU16L) .........................................3-1 System Integration Module (SIM/SIML) ............................................3-1 Standby RAM (SRAM) ......................................................................3-1 Masked ROM Module (MRM) — (MC68HC16Z2/Z3 Only) ...............3-2 Analog-to-Digital Converter (ADC) ....................................................3-2 Queued Serial Module (QSM) ...........................................................3-2 Multichannel Communication Interface (MCCI) — (MC68HC16Z4/CKZ4 Only) ..............................................................3-2 General-Purpose Timer (GPT) ..........................................................3-2 Intermodule Bus ........................................................................................3-2 System Block Diagram and Pin Assignment Diagrams .............................3-2 Pin Descriptions ......................................................................................3-11 Signal Descriptions ..................................................................................3-13 Internal Register Map ..............................................................................3-16 Address Space Maps ..............................................................................3-19 SECTION 4 CENTRAL PROCESSOR UNIT 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 General ......................................................................................................4-1 Register Model ..........................................................................................4-1 Accumulators .....................................................................................4-3 Index Registers .................................................................................4-3 Stack Pointer .....................................................................................4-3 Program Counter ...............................................................................4-3 Condition Code Register ...................................................................4-4 Address Extension Register and Address Extension Fields .............4-5 Page Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title Page 4.2.7 Multiply and Accumulate Registers ...................................................4-5 4.3 Memory Management ...............................................................................4-5 4.3.1 Address Extension ............................................................................4-6 4.3.2 Extension Fields ................................................................................4-6 4.4 Data Types ................................................................................................4-6 4.5 Memory Organization ................................................................................4-7 4.6 Addressing Modes .....................................................................................4-8 4.6.1 Immediate Addressing Modes ...........................................................4-9 4.6.2 Extended Addressing Modes ..........................................................4-10 4.6.3 Indexed Addressing Modes .............................................................4-10 4.6.4 Inherent Addressing Mode ..............................................................4-10 4.6.5 Accumulator Offset Addressing Mode .............................................4-10 4.6.6 Relative Addressing Modes .............................................................4-10 4.6.7 Post-Modified Index Addressing Mode ............................................4-10 4.6.8 Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode ..4-11 4.7 Instruction Set .........................................................................................4-11 4.7.1 Instruction Set Summary .................................................................4-11 4.8 Comparison of CPU16 and M68HC11 CPU Instruction Sets ..................4-31 4.9 Instruction Format ...................................................................................4-33 4.10 Execution Model ......................................................................................4-34 4.10.1 Microsequencer ...............................................................................4-35 4.10.2 Instruction Pipeline ..........................................................................4-35 4.10.3 Execution Unit .................................................................................4-35 4.11 Execution Process ...................................................................................4-36 4.11.1 Changes in Program Flow ...............................................................4-36 4.12 Instruction Timing ....................................................................................4-36 4.13 Exceptions ...............................................................................................4-37 4.13.1 Exception Vectors ...........................................................................4-37 4.13.2 Exception Stack Frame ...................................................................4-38 4.13.3 Exception Processing Sequence .....................................................4-39 4.13.4 Types of Exceptions ........................................................................4-39 4.13.4.1 Asynchronous Exceptions .......................................................4-39 4.13.4.2 Synchronous Exceptions .........................................................4-39 4.13.5 Multiple Exceptions .........................................................................4-40 4.13.6 RTI Instruction .................................................................................4-40 4.14 Development Support ..............................................................................4-40 4.14.1 Deterministic Opcode Tracking .......................................................4-40 4.14.1.1 IPIPE0/IPIPE1 Multiplexing .....................................................4-41 4.14.1.2 Combining Opcode Tracking with Other Capabilities ..............4-41 4.14.2 Breakpoints .....................................................................................4-41 4.14.3 Opcode Tracking and Breakpoints ..................................................4-42 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title Page Freescale Semiconductor, Inc... 4.14.4 Background Debug Mode ................................................................4-42 4.14.4.1 Enabling BDM .........................................................................4-42 4.14.4.2 BDM Sources ..........................................................................4-42 4.14.4.3 Entering BDM ..........................................................................4-42 4.14.4.4 BDM Commands .....................................................................4-43 4.14.4.5 Returning from BDM ...............................................................4-43 4.14.4.6 BDM Serial Interface ...............................................................4-44 4.15 Recommended BDM Connection ............................................................4-45 4.16 Digital Signal Processing .........................................................................4-45 SECTION 5 SYSTEM INTEGRATION MODULE 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.5 5.5.1 5.5.1.1 5.5.1.2 5.5.1.3 5.5.1.4 5.5.1.5 5.5.1.6 General ......................................................................................................5-1 System Configuration ................................................................................5-2 Module Mapping ................................................................................5-2 Interrupt Arbitration ............................................................................5-3 Show Internal Cycles .........................................................................5-3 Register Access ................................................................................5-3 Freeze Operation ..............................................................................5-3 System Clock ............................................................................................5-4 Clock Sources ...................................................................................5-5 Clock Synthesizer Operation .............................................................5-6 External Bus Clock ..........................................................................5-21 Low-Power Operation ......................................................................5-21 System Protection ...................................................................................5-24 Reset Status ....................................................................................5-24 Bus Monitor .....................................................................................5-24 Halt Monitor .....................................................................................5-25 Spurious Interrupt Monitor ...............................................................5-25 Software Watchdog .........................................................................5-25 Periodic Interrupt Timer ...................................................................5-27 Interrupt Priority and Vectoring ........................................................5-28 Low-Power STOP Operation ...........................................................5-29 External Bus Interface .............................................................................5-29 Bus Control Signals .........................................................................5-31 Address Bus ............................................................................5-31 Address Strobe .......................................................................5-31 Data Bus .................................................................................5-31 Data Strobe .............................................................................5-31 Read/Write Signal ...................................................................5-32 Size Signals ............................................................................5-32 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title Page 5.5.1.7 Function Codes .......................................................................5-32 5.5.1.8 Data Size Acknowledge Signals .............................................5-32 5.5.1.9 Bus Error Signal ......................................................................5-33 5.5.1.10 Halt Signal ...............................................................................5-33 5.5.1.11 Autovector Signal ....................................................................5-33 5.5.2 Dynamic Bus Sizing ........................................................................5-33 5.5.3 Operand Alignment .........................................................................5-35 5.5.4 Misaligned Operands ......................................................................5-35 5.5.5 Operand Transfer Cases .................................................................5-35 5.6 Bus Operation .........................................................................................5-36 5.6.1 Synchronization to CLKOUT ...........................................................5-36 5.6.2 Regular Bus Cycle ...........................................................................5-37 5.6.2.1 Read Cycle ..............................................................................5-37 5.6.2.2 Write Cycle ..............................................................................5-38 5.6.3 Fast Termination Cycles ..................................................................5-39 5.6.4 CPU Space Cycles ..........................................................................5-40 5.6.4.1 Breakpoint Acknowledge Cycle ...............................................5-41 5.6.4.2 LPSTOP Broadcast Cycle .......................................................5-42 5.6.5 Bus Exception Control Cycles .........................................................5-43 5.6.5.1 Bus Errors ...............................................................................5-44 5.6.5.2 Double Bus Faults ...................................................................5-45 5.6.5.3 Halt Operation .........................................................................5-45 5.6.6 External Bus Arbitration ...................................................................5-46 5.6.6.1 Show Cycles ...........................................................................5-47 5.7 Reset .......................................................................................................5-48 5.7.1 Reset Exception Processing ...........................................................5-48 5.7.2 Reset Control Logic .........................................................................5-48 5.7.3 Reset Mode Selection .....................................................................5-49 5.7.3.1 Data Bus Mode Selection ........................................................5-50 5.7.3.2 Clock Mode Selection .............................................................5-52 5.7.3.3 Breakpoint Mode Selection .....................................................5-52 5.7.4 MCU Module Pin Function During Reset ........................................5-52 5.7.5 Pin State During Reset ....................................................................5-53 5.7.5.1 Reset States of SIM Pins ........................................................5-54 5.7.5.2 Reset States of Pins Assigned to Other MCU Modules ..........5-54 5.7.6 Reset Timing ...................................................................................5-55 5.7.7 Power-On Reset ..............................................................................5-55 5.7.8 Use of the Three-State Control Pin .................................................5-56 5.7.9 Reset Processing Summary ............................................................5-57 5.7.10 Reset Status Register .....................................................................5-57 5.8 Interrupts .................................................................................................5-58 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title Page Freescale Semiconductor, Inc... 5.8.1 Interrupt Exception Processing .......................................................5-58 5.8.2 Interrupt Priority and Recognition ....................................................5-58 5.8.3 Interrupt Acknowledge and Arbitration ............................................5-59 5.8.4 Interrupt Processing Summary ........................................................5-60 5.8.5 Interrupt Acknowledge Bus Cycles ..................................................5-61 5.9 Chip-Selects ............................................................................................5-61 5.9.1 Chip-Select Registers ......................................................................5-63 5.9.1.1 Chip-Select Pin Assignment Registers ...................................5-64 5.9.1.2 Chip-Select Base Address Registers ......................................5-65 5.9.1.3 Chip-Select Option Registers ..................................................5-66 5.9.1.4 PORTC Data Register .............................................................5-67 5.9.2 Chip-Select Operation .....................................................................5-67 5.9.3 Using Chip-Select Signals for Interrupt Acknowledge .....................5-68 5.9.4 Chip-Select Reset Operation ...........................................................5-69 5.10 Parallel Input/Output Ports ......................................................................5-70 5.10.1 Pin Assignment Registers ...............................................................5-70 5.10.2 Data Direction Registers .................................................................5-70 5.10.3 Data Registers .................................................................................5-71 5.11 Factory Test ............................................................................................5-71 SECTION 6 STANDBY RAM MODULE 6.1 6.2 6.3 6.4 6.5 6.6 SRAM Register Block ................................................................................6-1 SRAM Array Address Mapping .................................................................6-2 SRAM Array Address Space Type ............................................................6-2 Normal Access ..........................................................................................6-2 Standby and Low-Power Stop Operation ..................................................6-2 Reset .........................................................................................................6-3 SECTION 7 MASKED ROM MODULE 7.1 7.2 7.3 7.4 7.5 7.6 7.7 MRM Register Block ..................................................................................7-1 MRM Array Address Mapping ...................................................................7-1 MRM Array Address Space Type ..............................................................7-2 Normal Access ..........................................................................................7-2 Low-Power Stop Mode Operation .............................................................7-3 ROM Signature ..........................................................................................7-3 Reset .........................................................................................................7-3 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title SECTION 8 ANALOG-TO-DIGITAL CONVERTER 8.1 8.2 8.2.1 8.2.2 8.2.3 8.3 8.4 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.5.1 8.7.5.2 8.7.6 8.7.7 8.7.8 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.8.5 8.8.6 8.8.6.1 8.8.6.2 General ......................................................................................................8-1 External Connections ................................................................................8-1 Analog Input Pins ..............................................................................8-2 Analog Reference Pins ......................................................................8-3 Analog Supply Pins ...........................................................................8-3 Programmer’s Model .................................................................................8-3 ADC Bus Interface Unit .............................................................................8-3 Special Operating Modes ..........................................................................8-3 Low-Power Stop Mode ......................................................................8-3 Freeze Mode .....................................................................................8-4 Analog Subsystem ....................................................................................8-4 Multiplexer .........................................................................................8-4 Sample Capacitor and Buffer Amplifier .............................................8-5 RC DAC Array ...................................................................................8-5 Comparator .......................................................................................8-6 Digital Control Subsystem .........................................................................8-6 Control/Status Registers ...................................................................8-6 Clock and Prescaler Control ..............................................................8-6 Sample Time .....................................................................................8-7 Resolution .........................................................................................8-7 Conversion Control Logic ..................................................................8-7 Conversion Parameters ............................................................8-8 Conversion Modes ....................................................................8-8 Conversion Timing ..........................................................................8-12 Successive Approximation Register ................................................8-13 Result Registers ..............................................................................8-13 Pin Considerations ..................................................................................8-14 Analog Reference Pins ....................................................................8-14 Analog Power Pins ..........................................................................8-14 Analog Supply Filtering and Grounding ...........................................8-16 Accommodating Positive/Negative Stress Conditions .....................8-18 Analog Input Considerations ...........................................................8-19 Analog Input Pins ............................................................................8-21 Settling Time for the External Circuit .......................................8-22 Error Resulting from Leakage .................................................8-23 Page Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title SECTION 9 QUEUED SERIAL MODULE 9.1 9.2 9.2.1 9.2.1.1 9.2.1.2 9.2.1.3 9.2.2 9.3 9.3.1 9.3.1.1 9.3.1.2 9.3.2 9.3.2.1 9.3.2.2 9.3.2.3 9.3.3 9.3.4 9.3.5 9.3.5.1 9.3.5.2 9.3.5.3 9.3.5.4 9.3.6 9.4 9.4.1 9.4.1.1 9.4.1.2 9.4.1.3 9.4.2 9.4.3 9.4.3.1 9.4.3.2 9.4.3.3 9.4.3.4 9.4.3.5 9.4.3.6 9.4.3.7 9.4.3.8 9.4.3.9 General ......................................................................................................9-1 QSM Registers and Address Map .............................................................9-2 QSM Global Registers .......................................................................9-2 Low-Power Stop Mode Operation .............................................9-2 Freeze Operation ......................................................................9-3 QSM Interrupts ..........................................................................9-3 QSM Pin Control Registers ...............................................................9-4 Queued Serial Peripheral Interface ...........................................................9-5 QSPI Registers ..................................................................................9-6 Control Registers ......................................................................9-6 Status Register ..........................................................................9-7 QSPI RAM .........................................................................................9-7 Receive RAM ............................................................................9-7 Transmit RAM ...........................................................................9-7 Command RAM .........................................................................9-8 QSPI Pins ..........................................................................................9-8 QSPI Operation .................................................................................9-8 QSPI Operating Modes .....................................................................9-9 Master Mode ...........................................................................9-16 Master Wrap-Around Mode .....................................................9-19 Slave Mode .............................................................................9-20 Slave Wrap-Around Mode .......................................................9-21 Peripheral Chip Selects ...................................................................9-21 Serial Communication Interface ..............................................................9-21 SCI Registers ..................................................................................9-24 Control Registers ....................................................................9-24 Status Register ........................................................................9-24 Data Register ..........................................................................9-24 SCI Pins ..........................................................................................9-25 SCI Operation ..................................................................................9-25 Definition of Terms ..................................................................9-25 Serial Formats .........................................................................9-25 Baud Clock ..............................................................................9-26 Parity Checking .......................................................................9-26 Transmitter Operation .............................................................9-27 Receiver Operation .................................................................9-28 Idle-Line Detection ..................................................................9-29 Receiver Wake-Up ..................................................................9-29 Internal Loop Mode .................................................................9-30 Page Freescale Semiconductor, Inc... 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TABLE OF CONTENTS Paragraph (Continued) Title SECTION 10 MULTICHANNEL COMMUNICATION INTERFACE 10.1 General ....................................................................................................10-1 10.2 MCCI Registers and Address Map ..........................................................10-2 10.2.1 MCCI Global Registers ....................................................................10-2 10.2.1.1 Low-Power Stop Mode ............................................................10-2 10.2.1.2 Privilege Levels .......................................................................10-3 10.2.1.3 MCCI Interrupts .......................................................................10-3 10.2.2 Pin Control and General-Purpose I/O .............................................10-4 10.3 Serial Peripheral Interface (SPI) ..............................................................10-4 10.3.1 SPI Registers ..................................................................................10-6 10.3.1.1 SPI Control Register (SPCR) ..................................................10-6 10.3.1.2 SPI Status Register (SPSR) ....................................................10-6 10.3.1.3 SPI Data Register (SPDR) ......................................................10-6 10.3.2 SPI Pins ...........................................................................................10-6 10.3.3 SPI Operating Modes ......................................................................10-7 10.3.3.1 Master Mode ...........................................................................10-7 10.3.3.2 Slave Mode .............................................................................10-8 10.3.4 SPI Clock Phase and Polarity Controls ...........................................10-8 10.3.4.1 CPHA = 0 Transfer Format .....................................................10-9 10.3.4.2 CPHA = 1 Transfer Format ...................................................10-10 10.3.5 SPI Serial Clock Baud Rate ..........................................................10-11 10.3.6 Wired-OR Open-Drain Outputs .....................................................10-11 10.3.7 Transfer Size and Direction ...........................................................10-11 10.3.8 Write Collision ...............................................................................10-12 10.3.9 Mode Fault ....................................................................................10-12 10.4 Serial Communication Interface (SCI) ...................................................10-13 10.4.1 SCI Registers ................................................................................10-13 10.4.1.1 SCI Control Registers ...........................................................10-13 10.4.1.2 SCI Status Register ...............................................................10-16 10.4.1.3 SCI Data Register .................................................................10-16 10.4.2 SCI Pins ........................................................................................10-16 10.4.3 Receive Data Pins (RXDA, RXDB) ...............................................10-17 10.4.4 Transmit Data Pins (TXDA, TXDB) ...............................................10-17 10.4.5 SCI Operation ................................................................................10-17 10.4.5.1 Definition of Terms ................................................................10-17 10.4.5.2 Serial Formats .......................................................................10-18 10.4.5.3 Baud Clock ............................................................................10-18 10.4.5.4 Parity Checking .....................................................................10-19 10.4.5.5 Transmitter Operation ...........................................................10-19 10.4.5.6 Receiver Operation ...............................................................10-20 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Page Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title Page 10.4.5.7 Idle-Line Detection ................................................................10-21 10.4.5.8 Receiver Wake-Up ................................................................10-22 10.4.5.9 Internal Loop .........................................................................10-22 10.5 MCCI Initialization .................................................................................10-23 SECTION 11 GENERAL-PURPOSE TIMER 11.1 General ....................................................................................................11-1 11.2 GPT Registers and Address Map ............................................................11-2 11.3 Special Modes of Operation ....................................................................11-3 11.3.1 Low-Power Stop Mode ....................................................................11-3 11.3.2 Freeze Mode ...................................................................................11-3 11.3.3 Single-Step Mode ............................................................................11-4 11.3.4 Test Mode .......................................................................................11-4 11.4 Polled and Interrupt-Driven Operation .....................................................11-4 11.4.1 Polled Operation ..............................................................................11-4 11.4.2 GPT Interrupts .................................................................................11-5 11.5 Pin Descriptions ......................................................................................11-7 11.5.1 Input Capture Pins ...........................................................................11-7 11.5.2 Input Capture/Output Compare Pin .................................................11-7 11.5.3 Output Compare Pins ......................................................................11-7 11.5.4 Pulse Accumulator Input Pin ...........................................................11-7 11.5.5 Pulse-Width Modulation ..................................................................11-8 11.5.6 Auxiliary Timer Clock Input ..............................................................11-8 11.6 General-Purpose I/O ...............................................................................11-8 11.7 Prescaler .................................................................................................11-8 11.8 Capture/Compare Unit ..........................................................................11-10 11.8.1 Timer Counter ...............................................................................11-10 11.8.2 Input Capture Functions ................................................................11-10 11.8.3 Output Compare Functions ...........................................................11-13 11.8.3.1 Output Compare 1 .................................................................11-14 11.8.3.2 Forced Output Compare .......................................................11-14 11.9 Input Capture 4/Output Compare 5 .......................................................11-14 11.10 Pulse Accumulator ................................................................................11-14 11.11 Pulse-Width Modulation Unit .................................................................11-16 11.11.1 PWM Counter ................................................................................11-18 11.11.2 PWM Function ...............................................................................11-18 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title APPENDIX A ELECTRICAL CHARACTERISTICS APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION B.1 B.2 Obtaining Updated M68HC16 Z-Series MCU Mechanical Information .... B-8 Ordering Information ................................................................................ B-8 APPENDIX C DEVELOPMENT SUPPORT C.1 C.2 M68MMDS1632 Modular Development System ...................................... C-1 M68MEVB1632 Modular Evaluation Board .............................................. C-2 APPENDIX D REGISTER SUMMARY D.1 Central Processing Unit ............................................................................ D-1 D.1.1 Condition Code Register .................................................................. D-3 D.2 System Integration Module ....................................................................... D-4 D.2.1 SIM Module Configuration Register ................................................. D-6 D.2.2 System Integration Test Register ..................................................... D-7 D.2.3 Clock Synthesizer Control Register .................................................. D-7 D.2.4 Reset Status Register ...................................................................... D-8 D.2.5 System Integration Test Register E .................................................. D-9 D.2.6 Port E Data Register ........................................................................ D-9 D.2.7 Port E Data Direction Register ......................................................... D-9 D.2.8 Port E Pin Assignment Register ..................................................... D-10 D.2.9 Port F Data Register ....................................................................... D-10 D.2.10 Port F Data Direction Register ....................................................... D-11 D.2.11 Port F Pin Assignment Register ..................................................... D-11 D.2.12 System Protection Control Register ............................................... D-12 D.2.13 Periodic Interrupt Control Register ................................................. D-13 D.2.14 Periodic Interrupt Timer Register ................................................... D-14 D.2.15 Software Watchdog Service Register ............................................. D-15 D.2.16 Port C Data Register ...................................................................... D-15 D.2.17 Chip-Select Pin Assignment Registers ........................................... D-15 D.2.18 Chip-Select Base Address Register Boot ....................................... D-17 D.2.19 Chip-Select Base Address Registers ............................................. D-17 D.2.20 Chip-Select Option Register Boot .................................................. D-18 D.2.21 Chip-Select Option Registers ......................................................... D-18 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Page Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph D.2.22 D.2.23 D.2.24 D.2.25 D.2.26 D.3 D.3.1 D.3.2 D.3.3 D.3.4 D.4 D.4.1 D.4.2 D.4.3 D.4.4 D.5 D.5.1 D.5.2 D.5.3 D.5.4 D.5.5 D.5.6 D.5.7 D.6 D.6.1 D.6.2 D.6.3 D.6.4 D.6.5 D.6.6 D.6.7 D.6.8 D.6.9 D.6.10 D.6.11 D.6.12 D.6.13 D.6.14 D.6.15 D.6.16 D.7 (Continued) Title Page Master Shift Registers .................................................................... D-22 Test Module Shift Count Register .................................................. D-22 Test Module Repetition Count Register ......................................... D-22 Test Module Control Register ......................................................... D-22 Test Module Distributed Register ................................................... D-22 Standby RAM Module ............................................................................ D-23 RAM Module Configuration Register .............................................. D-23 RAM Test Register ......................................................................... D-24 Array Base Address Register High ................................................. D-24 Array Base Address Register Low ................................................. D-24 Masked ROM Module ............................................................................. D-25 Masked ROM Module Configuration Register ................................ D-25 ROM Array Base Address Registers .............................................. D-27 ROM Signature Registers High ...................................................... D-27 ROM Bootstrap Words ................................................................... D-28 Analog-to-Digital Converter Module ....................................................... D-29 ADC Module Configuration Register .............................................. D-30 ADC Test Register ......................................................................... D-30 Port ADA Data Register ................................................................. D-30 ADC Control Register 0 .................................................................. D-31 ADC Control Register 1 .................................................................. D-32 ADC Status Register ...................................................................... D-36 Right Justified, Unsigned Result Register ...................................... D-36 Queued Serial Module ............................................................................ D-38 QSM Configuration Register .......................................................... D-38 QSM Test Register ......................................................................... D-39 QSM Interrupt Level Register/Interrupt Vector Register ................. D-39 SCI Control Register ...................................................................... D-40 SCI Control Register 1 ................................................................... D-41 SCI Status Register ........................................................................ D-43 SCI Data Register .......................................................................... D-44 Port QS Data Register .................................................................... D-44 Port QS Pin Assignment Register/Data Direction Register ............ D-45 QSPI Control Register 0 ................................................................. D-46 QSPI Control Register 1 ................................................................. D-48 QSPI Control Register 2 ................................................................. D-49 QSPI Control Register 3 ................................................................. D-50 Receive Data RAM ......................................................................... D-51 Transmit Data RAM ........................................................................ D-52 Command RAM .............................................................................. D-52 Multichannel Communication Interface Module ..................................... D-54 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title Page D.7.1 MCCI Module Configuration Register ............................................. D-54 D.7.2 MCCI Test Register ........................................................................ D-55 D.7.3 SCI Interrupt Level Register/MCCI Interrupt Vector Register ......... D-55 D.7.4 MCCI Interrupt Vector Register ...................................................... D-56 D.7.5 SPI Interrupt Level Register ........................................................... D-56 D.7.6 MCCI Pin Assignment Register ...................................................... D-57 D.7.7 MCCI Data Direction Register ........................................................ D-58 D.7.8 MCCI Port Data Registers .............................................................. D-59 D.7.9 SCI Control Register 0 ................................................................... D-59 D.7.11 SCI Status Register ........................................................................ D-62 D.7.12 SCI Data Register .......................................................................... D-63 D.7.13 SPI Control Register ....................................................................... D-64 D.7.14 SPI Status Register ........................................................................ D-65 D.7.15 SPI Data Register ........................................................................... D-66 D.8 General-Purpose Timer .......................................................................... D-67 D.8.1 GPT Module Configuration Register .............................................. D-67 D.8.2 GPT Test Register .......................................................................... D-68 D.8.3 GPT Interrupt Configuration Register ............................................. D-68 D.8.4 Port GP Data Direction Register/Data Register ............................. D-69 D.8.5 OC1 Action Mask Register/Data Register ...................................... D-69 D.8.6 Timer Counter Register .................................................................. D-70 D.8.7 Pulse Accumulator Control Register/Counter ................................. D-70 D.8.8 Input Capture Registers 1–3 .......................................................... D-71 D.8.9 Output Compare Registers 1–4 ...................................................... D-71 D.8.10 Input Capture 4/Output Compare 5 Register .................................. D-72 D.8.11 Timer Control Registers 1 and 2 .................................................... D-72 D.8.12 Timer Interrupt Mask Registers 1 and 2 ......................................... D-72 D.8.13 Timer Interrupt Flag Registers 1 and 2 ........................................... D-74 D.8.14 Compare Force Register/PWM Control Register C ........................ D-74 D.8.15 PWM Registers A/B ........................................................................ D-76 D.8.16 PWM Count Register ...................................................................... D-76 D.8.17 PWM Buffer Registers A/B ............................................................. D-76 D.8.18 GPT Prescaler ................................................................................ D-77 APPENDIX E INITIALIZATION AND PROGRAMMING EXAMPLES E.1 E.1.1 E.1.2 E.1.3 E.1.4 Initialization Programs .............................................................................. E-1 EQUATES.ASM ............................................................................... E-2 ORG00000.ASM .............................................................................. E-6 ORG00008.ASM .............................................................................. E-6 INITSYS.ASM ................................................................................. E-11 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph (Continued) Title Page Freescale Semiconductor, Inc... E.1.5 INITRAM.ASM ................................................................................ E-11 E.1.6 INITSCI.ASM .................................................................................. E-12 E.2 Programming Examples ......................................................................... E-12 E.2.1 SIM Programming Examples .......................................................... E-13 E.2.1.1 Example 1 - Using Ports E and F ........................................... E-13 E.2.1.2 Example 2 - Using Chip-Selects ............................................ E-14 E.2.1.3 Example 3 - Changing Clock Frequencies ............................. E-16 E.2.1.4 Example 4 - Software Watchdog, Periodic Interrupt, and Autovector Demo ............................................................ E-18 E.2.2 CPU16 Programming Example ...................................................... E-23 E.2.2.1 Example 5 - Indexed and Extended Addressing .................... E-23 E.2.3 QSM/SCI Programming Example ................................................... E-24 E.2.3.1 Example 6 - Using an SCI Port .............................................. E-24 E.2.4 GPT Programming Example .......................................................... E-25 E.2.4.1 Example 7 - Basic GPT Functions ......................................... E-25 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 Title Page Freescale Semiconductor, Inc... MC68HC16Z1/CK16Z1/CM16Z1 Block Diagram ........................................... 3-4 MC68HC16Z2/Z3 Block Diagram ................................................................... 3-5 MC68HC16Z4/CK16Z4 Block Diagram .......................................................... 3-6 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package ....................................................................................... 3-7 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 144-Pin Package ....................................................................................... 3-8 MC68HC16Z4/CKZ4 Pin Assignments for 132-Pin Package ......................... 3-9 MC68HC16Z4/CKZ4 Pin Assignments for 144-Pin Package ....................... 3-10 MC68HC16Z1/CKZ1/CMZ1 Address Map ................................................... 3-17 MC68HC16Z2/Z3 Address Map ................................................................... 3-18 MC68HC16Z4/CKZ4 Address Map .............................................................. 3-18 MC68HC16Z1/CKZ1/CMZ1 Combined Program and Data Space Map .................................................................................... 3-20 MC68HC16Z2/Z3 Combined Program and Data Space Map ...................... 3-21 MC68HC16Z4/CKZ4 Combined Program and Data Space Map ................. 3-22 MC68HC16Z1/CKZ1/CMZ1 Separate Program and Data Space Map .................................................................................... 3-23 MC68HC16Z2/Z3 Separate Program and Data Space Map ........................ 3-24 MC68HC16Z4/CKZ4 Separate Program and Data Space Map ................... 3-25 CPU16 Register Model ................................................................................... 4-2 Condition Code Register ................................................................................ 4-4 Data Types and Memory Organization ........................................................... 4-8 Basic Instruction Formats ............................................................................. 4-34 Instruction Execution Model ......................................................................... 4-35 Exception Stack Frame Format .................................................................... 4-38 BDM Serial I/O Block Diagram ..................................................................... 4-44 BDM Connector Pinout ................................................................................. 4-45 System Integration Module Block Diagram .................................................... 5-2 System Clock Block Diagram ......................................................................... 5-4 Slow Reference Crystal Circuit ....................................................................... 5-5 Fast Reference Crystal Circuit ....................................................................... 5-5 System Clock Filter Networks ........................................................................ 5-7 SIM LPSTOP Flowchart ............................................................................... 5-22 SIML LPSTOP Flowchart ............................................................................. 5-23 System Protection ........................................................................................ 5-24 Periodic Interrupt Timer and Software Watchdog Timer .............................. 5-27 MCU Basic System ...................................................................................... 5-30 Operand Byte Order ..................................................................................... 5-34 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 10-1 10-2 10-3 10-4 10-5 (Continued) Title Page Freescale Semiconductor, Inc... Word Read Cycle Flowchart ......................................................................... 5-38 Write Cycle Flowchart .................................................................................. 5-39 CPU Space Address Encoding .................................................................... 5-41 Breakpoint Operation Flowchart ................................................................... 5-42 LPSTOP Interrupt Mask Level ...................................................................... 5-43 Bus Arbitration Flowchart for Single Request ............................................... 5-47 Preferred Circuit for Data Bus Mode Select Conditioning ............................ 5-50 Alternate Circuit for Data Bus Mode Select Conditioning ............................. 5-51 Power-On Reset ........................................................................................... 5-56 Basic MCU System ...................................................................................... 5-62 Chip-Select Circuit Block Diagram ............................................................... 5-63 CPU Space Encoding for Interrupt Acknowledge ......................................... 5-68 ADC Block Diagram ....................................................................................... 8-2 8-Bit Conversion Timing ............................................................................... 8-12 10-Bit Conversion Timing ............................................................................. 8-13 Analog Input Circuitry ................................................................................... 8-15 Errors Resulting from Clipping ..................................................................... 8-16 Star-Ground at the Point of Power Supply Origin ......................................... 8-17 Input Pin Subjected to Negative Stress ........................................................ 8-18 Voltage Limiting Diodes in a Negative Stress Circuit ................................... 8-19 External Multiplexing of Analog Signal Sources ........................................... 8-20 Electrical Model of an A/D Input Pin ............................................................. 8-21 QSM Block Diagram ....................................................................................... 9-1 QSPI Block Diagram ...................................................................................... 9-5 QSPI RAM ...................................................................................................... 9-7 Flowchart of QSPI Initialization Operation .................................................... 9-10 Flowchart of QSPI Master Operation (Part 1) .............................................. 9-11 Flowchart of QSPI Master Operation (Part 2) .............................................. 9-12 Flowchart of QSPI Master Operation (Part 3) .............................................. 9-13 Flowchart of QSPI Slave Operation (Part 1) ................................................ 9-14 Flowchart of QSPI Slave Operation (Part 2) ................................................ 9-15 SCI Transmitter Block Diagram .................................................................... 9-22 SCI Receiver Block Diagram ........................................................................ 9-23 MCCI Block Diagram .................................................................................... 10-1 SPI Block Diagram ....................................................................................... 10-5 CPHA = 0 SPI Transfer Format .................................................................... 10-9 CPHA = 1 SPI Transfer Format .................................................................. 10-10 SCI Transmitter Block Diagram .................................................................. 10-14 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 10-6 11-1 11-2 11-3 11-4 11-5 11-6 (Continued) Title Page SCI Receiver Block Diagram ...................................................................... 10-15 GPT Block Diagram ...................................................................................... 11-2 Prescaler Block Diagram .............................................................................. 11-9 Capture/Compare Unit Block Diagram ....................................................... 11-11 Input Capture Timing Example ................................................................... 11-13 Pulse Accumulator Block Diagram ............................................................. 11-15 PWM Block Diagram .................................................................................. 11-17 CLKOUT Output Timing Diagram .................................................................A-28 External Clock Input Timing Diagram ...........................................................A-28 ECLK Output Timing Diagram ......................................................................A-28 Read Cycle Timing Diagram ........................................................................A-29 Write Cycle Timing Diagram .........................................................................A-30 Fast Termination Read Cycle Timing Diagram ............................................A-31 Fast Termination Write Cycle Timing Diagram .............................................A-32 Bus Arbitration Timing Diagram — Active Bus Case ...................................A-33 Bus Arbitration Timing Diagram — Idle Bus Case .......................................A-34 Show Cycle Timing Diagram ........................................................................A-35 Chip-Select Timing Diagram ........................................................................A-36 Reset and Mode Select Timing Diagram ......................................................A-36 Background Debug Mode Timing Diagram (Serial Communication) ............A-39 Background Debug Mode Timing Diagram (Freeze Assertion) ....................A-39 ECLK Timing Diagram ..................................................................................A-44 QSPI Timing — Master, CPHA = 0 ..............................................................A-47 QSPI Timing — Master, CPHA = 1 ..............................................................A-47 QSPI Timing — Slave, CPHA = 0 ................................................................A-48 QSPI Timing — Slave, CPHA = 1 ................................................................A-48 SPI Timing — Master, CPHA = 0 .................................................................A-51 SPI Timing — Master, CPHA = 1 .................................................................A-51 SPI Timing — Slave, CPHA = 0 ...................................................................A-52 SPI Timing — Slave, CPHA = 1 ...................................................................A-52 Input Signal Conditioner Timing ...................................................................A-53 Pulse Accumulator — Event Counting Mode (Leading Edge) ......................A-54 Pulse Accumulator — Gated Mode (Count While Pin High) ........................A-55 Pulse Accumulator — Using TOF as Gated Mode Clock .............................A-56 PWMx (PWMx Register = 01, Fast Mode) ...................................................A-56 Output Compare (Toggle Pin State) .............................................................A-57 Input Capture (Capture on Rising Edge) ......................................................A-58 General-Purpose Input .................................................................................A-59 General-Purpose Output (Causes Input Capture) ........................................A-60 Freescale Semiconductor, Inc... A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 A-21 A-22 A-23 A-24 A-25 A-26 A-27 A-28 A-29 A-30 A-31 A-32 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure A-33 A-34 A-35 A-36 A-37 B-1 (Continued) Title Page Force Compare (CLEAR) .............................................................................A-61 Low Voltage 8-Bit ADC Conversion Accuracy ..............................................A-68 8-Bit ADC Conversion Accuracy ..................................................................A-69 Low Voltage 10-Bit ADC Conversion Accuracy ............................................A-70 10-Bit ADC Conversion Accuracy ................................................................A-71 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package .......................................................................................B-2 MC68HC16Z4/CKZ4 Pin Assignments for 132-Pin Package .........................B-3 Case 831A-01 — 132-Pin Package Dimensions ............................................B-4 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 144-Pin Package .......................................................................................B-5 MC68HC16Z4/CKZ4 Pin Assignments for 144-Pin Package .........................B-6 Case 918 — 144-Pin Package Dimensions ...................................................B-7 CPU16 Register Model ...................................................................................D-2 Freescale Semiconductor, Inc... B-2 B-3 B-4 B-5 B-6 D-1 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF TABLES Table 1-1 1-2 3-1 3-2 3-3 3-4 3-5 Title Page M68HC16 Z-Series MCUs............................................................................... 1-1 Z-Series MCU Reference Frequencies ........................................................... 1-2 M68HC16 Z-Series Pin Characteristics......................................................... 3-11 M68HC16 Z-Series Driver Types .................................................................. 3-12 M68HC16 Z-Series Power Connections ....................................................... 3-13 M68HC16 Z-Series Signal Characteristics .................................................... 3-13 M68HC16 Z-Series Signal Function.............................................................. 3-15 Addressing Modes........................................................................................... 4-9 Instruction Set Summary ............................................................................... 4-12 Instruction Set Abbreviations and Symbols................................................... 4-30 CPU16 Implementation of M68HC11 CPU Instructions ................................ 4-32 Exception Vector Table ................................................................................. 4-38 IPIPE0/IPIPE1 Encoding ............................................................................... 4-41 Command Summary ..................................................................................... 4-43 Show Cycle Enable Bits .................................................................................. 5-3 16.78-MHz Clock Control Multipliers ............................................................... 5-9 20.97-MHz Clock Control Multipliers ............................................................. 5-11 25.17-MHz Clock Control Multipliers ............................................................. 5-13 16.78-MHz System Clock Frequencies ......................................................... 5-15 System Clock Frequencies for a 20.97-MHz System .................................... 5-17 System Clock Frequencies for a 25.17-MHz System .................................... 5-19 Bus Monitor Period........................................................................................ 5-25 MODCLK Pin and SWP Bit During Reset ..................................................... 5-26 Software Watchdog Divide Ratio................................................................... 5-27 MODCLK Pin and PTP Bit at Reset .............................................................. 5-28 Periodic Interrupt Priority............................................................................... 5-29 Size Signal Encoding .................................................................................... 5-32 Address Space Encoding .............................................................................. 5-32 Effect of DSACK Signals ............................................................................... 5-34 Operand Alignment ....................................................................................... 5-36 DSACK, BERR, and HALT Assertion Results ............................................... 5-44 Reset Source Summary ................................................................................ 5-49 Reset Mode Selection ................................................................................... 5-49 Module Pin Functions.................................................................................... 5-53 SIM Pin Reset States .................................................................................... 5-54 Chip-Select Pin Functions ............................................................................. 5-64 Pin Assignment Field Encoding..................................................................... 5-64 Block Size Encoding...................................................................................... 5-65 Freescale Semiconductor, Inc... 4-1 4-2 4-3 4-4 4-5 4-6 4-7 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF TABLES Table 5-25 5-26 6-1 6-2 7-1 7-2 (Continued) Title Page Chip-Select Base and Option Register Reset Values ................................... 5-69 CSBOOT Base and Option Register Reset Values....................................... 5-70 SRAM Configuration........................................................................................ 6-1 SRAM Array Address Space Type .................................................................. 6-2 ROM Array Space Field .................................................................................. 7-2 Wait States Field ............................................................................................. 7-3 FRZ Field Selection......................................................................................... 8-4 Multiplexer Channel Sources .......................................................................... 8-5 Prescaler Output ............................................................................................. 8-7 TS Field Selection ........................................................................................... 8-7 Conversion Parameters Controlled by ADCTL1.............................................. 8-8 ADC Conversion Modes.................................................................................. 8-8 Single-Channel Conversions (MULT = 0)...................................................... 8-10 Multiple-Channel Conversions (MULT = 1) ................................................... 8-11 Result Register Formats................................................................................ 8-14 External Circuit Settling Time (10-Bit Conversions) ...................................... 8-23 Error Resulting From Input Leakage (IOFF).................................................. 8-23 Effect of DDRQS on QSM Pin Function .......................................................... 9-4 QSPI Pins........................................................................................................ 9-8 Bits Per Transfer ........................................................................................... 9-18 Serial Frame Formats.................................................................................... 9-26 Effect of Parity Checking on Data Size ......................................................... 9-27 MCCI Interrupt Vectors.................................................................................. 10-3 Pin Assignments............................................................................................ 10-4 SPI Pin Functions.......................................................................................... 10-7 SCK Frequencies ........................................................................................ 10-11 SCI Pins ...................................................................................................... 10-17 Serial Frame Formats.................................................................................. 10-18 Effect of Parity Checking on Data Size ....................................................... 10-19 GPT Status Flags .......................................................................................... 11-5 GPT Interrupt Sources .................................................................................. 11-6 PWM Frequency Ranges ............................................................................ 11-18 Maximum Ratings............................................................................................A-1 Typical Ratings, 2.7 to 3.6V, 16.78-MHz Operation ........................................A-2 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 10-6 10-7 11-1 11-2 11-3 A-1 A-2 Freescale Semiconductor, Inc. LIST OF TABLES Table A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 A-21 A-22 A-23 A-24 A-25 A-26 A-27 A-28 A-29 A-30 A-31 A-32 A-33 A-34 A-35 A-36 A-37 A-38 B-1 D-1 D-2 (Continued) Title Page Typical Ratings, 5V, 16.78-MHz Operation .....................................................A-3 Typical Ratings, 20.97-MHz Operation ...........................................................A-3 Typical Ratings, 25.17-MHz ............................................................................A-4 Thermal Characteristics ..................................................................................A-5 Low Voltage Clock Control Timing ..................................................................A-6 16.78-MHz Clock Control Timing ....................................................................A-7 20.97-MHz Clock Control Timing ....................................................................A-8 25.17-MHz Clock Control Timing ....................................................................A-9 Low Voltage 16.78-MHz DC Characteristics .................................................A-10 16.78-MHz DC Characteristics......................................................................A-12 20.97-MHz DC Characteristics......................................................................A-14 25.17-MHz DC Characteristics......................................................................A-16 Low Voltage 16.78-MHz AC Timing ..............................................................A-19 16.78-MHz AC Timing ...................................................................................A-21 20.97-MHz AC Timing ...................................................................................A-23 25.17-MHz AC Timing ...................................................................................A-25 Low Voltage 16.78-MHz Background Debug Mode Timing ..........................A-37 16.78-MHz Background Debug Mode Timing ...............................................A-37 20.97-MHz Background Debug Mode Timing ...............................................A-38 25.17-MHz Background Debug Mode Timing ...............................................A-38 Low Voltage ECLK Bus Timing .....................................................................A-40 16.78-MHz ECLK Bus Timing .......................................................................A-41 20.97-MHz ECLK Bus Timing .......................................................................A-42 25.17-MHz ECLK Bus Timing .......................................................................A-43 Low Voltage QSPI Timing .............................................................................A-45 QSPI Timing ..................................................................................................A-46 Low Voltage SPI Timing ................................................................................A-49 SPI Timing.....................................................................................................A-50 General-Purpose Timer AC Characteristics ..................................................A-53 ADC Maximum Ratings .................................................................................A-62 Low Voltage ADC DC Electrical Characteristics (Operating) ........................A-63 Low Voltage ADC AC Characteristics (Operating) ........................................A-63 5V ADC DC Electrical Characteristics (Operating)........................................A-64 ADC AC Characteristics (Operating).............................................................A-65 Low Voltage ADC Conversion Characteristics (Operating) ...........................A-66 ADC Conversion Characteristics (Operating)................................................A-67 M68HC16 Z-Series Ordering Information........................................................B-8 Module Address Map ......................................................................................D-1 SIM Address Map............................................................................................D-4 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF TABLES Table D-3 D-4 D-5 D-6 D-7 D-8 D-9 D-10 D-11 D-12 D-13 D-14 D-15 D-16 D-17 D-18 D-19 D-20 D-21 D-22 D-23 D-24 D-25 D-26 D-27 D-28 D-29 D-30 D-31 D-32 D-33 D-34 D-35 D-36 D-37 D-38 D-39 D-40 D-41 D-42 D-43 (Continued) Title Page Show Cycle Enable Bits ..................................................................................D-6 Port E Pin Assignments.................................................................................D-10 Port F Pin Assignments.................................................................................D-11 Software Watchdog Divide Ratio...................................................................D-12 Bus Monitor Time-Out Period........................................................................D-13 Pin Assignment Field Encoding.....................................................................D-16 CSPAR0 Pin Assignments ............................................................................D-16 CSPAR1 Pin Assignments ............................................................................D-17 Reset Pin Function of CS[10:6] .....................................................................D-17 Block Size Field Bit Encoding........................................................................D-18 BYTE Field Bit Encoding ...............................................................................D-19 Read/Write Field Bit Encoding ......................................................................D-19 DSACK Field Encoding .................................................................................D-20 Memory Access Times at 16.78, 20.97, and 25.17 MHz...............................D-20 Address Space Bit Encodings .......................................................................D-21 Interrupt Priority Level Field Encoding ..........................................................D-21 SRAM Address Map......................................................................................D-23 SRAM Array Address Space Type ................................................................D-23 MRM Address Map........................................................................................D-25 ROM Array Space Field ................................................................................D-26 Wait States Field ...........................................................................................D-26 ADC Module Address Map............................................................................D-29 Freeze Encoding ...........................................................................................D-30 Sample Time Selection .................................................................................D-31 Prescaler Output ...........................................................................................D-32 ADC Conversion Mode..................................................................................D-33 Single-Channel Conversions (MULT = 0)......................................................D-34 Multiple-Channel Conversions (MULT = 1) ...................................................D-35 QSM Address Map ........................................................................................D-38 Examples of SCI Baud Rates........................................................................D-41 PQSPAR Pin Assignments............................................................................D-45 Effect of DDRQS on QSM Pin Function ........................................................D-46 Bits Per Transfer ...........................................................................................D-47 Examples of SCK Frequencies .....................................................................D-48 MCCI Address Map .......................................................................................D-54 Interrupt Vector Sources ...............................................................................D-56 MPAR Pin Assignments ................................................................................D-57 Effect of MDDR on MCCI Pin Function .........................................................D-58 Examples of SCI Baud Rates........................................................................D-60 GPT Address Map.........................................................................................D-67 GPT Interrupt Sources ..................................................................................D-69 M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. LIST OF TABLES Table D-44 D-45 D-46 D-47 D-48 D-49 D-50 (Continued) Title Page PAMOD and PEDGE Effects.........................................................................D-71 PACLK[1:0] Effects........................................................................................D-71 OM/OL[5:2] Effects........................................................................................D-72 EDGE[4:1] Effects .........................................................................................D-72 CPR[2:0]/Prescaler Select Field....................................................................D-73 PPR[2:0] Field ...............................................................................................D-75 PWM Frequency Ranges ..............................................................................D-76 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SECTION 1 INTRODUCTION M68HC16 Z-series microcontrollers (including the MC68HC16Z1, MC68CM16Z1, MC68CK16Z1, MC68HC16Z2, MC68HC16Z3, MC68HC16Z4, and MC68CK16Z4) are high-speed 16-bit control units that are upwardly code compatible with M68HC11 controllers. All are members of the M68HC16 Family of modular microcontrollers. M68HC16 microcontroller units (MCUs) are built from standard modules that interface via a common internal bus. Standardization facilitates rapid development of devices tailored for specific applications. M68HC16 Z-series MCUs incorporate a number of different modules. Refer to Table 1-1 for information on the contents of a specific Z-series MCU. (X) indicates that the module is used in the MCU. All of these modules are interconnected by the intermodule bus (IMB). Table 1-1 M68HC16 Z-Series MCUs Modules Central Processor Unit (CPU16) Low-Power Central Processor Unit (CPU16L) System Integration Module (SIM) Low-Power System Integration Module (SIML) Standby RAM (SRAM) Masked ROM Module (MRM) Analog-to-Digital Converter (ADC) Queued Serial Module (QSM) Multichannel Communication Interface (MCCI) General-Purpose Timer (GPT) MC68HC16Z1 MC68CK16Z11 MC68CM16Z11 X — X — 1 Kbyte — X X — X MC68HC16Z2 X — X — 2 Kbytes 8 Kbytes X X — X MC68HC16Z3 X — X — 4 Kbytes 8 Kbytes X X — X MC68HC16Z4 MC68CK16Z41 — X — X 1 Kbyte — X — X X Freescale Semiconductor, Inc... NOTES: 1. “C” designator indicates a 2.7V to 3.6V part; “M” indicates a fast reference frequency and “K” indicates a slow reference frequency. “HC” stands for HCMOS. The maximum system clock for M68HC16 Z-series MCUs can be either 16.78 MHz, 20.97 MHz, or 25.17 MHz. An internal phase-locked loop circuit synthesizes the system clock from a slow (typically 32.768 kHz) or fast (typically 4.194 MHz) reference, or uses an external frequency source. Refer to Table 1-2 for information on which reference frequency is applied to a particular MCU. (X) indicates the reference frequency applicable to the MCU. M68HC16 Z SERIES USER’S MANUAL INTRODUCTION For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc. Table 1-2 Z-Series MCU Reference Frequencies Nominal Reference Frequency1 MCU MC68HC16Z1 MC68CM16Z1 MC68CK16Z1 MC68HC16Z2 MC68HC16Z3 MC68HC16Z4 MC68CK16Z4 Slow (32.768 kHz) X — X — — X X Fast (4.194 MHz) — X — X X — — Freescale Semiconductor, Inc... NOTES: 1. The nominal slow reference frequency is 32.768 kHz, but can range from 20 to 50 kHz. The nominal fast reference frequency is 4.194 MHz, but can range from 1MHz to 6.25 MHz. System hardware and software allow changes in clock rate during operation. Because the MCUs are a fully static design, register and memory contents are not affected by clock rate changes. High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power consumption low. Power consumption can be minimized by stopping the system clocks. The M68HC16 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this capability. Individual stop bits in each module allow for selective power reduction. Documentation for the Modular Microcontroller Family follows the modular construction of the devices in the product line. Each device has a comprehensive user’s manual that provides sufficient information for normal operation of the device. The user’s manual is supplemented by module reference manuals that provide detailed information about module operation and applications. Refer to Freescale publication Advanced Microcontroller Unit (AMCU) Literature (BR1116/D) for a complete list of documentation to supplement this manual. INTRODUCTION 1-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 2 NOMENCLATURE The following tables show the nomenclature used throughout the M68HC16 Z-series manual. 2.1 Symbols and Operators Symbol + Function Addition Subtraction (two’s complement) or negation Multiplication Division Greater Less Equal Equal or greater Equal or less Not equal AND Inclusive OR (OR) Exclusive OR (EOR) Complementation Concatenation Transferred Exchanged Sign bit; also used to show tolerance Sign extension Binary value Hexadecimal value Freescale Semiconductor, Inc... * / > < = ≥ ≤ ≠ • ' ⊕ NOT : ⇒ ⇔ ± « % $ M68HC16 Z SERIES USER’S MANUAL NOMENCLATURE For More Information On This Product, Go to: www.freescale.com 2-1 Freescale Semiconductor, Inc. 2.2 CPU16 Register Mnemonics Mnemonic A AM B CCR D E EK HR IR IX Register Accumulator A Accumulator M Accumulator B Condition code register Accumulator D Accumulator E Extended addressing extension field MAC multiplier register MAC multiplicand register Index register X Index register Y Index register Z Address extension register Program counter Program counter extension field Stack pointer extension field Stack pointer Index register X extension field Index register Y extension field Index register Z extension field Modulo addressing index register X mask Modulo addressing index register Y mask LPSTOP mode control bit AM overflow flag Half carry flag AM extended overflow flag Negative flag Zero flag Two’s complement overflow flag Carry/borrow flag Interrupt priority field Saturation mode control bit Freescale Semiconductor, Inc... IY IZ K PC PK SK SP XK YK ZK XMSK YMSK S MV H EV N Z V C IP SM NOMENCLATURE 2-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 2.3 Register Mnemonics Mnemonic ADCMCR ADCTEST ADCTL[0:1] ADCSTAT CFORC CREG CR[0:F] CSBARBT CSBAR[0:10] CSORBT Register ADC Module Configuration Register ADC Test Register ADC Control Registers [0:1] ADC Status Register GPT Compare Force Register SIM Test Module Control Register QSM Command RAM [0:F] SIM Chip-Select Base Address Register Boot SIM Chip-Select Base Address Registers [0:10] SIM Chip-Select Option Register Boot SIM Chip-Select Option Registers [0:10] SIM Chip-Select Pin Assignment Registers [0:1] SIM Port E Data Direction Register SIM Port F Data Direction Register GPT Port GP Data Direction Register MCCI Data Direction Register QSM Port QS Data Direction Register SIM Test Module Distributed Register GPT Module Configuration Register GPT Module Test Register GPT Interrupt Configuration Register MCCI SCI Interrupt Register MCCI SPI Interrupt Register ADC Left-Justified Signed Result Registers [0:7] ADC Left-Justified Unsigned Result Registers [0:7] MCCI Interrupt Vector Register MCCI Module Configuration Register MCCI Pin Assignment Register Masked ROM Module Configuration Register MCCI Test Register GPT Output Compare 1 Action Data Register GPT Output Compare 1 Action Mask Register GPT Pulse Accumulator Counter Register GPT Pulse Accumulator Control Register SIM Port E Pin Assignment Register SIM Port F Pin Assignment Register Freescale Semiconductor, Inc... CSOR[0:10] CSPAR[0:1] DDRE DDRF DDRGP DDRM DDRQS DREG GPTMCR GPTMTR ICR ILSCI ILSPI LJSRR[0:7] LJURR[0:7] MIVR MMCR MPAR MRMCR MTEST OC1D OC1M PACNT PACTL PEPAR PFPAR M68HC16 Z SERIES USER’S MANUAL NOMENCLATURE For More Information On This Product, Go to: www.freescale.com 2-3 Freescale Semiconductor, Inc. Mnemonic PICR PITR PORTADA PORTC PORTE PORTF PORTGP PORTMC PORTMCP PORTQS PQSPAR PRESCL PWMA PWMB PWMBUFA PWMBUFB PWMC PWMCNT QILR QIVR QSMCR QTEST RAMBAH RAMBAL RAMMCR RAMTST RJURR[0:7] ROMBAH ROMBAL ROMBS[0:3] RR[0:F] RSR SCCR[0:1] SCCR0[A:B] SCCR1[A:B] SCDR SCDR[A:B] Register SIM Periodic Interrupt Control Register SIM Periodic Interrupt Timer Register ADC Port ADA Data Register SIM Port C Data Register SIM Port E Data Register [0:1] SIM Port F Data Register [0:1] GPT Port GP Data Register MCCI Port Data Register MCCI Port Pin State Register QSM Port QS Data Register QSM Port QS Pin Assignment Register GPT Prescaler Register GPT PWM Control Register A GPT PWM Control Register B GPT PWM Buffer Register A GPT PWM Buffer Register B GPT PWM Control Register C GPT PWM Counter Register QSM Interrupt Level Register QSM Interrupt Vector Register QSM Module Configuration Register QSM Test Register RAM Array Base Address Register High RAM Array Base Address Register Low RAM Module Configuration Register RAM Test Register ADC Right-Justified Unsigned Result Registers [0:7] ROM Array Base Address Register High ROM Array Base Address Register Low ROM Bootstrap Word Registers [0:3] QSM Receive Data RAM [0:F] SIM Reset Status Register QSM SCI Control Registers [0:1] MCCI SCIA/B Control Registers 0 [A:B] MCCI SCIA/B Control Registers 1 [A:B] QSM SCI Data Register MCCI SCIA/B Data Registers [A:B] Freescale Semiconductor, Inc... NOMENCLATURE 2-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Mnemonic SCSR SCSR[A:B] SIGHI SIGLO SIMCR SIMTR SIMTRE SPCR SPCR[0:3] SPDR SPSR SPSR SWSR SYNCR SYPCR TCNT TCTL[1:2] TFLG[1:2] TI4/O5 TIC[1:3] TMSK[1:2] TOC[1:4] TR[0:F] TSTMSRA TSTMSRB TSTRC TSTSC Register QSM SCI Status Register MCCI SCIA/B Status Registers [A:B] ROM Signature Register High ROM Signature Register Low SIM Module Configuration Register SIM Test Register SIM Test Register E MCCI SPI Control Register QSM SPI Control Registers [0:3] MCCI SPI Data Register QSM SPI Status Register MCCI SPI Status Register SIM Software Watchdog Service Register SIM Clock Synthesizer Control Register SIM System Protection Control Register GPT Timer Counter Register GPT Timer Control Registers [1:2] GPT Timer Flag Registers [1:2] GPT Timer Input Capture 4/Output Compare 5 Register GPT Timer Input Capture Registers [1:3] GPT Timer Mask Register [1:2] GPT Timer Output Compare Registers [1:4] QSM Transmit RAM [0:F] SIM Test Module Master Shift Register A SIM Test Module Master Shift Register B SIM Test Module Repetition Count Register SIM Test Module Shift Count Register Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL NOMENCLATURE For More Information On This Product, Go to: www.freescale.com 2-5 Freescale Semiconductor, Inc. 2.4 Conventions Logic level one is the voltage that corresponds to a Boolean true (1) state. Logic level zero is the voltage that corresponds to a Boolean false (0) state. Set refers specifically to establishing logic level one on a bit or bits. Clear refers specifically to establishing logic level zero on a bit or bits. Asserted means that a signal is in active logic state. An active low signal changes from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one. Negated means that an asserted signal changes logic state. An active low signal changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero. A specific mnemonic within a range is referred to by mnemonic and number. A15 is bit 15 of accumulator A; ADDR7 is line 7 of the address bus; CSOR0 is chip-select option register 0. A range of mnemonics is referred to by mnemonic and the numbers that define the range. VBR[4:0] are bits four to zero of the vector base register; CSOR[0:5] are the first six chip-select option registers. Parentheses are used to indicate the content of a register or memory location, rather than the register or memory location itself. For example, (A) is the content of accumulator A. (M : M + 1) is the content of the word at address M. LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes are spelled out. LSW means least significant word or words. MSW means most significant word or words. ADDR is the address bus. ADDR[7:0] are the eight LSB of the address bus. DATA is the data bus. DATA[15:8] are the eight MSB of the data bus. Freescale Semiconductor, Inc... NOMENCLATURE 2-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 3 OVERVIEW This section provides general information on M68HC16 Z-series MCUs. It lists features of each of the modules, shows device functional divisions and pin assignments, summarizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. Timing and electrical specifications for the entire microcontroller and for individual modules are provided in APPENDIX A ELECTRICAL CHARACTERISTICS. Comprehensive module register descriptions and memory maps are provided in APPENDIX D REGISTER SUMMARY. Freescale Semiconductor, Inc... 3.1 M68HC16 Z-Series MCU Features The following paragraphs highlight capabilities of each of the MCU modules. Each module is discussed separately in a subsequent section of this manual. 3.1.1 Central Processor Unit (CPU16/CPU16L) • 16-bit architecture • Full set of 16-bit instructions • Three 16-bit index registers • Two 16-bit accumulators • Control-oriented digital signal processing capability • Addresses up to 1 Mbyte of program memory; 1 Mbyte of data memory • Background debug mode • Fully static operation • Expanded LPSTOP operation on CPU16L (MC68HC16Z4, MC68CK16Z4 only) 3.1.2 System Integration Module (SIM/SIML) • External bus support • Programmable chip-select outputs • System protection logic • Watchdog timer, clock monitor, and bus monitor • Two 8-bit dual function input/output ports • One 7-bit dual function output port • Phase-locked loop (PLL) clock system • Expanded LPSTOP operation on SIML (MC68HC16Z4, MC68CK16Z4 only) 3.1.3 Standby RAM (SRAM) • 1-Kbyte static RAM (MC68HC16Z1/Z4 only) • 2-Kbyte static RAM (MC68HC16Z2 only) • 4-Kbyte static RAM (MC68HC16Z3 only) • External standby voltage supply input M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-1 Freescale Semiconductor, Inc. 3.1.4 Masked ROM Module (MRM) — (MC68HC16Z2/Z3 Only) • 8-Kbyte array, accessible as bytes or words • User-selectable default base address • User-selectable bootstrap ROM function • User-selectable ROM verification code 3.1.5 Analog-to-Digital Converter (ADC) • Eight channels, eight result registers • Eight automated modes • Three result alignment modes 3.1.6 Queued Serial Module (QSM) • Enhanced serial communication interface • Queued serial peripheral interface • One 8-bit dual function port 3.1.7 Multichannel Communication Interface (MCCI) — (MC68HC16Z4/CKZ4 Only) • Two channels of enhanced SCI (UART) • One channel of SPI 3.1.8 General-Purpose Timer (GPT) • Two 16-bit free-running counters with prescaler • Three input capture channels • Four output compare channels • One input capture/output compare channel • One pulse accumulator/event counter input • Two pulse width modulation outputs • Optional external clock input 3.2 Intermodule Bus The intermodule bus (IMB) is a standardized bus developed to facilitate the design of modular microcontrollers. It contains circuitry that supports exception processing, address space partitioning, multiple interrupt levels, and vectored interrupts. The standardized modules in M68HC16 Z-series MCUs communicate with one another via the IMB. Although the full IMB supports 24 address and 16 data lines, M68HC16 Z-series MCUs use only 20 address lines. ADDR[23:20] follow the state of ADDR19. 3.3 System Block Diagram and Pin Assignment Diagrams Figure 3-1 is a functional diagram of the MC68HC16Z1/CKZ1/CMZ1 MCU. Refer to Figure 3-2 for a functional diagram of the MC68HC16Z2/Z3 MCU. Figure 3-3 is a functional diagram of the MC68HC16Z4/CKZ4 MCU. Although diagram blocks represent the relative size of the physical modules, there is not a one-to-one correspondence between location and size of blocks in the diagram and location and size of integrated-circuit modules. Freescale Semiconductor, Inc... OVERVIEW 3-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. M68HC16 Z-series microcontrollers are available in both 132- and 144-pin packages. Figure 3-4 shows an MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 pin assignment drawing based on a 132-pin plastic surface-mount package. Figure 3-5 shows an MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 pin assignment drawing based on a 144-pin plastic surface-mount package. Figure 3-6 shows an MC68HC16Z4/CKZ4 pin assignment drawing based on a 132-pin plastic surface-mount package. Figure 3-7 shows an MC68HC16Z4/CKZ4 pin assignment drawing based on a 144-pin plastic surfacemount package. Refer to APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION for information on how to obtain package dimensions. Refer to subsequent paragraphs in this section for pin and signal descriptions. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-3 Freescale Semiconductor, Inc. PWMA PWMB PCLK PAI IC4/OC5/OC1/PGP7 OC4/OC1/PGP6 OC3/OC1/PGP5 OC2/OC1/PGP4 OC1/PGP3 IC3/PGP2 IC2/PGP1 IC1/PGP0 RXD TXD/PQS7 PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS/PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 TXD PCS3 PCS2 PCS1 PCS0 SCK MOSI MISO IC4/OC5/OC1 OC4/OC1 OC3/OC1 OC2/OC1 OC1 IC3 IC2 IC1 CSBOOT CHIP SELECT GPT CS[10:0] ECLK BGACK BG BR FC2 FC1 FC0 ADDR[23:19] SIM ADDR23/CS10/ECLK ADDR22/CS9/PC6 ADDR21/CS8/PC5 ADDR20/CS7/PC4 ADDR19/CS6/PC3 FC2/CS5/PC2 FC1/CS4/PC1 FC0/CS3/PC0 BGACK/CS2 BG/CS1 BR/CS0 PORT GP CONTROL CONTROL PORT C Freescale Semiconductor, Inc... PORT QS CONTROL ADDR[18:0] QSM EBI VDD VSS VDDA VSSA AN7/PADA7 AN6/PADA6 AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 VRH VRL AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 IMB SIZ1 SIZ0 AS DS PE3 AVEC DSACK1 DSACK0 CONTROL PORT E SIZ1/PE7 SIZ0/PE6 AS/PE5 DS/PE4 AVEC/PE2 DSACK1/PE1 DSACK0/PE0 DATA[15:0] R/W RESET HALT BERR IRQ7/PF7 IRQ6/PF6 IRQ5/PF5 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 MODCLK/PF0 CLKOUT XTAL EXTAL XFC VDDSYN ADC PORT AD CONTROL 1K SRAM CPU16 IRQ[7:1] CONTROL PORT F MODCLK CLOCK TEST FREEZE CONTROL TSC QUOT BKPT/DSCLK IPIPE1/DSI IPIPE0/DSO VSTBY BKPT IPIPE0 IPIPE1 DSI DSO DSCLK CONTROL TSC FREEZE/QUOT HC16Z1/CKZ1/CMZ1 BLOCK Figure 3-1 MC68HC16Z1/CK16Z1/CM16Z1 Block Diagram OVERVIEW 3-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. PWMA PWMB PCLK PAI IC4/OC5/OC1/PGP7 OC4/OC1/PGP6 OC3/OC1/PGP5 OC2/OC1/PGP4 OC1/PGP3 IC3/PGP2 IC2/PGP1 IC1/PGP0 RXD TXD/PQS7 PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS/PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 TXD PCS3 PCS2 PCS1 PCS0 SCK MOSI MISO IC4/OC5/OC1 OC4/OC1 OC3/OC1 OC2/OC1 OC1 IC3 IC2 IC1 CSBOOT CHIP SELECT GPT CS[10:0] ECLK BGACK BG BR FC2 FC1 FC0 ADDR[23:19] SIM ADDR23/CS10/ECLK ADDR22/CS9/PC6 ADDR21/CS8/PC5 ADDR20/CS7/PC4 ADDR19/CS6/PC3 FC2/CS5/PC2 FC1/CS4/PC1 FC0/CS3/PC0 BGACK/CS2 BG/CS1 BR/CS0 PORT GP CONTROL CONTROL PORT C Freescale Semiconductor, Inc... PORT QS CONTROL ADDR[18:0] QSM EBI VDD VSS VDDA VSSA AN7/PADA7 AN6/PADA6 AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 VRH VRL AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 IMB SIZ1 SIZ0 AS DS PE3 AVEC DSACK1 DSACK0 CONTROL PORT E SIZ1/PE7 SIZ0/PE6 AS/PE5 DS/PE4 AVEC/PE2 DSACK1/PE1 DSACK0/PE0 DATA[15:0] R/W RESET HALT BERR IRQ7/PF7 IRQ6/PF6 IRQ5/PF5 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 MODCLK/PF0 CLKOUT XTAL EXTAL XFC VDDSYN ADC SRAM MRM 2K/Z2 4K/Z3 CPU16 PORT AD CONTROL IRQ[7:1] CONTROL PORT F MODCLK CLOCK TEST FREEZE CONTROL TSC QUOT BKPT/DSCLK IPIPE1/DSI IPIPE0/DSO VSTBY BKPT IPIPE0 IPIPE1 DSI DSO DSCLK CONTROL TSC FREEZE/QUOT Z2/Z3 BLOCK Figure 3-2 MC68HC16Z2/Z3 Block Diagram M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-5 Freescale Semiconductor, Inc. PWMA PWMB PCLK PAI IC4/OC5/OC1/PGP7 OC4/OC1/PGP6 OC3/OC1/PGP5 OC2/OC1/PGP4 OC1/PGP3 IC3/PGP2 IC2/PGP1 IC1/PGP0 IC4/OC5/OC1 OC4/OC1 OC3/OC1 OC2/OC1 OC1 IC3 IC2 IC1 CSBOOT CHIP SELECT GPT CS[10:0] ECLK BGACK BG BR FC2 FC1 FC0 ADDR[23:19] SIML Freescale Semiconductor, Inc... EBI CONTROL PORT E TXDA/PMC7 RXDA/PMC6 TXDB/PMC5 RXDB/PMC4 SS/PMC3 SCK/PMC2 MOSI/PMC1 MISO/PMC0 TXDA RXDA TXDB RXDB SS SCK MOSI MISO ADDR23/CS10/ECLK ADDR22/CS9/PC6 ADDR21/CS8/PC5 ADDR20/CS7/PC4 ADDR19/CS6/PC3 FC2/CS5/PC2 FC1/CS4/PC1 FC0/CS3/PC0 BGACK/CS2 BG/CS1 BR/CS0 PORT GP CONTROL CONTROL PORT C PORT MCCI CONTROL ADDR[18:0] MCCI VDD VSS VDDA VSSA AN7/PADA7 AN6/PADA6 AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 VRH VRL AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 IMB SIZ1 SIZ0 AS DS PE3 AVEC DSACK1 DSACK0 SIZ1/PE7 SIZ0/PE6 AS/PE5 DS/PE4 AVEC/PE2 DSACK1/PE1 DSACK0/PE0 DATA[15:0] R/W RESET HALT BERR IRQ7/PF7 IRQ6/PF6 IRQ5/PF5 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 MODCLK/PF0 CLKOUT XTAL EXTAL XFC VDDSYN ADC PORT AD CONTROL 1K SRAM CPU16L IRQ[7:1] CONTROL PORT F MODCLK CLOCK TEST FREEZE CONTROL TSC QUOT BKPT/DSCLK IPIPE1/DSI IPIPE0/DSO VSTBY BKPT IPIPE0 IPIPE1 DSI DSO DSCLK CONTROL TSC FREEZE/QUOT HC16Z4/CK16Z4 BLOCK Figure 3-3 MC68HC16Z4/CK16Z4 Block Diagram OVERVIEW 3-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. RXD PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS/PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 VSS VDD IC1/PGP0 IC2/PGP1 IC3/PGP2 OC1/PGP3 OC2/OC1/PGP4 VSS VDD OC3/OC1/PGP5 OC4/OC1/PGP6 IC4/OC5/OC1/PGP7 PAI PWMA PWMB PCLK VSS VDD ADDR23/CS10/ECLK ADDR22/CS9/PC6 ADDR21/CS8/PC5 ADDR20/CS7/PC4 ADDR19/CS6/PC3 BGACK/CS2 BG/CS1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 Freescale Semiconductor, Inc... TXD/PQS7 ADDR1 ADDR2 VDD VSS ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 VSS ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 VDD VSS VDDA VSSA AN0/PADA0 AN1/PADA1 AN2/PADA2 AN3/PADA3 AN4/PADA4 AN5/PADA5 VRH 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 MC68HC16Z3 MMMMM1 ATWLYYWW2 BR/CS0 FC2/CS5/PC2 FC1/CS4/PC1 VDD VSS FC0/CS3/PC0 CSBOOT DATA0 DATA1 DATA2 DATA3 VSS DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 VDD VSS DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ADDR0 DSACK0/PE0 DSACK1/PE1 AVEC/PE2 DS/PE4 AS/PE5 VDD NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK Figure 3-4 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package M68HC16 Z SERIES USER’S MANUAL VRL AN6/PADA6 AN7/PADA7 VSTBY XTAL VDDSYN EXTAL VSS VDD XFC VDD VSS CLKOUT FREEZE/QUOT TSC BKPT/DSCLK IPIPE0/DSO IPIPE1/DSI RESET HALT BERR IRQ7/PF7 IRQ6/PF6 IRQ5/PF5 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 MODCLK/PF0 R/W SIZ1/PE7 SIZ0/PE6 VSS HC16Z1/CKZ1/CMZ1/Z2/Z3 132-PIN QFP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-7 Freescale Semiconductor, Inc. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VSS SIZ0/PE6 SIZ1/PE7 R/W MODCLK/PF0 IRQ1/PF1 IRQ2/PF2 IRQ3/PF3 IRQ4/PF4 IRQ5/PF5 IRQ6/PF6 IRQ7/PF7 BERR HALT RESET IPIPE1/DSI IPIPE0/DSO BKPT/DSCLK NC TSC FREEZE/QUOT CLKOUT VSS VDD XFC NC VDD VSS EXTAL VDDSYN XTAL VSTBY AN7/PADA7 AN6/PADA6 VRLP NC Freescale Semiconductor, Inc... VDD AS/PE5 DS/PE4 AVEC/PE2 DSACK1/PE1 DSACK0/PE0 ADDR0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 VSS NC VDD DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 NC VSS NC DATA3 DATA2 DATA1 DATA0 CSBOOT FC0/CS3/PC0 VSS VDD FC1/CS4/PC1 FC2/CS5/PC2 BR/CS0 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 MC68HC16Z3 MMMMM1 ATWLYYWW2 VRHP AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 VSSA VDDA VSS VDD ADDR18 ADDR17 ADDR16 ADDR15 NC ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 NC VSS NC ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 VSS VDD ADDR2 ADDR1 TXD/PQS7 NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK Figure 3-5 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 144-Pin Package 3-8 NC BG/CS1 BGACK/CS2 ADDR19/CS6/PC5 ADDR20/CS7/PC4 ADDR21/CS8/PC5 ADDR22/CS9/PC6 ADDR23/CS10 VDD VSS PCLK PWMB PWMA PAI IC4/OC5/OC1/PGP7 OC4/OC1/PGP6 OC3/OC1/PCP5 NC VDD VSS OC2/PGP4 OC1/PGP3 IC3/PGP2 IC2/PGP1 IC1/PGP0 VDD VSS MISO/PQS0 MOSI/PQS1 SCK/PQS2 PCS0/SS/PQS3 PCS1/PQS4 PCS2/PQS5 PCS3/PQS6 RXD NC HC16Z1/CKZ1/CMZ1/Z2/Z3 144-PIN QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 OVERVIEW For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. NC RXDA/PMC6 TXDB/PMC5 RXDB/PMC4 SS/PMC3 SCK/PMC2 MOSI/PMC1 MISO/PMC0 VSS VDD IC1/PGP0 IC2/PGP1 IC3/PGP2 OC1/PGP3 OC2/OC1/PGP4 VSS VDD OC3/OC1/PGP5 OC4/OC1/PGP6 IC4/OC5/OC1/PGP7 PAI PWMA PWMB PCLK VSS VDD ADDR23/CS10/ECLK ADDR22/CS9/PC6 ADDR21/CS8/PC5 ADDR20/CS7/PC4 ADDR19/CS6/PC3 BGACK/CS2 BG/CS1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 Freescale Semiconductor, Inc... TXDA/PMC7 ADDR1 ADDR2 VDD VSS ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 VSS ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 VDD VSS VDDA VSSA AN0/PADA0 AN1/PADA1 AN2/PADA2 AN3/PADA3 AN4/PADA4 AN5/PADA5 VRH 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MC68HC16Z4 MC68CK16Z4 MMMMM1 ATWLYYWW2 BR/CS0 FC2/CS5/PC2 FC1/CS4/PC1 VDD VSS FC0/CS3/PC0 CSBOOT DATA0 DATA1 DATA2 DATA3 VSS DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 VDD VSS DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ADDR0 DSACK0/PE0 DSACK1/PE1 AVEC/PE2 DS/PE4 AS/PE5 VDD NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK VRL AN6/PADA6 AN7/PADA7 VSTBY XTAL VDDSYN EXTAL VSS VDD XFC VDD VSS CLKOUT FREEZE/QUOT TSC BKPT/DSCLK IPIPE0/DSO IPIPE1/DSI RESET HALT BERR IRQ7/PF7 IRQ6/PF6 IRQ5/PF5 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 MODCLK/PF0 R/W SIZ1/PE7 SIZ0/PE6 VSS HC16Z4/CK16Z4 132-PIN QFP Figure 3-6 MC68HC16Z4/CKZ4 Pin Assignments for 132-Pin Package M68HC16 Z SERIES USER’S MANUAL 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-9 Freescale Semiconductor, Inc. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VSS SIZ0/PE6 SIZ1/PE7 R/W MODCLK/PF0 IRQ1/PF1 IRQ2/PF2 IRQ3/PF3 IRQ4/PF4 IRQ5/PF5 IRQ6/PF6 IRQ7/PF7 BERR HALT RESET IPIPE1/DSI IPIPE0/DSO BKPT/DSCLK NC TSC FREEZE/QUOT CLKOUT VSS VDD XFC NC VDD VSS EXTAL VDDSYN XTAL VSTBY AN7/PADA7 AN6/PADA6 VRLP NC Freescale Semiconductor, Inc... VDD AS/PE5 DS/PE4 AVEC/PE2 DSACK1/PE1 DSACK0/PE0 ADDR0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 VSS NC VDD DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 NC VSS NC DATA3 DATA2 DATA1 DATA0 CSBOOT FC0/CS3/PC0 VSS VDD FC1/CS4/PC1 FC2/CS5/PC2 BR/CS0 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 MC68HC16Z4 MC68CK16Z4 MMMMM1 ATWLYYWW2 VRHP AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 VSSA VDDA VSS VDD ADDR18 ADDR17 ADDR16 ADDR15 NC ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 NC VSS NC ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 VSS VDD ADDR2 ADDR1 TXDA/PMC7 NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK NC BG/CS1 BGACK/CS2 ADDR19/CS6/PC5 ADDR20/CS7/PC4 ADDR21/CS8/PC5 ADDR22/CS9/PC6 ADDR23/CS10 VDD VSS PCLK PWMB PWMA PAI IC4/OC5/OC1/PGP7 OC4/OC1/PGP6 OC3/OC1/PCP5 NC VDD VSS OC2/PGP4 OC1/PGP3 IC3/PGP2 IC2/PGP1 IC1/PGP0 VDD VSS MISO/PMC0 MOSI/PMC1 SCK/PMC2 SS/PMC3 RXDB/PMC4 TXDB/PMC5 NC RXDA/PMC6 NC HC16Z4/CK16Z4 144-PIN QFP Figure 3-7 MC68HC16Z4/CKZ4 Pin Assignments for 144-Pin Package 3-10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 OVERVIEW For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 3.4 Pin Descriptions The following tables are a summary of the functional characteristics of M68HC16 Zseries MCU pins. Table 3-1 shows all inputs and outputs. Digital inputs and outputs use CMOS logic levels. An entry in the “Discrete I/O” column indicates that a pin can also be used for general-purpose input, output, or both. The I/O port designation is given when it applies. Refer to Figure 3-1 for port organization. Table 3-2 shows types of output drivers. Table 3-3 shows characteristics of power pins. Table 3-1 M68HC16 Z-Series Pin Characteristics Pin Mnemonic ADDR23/CS10/ECLK ADDR[22:19]/CS[9:6] ADDR[18:0] AN[7:0]1 AS AVEC BERR BG/CS1 BGACK/CS2 BKPT/DSCLK BR/CS0 CLKOUT CSBOOT DATA[15:0]1 DS DSACK[1:0] DSI/IPIPE1 DSO/IPIPE0 EXTAL 2 Output Driver A A A — B B B B B — B A B AW B B A A — A A Bo A A B Bo Bo B Bo Bo A — Input Synchronized Y Y Y Y Y Y Y — Y Y Y — — Y Y Y Y — — Y — Y Y Y Y Y Y Y Y Y Y Y Input Hysteresis N N N N Y N N — N Y N — — N Y N Y — Special N — N Y Y Y Y Y N Y Y Y Y Discrete I/O O O — I I/O I/O — — — — O — — — I/O I/O — — — O — — I/O I/O I/O I/O I/O I/O I/O I/O I/O I Port Designation — PC[6:3] — PADA[7:0] PE5 PE2 — — — — — — — — PE4 PE[1:0] — — — PC[2:0] — — PGP7 PGP[2:0] PF[7:1] PQS0 PMC0 PF0 PQS1 PMC1 PGP[6:3] — Freescale Semiconductor, Inc... FC[2:0]/CS[5:3] FREEZE/QUOT HALT IC4/OC5 IC[3:1] IRQ[7:1] MISO MISO3 MODCLK1 MOSI MOSI3 OC[4:1] PAI4 M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-11 Freescale Semiconductor, Inc. Table 3-1 M68HC16 Z-Series Pin Characteristics (Continued) Pin Mnemonic PCLK4 PCS0/SS PCS[3:1] PWMA, PWMB5 R/W RESET RXD RXDA 3 Output Driver — Bo Bo A A Bo — Bo Bo Bo Bo B Bo — Bo Bo Bo — — Input Synchronized Y Y Y — Y Y N Y Y Y Y Y Y Y Y Y Y — — Input Hysteresis Y Y Y — N Y N Y Y Y Y Y Y Y Y Y Y — — Discrete I/O I I/O I/O O — — — — — — I/O I/O — — I/O — — Special Special Port Designation — PQS3 PQS[6:4] — — — — PMC6 PMC4 PMC2 PQS2 PE[7:6] PMC3 — PQS7 PMC7 PMC5 — — RXDB3 Freescale Semiconductor, Inc... SCK3 SCK SIZ[1:0] SS3 TSC TXD TXDA3 TXDB3 XFC2 XTAL2 NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK, QSM, MCCI and ADC pins are synchronized only when used as input port pins. 2. EXTAL, XFC, and XTAL are clock reference connections. 3. MCCI pins used only on the MC68HC16Z4/CK16Z4. 4. PAI and PCLK can be used for discrete input, but are not part of an I/O port. 5. PWMA and PWMB can be used for discrete output, but are not part of an I/O port. Table 3-2 M68HC16 Z-Series Driver Types Type A Aw B Bo I/O O O O O Three-state capable output signals Type A output with weak p-channel pull-up during reset Three-state output that includes circuitry to pull up output before high impedance is established, to ensure rapid rise time Type B output that can be operated in an open-drain mode Description OVERVIEW 3-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 3-3 M68HC16 Z-Series Power Connections Pin Mnemonic VSTBY VDDSYN VDDA/VSSA VRH/VRL VSS/VDD Description Standby RAM power Clock synthesizer power A/D converter power A/D reference voltage Microcontroller power Freescale Semiconductor, Inc... 3.5 Signal Descriptions The following tables define the M68HC16 Z-series MCU signals. Table 3-4 shows signal origin, type, and active state. Table 3-5 describes signal functions. Both tables are sorted alphabetically by mnemonic. MCU pins often have multiple functions. More than one description can apply to a pin. Table 3-4 M68HC16 Z-Series Signal Characteristics Signal Name ADDR[23:0] AN[7:0] AS AVEC BERR BG BGACK BKPT BR CLKOUT CS[10:0] CSBOOT DATA[15:0] DS DSACK[1:0] DSCLK DSI DSO EXTAL FC[2:0] FREEZE HALT IC[4:1] IPIPE0 IPIPE1 IRQ[7:1] MCU Module SIM ADC SIM SIM SIM SIM SIM CPU16 SIM SIM SIM SIM SIM SIM SIM CPU16 CPU16 CPU16 SIM SIM SIM SIM GPT CPU16 CPU16 SIM Signal Type Bus Input Output Input Input Output Input Input Input Output Output Output Bus Output Input Input Input Output Input Output Output Input/Output Input Output Output Input Active State — — 0 0 0 0 0 0 0 — 0 0 — 0 0 Serial Clock Serial Data Serial Data — — 1 0 — — — 0 M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-13 Freescale Semiconductor, Inc. Table 3-4 M68HC16 Z-Series Signal Characteristics (Continued) Signal Name MISO MISO1 MODCLK MOSI MOSI1 OC[5:1] PADA[7:0] PAI PC[6:0] PE[7:0] PF[7:0] PGP[7:0] PQS[7:0] PCLK PCS[3:0] PWMA, PWMB PMC[7:0] QUOT R/W RESET RXD RXDA1 RXDB1 SCK SCK1 SIZ[1:0] SS SS1 TSC TXD TXDA1 TXDB1 XFC XTAL 1 MCU Module QSM MCCI SIM QSM MCCI GPT ADC GPT SIM SIM SIM GPT QSM GPT QSM GPT MCCI SIM SIM SIM QSM MCCI MCCI QSM MCCI SIM QSM MCCI SIM QSM MCCI MCCI SIM SIM Signal Type Input/Output Input/Output Input Input/Output Input/Output Output Input Input Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Output Input/Output Output Output Input/Output Input Input Input Input/Output Input/Output Output Input Input Input Output Output Output Input Output Active State — — — — — — — — — — — — — — — — — — 1/0 0 — — — — — 1/0 0 0 1 — — — — — Freescale Semiconductor, Inc... NOTES: 1. Used only in the MC68HC16Z4/CK16Z4. OVERVIEW 3-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 3-5 M68HC16 Z-Series Signal Function Mnemonic ADDR[19:0] AN[7:0] AS AVEC BERR BG BGACK BKPT BR Signal Name Address Bus ADC Analog Input Address Strobe Autovector Bus Error Bus Grant Bus Grant Acknowledge Breakpoint Bus Request System Clockout Chip-Selects Boot Chip Select Data Bus Data Strobe Data and Size Acknowledge Development Serial In, Out, Clock Crystal Oscillator Function Codes Freeze Halt Interrupt Request Level Instruction Pipeline Master In Slave Out Master In Slave Out Clock Mode Select Master Out Slave In Master Out Slave In Port ADA Pulse Accumulator Input Auxiliary Timer Clock Port C Peripheral Chip Select Port E Inputs to ADC multiplexer Indicates that a valid address is on the address bus Requests an automatic vector during interrupt acknowledge Indicates that a bus error has occurred Indicates that the MCU has relinquished the bus Indicates that an external device has assumed bus mastership Signals a hardware breakpoint to the CPU Indicates that an external device requires bus mastership System clock output Select external devices at programmed addresses Chip select for external boot start-up ROM 16-bit data bus During a read cycle, indicates that an external device should place valid data on the data bus. During a write cycle, indicates that valid data is on the data bus. Provide asynchronous data transfers and dynamic bus sizing Serial I/O and clock for background debug mode Connections for clock synthesizer circuit reference a crystal or an external oscillator can be used Identify processor state and current address space Indicates that the CPU has entered background mode Suspend external bus activity Provides an interrupt priority level to the CPU Indicate instruction pipeline activity Serial input to QSPI in master mode; serial output from QSPI in slave mode Serial input to SPI in master mode; serial output from SPI in slave mode Selects the source and type of system clock Serial output from QSPI in master mode; serial input to QSPI in slave mode Serial output from SPI in master mode; serial input to SPI in slave mode ADC digital input port signals Input to the GPT pulse accumulator GPT external clock input Port C digital output port signals QSPI peripheral chip-selects Port E digital I/O port signals Function 20-bit address bus used by CPU16 Freescale Semiconductor, Inc... CLKOUT CS[10:0] CSBOOT DATA[15:0] DS DSACK[1:0] DSI, DSO, DSCLK EXTAL, XTAL FC[2:0] FREEZE HALT IRQ[7:1] IPIPE[1:0] MISO MISO1 MODCLK MOSI MOSI1 PADA[7:0] PAI PCLK PC[6:0] PCS[3:0] PE[7:0] M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-15 Freescale Semiconductor, Inc. Table 3-5 M68HC16 Z-Series Signal Function (Continued) Mnemonic PF[7:0] PGP[7:0] PQS[7:0] PWMA, PWMB QUOT R/W RESET RXD RXDA1 RXDB1 Signal Name Port F Port GP Port QS Pulse Width Modulation Quotient Out Read/Write Reset Receive Data (SCI) SCI A Receive Data SCI B Receive Data Serial Clock (QSPI) Serial Clock (SPI) Size Slave Select (QSPI) Slave Select (SPI) Three-State Control SCI Transmit Data 1 Function Port F digital I/O port signals GPT digital I/O port signals QSM digital I/O port signals Output for PWM Provides the quotient bit of the polynomial divider Indicates the direction of data transfer on the bus System reset Serial input to the SCI Serial input from SCI A Serial input from SCI B Clock output from QSPI in master mode; clock input to QSPI in slave mode Clock output from SPI in master mode; clock input to SPI in slave mode Indicates the number of bytes to be transferred during a bus cycle Causes serial transmission when QSPI is in slave mode; causes mode fault in master mode Causes serial transmission when the SPI is in slave mode; causes mode fault in master mode Places all output drivers in a high-impedance state Serial output from the SCI Serial output from SCI A Serial output from SCI B Connection for external phase-locked loop filter capacitor Freescale Semiconductor, Inc... SCK SCK1 SIZ[1:0] SS SS1 TSC TXD TXDA SCI A Transmit Data SCI B Transmit Data External Filter Capacitor TXDB1 XFC NOTES: 1. MCCI signals present only in MC68HC16Z4/CK16Z4. 3.6 Internal Register Map In Figures 3-8, 3-9, and 3-10, IMB ADDR[23:20] are represented by the letter Y. The value represented by Y determines the base address of MCU module control registers. Y is equal to M111, where M is the logic state of the module mapping (MM) bit in the system integration module configuration register (SIMCR). Since the CPU16 uses only ADDR[19:0], and ADDR[23:20] follow the logic state of ADDR19 when CPU driven, the CPU cannot access IMB addresses from $080000 to $F7FFFF. In order for the MCU to function correctly, MM must be set (Y must equal $F). If M is cleared, internal registers are mapped to base address $700000, and are inaccessible until a reset occurs. The SRAM array is positioned by a base address register in the SRAM CTRL block. Unimplemented blocks are mapped externally. OVERVIEW 3-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. $000000 $YFF700 $YFF73F ADC 64 BYTES $YFF900 $YFF93F $YFFA00 GPT 64 BYTES SIM 128 BYTES $YFFA7F $YFFB00 SRAM CONTROL 8 BYTES 1K SRAM ARRAY (MAPPED TO 1K BOUNDARY) Freescale Semiconductor, Inc... $YFFB07 $YFFC00 QSM 512 BYTES $YFFDFF $FFFFFF HC16Z1/CKZ1/CMZ1 ADDRESS MAP Figure 3-8 MC68HC16Z1/CKZ1/CMZ1 Address Map M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-17 Freescale Semiconductor, Inc. $000000 $YFF700 $YFF73F $YFF820 $YFF83F $YFF900 $YFF93F $YFFA00 SIM 128 BYTES $YFFA7F $YFFB00 SRAM CONTROL 8 BYTES 4K SRAM ARRAY (MAPPED TO 4K BOUNDARY) Z3 ONLY QSM 512 BYTES 2K SRAM ARRAY (MAPPED TO 2K BOUNDARY) Z2 ONLY ADC 64 BYTES ROM CONTROL 32 BYTES GPT 64 BYTES 8K ROM ARRAY (MAPPED TO 8K BOUNDARY) Freescale Semiconductor, Inc... $YFFB07 $YFFC00 $YFFDFF $FFFFFF HC16Z2/Z3 ADDRESS MAP Figure 3-9 MC68HC16Z2/Z3 Address Map $000000 $YFF700 $YFF73F ADC 64 BYTES $YFF900 $YFF93F $YFFA00 GPT 64 BYTES SIML 128 BYTES $YFFA7F $YFFB00 $YFFB07 $YFFC00 MCCI 64 BYTES $YFFC3F SRAM CONTROL 8 BYTES 1K SRAM ARRAY (MAPPED TO 1K BOUNDARY) $FFFFFF HC16Z4/CKZ4 ADDRESS MAP Figure 3-10 MC68HC16Z4/CKZ4 Address Map OVERVIEW 3-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 3.7 Address Space Maps Figures 3-11 through 3-16 show CPU16 address space for M68HC16 Z-series MCUs. Address space can be split into physically distinct program and data spaces by decoding the MCU function code outputs. Figures 3-11, 3-12, and 3-13 show the memory map of a system that has combined program and data spaces. Figures 3-14, 3-15, and 3-16 show the memory map when MCU function code outputs are decoded. Reset and exception vectors are mapped into bank 0 and cannot be relocated. The CPU16 program counter, stack pointer, and Z index register can be initialized to any address in pseudolinear memory, but exception vectors are limited to 16-bit addresses. To access locations outside of bank 0 during exception handler routines (including interrupt exceptions), a jump table must be used. Refer to SECTION 4 CENTRAL PROCESSOR UNIT for more information concerning memory management, extended addressing, and exception processing. Refer to SECTION 5 SYSTEM INTEGRATION MODULE for more information concerning function codes, address space types, resets, and interrupts. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-19 Freescale Semiconductor, Inc. $000000 $010000 $020000 $030000 512 KBYTE $040000 $050000 BANK 0 RESET AND EXCEPTION VECTORS BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 Freescale Semiconductor, Inc... $060000 $070000 $07FFFF $080000 UNDEFINED1 VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION 0000 0 RESET — INITIAL ZK, SK, AND PK 0002 RESET — INITIAL PC 0004 RESET — INITIAL SP 0006 RESET — INITIAL IZ (DIRECT PAGE) 0008 4 BKPT (BREAKPOINT) 000A 5 BERR (BUS ERROR) 000C 6 SWI (SOFTWARE INTERRUPT) 000E 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012–001C 9–E UNASSIGNED, RESERVED 001E F UNINITIALIZED INTERRUPT 0020 10 UNASSIGNED, RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002C 16 LEVEL 6 INTERRUPT AUTOVECTOR 002E 17 LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032–006E 19–37 UNASSIGNED, RESERVED 0070–01FE 38–FF USER-DEFINED INTERRUPTS $000000 $0001FE BANK 6 BANK 7 PROGRAM AND DATA SPACE UNDEFINED $YFF700 $F7FFFF $F80000 $F90000 $FA0000 $FB0000 512 KBYTE $FC0000 $FD0000 $FE0000 $FF0000 $FFFFFF NOTE: 1. THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24-BIT IMB ADDRESSES. THE CPU16 ADDRESS BUS IS 20 BITS WIDE, AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES [23:20]. THE BLOCK OF ADDRESSES FROM $080000 TO $F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB. MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16’S FLAT 20-BIT ADDRESS SPACE. THE CPU16 NEED ONLY GENERATE A 20-BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE. ADC BANK 8 $YFF73F BANK 9 BANK 10 GPT BANK 11 $YFF900 $YFF93F $YFFA00 BANK 12 SIM $YFFA7F BANK 13 SRAM (CONTROL) $YFFB00 $YFFB07 $YFFC00 BANK 14 BANK 15 INTERNAL REGISTERS QSM $YFFDFF HC16Z1/CK/CM MEM MAP (C) Figure 3-11 MC68HC16Z1/CKZ1/CMZ1 Combined Program and Data Space Map OVERVIEW 3-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. $000000 $010000 $020000 $030000 512 KBYTE $040000 $050000 BANK 0 RESET AND EXCEPTION VECTORS BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 Freescale Semiconductor, Inc... $060000 $070000 $07FFFF $080000 UNDEFINED1 VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION 0000 0 RESET — INITIAL ZK, SK, AND PK 0002 RESET — INITIAL PC 0004 RESET — INITIAL SP 0006 RESET — INITIAL IZ (DIRECT PAGE) 0008 4 BKPT (BREAKPOINT) 000A 5 BERR (BUS ERROR) 000C 6 SWI (SOFTWARE INTERRUPT) 000E 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012–001C 9–E UNASSIGNED, RESERVED 001E F UNINITIALIZED INTERRUPT 0020 10 UNASSIGNED, RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002C 16 LEVEL 6 INTERRUPT AUTOVECTOR 002E 17 LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032–006E 19–37 UNASSIGNED, RESERVED 0070–01FE 38–FF USER-DEFINED INTERRUPTS $000000 $0001FE BANK 6 BANK 7 PROGRAM AND DATA SPACE UNDEFINED $YFF700 $F7FFFF $F80000 $F90000 $FA0000 $FB0000 512 KBYTE $FC0000 $FD0000 $FE0000 $FF0000 $FFFFFF NOTE: 1. THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24-BIT IMB ADDRESSES. THE CPU16 ADDRESS BUS IS 20 BITS WIDE, AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES [23:20]. THE BLOCK OF ADDRESSES FROM $080000 TO $F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB. MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16’S FLAT 20-BIT ADDRESS SPACE. THE CPU16 NEED ONLY GENERATE A 20-BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE. ADC BANK 8 $YFF73F ROM (CONTROL) $YFF820 $YFF83F $YFF900 $YFF93F $YFFA00 SIM $YFFA7F BANK 9 BANK 10 GPT BANK 11 BANK 12 BANK 13 SRAM (CONTROL) $YFFB00 $YFFB07 $YFFC00 BANK 14 BANK 15 INTERNAL REGISTERS QSM $YFFDFF HC16 Z2/Z3 MEM MAP (C) Figure 3-12 MC68HC16Z2/Z3 Combined Program and Data Space Map M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-21 Freescale Semiconductor, Inc. $000000 $010000 $020000 $030000 512 KBYTE $040000 $050000 BANK 0 RESET AND EXCEPTION VECTORS BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 Freescale Semiconductor, Inc... $060000 $070000 $07FFFF $080000 UNDEFINED1 VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION 0000 0 RESET — INITIAL ZK, SK, AND PK 0002 RESET — INITIAL PC 0004 RESET — INITIAL SP 0006 RESET — INITIAL IZ (DIRECT PAGE) 0008 4 BKPT (BREAKPOINT) 000A 5 BERR (BUS ERROR) 000C 6 SWI (SOFTWARE INTERRUPT) 000E 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012–001C 9–E UNASSIGNED, RESERVED 001E F UNINITIALIZED INTERRUPT 0020 10 UNASSIGNED, RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002C 16 LEVEL 6 INTERRUPT AUTOVECTOR 002E 17 LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032–006E 19–37 UNASSIGNED, RESERVED 0070–01FE 38–FF USER-DEFINED INTERRUPTS $000000 $0001FE BANK 6 BANK 7 PROGRAM AND DATA SPACE UNDEFINED $YFF700 $F7FFFF $F80000 $F90000 $FA0000 $FB0000 512 KBYTE $FC0000 $FD0000 $FE0000 $FF0000 $FFFFFF NOTE: 1. THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24-BIT IMB ADDRESSES. THE CPU16 ADDRESS BUS IS 20 BITS WIDE, AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES [23:20]. THE BLOCK OF ADDRESSES FROM $080000 TO $F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB. MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16’S FLAT 20-BIT ADDRESS SPACE. THE CPU16 NEED ONLY GENERATE A 20-BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE. ADC BANK 8 $YFF73F BANK 9 BANK 10 GPT BANK 11 $YFF900 $YFF93F $YFFA00 BANK 12 SIML $YFFA7F BANK 13 SRAM (CONTROL) $YFFB00 $YFFB07 $YFFC00 BANK 14 MCCI BANK 15 INTERNAL REGISTERS $YFFC3F $YFFDFF HC16Z4/CKZ4 MEM MAP (C) Figure 3-13 MC68HC16Z4/CKZ4 Combined Program and Data Space Map OVERVIEW 3-22 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. $000000 $000008 $010000 $020000 $030000 512 KBYTE $040000 $050000 $060000 $070000 $07FFFF $080000 UNDEFINED1 BANK 0 BANK 1 VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION 0000 0 RESET — INITIAL ZK, SK, AND PK 0002 1 RESET — INITIAL PC 0004 2 RESET — INITIAL SP 0006 3 RESET — INITIAL IZ (DIRECT PAGE) BANK 0 EXCEPTION VECTORS BANK 1 $000000 $000008 $010000 $020000 $030000 $040000 $050000 $060000 BANK 2 BANK 3 BANK 4 Freescale Semiconductor, Inc... BANK 5 BANK 6 PROGRAM SPACE BANK 7 VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION 0008 4 BKPT (BREAKPOINT) 000A 5 BERR (BUS ERROR) 000C 6 SWI (SOFTWARE INTERRUPT) 000E 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012–001C 9–E UNASSIGNED, RESERVED 001E F UNINITIALIZED INTERRUPT 0020 10 UNASSIGNED, RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002C 16 LEVEL 6 INTERRUPT AUTOVECTOR 002E 17 LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032–006E 19–37 UNASSIGNED, RESERVED 0070–01FE 38–FF USER-DEFINED INTERRUPTS BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 DATA SPACE BANK 7 $070000 $07FFFF $080000 UNDEFINED1 UNDEFINED UNDEFINED $YFF700 $F7FFFF $F80000 $F90000 $FA0000 $FB0000 512 KBYTE $FC0000 $FD0000 $FE0000 $FF0000 $FFFFFF NOTE: 1. THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24-BIT IMB ADDRESSES. THE CPU16 ADDRESS BUS IS 20 BITS WIDE, AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES [23:20]. THE BLOCK OF ADDRESSES FROM $080000 TO $F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB. MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16’S FLAT 20-BIT ADDRESS SPACE. THE CPU16 NEED ONLY GENERATE A 20-BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE. ADC BANK 8 $YFF73F BANK 8 $F7FFFF $F80000 $F90000 $FA0000 $FB0000 $FC0000 $FD0000 $FE0000 $FF0000 INTERNAL REGISTERS BANK 9 BANK 9 BANK 10 $YFF900 $YFF93F BANK 10 GPT BANK 11 BANK 11 $YFFA00 BANK 12 SIM $YFFA7F BANK 12 BANK 13 $YFFB00 $YFFB07 SRAM (CONTROL) BANK 13 BANK 14 $YFFC00 QSM $YFFDFF BANK 14 BANK 15 BANK 15 $FFFFFF HC16Z1/CK/CM MEM MAP (S) Figure 3-14 MC68HC16Z1/CKZ1/CMZ1 Separate Program and Data Space Map M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-23 Freescale Semiconductor, Inc. $000000 $000008 $010000 $020000 $030000 512 KBYTE $040000 $050000 BANK 0 BANK 1 VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION 0000 0 RESET — INITIAL ZK, SK, AND PK 0002 1 RESET — INITIAL PC 0004 2 RESET — INITIAL SP 0006 3 RESET — INITIAL IZ (DIRECT PAGE) BANK 0 EXCEPTION VECTORS BANK 1 $000000 $000008 $010000 $020000 $030000 $040000 $050000 $060000 BANK 2 BANK 3 BANK 4 BANK 5 Freescale Semiconductor, Inc... $060000 $070000 $07FFFF $080000 UNDEFINED1 BANK 6 PROGRAM SPACE BANK 7 VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION 0008 4 BKPT (BREAKPOINT) 000A 5 BERR (BUS ERROR) 000C 6 SWI (SOFTWARE INTERRUPT) 000E 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012–001C 9–E UNASSIGNED, RESERVED 001E F UNINITIALIZED INTERRUPT 0020 10 UNASSIGNED, RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002C 16 LEVEL 6 INTERRUPT AUTOVECTOR 002E 17 LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032–006E 19–37 UNASSIGNED, RESERVED 0070–01FE 38–FF USER-DEFINED INTERRUPTS BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 DATA SPACE BANK 7 $070000 $07FFFF $080000 UNDEFINED1 UNDEFINED UNDEFINED $YFF700 $F7FFFF $F80000 $F90000 $FA0000 $FB0000 512 KBYTE $FC0000 $FD0000 $FE0000 $FF0000 $FFFFFF NOTE: 1. THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24-BIT IMB ADDRESSES. THE CPU16 ADDRESS BUS IS 20 BITS WIDE, AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES [23:20]. THE BLOCK OF ADDRESSES FROM $080000 TO $F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB. MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16’S FLAT 20-BIT ADDRESS SPACE. THE CPU16 NEED ONLY GENERATE A 20-BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE. ADC BANK 8 $YFF73F $YFF820 ROM (CONTROL) BANK 8 $F7FFFF $F80000 $F90000 $FA0000 $FB0000 $FC0000 $FD0000 $FE0000 $FF0000 INTERNAL REGISTERS BANK 9 BANK 9 $YFF83F BANK 10 $YFF900 $YFF93F BANK 10 GPT BANK 11 BANK 11 $YFFA00 BANK 12 SIM $YFFA7F BANK 12 BANK 13 $YFFB00 $YFFB07 SRAM (CONTROL) BANK 13 BANK 14 $YFFC00 QSM $YFFDFF BANK 14 BANK 15 BANK 15 $FFFFFF HC16 Z2/Z3 MEM MAP (S) Figure 3-15 MC68HC16Z2/Z3 Separate Program and Data Space Map OVERVIEW 3-24 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. $000000 $000008 $010000 $020000 $030000 512 KBYTE $040000 $050000 BANK 0 BANK 1 VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION 0000 0 RESET — INITIAL ZK, SK, AND PK 0002 1 RESET — INITIAL PC 0004 2 RESET — INITIAL SP 0006 3 RESET — INITIAL IZ (DIRECT PAGE) BANK 0 EXCEPTION VECTORS BANK 1 $000000 $000008 $010000 $020000 $030000 $040000 $050000 $060000 BANK 2 BANK 3 BANK 4 BANK 5 Freescale Semiconductor, Inc... $060000 $070000 $07FFFF $080000 UNDEFINED1 BANK 6 PROGRAM SPACE BANK 7 VECTOR VECTOR TYPE OF ADDRESS NUMBER EXCEPTION 0008 4 BKPT (BREAKPOINT) 000A 5 BERR (BUS ERROR) 000C 6 SWI (SOFTWARE INTERRUPT) 000E 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012–001C 9–E UNASSIGNED, RESERVED 001E F UNINITIALIZED INTERRUPT 0020 10 UNASSIGNED, RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002C 16 LEVEL 6 INTERRUPT AUTOVECTOR 002E 17 LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032–006E 19–37 UNASSIGNED, RESERVED 0070–01FE 38–FF USER-DEFINED INTERRUPTS BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 DATA SPACE BANK 7 $070000 $07FFFF $080000 UNDEFINED1 UNDEFINED UNDEFINED $YFF700 $F7FFFF $F80000 $F90000 $FA0000 $FB0000 512 KBYTE $FC0000 $FD0000 $FE0000 $FF0000 $FFFFFF NOTE: 1. THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24-BIT IMB ADDRESSES. THE CPU16 ADDRESS BUS IS 20 BITS WIDE, AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES [23:20]. THE BLOCK OF ADDRESSES FROM $080000 TO $F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB. MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16’S FLAT 20-BIT ADDRESS SPACE. THE CPU16 NEED ONLY GENERATE A 20-BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE. ADC BANK 8 $YFF73F BANK 8 $F7FFFF $F80000 $F90000 $FA0000 $FB0000 $FC0000 $FD0000 $FE0000 $FF0000 INTERNAL REGISTERS BANK 9 BANK 9 BANK 10 $YFF900 $YFF93F BANK 10 GPT BANK 11 BANK 11 $YFFA00 BANK 12 SIML $YFFA7F BANK 12 BANK 13 $YFFB00 $YFFB07 SRAM (CONTROL) BANK 13 BANK 14 $YFFC00 MCCI $YFFC3F $YFFDFF BANK 14 BANK 15 BANK 15 $FFFFFF HC16Z4/CKZ4 MEM MAP (S) Figure 3-16 MC68HC16Z4/CKZ4 Separate Program and Data Space Map M68HC16 Z SERIES USER’S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-25 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... OVERVIEW 3-26 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 4 CENTRAL PROCESSOR UNIT This section is an overview of the central processor unit (CPU16). For detailed information, refer to the CPU16 Reference Manual (CPU16RM/AD). 4.1 General The CPU16 provides compatibility with the M68HC11 CPU and also provides additional capabilities associated with 16- and 32-bit data sizes, 20-bit addressing, and digital signal processing. CPU16 registers are an integral part of the CPU and are not addressed as memory locations. The CPU16 treats all peripheral, I/O, and memory locations as parts of a linear one Megabyte address space. There are no special instructions for I/O that are separate from instructions for addressing memory. Address space is made up of sixteen 64Kbyte banks. Specialized bank addressing techniques and support registers provide transparent access across bank boundaries. The CPU16 interacts with external devices and with other modules within the microcontroller via a standardized bus and bus interface. There are bus protocols used for memory and peripheral accesses, as well as for managing a hierarchy of interrupt priorities. 4.2 Register Model Figure 4-1 shows the CPU16 register model. Refer to the paragraphs that follow for a detailed description of each register. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSOR UNIT For More Information On This Product, Go to: www.freescale.com 4-1 Freescale Semiconductor, Inc. 20 16 15 87 0 BIT POSITION A D B ACCUMULATORS A AND B ACCUMULATOR D (A:B) E ACCUMULATOR E XK IX INDEX REGISTER X Freescale Semiconductor, Inc... YK IY INDEX REGISTER Y ZK IZ INDEX REGISTER Z SK SP STACK POINTER SP PK PC PROGRAM COUNTER PC CCR PK CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK EK XK K YK ZK ADDRESS EXTENSION REGISTER K SK STACK EXTENSION FIELD SK HR MAC MULTIPLIER REGISTER HR IR MAC MULTIPLICAND REGISTER IR AM AM MAC ACCUMULATOR MSB[35:16] AM MAC ACCUMULATOR LSB[15:0] AM XMSK YMSK MAC XY MASK REGISTER CPU16 REGISTER MODEL Figure 4-1 CPU16 Register Model CENTRAL PROCESSOR UNIT 4-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 4.2.1 Accumulators The CPU16 has two 8-bit accumulators (A and B) and one 16-bit accumulator (E). In addition, accumulators A and B can be concatenated into a second 16-bit double accumulator (D). Accumulators A, B, and D are general-purpose registers that hold operands and results during mathematical and data manipulation operations. Accumulator E, which can be used in the same way as accumulator D, also extends CPU16 capabilities. It allows more data to be held within the CPU16 during operations, simplifies 32-bit arithmetic and digital signal processing, and provides a practical 16bit accumulator offset indexed addressing mode. Freescale Semiconductor, Inc... 4.2.2 Index Registers The CPU16 has three 16-bit index registers (IX, IY, and IZ). Each index register has an associated 4-bit extension field (XK, YK, and ZK). Concatenated registers and extension fields provide 20-bit indexed addressing and support data structure functions anywhere in the CPU16 address space. IX and IY can perform the same operations as M68HC11 registers of the same names, but the CPU16 instruction set provides additional indexed operations. IZ can perform the same operations as IX and IY. IZ also provides an additional indexed addressing capability that replaces M68HC11 direct addressing mode. Initial IZ and ZK extension field values are included in the RESET exception vector, so that ZK:IZ can be used as a direct page pointer out of reset. 4.2.3 Stack Pointer The CPU16 stack pointer (SP) is 16 bits wide. An associated 4-bit extension field (SK) provides 20-bit stack addressing. Stack implementation in the CPU16 is from high to low memory. The stack grows downward as it is filled. SK:SP are decremented each time data is pushed on the stack, and incremented each time data is pulled from the stack. SK:SP point to the next available stack address rather than to the address of the latest stack entry. Although the stack pointer is normally incremented or decremented by word address, it is possible to push and pull byte-sized data. Setting the stack pointer to an odd value causes data misalignment, which reduces performance. 4.2.4 Program Counter The CPU16 program counter (PC) is 16 bits wide. An associated 4-bit extension field (PK) provides 20-bit program addressing. CPU16 instructions are fetched from even word boundaries. Address line 0 always has a value of zero during instruction fetches to ensure that instructions are fetched from word-aligned addresses. M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSOR UNIT For More Information On This Product, Go to: www.freescale.com 4-3 Freescale Semiconductor, Inc. 4.2.5 Condition Code Register The 16-bit condition code register is composed of two functional blocks. The eight MSB, which correspond to the CCR on the M68HC11, contain the low-power stop control bit and processor status flags. The eight LSB contain the interrupt priority field, the DSP saturation mode control bit, and the program counter address extension field. Figure 4-2 shows the condition code register. Detailed descriptions of each status indicator and field in the register follow the figure. 15 S 14 MV 13 H 12 EV 11 N 10 Z 9 V 8 C 7 6 IP[2:0] 5 4 SM 3 2 PK[3:0] 1 0 Figure 4-2 Condition Code Register Freescale Semiconductor, Inc... S — STOP Enable 0 = Stop clock when LPSTOP instruction is executed. 1 = Perform NOP when LPSTOP instruction is executed. MV — Accumulator M overflow flag MV is set when an overflow into AM35 has occurred. H — Half Carry Flag H is set when a carry from A3 or B3 occurs during BCD addition. EV — Accumulator M Extension Overflow Flag EV is set when an overflow into AM31 has occurred. N — Negative Flag N is set under the following conditions: • When the MSB is set in the operand of a read operation. • When the MSB is set in the result of a logic or arithmetic operation. Z — Zero Flag Z is set under the following conditions: • When all bits are zero in the operand of a read operation. • When all bits are zero in the result of a logic or arithmetic operation. V — Overflow Flag V is set when a two’s complement overflow occurs as the result of an operation. C — Carry Flag C is set when a carry or borrow occurs during an arithmetic operation. This flag is also used during shift and rotate to facilitate multiple word operations. IP[2:0] — Interrupt Priority Field The priority value in this field (0 to 7) is used to mask interrupts. CENTRAL PROCESSOR UNIT 4-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SM — Saturate Mode Bit When SM is set and either EV or MV is set, data read from AM using TMER or TMET is given maximum positive or negative value, depending on the state of the AM sign bit before overflow. PK[3:0] — Program Counter Address Extension Field This field is concatenated with the program counter to form a 20-bit address. 4.2.6 Address Extension Register and Address Extension Fields There are six 4-bit address extension fields. EK, XK, YK, and ZK are contained by the address extension register (K), PK is part of the CCR, and SK stands alone. Extension fields are the bank portions of 20-bit concatenated bank:byte addresses used in the CPU16 linear memory management scheme. All extension fields except EK correspond directly to a register. XK, YK, and ZK extend registers IX, IY, and IZ. PK extends the PC; and SK extends the SP. EK holds the four MSB of the 20-bit address used by the extended addressing mode. 4.2.7 Multiply and Accumulate Registers The multiply and accumulate (MAC) registers are part of a CPU submodule that performs repetitive signed fractional multiplication and stores the cumulative result. These operations are part of control-oriented digital signal processing. There are four MAC registers. Register H contains the 16-bit signed fractional multiplier. Register I contains the 16-bit signed fractional multiplicand. Accumulator M is a specialized 36-bit product accumulation register. XMSK and YMSK contain 8-bit mask values used in modulo addressing. The CPU16 has a special subset of signal processing instructions that manipulate the MAC registers and perform signal processing calculations. 4.3 Memory Management The CPU16 provides a 1-Mbyte address space. There are 16 banks within the address space. Each bank is made up of 64 Kbytes addressed from $0000 to $FFFF. Banks are selected by means of the address extension fields associated with individual CPU16 registers. In addition, address space can be split into discrete 1-Mbyte program and data spaces by externally decoding the MCU’s function code outputs. When this technique is used, instruction fetches and reset vector fetches access program space, while exception vector fetches (other than for reset), data accesses, and stack accesses are made in data space. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSOR UNIT For More Information On This Product, Go to: www.freescale.com 4-5 Freescale Semiconductor, Inc. 4.3.1 Address Extension All CPU16 resources used to generate addresses are effectively 20 bits wide. These resources include the index registers, program counter, and stack pointer. All addressing modes use 20-bit addresses. Twenty-bit addresses are formed from a 16-bit byte address generated by an individual CPU16 register and a 4-bit address extension contained in an associated extension field. The byte address corresponds to ADDR[15:0] and the address extension corresponds to ADDR[19:16]. 4.3.2 Extension Fields Each of the six address extension fields is used for a different type of access. All but EK are associated with particular CPU16 registers. There are several ways to manipulate extension fields and the address map. Refer to the CPU16 Reference Manual (CPU16RM/AD) for detailed information. 4.4 Data Types The CPU16 uses the following types of data: • Bits • 4-bit signed integers • 8-bit (byte) signed and unsigned integers • 8-bit, 2-digit binary coded decimal (BCD) numbers • 16-bit (word) signed and unsigned integers • 32-bit (long word) signed and unsigned integers • 16-bit signed fractions • 32-bit signed fractions • 36-bit signed fixed-point numbers • 20-bit effective addresses There are eight bits in a byte and 16 bits in a word. Bit set and clear instructions use both byte and word operands. Bit test instructions use byte operands. Negative integers are represented in two’s complement form. Four-bit signed integers, packed two to a byte, are used only as X and Y offsets in MAC and RMAC operations. 32-bit integers are used only by extended multiply and divide instructions, and by the associated LDED and STED instructions. BCD numbers are packed, two digits per byte. BCD operations use byte operands. Signed 16-bit fractions are used by the fractional multiplication instructions, and as multiplicand and multiplier operands in the MAC unit. Bit 15 is the sign bit, and there is an implied radix point between bits 15 and 14. There are 15 bits of magnitude. The range of values is –1 ($8000) to 1 – 2-15 ($7FFF). Signed 32-bit fractions are used only by the fractional multiplication and division instructions. Bit 31 is the sign bit. An implied radix point lies between bits 31 and 30. There are 31 bits of magnitude. The range of values is –1 ($80000000) to 1 – 2-31 ($7FFFFFFF). CENTRAL PROCESSOR UNIT 4-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Signed 36-bit fixed-point numbers are used only by the MAC unit. Bit 35 is the sign bit. Bits [34:31] are sign extension bits. There is an implied radix point between bits 31 and 30. There are 31 bits of magnitude, but use of the extension bits allows representation of numbers in the range –16 ($800000000) to 15.999969482 ($7FFFFFFFF). 4.5 Memory Organization Both program and data memory are divided into sixteen 64-Kbyte banks. Addressing is linear. A 20-bit extended address can access any byte location in the appropriate address space. A word is composed of two consecutive bytes. A word address is normally an even byte address. Byte 0 of a word has a lower 16-bit address than byte 1. Long words and 32-bit signed fractions consist of two consecutive words, and are normally accessed at the address of byte 0 in word 0. Instruction fetches always access word addresses. Word operands are normally accessed at even byte addresses, but can be accessed at odd byte addresses, with a substantial performance penalty. To permit compatibility with the M68HC11, misaligned word transfers and misaligned stack accesses are allowed. Transferring a misaligned word requires two successive byte transfer operations. Figure 4-3 shows how each CPU16 data type is organized in memory. Consecutive even addresses show size and alignment. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSOR UNIT For More Information On This Product, Go to: www.freescale.com 4-7 Freescale Semiconductor, Inc. Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E ± ⇐ (Radix Point) ± ± ± ⇐ (Radix Point) ⇐ (Radix Point) ⇐ (Radix Point) ± BCD1 Type BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE0 X OFFSET ± Y OFFSET BCD0 WORD 0 WORD 1 MSW LONG WORD 0 LSW LONG WORD 0 MSW LONG WORD 1 LSW LONG WORD 1 16-BIT SIGNED FRACTION 0 16-BIT SIGNED FRACTION 1 MSW 32-BIT SIGNED FRACTION 0 LSW 32-BIT SIGNED FRACTION 0 MSW 32-BIT SIGNED FRACTION 1 LSW 32-BIT SIGNED FRACTION 1 0 0 ± BCD1 BYTE1 X OFFSET ± Y OFFSET BCD0 Freescale Semiconductor, Inc... MAC Data Types 35 ± « « 32 « 31 « 15 LSW 32-BIT SIGNED FRACTION ± ⇐ (Radix Point) 16-BIT SIGNED FRACTION ⇐ (Radix Point) MSW 32-BIT SIGNED FRACTION 0 16 Address Data Type 19 4-Bit Address Extension 16 15 16-Bit Byte Address 0 Figure 4-3 Data Types and Memory Organization 4.6 Addressing Modes The CPU16 uses nine types of addressing. There are one or more addressing modes within each type. Table 4-1 shows the addressing modes. CENTRAL PROCESSOR UNIT 4-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-1 Addressing Modes Mode Accumulator Offset Mnemonic E,X E,Y E,Z EXT EXT20 IMM8 IMM16 IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z IND20, X IND20, Y IND20, Z INH IXP REL8 REL16 Description Index register X with accumulator E offset Index register Y with accumulator E offset Index register Z with accumulator E offset Extended 20-bit extended 8-bit immediate 16-bit immediate Index register X with unsigned 8-bit offset Index register Y with unsigned 8-bit offset Index register Z with unsigned 8-bit offset Index register X with signed 16-bit offset Index register Y with signed 16-bit offset Index register Z with signed 16-bit offset Index register X with signed 20-bit offset Index register Y with signed 20-bit offset Index register Z with signed 20-bit offset Inherent Signed 8-bit offset added to index register X after effective address is used 8-bit relative 16-bit relative Extended Immediate Indexed 8-Bit Freescale Semiconductor, Inc... Indexed 16-Bit Indexed 20-Bit Inherent Post-Modified Index Relative All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an operand or an extension field to form a 20-bit effective address. NOTE Access across 64-Kbyte address boundaries is transparent. ADDR[19:16] of the effective address are changed to make an access across a bank boundary. Extension field values will not change as a result of effective address computation. 4.6.1 Immediate Addressing Modes In the immediate modes, an argument is contained in a byte or word immediately following the instruction. For IMM8 and IMM16 modes, the effective address is the address of the argument. There are three specialized forms of IMM8 addressing. • The AIS, AIX, AIY, AIZ, ADDD, and ADDE instructions decrease execution time by sign-extending the 8-bit immediate operand to 16 bits, then adding it to an appropriate register. • The MAC and RMAC instructions use an 8-bit immediate operand to specify two signed 4-bit index register offsets. • The PSHM and PULM instructions use an 8-bit immediate mask operand to indicate which registers must be pushed to or pulled from the stack. M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSOR UNIT For More Information On This Product, Go to: www.freescale.com 4-9 Freescale Semiconductor, Inc. 4.6.2 Extended Addressing Modes Regular extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective address is formed by concatenating the EK field and the 16-bit byte address. EXT20 mode is used only by the JMP and JSR instructions. These instructions contain a 20-bit effective address that is zero-extended to 24 bits to give the instruction an even number of bytes. 4.6.3 Indexed Addressing Modes In the indexed modes, registers IX, IY, and IZ, together with their associated extension fields, are used to calculate the effective address. For 8-bit indexed modes an 8-bit unsigned offset contained in the instruction is added to the value contained in an index register and its extension field. Freescale Semiconductor, Inc... For 16-bit modes, a 16-bit signed offset contained in the instruction is added to the value contained in an index register and its extension field. For 20-bit modes, a 20-bit signed offset (zero-extended to 24 bits) is added to the value contained in an index register. These modes are used for JMP and JSR instructions only. 4.6.4 Inherent Addressing Mode Inherent mode instructions use information directly available to the processor to determine the effective address. Operands, if any, are system resources and are thus not fetched from memory. 4.6.5 Accumulator Offset Addressing Mode Accumulator offset modes form an effective address by sign-extending the content of accumulator E to 20 bits, then adding the result to an index register and its associated extension field. This mode allows use of an index register and an accumulator within a loop without corrupting accumulator D. 4.6.6 Relative Addressing Modes Relative modes are used for branch and long branch instructions. If a branch condition is satisfied, a byte or word signed two’s complement offset is added to the concatenated PK field and program counter. The new PK : PC value is the effective address. 4.6.7 Post-Modified Index Addressing Mode Post-modified index mode is used by the MOVB and MOVW instructions. A signed 8bit offset is added to index register X after the effective address formed by XK : IX is used. CENTRAL PROCESSOR UNIT 4-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 4.6.8 Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode In M68HC11 systems, the direct addressing mode can be used to perform rapid accesses to RAM or I/O mapped from $0000 to $00FF. The CPU16 uses the first 512 bytes of bank 0 for exception vectors. To provide an enhanced replacement for the M68HC11’s direct addressing mode, the ZK field and index register Z have been assigned reset initialization vectors. By resetting the ZK field to a chosen page and using indexed mode addressing, a programmer can access useful data structures anywhere in the address map. 4.7 Instruction Set The CPU16 instruction set is based on the M68HC11 instruction set, but the opcode map has been rearranged to maximize performance with a 16-bit data bus. Most M68HC11 code can run on the CPU16 following reassembly. The user must take into account changed instruction times, the interrupt mask, and the changed interrupt stack frame (refer to Transporting M68HC11 Code to M68HC16 Devices,Freescale Programming Note M68HC16PN01/D, for more information). 4.7.1 Instruction Set Summary Table 4-2 is a quick reference to the entire CPU16 instruction set. Refer to the CPU16 Reference Manual (CPU16RM/AD) for detailed information about each instruction, assembler syntax, and condition code evaluation. Table 4-3 provides a key to the table nomenclature. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSOR UNIT For More Information On This Product, Go to: www.freescale.com 4-11 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary Mnemonic Operation Description (A ) + (B) ⇒ A (XK : IX) + (000 : B) ⇒ XK : IX (YK : IY) + (000 : B) ⇒ YK : IY (ZK : IZ) + (000 : B) ⇒ ZK : IZ (AM[31:16]) + (E) ⇒ AM (AM) + (E : D) ⇒ AM (A) + (M) + C ⇒ A Address Mode ABA ABX ABY ABZ ACE ACED ADCA Add B to A Add B to IX Add B to IY Add B to IZ Add E to AM Add E : D to AM Add with Carry to A INH INH INH INH INH INH IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z Opcode 370B 374F 375F 376F 3722 3723 43 53 63 73 1743 1753 1763 1773 2743 2753 2763 C3 D3 E3 F3 17C3 17D3 17E3 17F3 27C3 27D3 27E3 83 93 A3 37B3 37C3 37D3 37E3 37F3 2783 2793 27A3 3733 3743 3753 3763 3773 41 51 61 71 1741 1751 1761 1771 2741 2751 2761 Instruction Operand — — — — — — ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff jj kk gggg gggg gggg hh ll — — — jj kk gggg gggg gggg hh ll ff ff ff ii gggg gggg gggg hh ll — — — Cycles 2 2 2 2 2 4 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 S — — — — — — — MV — — — — ∆ ∆ — Condition Codes H ∆ — — — — — ∆ EV — — — — ∆ ∆ — N ∆ Z ∆ V ∆ C ∆ ———— ———— ———— ———— ———— ∆ ∆ ∆ ∆ Freescale Semiconductor, Inc... ADCB Add with Carry to B (B) + (M) + C ⇒ B — — ∆ — ∆ ∆ ∆ ∆ ADCD Add with Carry to D (D) + (M : M + 1) + C ⇒ D — — — — ∆ ∆ ∆ ∆ ADCE Add with Carry to E (E) + (M : M + 1) + C ⇒ E — — — — ∆ ∆ ∆ ∆ ADDA Add to A (A) + (M) ⇒ A — — ∆ — ∆ ∆ ∆ ∆ CENTRAL PROCESSING UNIT 4-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (B) + (M) ⇒ B Address Mode ADDB Add to B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM8 IMM16 IND16, X IND16, Y IND16, Z EXT INH INH INH INH INH INH INH IMM8 IMM16 IMM8 IMM16 IMM8 IMM16 IMM8 IMM16 IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z Opcode C1 D1 E1 F1 17C1 17D1 17E1 17F1 27C1 27D1 27E1 81 91 A1 FC 37B1 37C1 37D1 37E1 37F1 2781 2791 27A1 7C 3731 3741 3751 3761 3771 2778 37CD 37DD 37ED 374D 375D 376D 3F 373F 3C 373C 3D 373D 3E 373E 46 56 66 76 1746 1756 1766 1776 2746 2756 2766 Instruction Operand ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff ii jj kk gggg gggg gggg hh ll — — — ii jj kk gggg gggg gggg hh ll — — — — — — — ii jj kk ii jj kk ii jj kk ii jj kk ff ff ff ii gggg gggg gggg hh ll — — — Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 4 6 6 6 6 6 6 6 2 4 6 6 6 6 2 2 2 2 2 2 2 2 4 2 4 2 4 2 4 6 6 6 2 6 6 6 6 6 6 6 S — MV — Condition Codes H ∆ EV — N ∆ Z ∆ V ∆ C ∆ ADDD Add to D (D) + (M : M + 1) ⇒ D — — — — ∆ ∆ ∆ ∆ Freescale Semiconductor, Inc... ADDE Add to E (E) + (M : M + 1) ⇒ E — — — — ∆ ∆ ∆ ∆ ADE ADX ADY ADZ AEX AEY AEZ AIS AIX AIY AIZ ANDA Add D to E Add D to IX Add D to IY Add D to IZ Add E to IX Add E to IY Add E to IZ Add Immediate Data to Stack Pointer Add Immediate Value to IX Add Immediate Value to IY Add Immediate Value to IZ AND A (E) + (D) ⇒ E ( XK : IX ) + ( 20 « D ) ⇒ XK : IX ( YK : IY ) + ( 20 « D ) ⇒ YK : IY ( ZK : IZ ) + ( 20 « D ) ⇒ ZK : IZ ( XK : IX ) + ( 20 « E ) ⇒ XK : IX ( YK : IY ) + ( 20 « E ) ⇒ YK : IY ( ZK : IZ ) + ( 20 « E ) ⇒ ZK : IZ (SK : SP) + (20 « IMM) ⇒ SK : SP (XK : IX) + (20 « IMM) ⇒ XK : IX (YK : IY) + (20 « IMM) ⇒ YK : IY (ZK : IZ) + (20 « IMM) ⇒ ZK : IZ (A) • (M) ⇒ A — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ∆ ∆ ∆ ∆ ———— ———— ———— ———— ———— ———— ———— — — — ∆ ∆ ∆ ∆ ∆ —— —— —— 0 — M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-13 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (B) • (M) ⇒ B Address Mode ANDB AND B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT IMM16 IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH Opcode C6 D6 E6 F6 17C6 17D6 17E6 17F6 27C6 27D6 27E6 86 96 A6 37B6 37C6 37D6 37E6 37F6 2786 2796 27A6 3736 3746 3756 3766 3776 373A 04 14 24 1704 1714 1724 1734 3704 Instruction Operand ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff jj kk gggg gggg gggg hh ll — — — jj kk gggg gggg gggg hh ll jj kk ff ff ff gggg gggg gggg hh ll — Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 4 8 8 8 8 8 8 8 2 S — MV — Condition Codes H — EV — N ∆ Z ∆ V 0 C — ANDD AND D (D) • (M : M + 1) ⇒ D — — — — ∆ ∆ 0 — Freescale Semiconductor, Inc... ANDE AND E (E) • (M : M + 1) ⇒ E — — — — ∆ ∆ 0 — ANDP ASL 1 AND CCR Arithmetic Shift Left (CCR) • IMM16⇒ CCR ∆ — ∆ — ∆ — ∆ — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ASLA Arithmetic Shift Left A — — — — ∆ ∆ ∆ ∆ ASLB Arithmetic Shift Left B INH 3714 — 2 — — — — ∆ ∆ ∆ ∆ ASLD Arithmetic Shift Left D INH 27F4 — 2 — — — — ∆ ∆ ∆ ∆ ASLE Arithmetic Shift Left E INH 2774 — 2 — — — — ASLM Arithmetic Shift Left AM Arithmetic Shift Left Word INH 27B6 — 4 — — —— ASLW IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT 2704 2714 2724 2734 0D 1D 2D 170D 171D 172D 173D gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 8 8 8 8 — — — — ASR Arithmetic Shift Right — — — — CENTRAL PROCESSING UNIT 4-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Mode ASRA Arithmetic Shift Right A Arithmetic Shift Right B Arithmetic Shift Right D Arithmetic Shift Right E Arithmetic Shift Right AM Arithmetic Shift Right Word INH Opcode 370D Instruction Operand — Cycles 2 S — MV — Condition Codes H — EV — N Z V C ASRB INH 371D — 2 — — — — ASRD INH 27FD — 2 — — — — ASRE INH 277D — 2 — — — — ASRM INH 27BA — 4 — — — —— Freescale Semiconductor, Inc... ASRW IND16, X IND16, Y IND16, Z EXT If C = 0, branch (M) • (Mask) ⇒ M REL8 IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND16, X IND16, Y IND16, Z EXT 270D 271D 272D 273D B4 1708 1718 1728 08 18 28 38 2708 2718 2728 2738 B5 B7 BC 37A6 gggg gggg gggg hh ll rr mm ff mm ff mm ff mm gggg mm gggg mm gggg mm hh ll gggg mmmm gggg mmmm gggg mmmm hh ll mmmm rr rr rr — 8 8 8 8 6, 2 8 8 8 8 8 8 8 10 10 10 10 6, 2 6, 2 6, 2 — — — — — BCC 2 Branch if Carry Clear Clear Bit(s) — — — — — — — — ———— ∆ ∆ 0 — BCLR BCLRW Clear Bit(s) in a Word (M : M + 1) • (Mask) ⇒ M:M+1 — — — — ∆ ∆ 0 — BCS2 BEQ2 BGE2 BGND Branch if Carry Set Branch if Equal Branch if Greater Than or Equal to Zero Enter Background Debug Mode Branch if Greater Than Zero Branch if Higher Bit Test A If C = 1, branch If Z = 1, branch If N ⊕ V = 0, branch If BDM enabled, begin debug; else, illegal instruction trap If Z ' (N ⊕ V) = 0, branch If C ' Z = 0, branch (A) • (M) REL8 REL8 REL8 INH — — — — — — — — — — — — — — — — ———— ———— ———— ———— BGT2 BHI2 BITA REL8 REL8 IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z BE B2 49 59 69 79 1749 1759 1769 1779 2749 2759 2769 rr rr ff ff ff ii gggg gggg gggg hh ll — — — 6, 2 6, 2 6 6 6 2 6 6 6 6 6 6 6 — — — — — — — — — — — — ———— ———— ∆ ∆ 0 — M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-15 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (B) • (M) Address Mode BITB Bit Test B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z REL8 REL8 REL8 REL8 REL8 REL8 REL8 IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT BRN BRSET2 Branch Never Branch if Bit(s) Set If 1 = 0, branch If (M) • (Mask) = 0, branch REL8 IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT BSET Set Bit(s) (M) ' (Mask) ⇒ M IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND16, X IND16, Y IND16, Z EXT Opcode C9 D9 E9 F9 17C9 17D9 17E9 17F9 27C9 27D9 27E9 BF B3 BD BB B6 BA B0 CB DB EB 0A 1A 2A 3A B1 8B 9B AB 0B 1B 2B 3B 1709 1719 1729 09 19 29 39 2709 2719 2729 2739 Instruction Operand ff ff ff ii gggg gggg gggg hh ll — — — rr rr rr rr rr rr rr mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr rr mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr mm ff mm ff mm ff mm gggg mm gggg mm gggg mm hh ll gggg mmmm gggg mmmm gggg mmmm hh ll mmmm Cycles 6 6 6 2 6 6 6 6 6 6 6 6, 2 6, 2 6, 2 6, 2 6, 2 6, 2 6 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 2 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 8 8 8 8 8 8 8 10 10 10 10 — — — — ∆ ∆ 0 ∆ — — — — — — — — ———— ———— S — MV — Condition Codes H — EV — N ∆ Z ∆ V 0 C — BLE2 BLS2 Branch if Less Than or Equal to Zero Branch if Lower or Same Branch if Less Than Zero Branch if Minus Branch if Not Equal Branch if Plus Branch Always Branch if Bit(s) Clear If Z ' (N ⊕ V) = 1, branch If C ' Z = 1, branch If N ⊕ V = 1, branch If N = 1, branch If Z = 0, branch If N = 0, branch If 1 = 1, branch If (M) • (Mask) = 0, branch — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ———— ———— ———— ———— ———— ———— ———— ———— Freescale Semiconductor, Inc... BLT2 BMI2 BNE2 BPL2 BRA BRCLR2 BSETW Set Bit(s) in Word (M : M + 1) ' (Mask) ⇒M:M+1 — — — — ∆ ∆ 0 ∆ CENTRAL PROCESSING UNIT 4-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (PK : PC) - 2 ⇒ PK : PC Push (PC) (SK : SP) - 2 ⇒ SK : SP Push (CCR) (SK : SP) - 2 ⇒ SK : SP (PK : PC) + Offset ⇒ PK : PC If V = 0, branch If V = 1, branch (A) − (B) $00 ⇒ M Address Mode BSR Branch to Subroutine REL8 Opcode 36 Instruction Operand rr Cycles 10 S — MV — Condition Codes H — EV — N Z V C ———— BVC2 BVS2 CBA CLR Branch if Overflow Clear Branch if Overflow Set Compare A to B Clear a Byte in Memory REL8 REL8 INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH INH INH INH IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH INH INH IND16, X IND16, Y IND16, Z EXT B8 B9 371B 05 15 25 1705 1715 1725 1735 3705 3715 27F5 2775 27B7 2705 2715 2725 2735 48 58 68 78 1748 1758 1768 1778 2748 2758 2768 C8 D8 E8 F8 17C8 17D8 17E8 17F8 27C8 27D8 27E8 00 10 20 1700 1710 1720 1730 3700 3710 27F0 2770 2700 2710 2720 2730 rr rr — ff ff ff gggg gggg gggg hh ll — — — — — gggg gggg gggg hh ll ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff gggg gggg gggg hh ll — — — — gggg gggg gggg hh ll 6, 2 6, 2 2 4 4 4 6 6 6 6 2 2 2 2 2 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 8 8 8 8 8 8 8 2 2 2 2 8 8 8 8 — — — — — — — — — — — — — — — — ———— ———— ∆ 0 ∆ 1 ∆ 0 ∆ 0 Freescale Semiconductor, Inc... CLRA CLRB CLRD CLRE CLRM CLRW Clear A Clear B Clear D Clear E Clear AM Clear a Word in Memory $00 ⇒ A $00 ⇒ B $0000 ⇒ D $0000 ⇒ E $000000000 ⇒ AM[35:0] $0000 ⇒ M : M + 1 — — — — — — — — — — 0 — — — — — — — — — — — 0 — 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ———— CMPA Compare A to Memory (A) − (M) — — — — ∆ ∆ ∆ ∆ CMPB Compare B to Memory (B) − (M) — — — — ∆ ∆ ∆ ∆ COM One’s Complement $FF − (M) ⇒ M, or M ⇒ M — — — — ∆ ∆ 0 1 COMA COMB COMD COME COMW One’s Complement A One’s Complement B One’s Complement E One’s Complement Word $FF − (A) ⇒ A, or M ⇒ A $FF − (B) ⇒ B, or B ⇒ B $FFFF − (E) ⇒ E, or E ⇒ E $FFFF − M : M + 1 ⇒ M : M + 1, or (M : M + 1) ⇒ M:M+1 — — — — — — — — — — — — — — — — — — — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ 0 0 0 0 0 1 1 1 1 1 One’s Complement D $FFFF − (D) ⇒ D, or D ⇒ D M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-17 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (D) − (M : M + 1) Address Mode CPD Compare D to Memory IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH IND16, X IND16, Y IND16, Z EXT INH Opcode 88 98 A8 37B8 37C8 37D8 37E8 37F8 2788 2798 27A8 3738 3748 3758 3768 3778 4F 5F 6F 377F 174F 175F 176F 177F 4C 5C 6C 377C 174C 175C 176C 177C 4D 5D 6D 377D 174D 175D 176D 177D 4E 5E 6E 377E 174E 175E 176E 177E 3721 01 11 21 1701 1711 1721 1731 3701 3711 2701 2711 2721 2731 3728 Instruction Operand ff ff ff jj kk gggg gggg gggg hh ll — — — jjkk gggg gggg gggg hhll ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll — ff ff ff gggg gggg gggg hh ll — — gggg gggg gggg hh ll — Cycles 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 2 8 8 8 8 8 8 8 2 2 8 8 8 8 24 S — MV — Condition Codes H — EV — N ∆ Z ∆ V ∆ C ∆ CPE Compare E to Memory (E) − (M : M + 1) — — — — ∆ ∆ ∆ ∆ Freescale Semiconductor, Inc... CPS Compare Stack Pointer to Memory (SP) − (M : M + 1) — — — — ∆ ∆ ∆ ∆ CPX Compare IX to Memory (IX) − (M : M + 1) — — — — ∆ ∆ ∆ ∆ CPY Compare IY to Memory (IY) − (M : M + 1) — — — — ∆ ∆ ∆ ∆ CPZ Compare IZ to Memory (IZ) − (M : M + 1) — — — — DAA DEC Decimal Adjust A Decrement Memory (A)10 (M) − $01 ⇒ M — — — — — — — — ∆ ∆ ∆ ∆ U ∆ ∆ — DECA DECB DECW Decrement A Decrement B Decrement Memory Word (A) − $01 ⇒ A (B) − $01 ⇒ B (M : M + 1) − $0001 ⇒M:M+1 — — — — — — — — — — — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ — — — EDIV Extended Unsigned Integer Divide (E : D) / (IX) Quotient ⇒ IX Remainder ⇒ D — — — — ∆ ∆ ∆ ∆ CENTRAL PROCESSING UNIT 4-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (E : D) / (IX) Quotient ⇒ IX Remainder ⇒ D (E) ∗ (D) ⇒ E : D (E) ∗ (D) ⇒ E : D (A) ⊕ (M) ⇒ A Address Mode EDIVS Extended Signed Integer Divide Extended Unsigned Multiply Extended Signed Multiply Exclusive OR A INH Opcode 3729 Instruction Operand — Cycles 38 S — MV — Condition Codes H — EV — N ∆ Z ∆ V ∆ C ∆ EMUL EMULS EORA INH INH IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT INH INH INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH IND16, X IND16, Y IND16, Z EXT 3725 3726 44 54 64 74 1744 1754 1764 1774 2744 2754 2764 C4 D4 E4 F4 17C4 17D4 17E4 17F4 27C4 27D4 27E4 84 94 A4 37B4 37C4 37D4 37E4 37F4 2784 2794 27A4 3734 3744 3754 3764 3774 372B 3727 372A 03 13 23 1703 1713 1723 1733 3703 3713 2703 2713 2723 2733 — — ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff jj kk gggg gggg gggg hh ll — — — jj kk gggg gggg gggg hh ll — — — ff ff ff gggg gggg gggg hh ll — — gggg gggg gggg hh ll 10 8 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 22 8 22 8 8 8 8 8 8 8 2 2 8 8 8 8 — — — — — — — — — — — — ∆ ∆ ∆ ∆ ∆ ∆ — — 0 ∆ ∆ — Freescale Semiconductor, Inc... EORB Exclusive OR B (B) ⊕ (M) ⇒ B — — — — ∆ ∆ 0 — EORD Exclusive OR D (D) ⊕ (M : M + 1) ⇒ D — — — — ∆ ∆ 0 — EORE Exclusive OR E (E) ⊕ (M : M + 1) ⇒ E — — — — ∆ ∆ 0 — FDIV FMULS IDIV INC Fractional Unsigned Divide Fractional Signed Multiply Integer Divide Increment Memory (D) / (IX) ⇒ IX Remainder ⇒ D (E) ∗ (D) ⇒ E : D[31:1] 0 ⇒ D[0] (D) / (IX) ⇒ IX Remainder ⇒ D (M) + $01 ⇒ M — — — — — — — — — — — — — — — — — ∆ — ∆ ∆ ∆ ∆ ∆ ∆ ∆ 0 ∆ ∆ ∆ ∆ — INCA INCB INCW Increment A Increment B Increment Memory Word (A) + $01 ⇒ A (B) + $01 ⇒ B (M : M + 1) + $0001 ⇒M:M+1 — — — — — — — — — — — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ — — — M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-19 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description 〈ea〉 ⇒ PK : PC Address Mode JMP Jump EXT20 IND20, X IND20, Y IND20, Z EXT20 IND20, X IND20, Y IND20, Z REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 REL16 Opcode 7A 4B 5B 6B FA 89 99 A9 3784 3785 3787 3791 378C 378E 3782 378F 3783 378D 378B 3790 3786 378A 3780 3781 27F9 Instruction Operand zb hh ll zg gggg zg gggg zg gggg zb hh ll zg gggg zg gggg zg gggg rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr Cycles 6 8 8 8 10 12 12 12 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6, 4 6 6 10 S — MV — Condition Codes H — EV — N Z V C ———— JSR Jump to Subroutine Push (PC) (SK : SP) − $0002 ⇒ SK : SP Push (CCR) (SK : SP) − $0002 ⇒ SK : SP 〈ea〉 ⇒ PK : PC If C = 0, branch If C = 1, branch If Z = 1, branch If EV = 1, branch If N ⊕ V = 0, branch If Z ' (N ⊕ V) = 0, branch If C ' Z = 0, branch If Z ' (N ⊕ V) = 1, branch If C ' Z = 1, branch If N ⊕ V = 1, branch If N = 1, branch If MV = 1, branch If Z = 0, branch If N = 0, branch If 1 = 1, branch If 1 = 0, branch Push (PC) (SK : SP) − 2 ⇒ SK : SP Push (CCR) (SK : SP) − 2 ⇒ SK : SP (PK : PC) + Offset ⇒ PK : PC If V = 0, branch If V = 1, branch (M) ⇒ A — — — — ———— LBCC2 LBCS2 LBEQ2 Long Branch if Carry Clear Long Branch if Carry Set Long Branch if Equal to Zero Long Branch if EV Set Long Branch if Greater Than or Equal to Zero Long Branch if Greater Than Zero Long Branch if Higher Long Branch if Less Than or Equal to Zero Long Branch if Lower or Same Long Branch if Less Than Zero Long Branch if Minus Long Branch if MV Set Long Branch if Not Equal to Zero Long Branch if Plus Long Branch Always Long Branch Never Long Branch to Subroutine — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— Freescale Semiconductor, Inc... LBEV2 LBGE2 LBGT2 LBHI 2 LBLE2 LBLS2 LBLT2 LBMI2 LBMV2 LBNE2 LBPL2 LBRA LBRN LBSR LBVC2 LBVS2 LDAA Long Branch if Overflow Clear Long Branch if Overflow Set Load A REL16 REL16 IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z 3788 3789 45 55 65 75 1745 1755 1765 1775 2745 2755 2765 rrrr rrrr ff ff ff ii gggg gggg gggg hh ll — — — 6, 4 6, 4 6 6 6 2 6 6 6 6 6 6 6 — — — — — — — — — — — — ———— ———— ∆ ∆ 0 — CENTRAL PROCESSING UNIT 4-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (M) ⇒ B Address Mode LDAB Load B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT EXT INH Opcode C5 D5 E5 F5 17C5 17D5 17E5 17F5 27C5 27D5 27E5 85 95 A5 37B5 37C5 37D5 37E5 37F5 2785 2795 27A5 3735 3745 3755 3765 3775 2771 27B0 Instruction Operand ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff jj kk gggg gggg gggg hh ll — — — jj kk gggg gggg gggg hh ll hh ll — Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 8 8 S — MV — Condition Codes H — EV — N ∆ Z ∆ V 0 C ∆ LDD Load D (M : M + 1) ⇒ D — — — — ∆ ∆ 0 — Freescale Semiconductor, Inc... LDE Load E (M : M + 1) ⇒ E — — — — ∆ ∆ 0 — LDED LDHI Load Concatenated E and D Initialize H and I (M : M + 1) ⇒ E (M + 2 : M + 3) ⇒ D (M : M + 1)X ⇒ H R (M : M + 1)Y ⇒ I R (M : M + 1) ⇒ SP — — — — — — — — ———— ———— ∆ ∆ LDS Load SP IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IMM16 IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT CF DF EF 17CF 17DF 17EF 17FF 37BF CC DC EC 37BC 17CC 17DC 17EC 17FC CD DD ED 37BD 17CD 17DD 17ED 17FD CE DE EE 37BE 17CE 17DE 17EE 17FE ff ff ff gggg gggg gggg hh ll jj kk ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 6 4 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 — — — — 0 — LDX Load IX (M : M + 1) ⇒ IX — — — — ∆ ∆ 0 — LDY Load IY (M : M + 1) ⇒ IY — — — — ∆ ∆ 0 — LDZ Load IZ (M : M + 1) ⇒ IZ — — — — ∆ ∆ 0 — M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-21 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Mode LPSTOP Low Power Stop If S then STOP else NOP INH Opcode 27F1 Instruction Operand — Cycles 4, 20 S — MV — Condition Codes H — EV — N Z V C ———— LSR Logical Shift Right IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH 0F 1F 2F 170F 171F 172F 173F 370F ff ff ff gggg gggg gggg hh ll — 8 8 8 8 8 8 8 2 — — — — 0 ∆ ∆ ∆ LSRA Logical Shift Right A — — — — 0 ∆ ∆ ∆ LSRB Logical Shift Right B INH 371F — 2 — — — — 0 ∆ ∆ ∆ Freescale Semiconductor, Inc... LSRD Logical Shift Right D INH 27FF — 2 — — — — 0 ∆ ∆ ∆ LSRE Logical Shift Right E INH 277F — 2 — — — — 0 ∆ ∆ ∆ LSRW Logical Shift Right Word IND16, X IND16, Y IND16, Z EXT (HR) ∗ (IR) ⇒ E : D (AM) + (E : D) ⇒ AM Qualified (IX) ⇒ IX Qualified (IY) ⇒ IY (HR) ⇒ IZ (M : M + 1)X ⇒ HR (M : M + 1)Y ⇒ IR (M1) ⇒ M2 IMM8 270F 271F 272F 273F 7B gggg gggg gggg hh ll xoyo 8 8 8 8 12 — — — — 0 ∆ ∆ ∆ MAC Multiply and Accumulate Signed 16-Bit Fractions — ∆ — ∆ —— ∆ — MOVB Move Byte IXP to EXT EXT to IXP EXT to EXT IXP to EXT EXT to IXP EXT to EXT INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH INH INH IND16, X IND16, Y IND16, Z EXT INH 30 32 37FE 31 33 37FF 3724 02 12 22 1702 1712 1722 1732 3702 3712 27F2 2772 2702 2712 2722 2732 274C ff hh ll ff hh ll hh ll hh ll ff hh ll ff hh ll hh ll hh ll — ff ff ff gggg gggg gggg hh ll — — — — gggg gggg gggg hh ll — 8 8 10 8 8 10 10 8 8 8 8 8 8 8 2 2 2 2 8 8 8 8 2 — — — — ∆ ∆ 0 — MOVW Move Word (M : M + 11) ⇒ M : M + 12 — — — — ∆ ∆ 0 — MUL NEG Multiply Negate Memory (A) ∗ (B) ⇒ D $00 − (M) ⇒ M — — — — — — — — ——— ∆ ∆ ∆ ∆ ∆ NEGA NEGB NEGD NEGE NEGW Negate A Negate B Negate D Negate E Negate Memory Word $00 − (A) ⇒ A $00 − (B) ⇒ B $0000 − (D) ⇒ D $0000 − (E) ⇒ E $0000 − (M : M + 1) ⇒M:M+1 — — — — — — — — — — — — — — — — — — — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ NOP Null Operation — — — — — ———— CENTRAL PROCESSING UNIT 4-22 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (A) ' (M) ⇒ A Address Mode ORAA OR A IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT IMM16 INH Opcode 47 57 67 77 1747 1757 1767 1777 2747 2757 2767 C7 D7 E7 F7 17C7 17D7 17E7 17F7 27C7 27D7 27E7 87 97 A7 37B7 37C7 37D7 37E7 37F7 2787 2797 27A7 3737 3747 3757 3767 3777 373B 3708 Instruction Operand ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff jj kk gggg gggg gggg hh ll — — — jj kk gggg gggg gggg hh ll jj kk — Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 4 4 S — MV — Condition Codes H — EV — N ∆ Z ∆ V 0 C — ORAB OR B (B) ' (M) ⇒ B — — — — ∆ ∆ 0 — Freescale Semiconductor, Inc... ORD OR D (D) ' (M : M + 1) ⇒ D — — — — ∆ ∆ 0 — ORE OR E (E) ' (M : M + 1) ⇒ E — — — — ∆ ∆ 0 — ORP 1 PSHA OR Condition Code Register Push A (CCR) ' IMM16 ⇒ CCR (SK : SP) + $0001 ⇒ SK : SP Push (A) (SK : SP) − $0002 ⇒ SK : SP (SK : SP) + $0001 ⇒ SK : SP Push (B) (SK : SP) − $0002 ⇒ SK : SP For mask bits 0 to 7: If mask bit set Push register (SK : SP) − 2 ⇒ SK : SP ∆ — ∆ — ∆ — ∆ — ∆ ∆ ∆ ∆ ———— PSHB Push B INH 3718 — 4 — — — — ———— PSHM Push Multiple Registers Mask bits: 0=D 1=E 2 = IX 3 = IY 4 = IZ 5=K 6 = CCR 7 = (Reserved) IMM8 34 ii 4 + 2N — — — — ———— N= number of registers pushed PSHMAC PULA Push MAC Registers Pull A MAC Registers ⇒ Stack (SK : SP) + $0002 ⇒ SK : SP Pull (A) (SK : SP) – $0001 ⇒ SK : SP (SK : SP) + $0002 ⇒ SK : SP Pull (B) (SK : SP) – $0001 ⇒ SK : SP INH INH 27B8 3709 — — 14 6 — — — — — — — — ———— ———— PULB Pull B INH 3719 — 6 — — — — ———— M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-23 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Mode PULM1 Pull Multiple Registers Mask bits: 0 = CCR[15:4] 1=K 2 = IZ 3 = IY 4 = IX 5=E 6=D 7 = (Reserved) PULMAC RMAC Pull MAC State Repeating Multiply and Accumulate Signed 16-Bit Fractions For mask bits 0 to 7: If mask bit set (SK : SP) + 2 ⇒ SK : SP Pull register IMM8 Opcode 35 Instruction Operand ii Cycles 4+2(N+1) N= number of registers pulled S ∆ MV ∆ Condition Codes H ∆ EV ∆ N ∆ Z ∆ V ∆ C ∆ Stack ⇒ MAC Registers Repeat until (E) < 0 (AM) + (H) ∗ (I) ⇒ AM Qualified (IX) ⇒ IX; Qualified (IY) ⇒ IY; (M : M + 1)X ⇒ H; (M : M + 1) ⇒ I Y INH IMM8 27B9 FB — xoyo 16 6 + 12 per iteration — — — ∆ — — — ∆ ———— ———— Freescale Semiconductor, Inc... (E) − 1 ⇒ E Until (E) < $0000 ROL Rotate Left IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH 0C 1C 2C 170C 171C 172C 173C 370C ff ff ff gggg gggg gggg hh ll — 8 8 8 8 8 8 8 2 — — — — ∆ ∆ ∆ ∆ ROLA Rotate Left A — — — — ∆ ∆ ∆ ∆ ROLB Rotate Left B INH 371C — 2 — — — — ∆ ∆ ∆ ∆ ROLD Rotate Left D INH 27FC — 2 — — — — ∆ ∆ ∆ ∆ ROLE Rotate Left E INH 277C — 2 — — — — ∆ ∆ ∆ ∆ ROLW Rotate Left Word IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH 270C 271C 272C 273C 0E 1E 2E 170E 171E 172E 173E 370E gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll — 8 8 8 8 8 8 8 8 8 8 8 2 — — — — ∆ ∆ ∆ ∆ ROR Rotate Right Byte — — — — ∆ ∆ ∆ ∆ RORA Rotate Right A — — — — ∆ ∆ ∆ ∆ RORB Rotate Right B INH 371E — 2 — — — — ∆ ∆ ∆ ∆ RORD Rotate Right D INH 27FE — 2 — — — — ∆ ∆ ∆ ∆ RORE Rotate Right E INH 277E — 2 — — — — ∆ ∆ ∆ ∆ CENTRAL PROCESSING UNIT 4-24 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Address Mode RORW Rotate Right Word IND16, X IND16, Y IND16, Z EXT (SK : SP) + 2 ⇒ SK : SP Pull CCR (SK : SP) + 2 ⇒ SK : SP Pull PC (PK : PC) − 6 ⇒ PK : PC (SK : SP) + 2 ⇒ SK : SP Pull PK (SK : SP) + 2 ⇒ SK : SP Pull PC (PK : PC) − 2 ⇒ PK : PC (A) − (B) ⇒ A (A) − (M) − C ⇒ A INH Opcode 270E 271E 272E 273E 2777 Instruction Operand gggg gggg gggg hh ll — Cycles 8 8 8 8 12 S — MV — Condition Codes H — EV — N ∆ Z ∆ V ∆ C ∆ RTI 3 Return from Interrupt ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ RTS 4 Return from Subroutine INH 27F7 — 12 — — — — ———— SBA Subtract B from A Subtract with Carry from A INH IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z 370A 42 52 62 72 1742 1752 1762 1772 2742 2752 2762 C2 D2 E2 F2 17C2 17D2 17E2 17F2 27C2 27D2 27E2 82 92 A2 37B2 37C2 37D2 37E2 37F2 2782 2792 27A2 3732 3742 3752 3762 3772 2779 4A 5A 6A 174A 175A 176A 177A 274A 275A 276A — ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff jj kk gggg gggg gggg hh ll — — — jj kk gggg gggg gggg hh ll — ff ff ff gggg gggg gggg hh ll — — — 2 6 6 6 2 6 6 6 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 2 4 4 4 6 6 6 6 4 4 4 — — — — — — — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ Freescale Semiconductor, Inc... SBCA SBCB Subtract with Carry from B (B) − (M) − C ⇒ B — — — — ∆ ∆ ∆ ∆ SBCD Subtract with Carry from D (D) − (M : M + 1) − C ⇒ D — — — — ∆ ∆ ∆ ∆ SBCE Subtract with Carry from E (E) − (M : M + 1) − C ⇒ E — — — — ∆ ∆ ∆ ∆ SDE STAA Subtract D from E Store A (E) − (D)⇒ E (A) ⇒ M — — — — — — — — ∆ ∆ ∆ ∆ ∆ 0 ∆ — M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-25 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (B) ⇒ M Address Mode STAB Store B IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND16, X IND16, Y IND16, Z EXT EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z Opcode CA DA EA 17CA 17DA 17EA 17FA 27CA 27DA 27EA 8A 9A AA 37CA 37DA 37EA 37FA 278A 279A 27AA 374A 375A 376A 377A 2773 8F 9F AF 178F 179F 17AF 17BF 8C 9C AC 178C 179C 17AC 17BC 8D 9D AD 178D 179D 17AD 17BD 8E 9E AE 178E 179E 17AE 17BE 40 50 60 70 1740 1750 1760 1770 2740 2750 2760 Instruction Operand ff ff ff gggg gggg gggg hh ll — — — ff ff ff gggg gggg gggg hh ll — — — gggg gggg gggg hh ll hh ll ff ff ff gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll ff ff ff gggg gggg gggg hh ll ff ff ff ii gggg gggg gggg hh ll — — — Cycles 4 4 4 6 6 6 6 4 4 4 4 4 4 6 6 6 6 6 6 6 6 6 6 6 8 4 4 4 6 6 6 6 4 4 4 6 6 6 6 4 4 4 6 6 6 6 4 4 4 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 S — MV — Condition Codes H — EV — N ∆ Z ∆ V 0 C — STD Store D (D) ⇒ M : M + 1 — — — — ∆ ∆ 0 — Freescale Semiconductor, Inc... STE Store E (E) ⇒ M : M + 1 — — — — ∆ ∆ 0 — STED STS Store Concatenated D and E Store Stack Pointer (E) ⇒ M : M + 1 (D) ⇒ M + 2 : M + 3 (SP) ⇒ M : M + 1 — — — — — — — — ———— ∆ ∆ 0 — STX Store IX (IX) ⇒ M : M + 1 — — — — ∆ ∆ 0 — STY Store IY (IY) ⇒ M : M + 1 — — — — ∆ ∆ 0 — STZ Store Z (IZ) ⇒ M : M + 1 — — — — ∆ ∆ 0 — SUBA Subtract from A (A) − (M) ⇒ A — — — — ∆ ∆ ∆ ∆ CENTRAL PROCESSING UNIT 4-26 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (B) − (M) ⇒ B Address Mode SUBB Subtract from B IND8, X IND8, Y IND8, Z IMM8 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IND8, X IND8, Y IND8, Z IMM16 IND16, X IND16, Y IND16, Z EXT E, X E, Y E, Z IMM16 IND16, X IND16, Y IND16, Z EXT INH Opcode C0 D0 E0 F0 17C0 17D0 17E0 17F0 27C0 27D0 27E0 80 90 A0 37B0 37C0 37D0 37E0 37F0 2780 2790 27A0 3730 3740 3750 3760 3770 3720 Instruction Operand ff ff ff ii gggg gggg gggg hh ll — — — ff ff ff jj kk gggg gggg gggg hh ll — — — jj kk gggg gggg gggg hh ll — Cycles 6 6 6 2 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 4 6 6 6 6 16 S — MV — Condition Codes H — EV — N ∆ Z ∆ V ∆ C ∆ SUBD Subtract from D (D) − (M : M + 1) ⇒ D — — — — ∆ ∆ ∆ ∆ Freescale Semiconductor, Inc... SUBE Subtract from E (E) − (M : M + 1) ⇒ E — — — — ∆ ∆ ∆ ∆ SWI Software Interrupt (PK : PC) + $0002 ⇒ PK : PC Push (PC) (SK : SP) − $0002 ⇒ SK : SP Push (CCR) (SK : SP) − $0002 ⇒ SK : SP $0 ⇒ PK SWI Vector ⇒ PC If B7 = 1 then $FF ⇒ A else $00 ⇒ A (A) ⇒ B (A[7:0]) ⇒ CCR[15:8] (B) ⇒ A (B[3:0]) ⇒ EK (B[3:0]) ⇒ SK (B[3:0]) ⇒ XK (B[3:0]) ⇒ YK (B[3:0]) ⇒ ZK (D) ⇒ E (D[15:8]) ⇒ X MASK (D[7:0]) ⇒ Y MASK (D) ⇒ CCR[15:4] (E) ⇒ D (E) ⇒ AM[31:16] (D) ⇒ AM[15:0] AM[35:32] = AM31 (EK) ⇒ B[3:0] $0 ⇒ B[7:4] (E) ⇒ AM[31:16] $00 ⇒ AM[15:0] AM[35:32] = AM31 Rounded (AM) ⇒ Temp If (SM • (EV ' MV)) then Saturation Value ⇒ E else Temp[31:16] ⇒ E — — — — ———— SXT Sign Extend B into A INH 27F8 — 2 — — — — ∆ ∆ —— TAB TAP TBA TBEK TBSK TBXK TBYK TBZK TDE TDMSK TDP1 TED TEDM Transfer A to B Transfer A to CCR Transfer B to A Transfer B to EK Transfer B to SK Transfer B to XK Transfer B to YK Transfer B to ZK Transfer D to E Transfer D to XMSK : YMSK Transfer D to CCR Transfer E to D Transfer E and D to AM[31:0] Sign Extend AM Transfer EK to B Transfer E to AM[31:16] Sign Extend AM Clear AM LSB Transfer Rounded AM to E INH INH INH INH INH INH INH INH INH INH INH INH INH 3717 37FD 3707 27FA 379F 379C 379D 379E 277B 372F 372D 27FB 27B1 — — — — — — — — — — — — — 2 4 2 2 2 2 2 2 2 2 4 2 4 — ∆ — — — — — — — — ∆ — — — ∆ — — — — — — — — ∆ — 0 — ∆ — — — — — — — — ∆ — — — ∆ — — — — — — — — ∆ — 0 ∆ ∆ ∆ ∆ ∆ ∆ 0 ∆ 0 — ∆ — ———— ———— ———— ———— ———— ∆ ∆ 0 — ———— ∆ ∆ ∆ ∆ ∆ 0 ∆ — ———— TEKB TEM INH INH 27BB 27B2 — — 2 4 — — — 0 — — — 0 ———— ———— TMER INH 27B4 — 6 — ∆ — ∆ ∆ ∆ —— M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-27 Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description If (SM • (EV ' MV)) then Saturation Value ⇒ E else AM[31:16] ⇒ E AM[35:32] ⇒ IX[3:0] AM35 ⇒ IX[15:4] AM[31:16] ⇒ E AM[15:0] ⇒ D (CCR[15:8]) ⇒ A (CCR) ⇒ D (SK) ⇒ B[3:0] $0 ⇒ B[7:4] (M) − $00 Address Mode TMET Transfer Truncated AM to E Transfer AM to IX : E : D INH Opcode 27B5 Instruction Operand — Cycles 2 S — MV — Condition Codes H — EV — N ∆ Z ∆ V C —— TMXED INH 27B3 — 6 — — — — ———— TPA TPD TSKB TST Transfer CCR to A Transfer CCR to D Transfer SK to B Test Byte Zero or Minus INH INH INH IND8, X IND8, Y IND8, Z IND16, X IND16, Y IND16, Z EXT INH INH INH INH IND16, X IND16, Y IND16, Z EXT INH INH INH INH INH INH INH INH INH INH INH INH INH INH INH INH INH INH INH 37FC 372C 37AF 06 16 26 1706 1716 1726 1736 3706 3716 27F6 2776 2706 2716 2726 2736 274F 275F 276F 37AC 374E 275C 276C 37AD 375E 274D 276D 37AE 376E 274E 275E 27F3 371A 277A 37CC — — — ff ff ff gggg gggg gggg hh ll — — — — gggg gggg gggg hh ll — — — — — — — — — — — — — — — — — — — 2 2 2 6 6 6 6 6 6 6 2 2 2 2 6 6 6 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 8 2 2 2 — — — — — — — — — — — — — — — — ———— ———— ———— ∆ ∆ 0 0 Freescale Semiconductor, Inc... TSTA TSTB TSTD TSTE TSTW Test A for Zero or Minus Test B for Zero or Minus Test D for Zero or Minus Test E for Zero or Minus Test for Zero or Minus Word (A) − $00 (B) − $00 (D) − $0000 (E) − $0000 (M : M + 1) − $0000 — — — — — — — — — — — — — — — — — — — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ 0 0 0 0 0 0 0 0 0 0 TSX TSY TSZ TXKB TXS TXY TXZ TYKB TYS TYX TYZ TZKB TZS TZX TZY WAI XGAB XGDE XGDX Transfer SP to X Transfer SP to Y Transfer SP to Z Transfer XK to B Transfer X to SP Transfer X to Y Transfer X to Z Transfer YK to B Transfer Y to SP Transfer Y to X Transfer Y to Z Transfer ZK to B Transfer Z to SP Transfer Z to X Transfer Z to Y Wait for Interrupt Exchange A with B Exchange D with E Exchange D with IX (SK : SP) + $0002 ⇒ XK : IX (SK : SP) + $0002 ⇒ YK : IY (SK : SP) + $0002 ⇒ ZK : IZ (XK) ⇒ B[3:0] $0 ⇒ B[7:4] (XK : IX) − $0002 ⇒ SK : SP (XK : IX) ⇒ YK : IY (XK : IX) ⇒ ZK : IZ (YK) ⇒ B[3:0] $0 ⇒ B[7:4] (YK : IY) − $0002 ⇒ SK : SP (YK : IY) ⇒ XK : IX (YK : IY) ⇒ ZK : IZ (ZK) ⇒ B[3:0] $0 ⇒ B[7:4] (ZK : IZ) − $0002 ⇒ SK : SP (ZK : IZ) ⇒ XK : IX (ZK : IZ) ⇒ YK : IY WAIT (A) ⇔ (B) (D) ⇔ (E) (D) ⇔ (IX) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— CENTRAL PROCESSING UNIT 4-28 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description (D) ⇔ (IY) (D) ⇔ (IZ) (E) ⇔ (IX) (E) ⇔ (IY) (E) ⇔ (IZ) Address Mode XGDY XGDZ XGEX XGEY XGEZ Exchange D with IY Exchange D with IZ Exchange E with IX Exchange E with IY Exchange E with IZ INH INH INH INH INH Opcode 37DC 37EC 374C 375C 376C Instruction Operand — — — — — Cycles 2 2 2 2 2 S — — — — — MV — — — — — Condition Codes H — — — — — EV — — — — — N Z V C ———— ———— ———— ———— ———— NOTES: 1. CCR[15:4] change according to the results of the operation. The PK field is not affected. 2. Cycle times for conditional branches are shown in “taken, not taken” order. 3. CCR[15:0] change according to the copy of the CCR pulled from the stack. 4. PK field changes according to the state pulled from the stack. The rest of the CCR is not affected. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-29 Freescale Semiconductor, Inc. Table 4-3 Instruction Set Abbreviations and Symbols A — Accumulator A AM — Accumulator M B — Accumulator B CCR — Condition code register D — Accumulator D E — Accumulator E EK — Extended addressing extension field IR — MAC multiplicand register HR — MAC multiplier register IX — Index register X IY — Index register Y IZ — Index register Z K — Address extension register PC — Program counter X — Register used in operation M — Address of one memory byte M +1 — Address of byte at M + $0001 M : M + 1 — Address of one memory word (…)X — Contents of address pointed to by IX (...)Y — Contents of address pointed to by IY (...)Z — Contents of address pointed to by IZ E, X — IX with E offset E, Y — IY with E offset E, Z — IZ with E offset EXT — Extended EXT20 — 20-bit extended IMM8 — 8-bit immediate IMM16 — 16-bit immediate IND8, X — IX with unsigned 8-bit offset IND8, Y — IY with unsigned 8-bit offset IND8, Z — IZ with unsigned 8-bit offset IND16, X — IX with signed 16-bit offset IND16, Y — IY with signed 16-bit offset IND16, Z — IZ with signed 16-bit offset IND20, X — IX with signed 20-bit offset IND20, Y — IY with signed 20-bit offset IND20, Z — IZ with signed 20-bit offset INH — Inherent IXP — Post-modified indexed REL8 — 8-bit relative REL16 — 16-bit relative b — 4-bit address extension ff — 8-bit unsigned offset gggg — 16-bit signed offset hh — High byte of 16-bit extended address ii — 8-bit immediate data jj — High byte of 16-bit immediate data kk — Low byte of 16-bit immediate data ll — Low byte of 16-bit extended address mm — 8-bit mask mmmm — 16-bit mask rr — 8-bit unsigned relative offset rrrr — 16-bit signed relative offset xo — MAC index register X offset yo — MAC index register Y offset z — 4-bit zero extension + — Addition − — Subtraction or negation (two’s complement) ∗ — Multiplication / — Division > — Greater < — Less = — Equal ≥ — Equal or greater ≤ — Equal or less ≠ — Not equal • — AND ' — Inclusive OR (OR) ⊕ — Exclusive OR (EOR) NOT — Complementation : — Concatenation ⇒ — Transferred ⇔ — Exchanged ± — Sign bit; also used to show tolerance « — Sign extension % — Binary value $ — Hexadecimal value Freescale Semiconductor, Inc... PK — Program counter extension field SK — Stack pointer extension field SL — Multiply and accumulate sign latch SP — Stack pointer XK — Index register X extension field YK — Index register Y extension field ZK — Index register Z extension field XMSK — Modulo addressing index register X mask YMSK — Modulo addressing index register Y mask S — Stop disable control bit MV — AM overflow indicator H — Half carry indicator EV — AM extended overflow indicator N — Negative indicator Z — Zero indicator V — Two’s complement overflow indicator C — Carry/borrow indicator IP — Interrupt priority field SM — Saturation mode control bit PK — Program counter extension field — — Bit not affected ∆ — Bit changes as specified 0 — Bit cleared 1 — Bit set M — Memory location used in operation R — Result of operation S — Source data CENTRAL PROCESSING UNIT 4-30 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 4.8 Comparison of CPU16 and M68HC11 CPU Instruction Sets Most M68HC11 CPU instructions are a source-code compatible subset of the CPU16 instruction set. However, certain M68HC11 CPU instructions have been replaced by functionally equivalent CPU16 instructions, and some CPU16 instructions with the same mnemonics as M68HC11 CPU instructions operate differently. Table 4-4 shows the M68HC11 CPU instructions that either have been replaced by CPU16 instructions or that operate differently on the CPU16. Replacement instructions are not identical to M68HC11 CPU instructions. M68HC11 code must be altered to establish proper preconditions. All CPU16 instruction execution times differ from those of the M68HC11. Transporting M68HC11 Code to M68HC16 Devices, (M68HC16PN01/D), contains detailed information about differences between the two instruction sets. Refer to the CPU16 Reference Manual (CPU16RM/AD) for further details about CPU operations. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-31 Freescale Semiconductor, Inc. Table 4-4 CPU16 Implementation of M68HC11 CPU Instructions M68HC11 Instruction BHS BLO BSR CLC CLI CLV DES DEX DEY INS BCC only BCS only Generates a different stack frame Replaced by ANDP Replaced by ANDP Replaced by ANDP Replaced by AIS Replaced by AIX Replaced by AIY Replaced by AIS Replaced by AIX Replaced by AIY IND8 and EXT addressing modes replaced by IND20 and EXT20 modes IND8 and EXT addressing modes replaced by IND20 and EXT20 modes. Generates a different stack frame Use ASL instructions1 Replaced by PSHM Replaced by PSHM Replaced by PULM Replaced by PULM Reloads PC and CCR only Uses two-word stack frame Replaced by ORP Replaced by ORP Replaced by ORP Replaced by LPSTOP CPU16 CCR bits differ from M68HC11 CPU16 interrupt priority scheme differs from M68HC11 CPU16 CCR bits differ from M68HC11 CPU16 interrupt priority scheme differs from M68HC11 Adds two to SK : SP before transfer to XK : IX Adds two to SK : SP before transfer to YK : IY Subtracts two from XK : IX before transfer to SK : SP Transfers XK field to YK field Subtracts two from YK : IY before transfer to SK : SP Transfers YK field to XK field Waits indefinitely for interrupt or reset Generates a different stack frame CPU16 Implementation Freescale Semiconductor, Inc... INX INY JMP JSR LSL, LSLD PSHX PSHY PULX PULY RTI RTS SEC SEI SEV STOP TAP TPA TSX TSY TXS TXY TYS TYX WAI NOTES: 1. Freescale assemblers automatically translate ASL mnemonics. CENTRAL PROCESSING UNIT 4-32 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 4.9 Instruction Format CPU16 instructions consist of an 8-bit opcode that can be preceded by an 8-bit prebyte and followed by one or more operands. Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone. Page 1, 2, and 3 opcodes are pointed to by a prebyte code on page 0. The prebytes are $17 (page 1), $27 (page 2), and $37 (page 3). Operands can be four bits, eight bits or sixteen bits in length. Since the CPU16 fetches 16-bit instruction words from even-byte boundaries, each instruction must contain an even number of bytes. Operands are organized as bytes, words, or a combination of bytes and words. Operands of four bits are either zero-extended to eight bits, or packed two to a byte. The largest instructions are six bytes in length. Size, order, and function of operands are evaluated when an instruction is decoded. A page 0 opcode and an 8-bit operand can be fetched simultaneously. Instructions that use 8-bit indexed, immediate, and relative addressing modes have this form. Code written with these instructions is very compact. Figure 4-4 shows basic CPU16 instruction formats. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-33 Freescale Semiconductor, Inc. 8-Bit Opcode with 8-Bit Operand 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode Operand 8-Bit Opcode with 4-Bit Index Extensions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode X Extension Y Extension 8-Bit Opcode, Argument(s) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode Operand(s) Operand(s) Operand Freescale Semiconductor, Inc... 8-Bit Opcode with 8-Bit Prebyte, No Argument 15 14 13 12 11 10 9 8 7 6 5 4 Opcode 3 2 1 0 Prebyte 8-Bit Opcode with 8-Bit Prebyte, Argument(s) 15 14 13 12 11 10 9 8 7 6 5 4 Opcode Operand(s) Operand(s) 3 2 1 0 Prebyte 8-Bit Opcode with 20-Bit Argument 15 14 13 12 11 10 9 8 7 6 $0 Operand 5 4 3 2 1 0 Opcode Extension Figure 4-4 Basic Instruction Formats 4.10 Execution Model This description builds up a conceptual model of the mechanism the CPU16 uses to fetch and execute instructions. The functional divisions in the model do not necessarily correspond to physical subunits of the microprocessor. As shown in Figure 4-5, there are three functional blocks involved in fetching, decoding, and executing instructions. These are the microsequencer, the instruction pipeline, and the execution unit. These elements function concurrently. All three may be active at any given time. CENTRAL PROCESSING UNIT 4-34 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. IPIPE0 IPIPE1 MICROSEQUENCER INSTRUCTION PIPELINE Freescale Semiconductor, Inc... DATA BUS A B C EXECUTION UNIT 16 EXEC UNIT MODEL Figure 4-5 Instruction Execution Model 4.10.1 Microsequencer The microsequencer controls the order in which instructions are fetched, advanced through the pipeline, and executed. It increments the program counter and generates multiplexed external tracking signals IPIPE0 and IPIPE1 from internal signals that control execution sequence. 4.10.2 Instruction Pipeline The pipeline is a three stage FIFO that holds instructions while they are decoded and executed. Depending upon instruction size, as many as three instructions can be in the pipeline at one time (single-word instructions, one held in stage C, one being executed in stage B, and one latched in stage A). 4.10.3 Execution Unit The execution unit evaluates opcodes, interfaces with the microsequencer to advance instructions through the pipeline, and performs instruction operations. M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-35 Freescale Semiconductor, Inc. 4.11 Execution Process Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are evaluated in stage B. The execution unit can access operands in either stage A or stage B (stage B accesses are limited to 8-bit operands). When execution is complete, opcodes are moved from stage B to stage C, where they remain until the next instruction is complete. A prefetch mechanism in the microsequencer reads instruction words from memory and increments the program counter. When instruction execution begins, the program counter points to an address six bytes after the address of the first word of the instruction being executed. The number of machine cycles necessary to complete an execution sequence varies according to the complexity of the instruction. Refer to the CPU16 Reference Manual (CPU16RM/AD) for details. 4.11.1 Changes in Program Flow When program flow changes, instructions are fetched from a new address. Before execution can begin at the new address, instructions and operands from the previous instruction stream must be removed from the pipeline. If a change in flow is temporary, a return address must be stored, so that execution of the original instruction stream can resume after the change in flow. When an instruction that causes a change in program flow executes, PK : PC point to the address of the first word of the instruction + $0006. During execution of the instruction, PK : PC is loaded with the address of the first instruction word in the new instruction stream. However, stages A and B still contain words from the old instruction stream. Extra processing steps must be performed before execution from the new instruction stream. 4.12 Instruction Timing The execution time of CPU16 instructions has three components: • Bus cycles required to prefetch the next instruction • Bus cycles required for operand accesses • Time required for internal operations A bus cycle requires a minimum of two system clock periods. If the access time of a memory device is greater than two clock periods, bus cycles are longer. However, all bus cycles must be an integer number of clock periods. CPU16 internal operations are always an integer multiple of two clock periods. Dynamic bus sizing affects bus cycle time. The integration module manages all accesses. Refer to SECTION 5 SYSTEM INTEGRATION MODULE for more information. The CPU16 does not execute more than one instruction at a time. The total time required to execute a particular instruction stream can be calculated by summing the individual execution times of each instruction in the stream. CENTRAL PROCESSING UNIT 4-36 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Total execution time is calculated using the expression: ( CL T ) = ( CL P ) + ( CL O ) + ( CL I ) Where: (CLT) = Total clock periods per instruction (CLI) = Clock periods used for internal operation (CLP) = Clock periods used for program access (CLO) = Clock periods used for operand access Freescale Semiconductor, Inc... Refer to the CPU16 Reference Manual (CPU16RM/AD) for more information on this topic. 4.13 Exceptions An exception is an event that preempts normal instruction processing. Exception processing makes the transition from normal instruction execution to execution of a routine that deals with the exception. Each exception has an assigned vector that points to an associated handler routine. Exception processing includes all operations required to transfer control to a handler routine, but does not include execution of the handler routine itself. Keep the distinction between exception processing and execution of an exception handler in mind while reading this section. 4.13.1 Exception Vectors An exception vector is the address of a routine that handles an exception. Exception vectors are contained in a data structure called the exception vector table, which is located in the first 512 bytes of bank 0. Refer to Table 4-5 for the exception vector table. All vectors except the reset vector consist of one word and reside in data space. The reset vector consists of four words that reside in program space. Refer to SECTION 5 SYSTEM INTEGRATION MODULE for information concerning address space types and the function code outputs. There are 52 predefined or reserved vectors, and 200 user-defined vectors. Each vector is assigned an 8-bit number. Vector numbers for some exceptions are generated by external devices; others are supplied by the processor. There is a direct mapping of vector number to vector table address. The processor left shifts the vector number one place (multiplies by two) to convert it to an address. M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-37 Freescale Semiconductor, Inc. Table 4-5 Exception Vector Table Vector Number 0 Vector Address 0000 0002 0004 0006 4 5 6 7 8 0008 000A 000C 000E 0010 0012 – 001C 001E 0020 0022 0024 0026 0028 002A 002C 002E 0030 0032 – 006E 0070 – 01FE Address Space P P P P D D D D D D D D D D D D D D D D D D Type of Exception Reset — Initial ZK, SK, and PK Reset — Initial PC Reset — Initial SP Reset — Initial IZ (Direct Page) Breakpoint Bus Error Software Interrupt Illegal Instruction Division by Zero Unassigned, Reserved Uninitialized Interrupt Unassigned, Reserved Level 1 Interrupt Autovector Level 2 Interrupt Autovector Level 3 Interrupt Autovector Level 4 Interrupt Autovector Level 5 Interrupt Autovector Level 6 Interrupt Autovector Level 7 Interrupt Autovector Spurious Interrupt Unassigned, Reserved User-Defined Interrupts Freescale Semiconductor, Inc... 9–E F 10 11 12 13 14 15 16 17 18 19 – 37 38 – FF 4.13.2 Exception Stack Frame During exception processing, the contents of the program counter and condition code register are stacked at a location pointed to by SK : SP. Unless it is altered during exception processing, the stacked PK : PC value is the address of the next instruction in the current instruction stream, plus $0006. Figure 4-6 shows the exception stack frame. Low Address Condition Code Register High Address Program Counter ⇐ SP Before Exception Stacking ⇐ SP After Exception Stacking Figure 4-6 Exception Stack Frame Format CENTRAL PROCESSING UNIT 4-38 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 4.13.3 Exception Processing Sequence Exception processing is performed in four phases. Priority of all pending exceptions is evaluated and the highest priority exception is processed first. Processor state is stacked, then the CCR PK extension field is cleared. An exception vector number is acquired and converted to a vector address. The content of the vector address is loaded into the PC and the processor jumps to the exception handler routine. There are variations within each phase for differing types of exceptions. However, all vectors except RESET are 16-bit addresses, and the PK field is cleared during exception processing. Consequently, exception handlers must be located within bank 0 or vectors must point to a jump table in bank 0. 4.13.4 Types of Exceptions Exceptions can be either internally or externally generated. External exceptions, which are defined as asynchronous, include interrupts, bus errors, breakpoints, and resets. Internal exceptions, which are defined as synchronous, include the software interrupt (SWI) instruction, the background (BGND) instruction, illegal instruction exceptions, and the divide-by-zero exception. 4.13.4.1 Asynchronous Exceptions Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing is synchronized. For all asynchronous exceptions except RESET, exception processing begins at the first instruction boundary following recognition of an exception. Refer to 5.8.1 Interrupt Exception Processing for more information concerning asynchronous exceptions. Because of pipelining, the stacked return PK : PC value for all asynchronous exceptions, other than reset, is equal to the address of the next instruction in the current instruction stream plus $0006. The RTI instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked value to resume execution of the interrupted instruction stream. 4.13.4.2 Synchronous Exceptions Synchronous exception processing is part of an instruction definition. Exception processing for synchronous exceptions is always completed, and the first instruction of the handler routine is always executed, before interrupts are detected. Because of pipelining, the value of PK : PC at the time a synchronous exception executes is equal to the address of the instruction that causes the exception plus $0006. Because RTI always subtracts $0006 upon return, the stacked PK : PC must be adjusted by the instruction that caused the exception so that execution resumes with the following instruction. For this reason, $0002 is added to the PK : PC value before it is stacked. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-39 Freescale Semiconductor, Inc. 4.13.5 Multiple Exceptions Each exception has a hardware priority based upon its relative importance to system operation. Asynchronous exceptions have higher priorities than synchronous exceptions. Exception processing for multiple exceptions is completed by priority, from highest to lowest. Priority governs the order in which exception processing occurs, not the order in which exception handlers are executed. Unless a bus error, a breakpoint, or a reset occurs during exception processing, the first instruction of all exception handler routines is guaranteed to execute before another exception is processed. Because interrupt exceptions have higher priority than synchronous exceptions, the first instruction in an interrupt handler is executed before other interrupts are sensed. Freescale Semiconductor, Inc... Bus error, breakpoint, and reset exceptions that occur during exception processing of a previous exception are processed before the first instruction of that exception’s handler routine. The converse is not true. If an interrupt occurs during bus error exception processing, for example, the first instruction of the exception handler is executed before interrupts are sensed. This permits the exception handler to mask interrupts during execution. Refer to SECTION 5 SYSTEM INTEGRATION MODULE for detailed information concerning interrupts and system reset. For information concerning processing of specific exceptions, refer to the CPU16 Reference Manual (CPU16RM/AD). 4.13.6 RTI Instruction The return-from-interrupt instruction (RTI) must be the last instruction in all exception handlers except the RESET handler. RTI pulls the exception stack frame that was pushed onto the system stack during exception processing, and restores processor state. Normal program flow resumes at the address of the instruction that follows the last instruction executed before exception processing began. RTI is not used in the RESET handler because RESET initializes the stack pointer and does not create a stack frame. 4.14 Development Support The CPU16 incorporates powerful tools for tracking program execution and for system debugging. These tools are deterministic opcode tracking, breakpoint exceptions, and background debug mode. Judicious use of CPU16 capabilities permits in-circuit emulation and system debugging using a bus state analyzer, a simple serial interface, and a terminal. 4.14.1 Deterministic Opcode Tracking The CPU16 has two multiplexed outputs, IPIPE0 and IPIPE1, that enable external hardware to monitor the instruction pipeline during normal program execution. The signals IPIPE0 and IPIPE1 can be demultiplexed into six pipeline state signals that allow a state analyzer to synchronize with instruction stream activity. CENTRAL PROCESSING UNIT 4-40 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 4.14.1.1 IPIPE0/IPIPE1 Multiplexing Six types of information are required to track pipeline activity. To generate the six state signals, eight pipeline states are encoded and multiplexed into IPIPE0 and IPIPE1. The multiplexed signals have two phases. State signals are active low. Table 4-6 shows the encoding scheme. Table 4-6 IPIPE0/IPIPE1 Encoding Phase IPIPE1 State 0 0 1 1 0 0 1 1 IPIPE0 State 0 1 0 1 0 1 0 1 State Signal Name START and FETCH FETCH START NULL INVALID ADVANCE EXCEPTION NULL 1 Freescale Semiconductor, Inc... 2 IPIPE0 and IPIPE1 are timed so that a logic analyzer can capture all six pipeline state signals and address, data, or control bus state in any single bus cycle. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for specifications. State signals can be latched asynchronously on the falling and rising edges of either address strobe (AS) or data strobe (DS). They can also be latched synchronously using the microcontroller CLKOUT signal. Refer to the CPU16 Reference Manual (CPU16RM/AD) for more information on the CLKOUT signal, state signals, and state signal demux logic. 4.14.1.2 Combining Opcode Tracking with Other Capabilities Pipeline state signals are useful during normal instruction execution and execution of exception handlers. The signals provide a complete model of the pipeline up to the point a breakpoint is acknowledged. Breakpoints are acknowledged after an instruction has executed, when it is in pipeline stage C. A breakpoint can initiate either exception processing or background debug mode. IPIPE0/IPIPE1 are not usable when the CPU16 is in background debug mode. 4.14.2 Breakpoints Breakpoints are set by assertion of the microcontroller BKPT pin. The CPU16 supports breakpoints on any memory access. Acknowledged breakpoints can initiate either exception processing or background debug mode. After BDM has been enabled, the CPU16 will enter BDM when the BKPT input is asserted. • If BKPT assertion is synchronized with an instruction prefetch, the instruction is tagged with the breakpoint when it enters the pipeline, and the breakpoint occurs after the instruction executes. • If BKPT assertion is synchronized with an operand fetch, breakpoint processing occurs at the end of the instruction during which BKPT is latched. M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-41 Freescale Semiconductor, Inc. Breakpoints on instructions that are flushed from the pipeline before execution are not acknowledged. Operand breakpoints are always acknowledged. There is no breakpoint acknowledge bus cycle when BDM is entered. Refer to 5.6.4.1 Breakpoint Acknowledge Cycle for more information about breakpoints. 4.14.3 Opcode Tracking and Breakpoints Breakpoints are acknowledged after a tagged instruction has executed, that is, when the instruction is copied from pipeline stage B to stage C. Stage C contains the opcode of the previous instruction when execution of the current instruction begins. When an instruction is tagged, IPIPE0/IPIPE1 reflect the start of execution and the appropriate number of pipeline advances and operand fetches before the breakpoint is acknowledged. If background debug mode is enabled, these signals model the pipeline before BDM is entered. 4.14.4 Background Debug Mode Microprocessor debugging programs are generally implemented in external software. CPU16 BDM provides a debugger implemented in CPU microcode. BDM incorporates a full set of debug options. Registers can be viewed and altered, memory can be read or written, and test features can be invoked. BDM is an alternate CPU16 operating mode. While the CPU16 is in BDM, normal instruction execution is suspended, and special microcode performs debugging functions under external control. While in BDM, the CPU16 ceases to fetch instructions through the data bus and communicates with the development system through a dedicated serial interface. 4.14.4.1 Enabling BDM The CPU16 samples the BKPT input during reset to determine whether to enable BDM. When BKPT is asserted at the rising edge of the RESET signal, BDM operation is enabled. BDM remains enabled until the next system reset. If BKPT is at logic level one on the trailing edge of RESET, BDM is disabled. BKPT is relatched on each rising transition of RESET. BKPT is synchronized internally and must be asserted for at least two clock cycles before negation of RESET. 4.14.4.2 BDM Sources When BDM is enabled, external breakpoint hardware and the BGND instruction can cause the CPU16 to enter BDM. If BDM is not enabled when a breakpoint occurs, a breakpoint exception is processed. 4.14.4.3 Entering BDM When the CPU16 detects a breakpoint or decodes a BGND instruction when BDM is enabled, it suspends instruction execution and asserts the FREEZE signal. Once FREEZE has been asserted, the CPU16 enables the BDM serial communication hardware and awaits a command. Assertion of FREEZE causes opcode tracking signals IPIPE0 and IPIPE1 to change definition and become serial communication signals DSO and DSI. FREEZE is asserted at the next instruction boundary after the assertion Freescale Semiconductor, Inc... CENTRAL PROCESSING UNIT 4-42 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. of BKPT or execution of the BGND instruction. IPIPE0 and IPIPE1 change function before an exception signal can be generated. The development system must use FREEZE assertion as an indication that BDM has been entered. When BDM is exited, FREEZE is negated before initiation of normal bus cycles. IPIPE0 and IPIPE1 are valid when normal instruction prefetch begins. 4.14.4.4 BDM Commands Commands consist of one 16-bit operation word and can include one or more 16-bit extension words. Each incoming word is read as it is assembled by the serial interface. The microcode routine corresponding to a command is executed as soon as the command is complete. Result operands are loaded into the output shift register to be shifted out as the next command is read. This process is repeated for each command until the CPU returns to normal operating mode. The BDM command set is summarized in Table 4-7. Refer to the CPU16 Reference Manual (CPU16RM/AD) for a BDM command glossary. Table 4-7 Command Summary Command Read Registers from Mask Write Registers from Mask Read MAC Registers Write MAC Registers Read PC and SP Write PC and SP Read Data Memory Write Data Memory Read Program Memory Write Program Memory Execute from Current PK : PC Null Operation Mnemonic RREGM WREGM RDMAC WRMAC RPCSP WPCSP RDMEM WDMEM RPMEM WPMEM GO NOP Description Read contents of registers specified by command word register mask Write to registers specified by command word register mask Read contents of entire multiply and accumulate register set Write to entire multiply and accumulate register set Read contents of program counter and stack pointer Write to program counter and stack pointer Read byte from specified 20-bit address in data space Write byte to specified 20-bit address in data space Read word from specified 20-bit address in program space Write word to specified 20-bit address in program space Instruction pipeline flushed and refilled; instructions executed from current PC – $0006 Null command performs no operation Freescale Semiconductor, Inc... 4.14.4.5 Returning from BDM BDM is terminated when a resume execution (GO) command is received. GO refills the instruction pipeline from address (PK : PC – $0006). FREEZE is negated before the first prefetch. Upon negation of FREEZE, the BDM serial subsystem is disabled and the DSO/DSI signals revert to IPIPE0/IPIPE1 functionality. M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-43 Freescale Semiconductor, Inc. 4.14.4.6 BDM Serial Interface The BDM serial interface uses a synchronous protocol similar to that of the Freescale serial peripheral interface (SPI). Figure 4-7 is a diagram of the serial logic required to use BDM with a development system. CPU INSTRUCTION REGISTER BUS 16 RCV DATA LATCH DEVELOPMENT SYSTEM DATA 16 0 COMMAND LATCH Freescale Semiconductor, Inc... SERIAL IN PARALLEL OUT DSI PARALLEL IN SERIAL OUT DSO PARALLEL IN SERIAL OUT 16 STATUS EXECUTION UNIT SYNCHRONIZE MICROSEQUENCER STATUS RESULT LATCH 16 DATA SERIAL IN PARALLEL OUT CONTROL LOGIC DSCLK CONTROL LOGIC SERIAL CLOCK BDM SER COM BLOCK Figure 4-7 BDM Serial I/O Block Diagram The development system serves as the master of the serial link, and is responsible for the generation of the serial interface clock signal (DSCLK). Serial clock frequency range is from DC to one-half the CPU16 clock frequency. If DSCLK is derived from the CPU16 system clock, development system serial logic can be synchronized with the target processor. The serial interface operates in full-duplex mode. Data transfers occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data is transmitted MSB first, and is latched on the rising edge of DSCLK. The serial data word is 17 bits wide, which includes 16 data bits and a status/control bit. Bit 16 indicates status of CPU-generated messages. Command and data transfers initiated by the development system must clear bit 16. All commands that return a result return 16 bits of data plus one status bit. CENTRAL PROCESSING UNIT 4-44 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 4.15 Recommended BDM Connection In order to use BDM development tools when an MCU is installed in a system, Freescale recommends that appropriate signal lines be routed to a male Berg connector or double-row header installed on the circuit board with the MCU. Refer to Figure 4-8. DS GND GND RESET VDD 1 3 5 7 9 2 4 6 8 10 BERR BKPT/DSCLK FREEZE IPIPE1/DSI IPIPE0/DSO Freescale Semiconductor, Inc... BDM CONN Figure 4-8 BDM Connector Pinout 4.16 Digital Signal Processing The CPU16 performs low-frequency digital signal processing (DSP) algorithms in real time. The most common DSP operation in embedded control applications is filtering, but the CPU16 can perform several other useful DSP functions. These include autocorrelation (detecting a periodic signal in the presence of noise), cross-correlation (determining the presence of a defined periodic signal), and closed-loop control routines (selective filtration in a feedback path). Although derivation of DSP algorithms is often a complex mathematical task, the algorithms themselves typically consist of a series of multiply and accumulate (MAC) operations. The CPU16 contains a dedicated set of registers that perform MAC operations. As a group, these registers are called the MAC unit. DSP operations generally require a large number of MAC iterations. The CPU16 instruction set includes instructions that perform MAC setup and repetitive MAC operations. Other instructions, such as 32-bit load and store instructions, can also be used in DSP routines. Many DSP algorithms require extensive data address manipulation. To increase throughput, the CPU16 performs effective address calculations and data prefetches during MAC operations. In addition, the MAC unit provides modulo addressing to implement circular DSP buffers efficiently. Refer to the CPU16 Reference Manual (CPU16RM/AD) for detailed information concerning the MAC unit and execution of DSP instructions. M68HC16 Z SERIES USER’S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com 4-45 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... CENTRAL PROCESSING UNIT 4-46 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 5 SYSTEM INTEGRATION MODULE This section is an overview of the system integration module (SIM). Refer to the SIM Reference Manual (SIMRM/AD) for a comprehensive discussion of SIM capabilities. Refer to D.2 System Integration Module for information concerning the SIM address map and register structure. 5.1 General The SIM consists of six functional blocks. Figure 5-1 shows a block diagram of the SIM. The system configuration block controls MCU configuration parameters. The system clock generates clock signals used by the SIM, other IMB modules, and external devices. The system protection block provides bus and software watchdog monitors. In addition, it also provides a periodic interrupt timer to support execution of time-critical control routines. The external bus interface handles the transfer of information between IMB modules and external address space. The chip-select block provides 12 chip-select signals. Each chip-select signal has an associated base address register and option register that contain the programmable characteristics of that chip-select. The system test block incorporates hardware necessary for testing the MCU. It is used to perform factory tests, and its use in normal applications is not supported. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-1 Freescale Semiconductor, Inc. SYSTEM CONFIGURATION CLOCK SYNTHESIZER XTAL CLKOUT EXTAL MODCLK SYSTEM PROTECTION CHIP-SELECTS CHIP-SELECTS Freescale Semiconductor, Inc... EXTERNAL BUS EXTERNAL BUS INTERFACE RESET FACTORY TEST TSC FREEZE/QUOT Z SERIES SIM BLOCK Figure 5-1 System Integration Module Block Diagram 5.2 System Configuration The SIM configuration register (SIMCR) governs several aspects of system operation. The following paragraphs describe those configuration options controlled by SIMCR. 5.2.1 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping (MM) bit in the SIM configuration register (SIMCR) determines where the control register block is located in the system memory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when MM = 1, register addresses range from $FFF000 to $FFFFFF. In M68HC16 Z-series MCUs, ADDR[23:20] follow the logic state of ADDR19 unless externally driven. MM corresponds to IMB ADDR23. If MM is cleared, the SIM maps IMB modules into address space $7FF000 – $7FFFFF, which is inaccessible to the CPU16. Modules remain inaccessible until reset occurs. The reset state of MM is one, but the bit can be written once. Initialization software should make certain MM remains set. SYSTEM INTEGRATION MODULE 5-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 5.2.2 Interrupt Arbitration Each module that can request interrupts has an interrupt arbitration (IARB) field. Arbitration between interrupt requests of the same priority is performed by serial contention between IARB field bit values. Contention will take place whenever an interrupt request is acknowledged, even when there is only a single request pending. For an interrupt to be serviced, the appropriate IARB field must have a non-zero value. If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU16 processes a spurious interrupt exception. Because the SIM routes external interrupt requests to the CPU16, the SIM IARB field value is used for arbitration between internal and external interrupts of the same priority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is %0000, which prevents SIM interrupts from being discarded during initialization. Refer to 5.8 Interrupts for a discussion of interrupt arbitration. 5.2.3 Show Internal Cycles A show cycle allows internal bus transfers to be monitored externally. The SHEN field in SIMCR determines what the external bus interface does during internal transfer operations. Table 5-1 shows whether data is driven externally, and whether external bus arbitration can occur. Refer to 5.6.6.1 Show Cycles for more information. Table 5-1 Show Cycle Enable Bits SHEN[1:0] 00 01 10 11 Action Show cycles disabled, external arbitration enabled Show cycles enabled, external arbitration disabled Show cycles enabled, external arbitration enabled Show cycles enabled, external arbitration enabled; internal activity is halted by a bus grant Freescale Semiconductor, Inc... 5.2.4 Register Access M68HC16 Z-series MCUs always operate at the supervisor level. The state of the SUPV bit has no meaning. 5.2.5 Freeze Operation The FREEZE signal halts MCU operations during debugging. FREEZE is asserted internally by the CPU16 if a breakpoint occurs while background mode is enabled. When FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt timer are affected. The halt monitor and spurious interrupt monitor continue to operate normally. Setting the freeze bus monitor (FRZBM) bit in SIMCR disables the bus monitor when FREEZE is asserted. Setting the freeze software watchdog (FRZSW) bit disables the software watchdog and the periodic interrupt timer when FREEZE is asserted. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-3 Freescale Semiconductor, Inc. 5.3 System Clock The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral bus. Because the MCU is a fully static design, register and memory contents are not affected when the clock rate changes. System hardware and software support changes in clock rate during operation. The system clock signal can be generated from one of three sources. An internal phase-locked loop (PLL) can synthesize the clock from a fast reference, a slow reference, or the clock signal can be directly input from an external frequency source. NOTE Whether the PLL can use a fast or slow reference is determined by the device. A particular device cannot use both a fast and slow reference. The fast reference is typically a 4.194-MHz crystal; the slow reference is typically a 32.768-kHz crystal. Each reference frequency may be generated by sources other than a crystal. Keep these sources in mind while reading the rest of this section. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for clock specifications. Figure 5-2 is a block diagram of the clock submodule. Freescale Semiconductor, Inc... MODCLK EXTAL XTAL XFC VDDSYN CLKOUT CRYSTAL OSCILLATOR 1281 PHASE COMPARATOR LOW-PASS FILTER VCO FEEDBACK DIVIDER W Y SYSTEM CLOCK CONTROL X SYSTEM CLOCK NOTES: 1. ÷ 128 IS PRESENT ONLY ON DEVICES WITH A FAST REFERENCE OSCILLATOR. Z SERIES PLL BLOCK Figure 5-2 System Clock Block Diagram SYSTEM INTEGRATION MODULE 5-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 5.3.1 Clock Sources The state of the clock mode (MODCLK) pin during reset determines the system clock source. When MODCLK is held high during reset, the clock synthesizer generates a clock signal from an external reference frequency. The clock synthesizer control register (SYNCR) determines operating frequency and mode of operation. When MODCLK is held low during reset, the clock synthesizer is disabled and an external system clock signal must be driven onto the EXTAL pin. The input clock, referred to as fref, can be either a crystal or an external clock source. The output of the clock system is referred to as fsys. Ensure that fref and fsys are within normal operating limits. To generate a reference frequency using the crystal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. Typically, a 32.768-kHz crystal is used for a slow reference, but the frequency may vary between 25 kHz to 50 kHz. Figure 5-3 shows a typical circuit. C1 22 pF* Freescale Semiconductor, Inc... R1 330K XTAL R2 10M EXTAL C2 22 pF* VSSI * RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-kHz CRYSTAL. SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT. 32 OSCILLATOR Figure 5-3 Slow Reference Crystal Circuit A 4.194-MHz crystal is typically used for a fast reference, but the frequency may vary between one MHz up to six MHz. Figure 5-4 shows a typical circuit. C1 27 PF* R1 1.5KΩ XTAL R2 1MΩ EXTAL C2 27 PF* VSSI * RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A KDS041-18 4.194 MHz CRYSTAL. SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT. 16 OSCILLATOR 4M Figure 5-4 Fast Reference Crystal Circuit M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-5 Freescale Semiconductor, Inc. If a fast or slow reference frequency is provided to the PLL from a source other than a crystal, or an external system clock signal is applied through the EXTAL pin, the XTAL pin must be left floating. 5.3.2 Clock Synthesizer Operation VDDSYN is used to power the clock circuits when the system clock is synthesized from either a crystal or an externally supplied reference frequency. A separate power source increases MCU noise immunity and can be used to run the clock when the MCU is powered down. A quiet power supply must be used as the VDDSYN source. Adequate external bypass capacitors should be placed as close as possible to the VDDSYN pin to assure a stable operating frequency. When an external system clock signal is applied and the PLL is disabled, VDDSYN should be connected to the VDD supply. Freescale Semiconductor, Inc... A voltage controlled oscillator (VCO) in the PLL generates the system clock signal. To maintain a 50% clock duty cycle, the VCO frequency (fVCO) is either two or four times the system clock frequency, depending on the state of the X bit in SYNCR. The clock signal is fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator. The other phase comparator input is a reference signal, either from the crystal oscillator or from an external source. The comparator generates a control signal proportional to the difference in phase between the two inputs. This signal is low-pass filtered and used to correct the VCO output frequency. Filter circuit implementation can vary, depending upon the external environment and required clock stability. Figure 5-5 shows two recommended system clock filter networks. XFC pin leakage must be kept as low as possible to maintain optimum stability and PLL performance. NOTE The standard filter used in normal operating environments is a single 0.1 µf capacitor, connected from the XFC pin to the VDDSYN supply pin. An alternate filter can be used in high-stability operating environments to reduce PLL jitter under noisy system conditions. Current systems that are operating correctly may not require this filter. If the PLL is not enabled (MODCLK = 0 at reset), the XFC filter is not required. Versions of the SIM that are configured for either slow or fast reference use the same filter component values. An external filter network connected to the XFC pin is not required when an external system clock signal is applied and the PLL is disabled (MODCLK = 0 at reset). The XFC pin must be left floating in this case. SYSTEM INTEGRATION MODULE 5-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. C3 0.1 µF C1 0.1 µF XFC1 VDDSYN C3 0.1 µF C1 0.1 µF R1 18 kΩ XFC1, 2 C4 0.01 µF VSS VSS C4 0.01 µF C2 0.01 µF VDDSYN NORMAL OPERATING ENVIRONMENT HIGH-STABILITY OPERATING ENVIRONMENT 1. MAINTAIN LOW LEAKAGE ON THE XFC NODE. REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION. 2. RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW FREQUENCY NOISE. Freescale Semiconductor, Inc... NORMAL/HIGH-STABILITY XFC CONN Figure 5-5 System Clock Filter Networks The synthesizer locks when the VCO frequency is equal to fref. Lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs. Whenever a comparator input changes, the synthesizer must relock. Lock status is shown by the SLOCK bit in SYNCR. During power-up, the MCU does not come out of reset until the synthesizer locks. Crystal type, characteristic frequency, and layout of external oscillator circuitry affect lock time. When the clock synthesizer is used, SYNCR determines the system clock frequency and certain operating parameters. The W and Y[5:0] bits are located in the PLL feedback path, enabling frequency multiplication by a factor of up to 256. When the W or Y values change, VCO frequency changes, and there is a VCO relock delay. The SYNCR X bit controls a divide-by circuit that is not in the synthesizer feedback loop. When X = 0 (reset state), a divide-by-four circuit is enabled, and the system clock frequency is one-fourth the VCO frequency (fVCO). When X = 1, a divide-by-two circuit is enabled and system clock frequency is one-half the VCO frequency (fVCO). There is no relock delay when clock speed is changed by the X bit. When a slow reference is used, one W bit and six Y bits are located in the PLL feedback path, enabling frequency multiplication by a factor of up to 256. The X bit is located in the VCO clock output path to enable dividing the system clock frequency by two without disturbing the PLL. When using a slow reference, the clock frequency is determined by SYNCR bit settings as follows: f sys = 4f ref ( Y + 1 ) ( 2 ( 2W + X ) ) The reset state of SYNCR ($3F00) results in a power-on fsys of 8.388 MHz when fref is 32.768 kHz. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-7 Freescale Semiconductor, Inc. When a fast reference is used, three W bits are located in the PLL feedback path, enabling frequency multiplication by a factor from one to eight. Three Y bits and the X bit are located in the VCO clock output path to provide the ability to slow the system clock without disturbing the PLL. When using a fast reference, the clock frequency is determined by SYNCR bit settings as follows: f ref ( 2W + X ) f sys = --------- [ 4 ( Y + 1 ) ( 2 )] 128 The reset state of SYNCR ($3F00) results in a power-on fsys of 8.388 MHz when fref is 4.194 MHz. Freescale Semiconductor, Inc... For the device to perform correctly, both the clock frequency and VCO frequency (selected by the W, X, and Y bits) must be within the limits specified for the MCU. In order for the VCO frequency to be within specifications (less than or equal to the maximum system clock frequency multiplied by two), the X bit must be set for system clock frequencies greater than one-half the maximum specified system clock. Internal VCO frequency is determined by the following equations: f VCO = 4f sys if X = 0 or f VCO = 2f sys if X = 1 On both slow and fast reference devices, when an external system clock signal is applied (MODCLK = 0 during reset), the PLL is disabled. The duty cycle of this signal is critical, especially at operating frequencies close to maximum. The relationship between clock signal duty cycle and clock signal period is expressed as follows: Minimum External Clock Period = Minimum External Clock High/Low Time ---------------------------------------------------------------------------------------------------------------------------------------------------------------------50% – Percentage Variation of External Clock Input Duty Cycle Tables 5-2, 5-3, and 5-4 show clock control multipliers for all possible combinations of SYNCR bits. To obtain clock frequency, find the counter modulus in the leftmost column, then multiply the reference frequency by the value in the appropriate prescaler cell. Shaded areas indicate which values exceed the specifications for a device rated at a particular operating frequency. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for maximum allowable clock rate. Tables 5-5, 5-6, and 5-7 show actual clock frequencies for the same combinations of SYNCR bits. To obtain clock frequency, find the counter modulus in the leftmost column, then refer to appropriate prescaler cell. Shaded areas indicate which values exceed the specifications for a device rated at a particular operating frequency. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for maximum system frequency (f ). SYSTEM INTEGRATION MODULE 5-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-2 16.78-MHz Clock Control Multipliers (Shaded cells represent values that exceed 16.78 MHz specifications.) Prescalers Modulus Y 000000 000001 000010 000011 000100 000101 [W:X] = 00 (fVCO = 2 × Value) Slow 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 Fast .03125 .0625 .09375 .125 .15625 .1875 .21875 .25 .21825 .3125 .34375 .375 .40625 .4375 .46875 .5 .53125 .5625 .59375 .625 .65625 .6875 .71875 .75 .78125 .8125 .84375 .875 .90625 .9375 .96875 1 [W:X] = 01 (fVCO = Value) Slow 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 Fast .625 .125 .1875 .25 .3125 .375 .4375 .5 .5625 .625 .6875 .75 .8125 .875 .9375 1 1.0625 1.125 1.1875 1.25 1.3125 1.375 1.4375 1.5 1.5625 1.625 1.6875 1.75 1.8125 1.875 1.9375 2 [W:X] = 10 (fVCO = 2 × Value) Slow 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 512 Fast .125 .25 .375 .5 .625 .75 .875 1 1.125 1.25 1.375 1.5 1.625 1.75 1.875 2 2.125 2.25 2.375 2.5 2.625 2.75 2.875 3 3.125 3.25 3.375 3.5 3.625 3.75 3.875 4 [W:X] = 11 (fVCO = Value) Slow 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 Fast .25 .5 .75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 7.25 7.5 7.75 8 Freescale Semiconductor, Inc... 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-9 Freescale Semiconductor, Inc. Table 5-2 16.78-MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 16.78 MHz specifications.) Prescalers Modulus Y 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 [W:X] = 00 (fVCO = 2 × Value) Slow 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 228 232 236 240 244 248 252 256 Fast 1.03125 1.0625 1.09375 1.125 1.15625 1.1875 1.21875 1.25 1.28125 1.3125 1.34375 1.375 1.40625 1.4375 1.46875 1.5 1.53125 1.5625 1.59375 1.625 1.65625 1.6875 1.71875 1.75 1.78125 1.8125 1.84375 1.875 1.90625 1.9375 1.96875 2 [W:X] = 01 (fVCO = Value) Slow 264 272 280 288 296 304 312 320 328 336 344 352 360 368 376 384 392 400 408 416 424 432 440 448 456 464 472 480 488 496 504 512 Fast 2.0625 2.125 2.1875 2.25 2.3125 2.375 2.4375 2.5 2.5625 2.625 2.6875 2.75 2.8125 2.875 2.9375 3 3.0625 3.125 3.1875 3.25 3.3125 3.375 3.4375 3.5 3.5625 3.625 3.6875 3.75 3.8125 3.875 3.9375 4 [W:X] = 10 (fVCO = 2 × Value) Slow 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1008 1024 Fast 4.125 4.25 4.375 4.5 4.675 4.75 4.875 5 5.125 5.25 5.375 5.5 5.625 5.75 5.875 6 6.125 6.25 6.375 6.5 6.625 6.75 6.875 7 7.125 7.25 7.375 7.5 7.625 7.75 7.875 8 [W:X] = 11 (fVCO = Value) Slow 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016 2048 Fast 8.25 8.5 8.75 9 9.25 9.5 9.75 10 10.25 10.5 10.75 11 11.25 11.5 11.75 12 12.25 12.5 12.75 13 13.25 13.5 13.75 14 14.25 14.5 14.75 15 15.25 15.5 15.75 16 Freescale Semiconductor, Inc... SYSTEM INTEGRATION MODULE 5-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-3 20.97-MHz Clock Control Multipliers (Shaded cells represent values that exceed 20.97 MHz specifications.) Prescalers Modulus Y 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 [W:X] = 00 (fVCO = 2 × Value) Slow 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 Fast .03125 .0625 .09375 .125 .15625 .1875 .21875 .25 .21825 .3125 .34375 .375 .40625 .4375 .46875 .5 .53125 .5625 .59375 .625 .65625 .6875 .71875 .75 .78125 .8125 .84375 .875 .90625 .9375 .96875 1 [W:X] = 01 (fVCO = Value) Slow 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 Fast .625 .125 .1875 .25 .3125 .375 .4375 .5 .5625 .625 .6875 .75 .8125 .875 .9375 1 1.0625 1.125 1.1875 1.25 1.3125 1.375 1.4375 1.5 1.5625 1.625 1.6875 1.75 1.8125 1.875 1.9375 2 [W:X] = 10 (fVCO = 2 × Value) Slow 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 512 Fast .125 .25 .375 .5 .625 .75 .875 1 1.125 1.25 1.375 1.5 1.625 1.75 1.875 2 2.125 2.25 2.375 2.5 2.625 2.75 2.875 3 3.125 3.25 3.375 3.5 3.625 3.75 3.875 4 [W:X] = 11 (fVCO = Value) Slow 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 Fast .25 .5 .75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 7.25 7.5 7.75 8 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-11 Freescale Semiconductor, Inc. Table 5-3 20.97-MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 20.97 MHz specifications.) Prescalers Modulus Y 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 [W:X] = 00 (fVCO = 2 × Value) Slow 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 228 232 236 240 244 248 252 256 Fast 1.03125 1.0625 1.09375 1.125 1.15625 1.1875 1.21875 1.25 1.28125 1.3125 1.34375 1.375 1.40625 1.4375 1.46875 1.5 1.53125 1.5625 1.59375 1.625 1.65625 1.6875 1.71875 1.75 1.78125 1.8125 1.84375 1.875 1.90625 1.9375 1.96875 2 [W:X] = 01 (fVCO = Value) Slow 264 272 280 288 296 304 312 320 328 336 344 352 360 368 376 384 392 400 408 416 424 432 440 448 456 464 472 480 488 496 504 512 Fast 2.0625 2.125 2.1875 2.25 2.3125 2.375 2.4375 2.5 2.5625 2.625 2.6875 2.75 2.8125 2.875 2.9375 3 3.0625 3.125 3.1875 3.25 3.3125 3.375 3.4375 3.5 3.5625 3.625 3.6875 3.75 3.8125 3.875 3.9375 4 [W:X] = 10 (fVCO = 2 × Value) Slow 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1008 1024 Fast 4.125 4.25 4.375 4.5 4.675 4.75 4.875 5 5.125 5.25 5.375 5.5 5.625 5.75 5.875 6 6.125 6.25 6.375 6.5 6.625 6.75 6.875 7 7.125 7.25 7.375 7.5 7.625 7.75 7.875 8 [W:X] = 11 (fVCO = Value) Slow 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016 2048 Fast 8.25 8.5 8.75 9 9.25 9.5 9.75 10 10.25 10.5 10.75 11 11.25 11.5 11.75 12 12.25 12.5 12.75 13 13.25 13.5 13.75 14 14.25 14.5 14.75 15 15.25 15.5 15.75 16 Freescale Semiconductor, Inc... SYSTEM INTEGRATION MODULE 5-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-4 25.17-MHz Clock Control Multipliers (Shaded cells represent values that exceed 25.17 MHz specifications.) Prescalers Modulus Y 000000 000001 000010 000011 000100 000101 [W:X] = 00 (fVCO = 2 × Value) Slow 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 Fast .03125 .0625 .09375 .125 .15625 .1875 .21875 .25 .21825 .3125 .34375 .375 .40625 .4375 .46875 .5 .53125 .5625 .59375 .625 .65625 .6875 .71875 .75 .78125 .8125 .84375 .875 .90625 .9375 .96875 1 [W:X] = 01 (fVCO = Value) Slow 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 Fast .625 .125 .1875 .25 .3125 .375 .4375 .5 .5625 .625 .6875 .75 .8125 .875 .9375 1 1.0625 1.125 1.1875 1.25 1.3125 1.375 1.4375 1.5 1.5625 1.625 1.6875 1.75 1.8125 1.875 1.9375 2 [W:X] = 10 (fVCO = 2 × Value) Slow 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 512 Fast .125 .25 .375 .5 .625 .75 .875 1 1.125 1.25 1.375 1.5 1.625 1.75 1.875 2 2.125 2.25 2.375 2.5 2.625 2.75 2.875 3 3.125 3.25 3.375 3.5 3.625 3.75 3.875 4 [W:X] = 11 (fVCO = Value) Slow 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 Fast .25 .5 .75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 7.25 7.5 7.75 8 Freescale Semiconductor, Inc... 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-13 Freescale Semiconductor, Inc. Table 5-4 25.17-MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 25.17 MHz specifications.) Prescalers Modulus Y 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 [W:X] = 00 (fVCO = 2 × Value) Slow 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 228 232 236 240 244 248 252 256 Fast 1.03125 1.0625 1.09375 1.125 1.15625 1.1875 1.21875 1.25 1.28125 1.3125 1.34375 1.375 1.40625 1.4375 1.46875 1.5 1.53125 1.5625 1.59375 1.625 1.65625 1.6875 1.71875 1.75 1.78125 1.8125 1.84375 1.875 1.90625 1.9375 1.96875 2 [W:X] = 01 (fVCO = Value) Slow 264 272 280 288 296 304 312 320 328 336 344 352 360 368 376 384 392 400 408 416 424 432 440 448 456 464 472 480 488 496 504 512 Fast 2.0625 2.125 2.1875 2.25 2.3125 2.375 2.4375 2.5 2.5625 2.625 2.6875 2.75 2.8125 2.875 2.9375 3 3.0625 3.125 3.1875 3.25 3.3125 3.375 3.4375 3.5 3.5625 3.625 3.6875 3.75 3.8125 3.875 3.9375 4 [W:X] = 10 (fVCO = 2 × Value) Slow 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1008 1024 Fast 4.125 4.25 4.375 4.5 4.675 4.75 4.875 5 5.125 5.25 5.375 5.5 5.625 5.75 5.875 6 6.125 6.25 6.375 6.5 6.625 6.75 6.875 7 7.125 7.25 7.375 7.5 7.625 7.75 7.875 8 [W:X] = 11 (fVCO = Value) Slow 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016 2048 Fast 8.25 8.5 8.75 9 9.25 9.5 9.75 10 10.25 10.5 10.75 11 11.25 11.5 11.75 12 12.25 12.5 12.75 13 13.25 13.5 13.75 14 14.25 14.5 14.75 15 15.25 15.5 15.75 16 Freescale Semiconductor, Inc... SYSTEM INTEGRATION MODULE 5-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-5 16.78-MHz System Clock Frequencies (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus Y 000000 000001 000010 000011 000100 000101 000110 [W:X] = 00 (fVCO = 2 × Value) 131 kHz 262 393 524 655 786 918 1049 1180 1311 1442 1573 1704 1835 1966 2097 2228 2359 2490 2621 2753 2884 3015 3146 3277 3408 3539 3670 3801 3932 4063 4194 Prescaler [W:X] = 01 (fVCO = Value) 262 kHz 524 786 1049 1311 1573 1835 2097 2359 2621 2884 3146 3408 3670 3932 4194 4456 4719 4981 5243 5505 5767 6029 6291 6554 6816 7078 7340 7602 7864 8126 8389 [W:X] = 10 (fVCO = 2 × Value) 524 kHz 1049 1573 2097 2621 3146 3670 4194 4719 5243 5767 6291 6816 7340 7864 8389 8913 9437 9961 10486 11010 11534 12059 12583 13107 13631 14156 14680 15204 15729 16253 16777 [W:X] = 11 (fVCO = Value) 1049 kHz 2097 3146 4194 5243 6291 7340 8389 9437 10486 11534 12583 13631 14680 15729 16777 17826 18874 19923 20972 22020 23069 24117 25166 26214 27263 28312 29360 30409 31457 32506 33554 Freescale Semiconductor, Inc... 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-15 Freescale Semiconductor, Inc. Table 5-5 16.78-MHz System Clock Frequencies (Continued) (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus Y 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 [W:X] = 00 (fVCO = 2 × Value) 4325 kHz 4456 4588 4719 4850 4981 5112 5243 5374 5505 5636 5767 5898 6029 6160 6291 6423 6554 6685 6816 6947 7078 7209 7340 7471 7602 7733 7864 7995 8126 8258 8389 Prescaler [W:X] = 01 (fVCO = Value) 8651 kHz 8913 9175 9437 9699 9961 10224 10486 10748 11010 11272 11534 11796 12059 12321 12583 12845 13107 13369 13631 13894 14156 14418 14680 14942 15204 15466 15729 15991 16253 16515 16777 [W:X] = 10 (fVCO = 2 × Value) 17302 kHz 17826 18350 18874 19399 19923 20447 20972 21496 22020 22544 23069 23593 24117 24642 25166 25690 26214 26739 27263 27787 28312 28836 29360 2988 30409 30933 31457 31982 32506 33030 33554 [W:X] = 11 (fVCO = Value) 34603 kHz 35652 36700 37749 38797 39846 40894 41943 42992 44040 45089 46137 47186 48234 49283 50332 51380 52428 53477 54526 55575 56623 57672 58720 59769 60817 61866 62915 63963 65011 66060 67109 Freescale Semiconductor, Inc... SYSTEM INTEGRATION MODULE 5-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-6 System Clock Frequencies for a 20.97-MHz System (Shaded cells represent values that exceed 20.97 MHz specifications.) Modulus Y 000000 000001 000010 000011 000100 000101 000110 [W:X] = 00 (fVCO = 2 × Value) 131 kHz 262 393 524 655 786 918 1049 1180 1311 1442 1573 1704 1835 1966 2097 2228 2359 2490 2621 2753 2884 3015 3146 3277 3408 3539 3670 3801 3932 4063 4194 Prescaler [W:X] = 01 (fVCO = Value) 262 kHz 524 786 1049 1311 1573 1835 2097 2359 2621 2884 3146 3408 3670 3932 4194 4456 4719 4981 5243 5505 5767 6029 6291 6554 6816 7078 7340 7602 7864 8126 8389 [W:X] = 10 (fVCO = 2 × Value) 524 kHz 1049 1573 2097 2621 3146 3670 4194 4719 5243 5767 6291 6816 7340 7864 8389 8913 9437 9961 10486 11010 11534 12059 12583 13107 13631 14156 14680 15204 15729 16253 16777 [W:X] = 11 (fVCO = Value) 1049 kHz 2097 3146 4194 5243 6291 7340 8389 9437 10486 11534 12583 13631 14680 15729 16777 17826 18874 19923 20972 22020 23069 24117 25166 26214 27263 28312 29360 30409 31457 32506 33554 Freescale Semiconductor, Inc... 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-17 Freescale Semiconductor, Inc. Table 5-6 System Clock Frequencies for a 20.97-MHz System (Continued) (Shaded cells represent values that exceed 20.97 MHz specifications.) Modulus Y 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 [W:X] = 00 (fVCO = 2 × Value) 4325 kHz 4456 4588 4719 4850 4981 5112 5243 5374 5505 5636 5767 5898 6029 6160 6291 6423 6554 6685 6816 6947 7078 7209 7340 7471 7602 7733 7864 7995 8126 8258 8389 Prescaler [W:X] = 01 (fVCO = Value) 8651 kHz 8913 9175 9437 9699 9961 10224 10486 10748 11010 11272 11534 11796 12059 12321 12583 12845 13107 13369 13631 13894 14156 14418 14680 14942 15204 15466 15729 15991 16253 16515 16777 [W:X] = 10 (fVCO = 2 × Value) 17302 kHz 17826 18350 18874 19399 19923 20447 20972 21496 22020 22544 23069 23593 24117 24642 25166 25690 26214 26739 27263 27787 28312 28836 29360 2988 30409 30933 31457 31982 32506 33030 33554 [W:X] = 11 (fVCO = Value) 34603 kHz 35652 36700 37749 38797 39846 40894 41943 42992 44040 45089 46137 47186 48234 49283 50332 51380 52428 53477 54526 55575 56623 57672 58720 59769 60817 61866 62915 63963 65011 66060 67109 Freescale Semiconductor, Inc... SYSTEM INTEGRATION MODULE 5-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-7 System Clock Frequencies for a 25.17-MHz System (Shaded cells represent values that exceed 25.17 MHz specifications.) Modulus Y 000000 000001 000010 000011 000100 000101 000110 [W:X] = 00 (fVCO = 2 × Value) 131 kHz 262 393 524 655 786 918 1049 1180 1311 1442 1573 1704 1835 1966 2097 2228 2359 2490 2621 2753 2884 3015 3146 3277 3408 3539 3670 3801 3932 4063 4194 Prescaler [W:X] = 01 (fVCO = Value) 262 kHz 524 786 1049 1311 1573 1835 2097 2359 2621 2884 3146 3408 3670 3932 4194 4456 4719 4981 5243 5505 5767 6029 6291 6554 6816 7078 7340 7602 7864 8126 8389 [W:X] = 10 (fVCO = 2 × Value) 524 kHz 1049 1573 2097 2621 3146 3670 4194 4719 5243 5767 6291 6816 7340 7864 8389 8913 9437 9961 10486 11010 11534 12059 12583 13107 13631 14156 14680 15204 15729 16253 16777 [W:X] = 11 (fVCO = Value) 1049 kHz 2097 3146 4194 5243 6291 7340 8389 9437 10486 11534 12583 13631 14680 15729 16777 17826 18874 19923 20972 22020 23069 24117 25166 26214 27263 28312 29360 30409 31457 32506 33554 Freescale Semiconductor, Inc... 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-19 Freescale Semiconductor, Inc. Table 5-7 System Clock Frequencies for a 25.17-MHz System (Continued) (Shaded cells represent values that exceed 25.17 MHz specifications.) Modulus Y 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 [W:X] = 00 (fVCO = 2 × Value) 4325 kHz 4456 4588 4719 4850 4981 5112 5243 5374 5505 5636 5767 5898 6029 6160 6291 6423 6554 6685 6816 6947 7078 7209 7340 7471 7602 7733 7864 7995 8126 8258 8389 Prescaler [W:X] = 01 (fVCO = Value) 8651 kHz 8913 9175 9437 9699 9961 10224 10486 10748 11010 11272 11534 11796 12059 12321 12583 12845 13107 13369 13631 13894 14156 14418 14680 14942 15204 15466 15729 15991 16253 16515 16777 [W:X] = 10 (fVCO = 2 × Value) 17302 kHz 17826 18350 18874 19399 19923 20447 20972 21496 22020 22544 23069 23593 24117 24642 25166 25690 26214 26739 27263 27787 28312 28836 29360 2988 30409 30933 31457 31982 32506 33030 33554 [W:X] = 11 (fVCO = Value) 34603 kHz 35652 36700 37749 38797 39846 40894 41943 42992 44040 45089 46137 47186 48234 49283 50332 51380 52428 53477 54526 55575 56623 57672 58720 59769 60817 61866 62915 63963 65011 66060 67109 Freescale Semiconductor, Inc... SYSTEM INTEGRATION MODULE 5-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 5.3.3 External Bus Clock The state of the E-clock division bit (EDIV) in SYNCR determines clock rate for the Eclock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripherals. ECLK frequency can be set to system clock frequency divided by eight or system clock frequency divided by sixteen. The clock is enabled by the CS10PA[1:0] field in chip-select pin assignment register 1 (CSPAR1). ECLK operation during low-power stop is described in the following paragraph. Refer to 5.9 Chip-Selects for more information about the external bus clock. 5.3.4 Low-Power Operation Low-power operation is initiated by the CPU16. To reduce power consumption selectively, the CPU can set the STOP bits in each module configuration register. To minimize overall microcontroller power consumption, the CPU can execute the LPSTOP instruction which causes the SIM to turn off the system clock. When individual module STOP bits are set, clock signals inside each module are turned off, but module registers are still accessible. When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the current interrupt mask into the clock control logic. The SIM brings the MCU out of low-power stop mode when one of the following exceptions occur: • RESET • Trace • SIM interrupt of higher priority than the stored interrupt mask Refer to 5.6.4.2 LPSTOP Broadcast Cycle for more information. During a low-power stop mode, unless the system clock signal is supplied by an external source and that source is removed, the SIM clock control logic and the SIM clock signal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK. The SIM can also continue to generate the CLKOUT signal while in low-power stop mode. During low-power stop mode, the address bus continues to drive the LPSTOP instruction, and bus control signals are negated. I/O pins configured as outputs continue to hold their previous state; I/O pins configured as inputs will be in a high-impedance state. STSIM and STEXT bits in SYNCR determine clock operation during low-power stop mode. The flowchart shown in Figure 5-6 summarizes the effects of the STSIM and STEXT bits when MC68HC16Z1, MC68CK16Z1, MC68CM16Z1, MC68HC16Z2, and MC68HC16Z3 MCUs enter normal low-power stop mode. Any clock in the off state is held low. If the synthesizer VCO is turned off during low-power stop mode, there is a PLL relock delay after the VCO is turned back on. Figure 5-7 summarizes the effects of the STSIM and STEXT bits when MC68HC16Z4 and MC68CK16Z4 MCUs enter normal low-power stop mode. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-21 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. NOTE The internal oscillator which supplies the input frequency for the PLL always runs when a crystal is used. SET UP INTERRUPT TO WAKE UP MCU FROM LPSTOP USING EXTERNAL CLOCK? YES NO Freescale Semiconductor, Inc... USE SYSTEM CLOCK AS SIMCLK IN LPSTOP? YES SET STSIM = 1 fsimclk1 = fsys IN LPSTOP NO SET STSIM = 0 fsimclk1 = fref IN LPSTOP WANT CLKOUT ON IN LPSTOP? YES NO WANT CLKOUT ON IN LPSTOP? YES NO SET STEXT = 1 fclkout2 = fsys feclk = ÷ fsys IN LPSTOP SET STEXT = 0 fclkout2 = 0 Hz feclk = 0 Hz IN LPSTOP SET STEXT = 1 fclkout2 = fref feclk = 0 Hz IN LPSTOP SET STEXT = 0 fclkout2 = 0 Hz feclk = 0 Hz IN LPSTOP ENTER LPSTOP NOTES: 1. THE SIMCLK IS USED BY THE PIT, IRQ, AND INPUT BLOCKS OF THE SIM. 2. CLKOUT CONTROL DURING LPSTOP IS OVERRIDDEN BY THE EXOFF BIT IN SIMCR. IF EXOFF = 1, THE CLKOUT PIN IS ALWAYS IN A HIGH-IMPEDANCE STATE AND STEXT HAS NO EFFECT IN LPSTOP. IF EXOFF = 0, CLKOUT IS CONTROLLED BY STEXT IN LPSTOP. SIM LPSTOPFLOW Figure 5-6 SIM LPSTOP Flowchart SYSTEM INTEGRATION MODULE 5-22 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SET UP INTERRUPT TO WAKE UP MCU FROM LPSTOP LEAVE IMBCLK1 ON IN LPSTOP? YES SET STOP BITS FOR MODULES THAT WILL NOT BE ACTIVE IN LPSTOP NO Freescale Semiconductor, Inc... SET STCPU2 = 1 fimbclk = fsys IN LPSTOP SET STCPU2 = 0 fimbclk = 0 Hz IN LPSTOP USING EXTERNAL CLOCK? YES NO USE SYSTEM CLOCK AS SIMCLK IN LPSTOP? YES SET STSIM = 1 fsimclk3 = fsys IN LPSTOP NO SET STSIM = 0 fsimclk3 = fref IN LPSTOP WANT CLKOUT ON IN LPSTOP? YES NO WANT CLKOUT ON IN LPSTOP? YES NO SET STEXT = 1 fclkout4 = fsys feclk = ÷ fsys IN LPSTOP SET STEXT = 0 fclkout4 = 0 Hz feclk = ÷ 0 Hz IN LPSTOP SET STEXT = 1 fclkout4 = fref feclk = ÷ 0 Hz IN LPSTOP SET STEXT = 0 fclkout4 = 0 Hz feclk = ÷ 0 Hz IN LPSTOP ENTER LPSTOP NOTES: 1. IMBCLK IS THE CLOCK USED BY THE CPU16L, SIML, ADC, MCCI, AND THE GPT. 2. WHEN STCPU = 1, THE CPU16L IS SHUT DOWN IN LPSTOP. ALL OTHER MODULES WILL REMAIN ACTIVE UNLESS THE STOP BITS IN THEIR MODULE CONFIGURATION REGISTERS ARE SET PRIOR TO ENTERING LPSTOP. 3. THE SIMCLK IS USED BY THE PIT, IRQ, AND INPUT BLOCKS OF THE SIML. 4. CLKOUT CONTROL DURING LPSTOP IS OVERRIDDEN BY THE EXOFF BIT IN SIMCR. IF EXOFF = 1, THE CLKOUT PIN IS ALWAYS IN A HIGH-IMPEDANCE STATE AND STEXT HAS NO EFFECT IN LPSTOP. IF EXOFF = 0, CLKOUT IS CONTROLLED BY STEXT IN LPSTOP. WHEN STCPU = 1, THE CPU16L IS DISABLED IN LPSTOP, BUT ALL OTHER MODULES REMAIN ACTIVE OR STOPPED ACCORDING TO THE SETTING. SIML LPSTOP FLOWCHART Figure 5-7 SIML LPSTOP Flowchart M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-23 Freescale Semiconductor, Inc. 5.4 System Protection The system protection block preserves reset status, monitors internal activity, and provides periodic interrupt generation. Figure 5-8 is a block diagram of the submodule. MODULE CONFIGURATION AND TEST RESET STATUS Freescale Semiconductor, Inc... HALT MONITOR RESET REQUEST BUS MONITOR BERR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG TIMER 29 PRESCALER PERIODIC INTERRUPT TIMER RESET REQUEST CLOCK IRQ[7:1] SYS PROTECT BLOCK Figure 5-8 System Protection 5.4.1 Reset Status The reset status register (RSR) latches internal MCU status during reset. Refer to 5.7.10 Reset Status Register for more information. 5.4.2 Bus Monitor The internal bus monitor checks data size acknowledge (DSACK) or autovector (AVEC) signal response times during normal bus cycles. The monitor asserts the internal bus error (BERR) signal when the response time is excessively long. DSACK and AVEC response times are measured in clock cycles. Maximum allowable response time can be selected by setting the bus monitor timing (BMT[1:0]) field in the system protection control register (SYPCR). Table 5-8 shows the periods allowed. SYSTEM INTEGRATION MODULE 5-24 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-8 Bus Monitor Period BMT[1:0] 00 01 10 11 Bus Monitor Time-Out Period 64 system clocks 32 system clocks 16 system clocks 8 system clocks The monitor does not check DSACK response on the external bus unless the CPU16 initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. If a system contains external bus masters, an external bus monitor must be implemented and the internal-to-external bus monitor option must be disabled. Freescale Semiconductor, Inc... When monitoring transfers to an 8-bit port, the bus monitor does not reset until both byte accesses of a word transfer are completed. Monitor time-out period must be at least twice the number of clocks that a single byte access requires. 5.4.3 Halt Monitor The halt monitor responds to an assertion of the HALT signal on the internal bus, caused by a double bus fault. A flag in the reset status register (RSR) can indicate that the last reset was caused by the halt monitor. Halt monitor reset can be inhibited by the halt monitor enable (HME) bit in SYPCR. Refer to 5.6.5.2 Double Bus Faults for more information. 5.4.4 Spurious Interrupt Monitor During interrupt exception processing, the CPU16 normally acknowledges an interrupt request, arbitrates among various sources of interrupt, recognizes the highest priority source, and then acquires a vector or responds to a request for autovectoring. The spurious interrupt monitor asserts the internal bus error signal (BERR) if no interrupt arbitration occurs during interrupt exception processing. The assertion of BERR causes the CPU16 to load the spurious interrupt exception vector into the program counter. The spurious interrupt monitor cannot be disabled. Refer to 5.8 Interrupts for further information. For detailed information about interrupt exception processing, refer to 4.13 Exceptions. 5.4.5 Software Watchdog The software watchdog is controlled by the software watchdog enable (SWE) bit in SYPCR. When enabled, the watchdog requires that a service sequence be written to the software watchdog service register (SWSR) on a periodic basis. If servicing does not take place, the watchdog times out and asserts the RESET signal. Each time the service sequence is written, the software watchdog timer restarts. The sequence to restart the software watchdog consists of the following steps: • Write $55 to SWSR. • Write $AA to SWSR. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-25 Freescale Semiconductor, Inc. Both writes must occur before time-out in the order listed. Any number of instructions can be executed between the two writes. Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the software watchdog timing (SWT[1:0]) field in SYPCR. SWP determines system clock prescaling for the watchdog timer and determines that one of two options, either no prescaling or prescaling by a factor of 512, can be selected. The value of SWP is affected by the state of the MODCLK pin during reset, as shown in Table 5-9. System software can change SWP value. Table 5-9 MODCLK Pin and SWP Bit During Reset MODCLK SWP 1 (÷ 512) 0 (÷ 1) Freescale Semiconductor, Inc... 0 (External Clock) 1 (Internal Clock) SWT[1:0] selects the divide ratio used to establish the software watchdog time-out period. The following equation calculates the time-out period for a slow reference frequency, where fref is equal to the EXTAL crystal frequency. Divide Ratio Specified by SWP and SWT[1:0] Time-Out Period = ----------------------------------------------------------------------------------------------------------------------f ref The following equation calculates the time-out period for a fast reference frequency, where fref is equal to the EXTAL crystal frequency. ( 128 ) ( Divide Ratio Specified by SWP and SWT[1:0] ) Time-Out Period = -----------------------------------------------------------------------------------------------------------------------------------------f ref The following equation calculates the time-out period for an externally input clock frequency on both slow and fast reference frequency devices, when fsys is equal to the system clock frequency. Divide Ratio Specified by SWP and SWT[1:0] Time-Out Period = ----------------------------------------------------------------------------------------------------------------------f sys Table 5-10 shows the divide ratio for each combination of SWP and SWT[1:0] bits. When SWT[1:0] are modified, a watchdog service sequence must be performed before the new time-out period can take effect. SYSTEM INTEGRATION MODULE 5-26 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-10 Software Watchdog Divide Ratio SWP 0 0 0 0 1 1 1 1 SWT[1:0] 00 01 10 11 00 01 10 11 Divide Ratio 29 211 213 215 218 220 222 224 Freescale Semiconductor, Inc... Figure 5-9 is a block diagram of the watchdog timer and the clock control for the periodic interrupt timer. EXTAL XTAL FREEZE MODCLK CRYSTAL OSCILLATOR 1281 CLOCK SELECT AND DISABLE 29 PRESCALER SWP CLOCK SELECT PTP 4 SOFTWARE WATCHDOG RESET LPSTOP SWE SWT1 SWT0 SOFTWARE WATCHDOG TIMER (215 DIVIDER CHAIN — 4 TAPS) SWSR PERIODIC INTERRUPT TIMER (8-BIT MODULUS COUNTER) PICR PITR PIT INTERRUPT NOTES: 1. ÷ 128 IS PRESENT ONLY ON DEVICES WITH A FAST REFERENCE OSCILLATOR. PIT WATCHDOG BLOCK 16 Figure 5-9 Periodic Interrupt Timer and Software Watchdog Timer 5.4.6 Periodic Interrupt Timer The periodic interrupt timer (PIT) allows the generation of interrupts of specific priority at predetermined intervals. This capability is often used to schedule control system tasks that must be performed within time constraints. The timer consists of a prescaler, a modulus counter, and registers that determine interrupt timing, priority and vector assignment. Refer to 4.13 Exceptions for further information about interrupt exception processing. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-27 Freescale Semiconductor, Inc. The periodic interrupt timer modulus counter is clocked by one of two signals. When the PLL is enabled (MODCLK = 1 during reset), fref is used with a slow reference oscillator; fref 128 is used with fast reference oscillator. When the PLL is disabled (MODCLK = 0 during reset), fref is used. The value of the periodic timer prescaler (PTP) bit in the periodic interrupt timer register (PITR) determines system clock prescaling for the periodic interrupt timer. One of two options, either no prescaling, or prescaling by a factor of 512, can be selected. The value of PTP is affected by the state of the MODCLK pin during reset, as shown in Table 5-11. System software can change PTP value. Table 5-11 MODCLK Pin and PTP Bit at Reset MODCLK 0 (External Clock) 1 (Internal Clock) PTP 1 (÷ 512) 0 (÷ 1) Freescale Semiconductor, Inc... Either clock signal selected by the PTP is divided by four before driving the modulus counter. The modulus counter is initialized by writing a value to the periodic interrupt timer modulus (PITM[7:0]) field in PITR. A zero value turns off the periodic timer. When the modulus counter value reaches zero, an interrupt is generated. The modulus counter is then reloaded with the value in PITM[7:0] and counting repeats. If a new value is written to PITR, it is loaded into the modulus counter when the current count is completed. The following equation calculates the PIT period when a slow reference frequency is used: ( PITM[7:0] ) ( 1 if PTP = 0, 512 if PTP = 1 ) ( 4 ) PIT Period = -------------------------------------------------------------------------------------------------------------------f ref The following equation calculates the PIT period when a fast reference frequency is used: ( 128 ) ( PITM[7:0] ) ( 1 if PTP = 0, 512 if PTP = 1 ) ( 4 ) PIT Period = ----------------------------------------------------------------------------------------------------------------------------------f ref The following equation calculates the PIT period for an externally input clock frequency on both slow and fast reference frequency devices. ( PITM[7:0] ) ( 1 if PTP = 0, 512 if PTP = 1 ) ( 4 ) PIT Period = -------------------------------------------------------------------------------------------------------------------f sys 5.4.7 Interrupt Priority and Vectoring Interrupt priority and vectoring are determined by the values of the periodic interrupt request level (PIRQL[2:0]) and periodic interrupt vector (PIV) fields in the periodic interrupt control register (PICR). SYSTEM INTEGRATION MODULE 5-28 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. The PIRQL field is compared to the CPU16 interrupt priority mask to determine whether the interrupt is recognized. Table 5-12 shows PIRQL[2:0] priority values. Because of SIM hardware prioritization, a PIT interrupt is serviced before an external interrupt request of the same priority. The periodic timer continues to run when the interrupt is disabled. Table 5-12 Periodic Interrupt Priority PIRQL[2:0] 000 001 010 011 100 101 110 111 Priority Level Periodic Interrupt Disabled Interrupt priority level 1 Interrupt priority level 2 Interrupt priority level 3 Interrupt priority level 4 Interrupt priority level 5 Interrupt priority level 6 Interrupt priority level 7 Freescale Semiconductor, Inc... The PIV field contains the periodic interrupt vector. The vector is placed on the IMB when an interrupt request is made. The vector number is used to calculate the address of the appropriate exception vector in the exception vector table. The reset value of the PIV field is $0F, which corresponds to the uninitialized interrupt exception vector. 5.4.8 Low-Power STOP Operation When the CPU16 executes the LPSTOP instruction, the current interrupt priority mask is stored in the clock control logic, internal clocks are disabled according to the state of the STSIM bit in the SYNCR, and the MCU enters low-power stop mode. The bus monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power stop. During low-power stop mode, the clock input to the software watchdog timer is disabled and the timer stops. The software watchdog begins to run again on the first rising clock edge after low-power stop mode ends. The watchdog is not reset by low-power stop mode. A service sequence must be performed to reset the timer. The periodic interrupt timer does not respond to the LPSTOP instruction, but continues to run during LPSTOP. To stop the periodic interrupt timer, PITR must be loaded with a zero value before the LPSTOP instruction is executed. A PIT interrupt, or an external interrupt request, can bring the MCU out of the low-power stop mode if it has a higher priority than the interrupt mask value stored in the clock control logic when low-power stop mode is initiated. LPSTOP can be terminated by a reset. 5.5 External Bus Interface The external bus interface (EBI) transfers information between the internal MCU bus and external devices. Figure 5-10 shows a basic system with external memory and peripherals. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-29 Freescale Semiconductor, Inc. VDD VDD VDD VDD VDD VDD 10 kΩ DSACK1 DSACK0 R/W CS3 CS4 IRQ7 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ DTACK R/W CS IACK IRQ ADDR[3:0] RS[4:1] DATA[15:8] D[7:0] VDD ADDR[17:0] DATA[15:0] Freescale Semiconductor, Inc... 10 kΩ CSBOOT1 CE OE WE ADDR[17:1] A[16:0] DATA[15:0] VDD VDD DQ[15:0] M68HC16 Z-SERIES MCU 10 kΩ CS01 CS11 10 kΩ E W ADDR[15:1] A[14:0] DATA[15:8] DQ[7:0] VDD 10 kΩ CS21 ADDR[15:1] E W A[14:0] DATA[7:0] DQ[7:0] MCM6206D MCM6206D G G NOTES: 1. ALL CHIP-SELECT LINES IN THIS EXAMPLE MUST BE CONFIGURED AS 16-BIT. HC16 SIM/SCIM BUS Figure 5-10 MCU Basic System SYSTEM INTEGRATION MODULE 5-30 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL (SRAM 32K X 8) (SRAM 32K X 8) (FLASH 64K X 16) (ASYNC BUS PERIPHERAL) MC68HC681 Freescale Semiconductor, Inc. The external bus has 24 address lines and 16 data lines. ADDR[19:0] are normal address outputs; ADDR[23:20] follow the output state of ADDR19. The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and longword transfers. Port width is the maximum number of bits accepted or provided by the external memory system during a bus transfer. Widths of eight and sixteen bits are accessed through the use of asynchronous cycles controlled by the size (SIZ1 and SIZ0) and data size acknowledge (DSACK1 and DSACK0) pins. Multiple bus cycles may be required for dynamically sized transfers. To add flexibility and minimize the necessity for external logic, MCU chip-select logic is synchronized with EBI transfers. Refer to 5.9 Chip-Selects for more information. 5.5.1 Bus Control Signals The address bus provides addressing information to external devices. The data bus transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data. Control signals indicate the beginning of each bus cycle, the address space, the size of the transfer, and the type of cycle. External devices decode these signals and respond to transfer data and terminate the bus cycle. The EBI can operate in an asynchronous mode for any port width. 5.5.1.1 Address Bus Bus signals ADDR[19:0] define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. 5.5.1.2 Address Strobe Address strobe (AS) is a timing signal that indicates the validity of an address on the address bus and of many control signals. 5.5.1.3 Data Bus Signals DATA[15:0] form a bidirectional, non-multiplexed parallel bus that transfers data to or from the MCU. A read or write operation can transfer eight or sixteen bits of data in one bus cycle. For a write cycle, all sixteen bits of the data bus are driven, regardless of the port width or operand size. 5.5.1.4 Data Strobe Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle, DS signals an external device that data on the bus is valid. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-31 Freescale Semiconductor, Inc. 5.5.1.5 Read/Write Signal The read/write signal (R/W) determines the direction of the transfer during a bus cycle. This signal changes state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for two consecutive write cycles. 5.5.1.6 Size Signals Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during an operand cycle. They are valid while AS is asserted. Table 5-13 shows SIZ0 and SIZ1 encoding. Table 5-13 Size Signal Encoding Freescale Semiconductor, Inc... SIZ1 0 1 1 0 SIZ0 1 0 1 0 Transfer Size Byte Word 3 Byte Long Word 5.5.1.7 Function Codes The CPU generates function code signals (FC[2:0]) to indicate the type of activity occurring on the data or address bus. These signals can be considered address extensions that can be externally decoded to determine which of eight external address spaces is accessed during a bus cycle. Because the CPU16 always operates in supervisor mode (FC2 = 1), address spaces 0 to 3 are not used. Address space 7 is designated CPU space. CPU space is used for control information not normally associated with read or write bus cycles. Function codes are valid while AS is asserted. Table 5-14 shows address space encoding. Table 5-14 Address Space Encoding FC2 1 1 1 1 FC1 0 0 1 1 FC0 0 1 0 1 Address Space Reserved Data space Program space CPU space 5.5.1.8 Data Size Acknowledge Signals During normal bus transfers, external devices assert the data size acknowledge signals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these signals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the signals indicate that an external device has successfully stored data and that the cycle can terminate. DSACK[1:0] can also be supplied internally by chip-select logic. Refer to 5.9 Chip-Selects for more information. SYSTEM INTEGRATION MODULE 5-32 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 5.5.1.9 Bus Error Signal The bus error signal (BERR) is asserted when a bus cycle is not properly terminated by DSACK or AVEC assertion. It can also be asserted in conjunction with DSACK to indicate a bus error condition, provided it meets the appropriate timing requirements. Refer to 5.6.5 Bus Exception Control Cycles for more information. The internal bus monitor can generate the BERR signal for internal-to-internal and internal-to-external transfers. In systems with an external bus master, the SIM bus monitor must be disabled and external logic must be provided to drive the BERR pin, because the internal BERR monitor has no information about transfers initiated by an external bus master. Refer to 5.6.6 External Bus Arbitration for more information. 5.5.1.10 Halt Signal The halt signal (HALT) can be asserted by an external device for debugging purposes to cause single bus cycle operation or (in combination with BERR) a retry of a bus cycle in error. The HALT signal affects external bus cycles only. As a result, a program not requiring use of the external bus may continue executing, unaffected by the HALT signal. When the MCU completes a bus cycle with the HALT signal asserted, DATA[15:0] is placed in a high-impedance state and bus control signals are driven inactive; the address, function code, size, and read/write signals remain in the same state. If HALT is still asserted once bus mastership is returned to the MCU, the address, function code, size, and read/write signals are again driven to their previous states. The MCU does not service interrupt requests while it is halted. Refer to 5.6.5 Bus Exception Control Cycles for further information. 5.5.1.11 Autovector Signal The autovector signal (AVEC) can be used to terminate external interrupt acknowledgment cycles. Assertion of AVEC causes the CPU16 to generate vector numbers to locate an interrupt handler routine. If AVEC is continuously asserted, autovectors are generated for all external interrupt requests. AVEC is ignored during all other bus cycles. Refer to 5.8 Interrupts for more information. AVEC for external interrupt requests can also be supplied internally by chip-select logic. Refer to 5.9 Chip-Selects for more information. The autovector function is disabled when there is an external bus master. Refer to 5.6.6 External Bus Arbitration for more information. 5.5.2 Dynamic Bus Sizing The MCU dynamically interprets the port size of an addressed device during each bus cycle, allowing operand transfers to or from 8-bit and 16-bit ports. During a bus transfer cycle, an external device signals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK inputs, as shown in Table 5-15. Chip-select logic can generate data size acknowledge signals for an external device. Refer to 5.9 Chip-Selects for more information. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-33 Freescale Semiconductor, Inc. Table 5-15 Effect of DSACK Signals DSACK1 1 1 0 0 DSACK0 1 0 1 0 Result Insert wait states in current bus cycle Complete cycle — Data bus port size is eight bits Complete cycle — Data bus port size is sixteen bits Reserved Freescale Semiconductor, Inc... If the CPU is executing an instruction that reads a long-word operand from a 16-bit port, the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the DSACK signals to indicate the port width. For instance, a 16-bit external device always returns DSACK for a 16-bit port (regardless of whether the bus cycle is a byte or word operation). Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0], and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the MCU transfers valid data. The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word operation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are designated as shown in Figure 5-11. OP[0:3] represent the order of access. For instance, OP0 is the most significant byte of a long-word operand, and is accessed first, while OP3, the least significant byte, is accessed last. The two bytes of a word-length operand are OP0 (most significant) and OP1. The single byte of a byte-length operand is OP0. OPERAND 31 LONG WORD THREE BYTE WORD BYTE OP0 24 23 OP1 OP0 BYTE ORDER 16 15 OP2 OP1 OP0 87 OP3 OP2 OP1 OP0 OPERAND BYTE ORDER 0 Figure 5-11 Operand Byte Order SYSTEM INTEGRATION MODULE 5-34 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 5.5.3 Operand Alignment The EBI data multiplexer establishes the necessary connections for different combinations of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during the current bus cycle. The number of bytes transferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width. ADDR0 also affects the operation of the data multiplexer. During a bus transfer, ADDR[23:1] indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the byte offset from the base. NOTE ADDR[23:20] follow the state of ADDR19 in the MCU. 5.5.4 Misaligned Operands The CPU16 uses a basic operand size of 16 bits. An operand is misaligned when it overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even address), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address. The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU transfers a long-word operand through a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word is transferred on a following bus cycle. The CPU16 can perform misaligned word transfers. This capability makes it compatible with the M68HC11 CPU. The CPU16 treats misaligned long-word transfers as two misaligned word transfers. 5.5.5 Operand Transfer Cases Table 5-16 shows how operands are aligned for various types of transfers. OPn entries are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-35 Freescale Semiconductor, Inc. Table 5-16 Operand Alignment Current Cycle 1 2 3 4 5 6 7 Transfer Case Byte to 8-bit port (even) Byte to 8-bit port (odd) Byte to 16-bit port (even) Byte to 16-bit port (odd) Word to 8-bit port (aligned) Word to 8-bit port (misaligned) Word to 16-bit port (aligned) Word to 16-bit port (misaligned) Long word to 8-bit port (aligned) Long word to 8-bit port (misaligned)2 Long word to 16-bit port (aligned) Long word to 16-bit port (misaligned)2 Three byte to 8-bit port3 SIZ1 0 0 0 0 1 1 1 1 0 1 0 1 1 SIZ0 1 1 1 1 0 0 0 0 0 0 0 0 1 ADDR0 0 1 0 1 0 1 0 1 0 1 0 1 1 DSACK1 DSACK0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 DATA [15:8] OP0 OP0 OP0 (OP0) OP0 OP0 OP0 (OP0) OP0 OP0 OP0 (OP0) OP0 DATA [7:0] (OP0)1 (OP0) (OP0) OP0 (OP1) (OP0) OP1 OP0 (OP1) (OP0) OP1 OP0 (OP0) Next Cycle — — — — 2 1 — 3 13 1 7 3 5 Freescale Semiconductor, Inc... 8 9 10 11 12 13 NOTES: 1. Operands in parentheses are ignored by the CPU16 during read cycles. 2. The CPU16 treats misaligned long-word transfers as two misaligned-word transfers. 3. Three byte transfer cases occur only as a result of an aligned long word to 8-bit port transfer. 5.6 Bus Operation Internal microcontroller modules are typically accessed in two system clock cycles. Regular external bus cycles use handshaking between the MCU and external peripherals to manage transfer size and data. These accesses take three system clock cycles, with no wait states. During regular cycles, wait states can be inserted as needed by bus control logic. Refer to 5.6.2 Regular Bus Cycle for more information. Fast-termination cycles, which are two-cycle external accesses with no wait states, use chip-select logic to generate handshaking signals internally. Refer to 5.6.3 Fast Termination Cycles and 5.9 Chip-Selects for more information. Bus control signal timing, as well as chip-select signal timing, are specified in APPENDIX A ELECTRICAL CHARACTERISTICS. Refer to the SIM Reference Manual (SIMRM/AD) for more information about each type of bus cycle. 5.6.1 Synchronization to CLKOUT External devices connected to the MCU bus can operate at a clock frequency different from the frequencies of the MCU as long as the external devices satisfy the interface signal timing constraints. Although bus cycles are classified as asynchronous, they are interpreted relative to the MCU system clock output (CLKOUT). SYSTEM INTEGRATION MODULE 5-36 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Descriptions are made in terms of individual system clock states, labelled {S0, S1, S2,..., SN}. The designation “state” refers to the logic level of the clock signal, and does not correspond to any implemented machine state. A clock cycle consists of two successive states. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information on clock control timing. Bus cycles terminated by DSACK assertion normally require a minimum of three CLKOUT cycles. To support systems that use CLKOUT to generate DSACK and other inputs, asynchronous input setup time and asynchronous input hold times are specified. When these specifications are met, the MCU is guaranteed to recognize the appropriate signal on a specific edge of the CLKOUT signal. 5.6.2 Regular Bus Cycle The following paragraphs contain a discussion of cycles that use external bus control logic. Refer to 5.6.3 Fast Termination Cycles for information about fast termination cycles. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. The SIZ signals and ADDR0 are externally decoded to select the active portion of the data bus. Refer to 5.5.2 Dynamic Bus Sizing. When AS, DS, and R/W are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle), then asserts a DSACK[1:0] combination that indicates port size. The DSACK[1:0] signals can be asserted before the data from a peripheral device is valid on a read cycle. To ensure valid data is latched into the MCU, a maximum period between DSACK assertion and DS assertion is specified. There is no specified maximum for the period between the assertion of AS and DSACK. Although the MCU can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK, the MCU inserts wait cycles in clock period increments until either DSACK signal goes low. If bus termination signals remain unasserted, the MCU will continue to insert wait states, and the bus cycle will never end. If no peripheral responds to an access, or if an access is invalid, external logic should assert the BERR or HALT signals to abort the bus cycle (when BERR and HALT are asserted simultaneously, the CPU16 acts as though only BERR is asserted). When enabled, the SIM bus monitor asserts BERR when DSACK response time exceeds a predetermined limit. The bus monitor time-out period is determined by the BMT[1:0] field in SYPCR. The maximum bus monitor timeout period is 64 system clock cycles. 5.6.2.1 Read Cycle During a read cycle, the MCU transfers data from an external memory or peripheral device. If the instruction specifies a long-word or word operation, the MCU attempts to read two bytes at once. For a byte operation, the MCU reads one byte. The portion of the data bus from which each byte is read depends on operand size, peripheral address, and peripheral port size. Figure 5-12 is a flowchart of a word read cycle. Refer to 5.5.2 Dynamic Bus Sizing, 5.5.4 Misaligned Operands, and the SIM Reference Manual (SIMRM/AD) for more information. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-37 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MCU ADDRESS DEVICE (S0) 1) SET R/W TO READ 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE PERIPHERAL ASSERT AS AND DS (S1) PRESENT DATA (S2) 1) DECODE ADDR, R/W, SIZ[1:0], DS 2) PLACE DATA ON DATA[15:0] OR DATA[15:8] IF 8-BIT DATA 3) DRIVE DSACK SIGNALS DECODE DSACK (S3) Freescale Semiconductor, Inc... LATCH DATA (S4) NEGATE AS AND DS (S5) TERMINATE CYCLE (S5) 1) REMOVE DATA FROM DATA BUS 2) NEGATE DSACK RD CYC FLOW START NEXT CYCLE (S0) Figure 5-12 Word Read Cycle Flowchart 5.6.2.2 Write Cycle During a write cycle, the MCU transfers data to an external memory or peripheral device. If the instruction specifies a long-word or word operation, the MCU attempts to write two bytes at once. For a byte operation, the MCU writes one byte. The portion of the data bus upon which each byte is written depends on operand size, peripheral address, and peripheral port size. Refer to 5.5.2 Dynamic Bus Sizing and 5.5.4 Misaligned Operands for more information. Figure 5-13 is a flowchart of a write-cycle operation for a word transfer. Refer to the SIM Reference Manual (SIMRM/AD) for more information. SYSTEM INTEGRATION MODULE 5-38 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. MCU ADDRESS DEVICE (S0) 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE PERIPHERAL ASSERT AS (S1) Freescale Semiconductor, Inc... PLACE DATA ON DATA[15:0] (S2) ASSERT DS AND WAIT FOR DSACK (S3) ACCEPT DATA (S2 + S3) 1) DECODE ADDRESS 2) LATCH DATA FROM DATA BUS 3) ASSERT DSACK SIGNALS OPTIONAL STATE (S4) NO CHANGE TERMINATE OUTPUT TRANSFER (S5) 1) NEGATE DS AND AS 2) REMOVE DATA FROM DATA BUS TERMINATE CYCLE NEGATE DSACK START NEXT CYCLE WR CYC FLOW Figure 5-13 Write Cycle Flowchart 5.6.3 Fast Termination Cycles When an external device can meet fast access timing, an internal chip-select circuit fast termination option can provide a two-cycle external bus transfer. Because the chip-select circuits are driven from the system clock, the bus cycle termination is inherently synchronized with the system clock. If multiple chip-selects are to be used to provide control signals to a single device and match conditions occur simultaneously, all MODE, STRB, and associated DSACK fields must be programmed to the same value. This prevents a conflict on the internal bus when the wait states are loaded into the DSACK counter shared by all chip-selects. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-39 Freescale Semiconductor, Inc. Fast termination cycles use internal handshaking signals generated by the chip-select logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. When AS, DS, and R/W are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle). At the appropriate time, chipselect logic asserts data size acknowledge signals. The DSACK option fields in the chip-select option registers determine whether internally generated DSACK or externally generated DSACK is used. The external DSACK lines are always active, regardless of the setting of the DSACK field in the chip-select option registers. Thus, an external DSACK can always terminate a bus cycle. Holding a DSACK line low will cause essentially all external bus cycles to be three-cycle (zero wait states) accesses unless the chip-select option register specifies fast accesses. Freescale Semiconductor, Inc... NOTE There are certain exceptions to the three-cycle rule when one or both DSACK lines are asserted. Check the current device and mask set errata for details. For fast termination cycles, the fast termination encoding (%1110) must be used. Refer to 5.9.1 Chip-Select Registers for information about fast termination setup. To use fast termination, an external device must be fast enough to have data ready within the specified setup time (for example, by the falling edge of S4). Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for information about fast termination timing. When fast termination is in use, DS is asserted during read cycles but not during write cycles. The STRB field in the chip-select option register used must be programmed with the address strobe encoding to assert the chip-select signal for a fast termination write. 5.6.4 CPU Space Cycles Function code signals FC[2:0] designate which of eight external address spaces is accessed during a bus cycle. Address space 7 is designated CPU space. CPU space is used for control information not normally associated with read or write bus cycles. Function codes are valid only while AS is asserted. Refer to 5.5.1.7 Function Codes for more information on codes and encoding. During a CPU space access, ADDR[19:16] are encoded to reflect the type of access being made. Three encodings are used by the MCU, as shown in Figure 5-14. These encodings represent breakpoint acknowledge (type $0) cycles, low power stop broadcast (type $3) cycles, and interrupt acknowledge (type $F) cycles. Type $0 and type $3 cycles are discussed in the following paragraphs. Refer to 5.8 Interrupts for information about interrupt acknowledge bus cycles. SYSTEM INTEGRATION MODULE 5-40 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. CPU SPACE CYCLES FUNCTION CODE BREAKPOINT ACKNOWLEDGE 2 0 111 2 0 111 2 0 111 ADDRESS BUS 23 19 16 4 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPT# T 0 23 19 16 0 000000111111111111111110 23 19 16 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1 CPU SPACE TYPE FIELD CPU SPACE CYC TIM LOW POWER STOP BROADCAST INTERRUPT ACKNOWLEDGE Freescale Semiconductor, Inc... Figure 5-14 CPU Space Address Encoding 5.6.4.1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at a predefined point during system development. In M68HC16 Z-series MCUs, breakpoints are treated as a type of exception processing. Breakpoints can be used alone or in conjunction with background debug mode. M68HC16 Z series MCUs have only one source and type of breakpoint. This is a hardware breakpoint initiated by assertion of the BKPT input. Other modular microcontrollers may have more than one source or type. The breakpoint acknowledge cycle discussed here is the bus cycle that occurs as a part of breakpoint exception processing when a breakpoint is initiated while background debug mode is not enabled. BKPT is sampled on the same clock phase as data. BKPT is valid, the data is tagged as it enters the CPU16 pipeline. When BKPT is asserted while data is valid during an instruction prefetch, the acknowledge cycle occurs immediately after that instruction has executed. When BKPT is asserted while data is valid during an operand fetch, the acknowledge cycle occurs immediately after execution of the instruction during which it is latched. If BKPT is asserted for only one bus cycle and a pipe flush occurs before BKPT is detected by the CPU16, no acknowledge cycle occurs. To ensure detection, BKPT should be asserted until a breakpoint acknowledge cycle is recognized. When BKPT assertion is acknowledged by the CPU16, the MCU performs a word read from CPU space address $00001E. This corresponds to the breakpoint number field (ADDR[4:2]) and the type bit (T) being set to all ones (source 7, type 1). If this bus cycle is terminated by BERR or by DSACK, the MCU performs breakpoint exception processing. Refer to Figure 5-15 for a flowchart of the breakpoint operation. Refer to the SIM Reference Manual (SIMRM/AD) for further information. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-41 Freescale Semiconductor, Inc. BREAKPOINT OPERATION FLOW CPU16 ACKNOWLEDGE BREAKPOINT 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] 4) PLACE ALL ONES ON ADDR[4:2] 5) SET ADDR1 TO ONE 6) SET SIZE TO WORD 7) ASSERT AS AND DS ASSERT DSACK OR BERR TO INITIATE EXCEPTION PROCESSING NEGATE AS or DS PERIPHERAL Freescale Semiconductor, Inc... NEGATE DSACK or BERR INITIATE HARDWARE BREAKPOINT PROCESSING CPU16 BREAKPOINT OPERATION FLOW Figure 5-15 Breakpoint Operation Flowchart 5.6.4.2 LPSTOP Broadcast Cycle Low-power stop mode is initiated by the CPU16. Individual modules can be stopped by setting the STOP bits in each module configuration register. The SIM can turn off system clocks after execution of the LPSTOP instruction. When the CPU16 executes LPSTOP, the LPSTOP broadcast cycle is generated. The SIM brings the MCU out of low-power mode when either an interrupt of higher priority than the interrupt mask level in the CPU16 condition code register or a reset occurs. Refer to 5.3.4 Low-Power Operation and SECTION 4 CENTRAL PROCESSOR UNIT for more information. During an LPSTOP broadcast cycle, the CPU16 performs a CPU space write to address $3FFFE. This write puts a copy of the interrupt mask value in the clock control logic. The mask is encoded on the data bus as shown in Figure 5-16. The LPSTOP CPU space cycle is shown externally (if the bus is available) as an indication to external devices that the MCU is going into low-power stop mode. The SIM provides an internally generated DSACK response to this cycle. The timing of this bus cycle is the same as for a fast termination write cycle. If the bus is not available (arbitrated away), the LPSTOP broadcast cycle is not shown externally. NOTE BERR during the LPSTOP broadcast cycle is ignored. SYSTEM INTEGRATION MODULE 5-42 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 IP MASK 0 LPSTOP MASK LEVEL Figure 5-16 LPSTOP Interrupt Mask Level 5.6.5 Bus Exception Control Cycles An external device or a chip-select circuit must assert at least one of the DSACK[1:0] signals or the AVEC signal to terminate a bus cycle normally. Bus exception control cycles are used when bus cycles are not terminated in the expected manner. There are two sources of bus exception control cycles. • Bus error signal (BERR) — When neither DSACK nor AVEC is asserted within a specified period after assertion of AS, the internal bus monitor asserts internal BERR. — The spurious interrupt monitor asserts internal BERR when an interrupt request is acknowledged and no IARB contention occurs. BERR assertion terminates a cycle and causes the MCU to process a bus error exception. — External devices can assert BERR to indicate an external bus error. • Halt signal (HALT) — HALT can be asserted by an external device to cause single bus cycle operation. HALT is typically used for debugging purposes. To control termination of a bus cycle for a bus error condition properly, DSACK, BERR, and HALT must be asserted and negated synchronously with the rising edge of CLKOUT. This ensures that setup time and hold time requirements are met for the same falling edge of the MCU clock when two signals are asserted simultaneously. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information. External circuitry that provides these signals must be designed with these constraints in mind, or the internal bus monitor must be used. Table 5-17 is a summary of the acceptable bus cycle terminations for asynchronous cycles in relation to DSACK assertion. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-43 Freescale Semiconductor, Inc. Table 5-17 DSACK, BERR, and HALT Assertion Results Type of Termination NORMAL Control Signal DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT Asserted on Rising Edge of State 1 S+2 S A2 NA3 NA A NA A/RA NA/A A NA A A NA NA/A A A/S A NA NA RA4 NA X5 RA NA RA X RA X X RA NA X RA RA X A A Description of Result Normal cycle terminate and continue. HALT Normal cycle terminate and halt. Continue when HALT is negated. Terminate and take bus error exception. BUS ERROR 1 BUS ERROR 2 Terminate and take bus error exception. Freescale Semiconductor, Inc... BUS ERROR 3 BUS ERROR 4 Terminate and take bus error exception. Terminate and take bus error exception. NOTES: 1. S = The number of current even bus state (for example, S2, S4, etc.) 2. A = Signal is asserted in this bus state. 3. NA = Signal is not asserted in this state. 4. RA = Signal was asserted in previous state and remains asserted in this state. 5. X = Don’t care 5.6.5.1 Bus Errors The CPU16 treats bus errors as a type of exception. Bus error exception processing begins when the CPU16 detects assertion of the IMB BERR signal. BERR assertions do not force immediate exception processing. The signal is synchronized with normal bus cycles and is latched into the CPU16 at the end of the bus cycle in which it was asserted. Because bus cycles can overlap instruction boundaries, bus error exception processing may not occur at the end of the instruction in which the bus cycle begins. Timing of BERR detection/acknowledge is dependent upon several factors: • Which bus cycle of an instruction is terminated by assertion of BERR. • The number of bus cycles in the instruction during which BERR is asserted. • The number of bus cycles in the instruction following the instruction in which BERR is asserted. • Whether BERR is asserted during a program space access or a data space access. Because of these factors, it is impossible to predict precisely how long after occurrence of a bus error the bus error exception is processed. SYSTEM INTEGRATION MODULE 5-44 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. NOTE The external bus interface does not latch data when an external bus cycle is terminated by a bus error. When this occurs during an instruction prefetch, the IMB precharge state (bus pulled high, or $FF) is latched into the CPU16 instruction register, with indeterminate results. 5.6.5.2 Double Bus Faults Exception processing for bus error exceptions follows the standard exception processing sequence. Refer to 4.13 Exceptions for more information. However, two special cases of bus error, called double bus faults, can abort exception processing. Freescale Semiconductor, Inc... BERR assertion is not detected until an instruction is complete. The BERR latch is cleared by the first instruction of the BERR exception handler. Double bus fault occurs in two ways: 1. When bus error exception processing begins, and a second BERR is detected before the first instruction of the exception handler is executed. 2. When one or more bus errors occur before the first instruction after a RESET exception is executed. Multiple bus errors within a single instruction that can generate multiple bus cycles cause a single bus error exception after the instruction has been executed. Immediately after assertion of a second BERR, the MCU halts and drives the HALT line low. Only a reset can restart a halted MCU. However, bus arbitration can still occur. Refer to 5.6.6 External Bus Arbitration for more information. A bus error or address error that occurs after exception processing has been completed (during the execution of the exception handler routine, or later) does not cause a double bus fault. The MCU continues to retry the same bus cycle as long as the external hardware requests it. 5.6.5.3 Halt Operation When HALT is asserted while BERR is not asserted, the MCU halts external bus activity after negation of DSACK. The MCU may complete the current word transfer in progress. For a long-word to byte transfer, this could be after S2 or S4. For a word to byte transfer, activity ceases after S2. Negating and reasserting HALT according to timing requirements provides single-step (bus cycle to bus cycle) operation. The HALT signal affects external bus cycles only, so that a program that does not use external bus can continue executing. During dynamically-sized 8-bit transfers, external bus activity may not stop at the next cycle boundary. Occurrence of a bus error while HALT is asserted causes the CPU16 to process a bus error exception. When the MCU completes a bus cycle while the HALT signal is asserted, the data bus goes into a high-impedance state and the AS and DS signals are driven to their inactive states. Address, function code, size, and read/write signals remain in the same state. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-45 Freescale Semiconductor, Inc. The halt operation has no effect on bus arbitration. However, when external bus arbitration occurs while the MCU is halted, address and control signals go into a high-impedance state. If HALT is still asserted when the MCU regains control of the bus, address, function code, size, and read/write signals revert to the previous driven states. The MCU cannot service interrupt requests while halted. 5.6.6 External Bus Arbitration The MCU bus design provides for a single bus master at any one time. Either the MCU or an external device can be master. Bus arbitration protocols determine when an external device can become bus master. Bus arbitration requests are recognized during normal processing, HALT assertion, and when the CPU has halted due to a double bus fault. Freescale Semiconductor, Inc... The bus controller in the MCU manages bus arbitration signals so that the MCU has the lowest priority. External devices that need to obtain the bus must assert bus arbitration signals in the sequences described in the following paragraphs. Systems that include several devices that can become bus master require external circuitry to assign priorities to the devices, so that when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first. The protocol sequence is: 1. An external device asserts the bus request signal (BR). 2. The MCU asserts the bus grant signal (BG) to indicate that the bus is available. 3. An external device asserts the bus grant acknowledge (BGACK) signal to indicate that it has assumed bus mastership. BR can be asserted during a bus cycle or between cycles. BG is asserted in response to BR. To guarantee operand coherency, BG is only asserted at the end of operand transfer. If more than one external device can be bus master, required external arbitration must begin when a requesting device receives BG. An external device must assert BGACK when it assumes mastership, and must maintain BGACK assertion as long as it is bus master. Two conditions must be met for an external device to assume bus mastership. The device must receive BG through the arbitration process, and BGACK must be inactive, indicating that no other bus master is active. This technique allows the processing of bus requests during data transfer cycles. BG is negated a few clock cycles after BGACK transition. However, if bus requests are still pending after BG is negated, the MCU asserts BG again within a few clock cycles. This additional BG assertion allows external arbitration circuitry to select the next bus master before the current master has released the bus. Refer to Figure 5-17, which shows bus arbitration for a single device. The flowchart shows BR negated at the same time BGACK is asserted. SYSTEM INTEGRATION MODULE 5-46 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. MCU REQUESTING DEVICE REQUEST THE BUS GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) 1) ASSERT BUS REQUEST (BR) ACKNOWLEDGE BUS MASTERSHIP 1) EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3) NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4) BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PROCESSOR USES TERMINATE ARBITRATION 1) NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED) Freescale Semiconductor, Inc... RELEASE BUS MASTERSHIP RE-ARBITRATE OR RESUME PROCESSOR OPERATION 1) NEGATE BGACK BUS ARB FLOW Figure 5-17 Bus Arbitration Flowchart for Single Request 5.6.6.1 Show Cycles The MCU normally performs internal data transfers without affecting the external bus, but it is possible to show these transfers during debugging. AS is not asserted externally during show cycles. Show cycles are controlled by the SHEN[1:0] in SIMCR. This field is set to %00 by reset. When show cycles are disabled, the address bus, function codes, size, and read/ write signals reflect internal bus activity, but AS and DS are not asserted externally and external data bus pins are in high-impedance state during internal accesses. Refer to 5.2.3 Show Internal Cycles and the SIM Reference Manual (SIMRM/AD) for more information. When show cycles are enabled, DS is asserted externally during internal cycles, and internal data is driven out on the external data bus. Because internal cycles normally continue to run when the external bus is granted, one SHEN[1:0] encoding halts internal bus activity while there is an external master. SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion of the data bus is valid during the cycle. During a byte write to an internal address, the portion of the bus that represents the byte that is not written reflects internal bus conditions, and is indeterminate. During a byte write to an external address, the data multiplexer in the SIM causes the value of the byte that is written to be driven out on both bytes of the data bus. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-47 Freescale Semiconductor, Inc. 5.7 Reset Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. The RESET input is synchronized to the system clock. If there is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked to allow completion of write cycles in progress at the time RESET is asserted. Reset procedures handle system initialization and recovery from catastrophic failure. The MCU performs resets with a combination of hardware and software. The SIM determines whether a reset is valid, asserts control signals, performs basic system configuration and boot ROM selection based on hardware mode-select inputs, then passes control to the CPU16. 5.7.1 Reset Exception Processing The CPU16 processes resets as a type of asynchronous exception. An exception is an event that preempts normal processing, and can be caused by internal or external events. Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception. Each exception has an assigned vector that points to an associated handler routine. These vectors are stored in the exception vector table. The exception vector table consists of 256 four-byte vectors and occupies 512 bytes of address space. The exception vector table can be relocated in memory by changing its base address in the vector base register (VBR). The CPU16 uses vector numbers to calculate displacement into the table. Refer to 4.13 Exceptions for more information. Reset is the highest-priority CPU16 exception. Unlike all other exceptions, a reset occurs at the end of a bus cycle, and not at an instruction boundary. Handling resets in this way prevents write cycles in progress at the time the reset signal is asserted from being corrupted. However, any processing in progress is aborted by the reset exception, and cannot be restarted. Only essential reset tasks are performed during exception processing. Other initialization tasks must be accomplished by the exception handler routine. Refer to 5.7.9 Reset Processing Summary for details on exception processing. 5.7.2 Reset Control Logic SIM reset control logic determines the cause of a reset, synchronizes request signals to CLKOUT, and asserts reset control signals. Reset control logic can drive three different internal signals. • EXTRST (external reset) drives the external reset pin. • CLKRST (clock reset) resets the clock module. • MSTRST (master reset) goes to all other internal circuits. All resets are gated by CLKOUT. Asynchronous resets are assumed to be catastrophic. An asynchronous reset can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. The SIM bus monitor is automatically enabled for synchronous resets. When a bus cycle does not terminate normally, the bus monitor terminates it. Table 5-18 is a summary of reset sources. Freescale Semiconductor, Inc... SYSTEM INTEGRATION MODULE 5-48 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-18 Reset Source Summary Type External Power up Software watchdog HALT Loss of clock Test Source External EBI Monitor Monitor Clock Test Timing Synch Asynch Asynch Asynch Synch Synch Cause RESET pin VDD Time out Internal HALT assertion (e.g. double bus fault) Loss of reference Test mode Reset Lines Asserted by Controller MSTRST CLKRST EXTRST MSTRST MSTRST MSTRST MSTRST MSTRST CLKRST CLKRST CLKRST CLKRST — EXTRST EXTRST EXTRST EXTRST EXTRST Freescale Semiconductor, Inc... Internal single byte or aligned word writes are guaranteed valid for synchronous resets. External writes are also guaranteed to complete, provided the external configuration logic on the data bus is conditioned as shown in Figure 5-18. 5.7.3 Reset Mode Selection The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines what happens during subsequent breakpoint assertions. Table 5-19 is a summary of reset mode selection options. Table 5-19 Reset Mode Selection Mode Select Pin DATA0 DATA1 Default Function (Pin Left High) CSBOOT 16-Bit CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS[7:6] CS[8:6] CS[9:6] CS[10:6] DSACK[1:0], AVEC, DS, AS, SIZ[1:0] IRQ[7:1] MODCLK Normal Operation1 VCO = System Clock Background Mode Disabled Alternate Function (Pin Pulled Low) CSBOOT 8-Bit BR BG BGACK FC0 FC1 FC2 ADDR19 ADDR[20:19] ADDR[21:19] ADDR[22:19] ADDR[23:19] PORTE DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA11 MODCLK BKPT PORTF Reserved EXTAL = System Clock Background Mode Enabled NOTES: 1. DATA11 must remain high during reset to ensure normal operation. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-49 Freescale Semiconductor, Inc. 5.7.3.1 Data Bus Mode Selection All data lines have weak internal pull-up devices. When pins are held high by the internal pull-ups, the MCU uses a default operating configuration. However, specific lines can be held low externally during reset to achieve an alternate configuration. NOTE External bus loading can overcome the weak internal pull-up drivers on data bus lines and hold pins low during reset. Use an active device to hold data bus lines low. Data bus configuration logic must release the bus before the first bus cycle after reset to prevent conflict with external memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is released. If external mode selection logic causes a conflict of this type, an isolation resistor on the driven lines may be required. Figure 5-18 shows a recommended method for conditioning the mode select signals. DATA15 Freescale Semiconductor, Inc... DATA8 DATA7 DATA0 OUT1 OUT8 74HC244 OE IN8 OUT1 OUT8 74HC244 OE IN8 IN1 VDD VDD VDD TIE INPUTS HIGH OR LOW AS NEEDED IN1 TIE INPUTS HIGH OR LOW AS NEEDED 820 Ω RESET 10 kΩ 10 kΩ DS R/W DATA BUS SELECT CONDITIONING Figure 5-18 Preferred Circuit for Data Bus Mode Select Conditioning SYSTEM INTEGRATION MODULE 5-50 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. The mode configuration drivers are conditioned with R/W and DS to prevent conflicts between external devices and the MCU when reset is asserted. If external RESET is asserted during an external write cycle, R/W conditioning (as shown in Figure 5-18) prevents corruption of the data during the write. Similarly, DS conditions the mode configuration drivers so that external reads are not corrupted when RESET is asserted during an external read cycle. Alternate methods can be used for driving data bus pins low during reset. Figure 5-19 shows two of these options. The simplest is to connect a resistor in series with a diode from the data bus pin to the RESET line. A bipolar transistor can be used for the same purpose, but an additional current limiting resistor must be connected between the base of the transistor and the RESET pin. If a MOSFET is substituted for the bipolar transistor, only the 1 kΩ isolation resistor is required. These simpler circuits do not offer the protection from potential memory corruption during RESET assertion as does the circuit shown in Figure 5-18. DATA PIN DATA PIN 1 kΩ 1 kΩ 2 kΩ 1N4148 RESET 2N3906 Freescale Semiconductor, Inc... RESET ALTERNATE DATA BUS CONDITION CIRCUIT Figure 5-19 Alternate Circuit for Data Bus Mode Select Conditioning Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARACTERISTICS. Do not confuse pin function with pin electrical state. Refer to 5.7.5 Pin State During Reset for more information. Unlike other chip-select signals, the boot ROM chip-select (CSBOOT) is active at the release of RESET. During reset exception processing, the MCU fetches initialization vectors beginning at address $000000 in supervisor program space. An external memory device containing vectors located at these addresses can be enabled by CSBOOT after a reset. The logic level of DATA0 during reset selects boot ROM port size for dynamic bus allocation. When DATA0 is held low, port size is eight bits; when DATA0 is held high, either by the weak internal pull-up driver or by an external pull-up, port size is 16 bits. Refer to 5.9.4 Chip-Select Reset Operation for more information. DATA1 and DATA2 determine the functions of CS[2:0] and CS[5:3], respectively. DATA[7:3] determine the functions of an associated chip-select and all lower-numbered chip-selects down through CS6. For example, if DATA5 is pulled low during reset, CS[8:6] are assigned alternate function as ADDR[21:19], and CS[10:9] remain chip-selects. Refer to 5.9.4 Chip-Select Reset Operation for more information. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-51 Freescale Semiconductor, Inc. DATA8 determines the function of the DSACK[1:0], AVEC, DS, AS, and SIZE pins. If DATA8 is held low during reset, these pins are assigned to I/O port E. DATA9 determines the function of interrupt request pins IRQ[7:1] and the clock mode select pin (MODCLK). When DATA9 is held low during reset, these pins are assigned to I/O port F. 5.7.3.2 Clock Mode Selection The state of the clock mode (MODCLK) pin during reset determines what clock source the MCU uses. When MODCLK is held high during reset, the clock signal is generated from a reference frequency using the clock synthesizer. When MODCLK is held low during reset, the clock synthesizer is disabled, and an external system clock signal must be applied. Refer to 5.3 System Clock for more information. Freescale Semiconductor, Inc... NOTE The MODCLK pin can also be used as parallel I/O pin PF0. To prevent inadvertent clock mode selection by logic connected to port F, use an active device to drive MODCLK during reset. 5.7.3.3 Breakpoint Mode Selection Background debug mode (BDM) is enabled when the breakpoint (BKPT) pin is sampled at a logic level zero at the release of RESET. Subsequent assertion of the BKPT pin or the internal breakpoint signal (for instance, the execution of the CPU16 BKPT instruction) will place the CPU16 in BDM. If BKPT is sampled at a logic level one at the rising edge of RESET, BDM is disabled. Assertion of the BKPT pin or execution of the BKPT instruction will result in normal breakpoint exception processing. BDM remains enabled until the next system reset. BKPT is relatched on each rising transition of RESET. BKPT is internally synchronized and must be held low for at least two clock cycles prior to RESET negation for BDM to be enabled. BKPT assertion logic must be designed with special care. If BKPT assertion extends into the first bus cycle following the release of RESET, the bus cycle could inadvertently be tagged with a breakpoint. Refer to 4.14.4 Background Debug Mode and the CPU16 Reference Manual (CPU16RM/AD) for more information on background debug mode. Refer to the SIM Reference Manual (SIMRM/AD) and APPENDIX A ELECTRICAL CHARACTERISTICS for more information concerning BKPT signal timing. 5.7.4 MCU Module Pin Function During Reset Usually, module pins default to port functions and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers and by clearing the appropriate port data direction registers. Refer to individual module sections in this manual for more information. Table 5-20 is a summary of module pin function out of reset. Refer to APPENDIX D REGISTER SUMMARY for register function and reset state. SYSTEM INTEGRATION MODULE 5-52 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 5-20 Module Pin Functions Module1 Pin Mnemonic PADA[7:0]/AN[7:0] ADC VRH VRL DSI/IPIPE1 CPU DSO/IPIPE0 BKPT/DSCLK PGP7/IC4/OC5 PGP[6:3]/OC[4:1] GPT PGP[2:0]/IC[3:1] PAI PCLK PWMA, PWMB PQS7/TXD PQS[6:4]/PCS[3:1] PQS3/PCS0/SS QSM PQS2/SCK PQS1/MOSI PQS0/MISO RXD PMC7/TXDA PMC6/RXDA PMC5/TXDB MCCI PMC4/RXDB PMC3/SS PMC2/SCK PMC1/MOSI PMC0/MISO Function Discrete input Reference voltage Reference voltage DSI/IPIPE1 DSO/IPIPE0 BKPT/DSCLK Discrete input Discrete input Discrete input Discrete input Discrete input Discrete output Discrete input Discrete input Discrete input Discrete input Discrete input Discrete input RXD Discrete input Discrete input Discrete input Discrete input Discrete input Discrete input Discrete input Discrete input Freescale Semiconductor, Inc... NOTES: 1. Module port pins may be in an indeterminate state for up to 15 milliseconds at power-up. 5.7.5 Pin State During Reset It is important to keep the distinction between pin function and pin electrical state clear. Although control register values and mode select inputs determine pin function, a pin driver can be active, inactive or in high-impedance state while reset occurs. During power-on reset, pin state is subject to the constraints discussed in 5.7.7 Power-On Reset. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-53 Freescale Semiconductor, Inc. NOTE Pins that are not used should either be configured as outputs, or (if configured as inputs) pulled to the appropriate inactive state. This decreases additional IDD caused by digital inputs floating near mid-supply level. 5.7.5.1 Reset States of SIM Pins Generally, while RESET is asserted, SIM pins either go to an inactive high-impedance state or are driven to their inactive states. After RESET is released, mode selection occurs, and reset exception processing begins. Pins configured as inputs must be driven to the desired active state. Pull-up or pull-down circuitry may be necessary. Pins configured as outputs begin to function after RESET is released. Table 5-21 is a summary of SIM pin states during reset. Table 5-21 SIM Pin Reset States Pin(s) CS10/ADDR23/ECLK CS[9:6]/ADDR[22:19]/PC[6:3] ADDR[18:0] AS/PE5 AVEC/PE2 BERR CS1/BG CS2/BGACK CS0/BR CLKOUT CSBOOT DATA[15:0] DS/PE4 DSACK0/PE0 DSACK1/PE1 CS[5:3]/FC[2:0]/PC[2:0] HALT IRQ[7:1]/PF[7:1] MODCLK/PF0 R/W RESET SIZ[1:0]/PE[7:6] TSC Pin State While RESET Asserted VDD VDD High-Z High-Z High-Z High-Z VDD VDD VDD Output VDD Mode select High-Z High-Z High-Z VDD High-Z High-Z Mode Select High-Z Asserted High-Z Mode select Pin State After RESET Released Default Function Pin Function CS10 CS[9:6] ADDR[18:0] AS AVEC BERR CS1 CS2 CS0 CLKOUT CSBOOT DATA[15:0] DS DSACK0 DSACK1 CS[5:3] HALT IRQ[7:1] MODCLK R/W RESET SIZ[1:0] TSC Pin State VDD VDD Unknown Output Input Input VDD VDD VDD Output VSS Input Output Input Input VDD Input Input Input Output Input Unknown Input Alternate Function Pin Function ADDR23 ADDR[22:19] ADDR[18:0] PE5 PE2 BERR BG BGACK BR CLKOUT CSBOOT DATA[15:0] PE4 PE0 PE1 FC[2:0] HALT PF[7:1] PF0 R/W RESET PE[7:6] TSC Pin State Unknown Unknown Unknown Input Input Input VDD Input Input Output VSS Input Input Input Input Unknown Input Input Input Output Input Input Input Freescale Semiconductor, Inc... 5.7.5.2 Reset States of Pins Assigned to Other MCU Modules As a rule, module pins that are assigned to general-purpose I/O ports go into a highimpedance state following reset. However, during power-on reset, module port pins may be in an indeterminate state for a short period. Refer to 5.7.7 Power-On Reset for more information. SYSTEM INTEGRATION MODULE 5-54 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 5.7.6 Reset Timing The RESET input must be asserted for a specified minimum period for reset to occur. External RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is asserted, SIM pins are either in an inactive, high-impedance state or are driven to their inactive states. When an external device asserts RESET for the proper period, reset control logic clocks the signal into an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer being externally driven to guarantee this length of reset to the entire system. If an internal source asserts a reset signal, the reset control logic asserts the RESET pin for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert the RESET pin until the internal reset signal is negated. After 512 cycles have elapsed, the RESET pin goes to an inactive, high-impedance state for ten cycles. At the end of this 10-cycle period, the RESET input is tested. When the input is at logic level one, reset exception processing begins. If, however, the RESET input is at logic level zero, reset control logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-impedance state for ten cycles, then it is tested again. The process repeats until external RESET is released. 5.7.7 Power-On Reset When the SIM clock synthesizer is used to generate system clocks, power-on reset involves special circumstances related to application of the system and the clock synthesizer power. Regardless of clock source, voltage must be applied to clock synthesizer power input pin VDDSYN for the MCU to operate. The following discussion assumes that VDDSYN is applied before and during reset, which minimizes crystal start-up time. When VDDSYN is applied at power-on, start-up time is affected by specific crystal parameters and by oscillator circuit design. VDD ramp-up time also affects pin state during reset. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage and timing specifications. During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST) and external (EXTRST) reset lines. The power-on reset circuit releases the internal reset line as VDD ramps up to the minimum operating voltage, and SIM pins are initialized to the values shown in Table 5-21. When VDD reaches the minimum operating voltage, the clock synthesizer VCO begins operation. Clock frequency ramps up to specified limp mode frequency (flimp). The external RESET line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse. NOTE VDDSYN and all VDD pins must be powered. Applying power to VDDSYN only will cause errant behavior of the MCU. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-55 Freescale Semiconductor, Inc. The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running and MSTRST is asserted for at least four clock cycles, these modules reset. VDD ramp time and VCO frequency ramp time determine how long the four cycles take. Worst case is approximately 15 milliseconds. During this period, module port pins may be in an indeterminate state. While input-only pins can be put in a known state by external pull-up resistors, external logic on input/output or output-only pins during this time must condition the lines. Active drivers require high-impedance buffers or isolation resistors to prevent conflict. Figure 5-20 is a timing diagram for power-on reset. It shows the relationships between RESET, VDD, and bus signals. Freescale Semiconductor, Inc... CLKOUT VCO LOCK VDD 2 CLOCKS RESET 512 CLOCKS 10 CLOCKS BUS CYCLES BUS STATE UNKNOWN ADDRESS AND CONTROL SIGNALS THREE-STATED 1 2 NOTES: 1. INTERNAL START-UP TIME 2. FIRST INSTRUCTION FETCHED 16 POR TIM Figure 5-20 Power-On Reset 5.7.8 Use of the Three-State Control Pin Asserting the three-state control (TSC) input causes the MCU to put all output drivers in a disabled, high-impedance state. The signal must remain asserted for approximately ten clock cycles in order for drivers to change state. When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-up time affects how long the ten cycles take. Worst case is approximately 20 milliseconds from TSC assertion. When an external clock signal is applied (MODCLK held low during reset), pins go to high-impedance state as soon after TSC assertion as approximately ten clock pulses have been applied to the EXTAL pin. SYSTEM INTEGRATION MODULE 5-56 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. NOTE When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. Once the output drivers change state, the MCU must be powered down and restarted before normal operation can resume. 5.7.9 Reset Processing Summary To prevent write cycles in progress from being corrupted, a reset is recognized at the end of a bus cycle, and not at an instruction boundary. Any processing in progress at the time a reset occurs is aborted. After SIM reset control logic has synchronized an internal or external reset request, the MSTRST signal is asserted. The following events take place when MSTRST is asserted. Freescale Semiconductor, Inc... A. Instruction execution is aborted. B. The condition code register is initialized. 1. The IP field is set to $7, disabling all interrupts below priority 7. 2. The S bit is set, disabling LPSTOP mode. 3. The SM bit is cleared, disabling MAC saturation mode. C. The K register is cleared. NOTE All CCR bits that are not initialized are not affected by reset. However, out of power-on reset, these bits are indeterminate. The following events take place when MSTRST is negated after assertion. A. The CPU16 samples the BKPT input. B. The CPU16 fetches RESET vectors in the following order: 1. Initial ZK, SK, and PK extension field values 2. Initial PC 3. Initial SP 4. Initial IZ value Vectors can be fetched from internal RAM or from external ROM enabled by the CSBOOT signal. C. The CPU16 begins fetching instructions pointed to by the initial PK : PC. 5.7.10 Reset Status Register The reset status register (RSR) contains a bit for each reset source in the MCU. When a reset occurs, a bit corresponding to the reset type is set. When multiple causes of reset occur at the same time, more than one bit in RSR may be set. The reset status register is updated by the reset control logic when the RESET signal is released. Refer to APPENDIX D REGISTER SUMMARY. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-57 Freescale Semiconductor, Inc. 5.8 Interrupts Interrupt recognition and servicing involve complex interaction between the SIM, the CPU16, and a device or module requesting interrupt service. This discussion provides an overview of the entire interrupt process. Chip-select logic can also be used to respond to interrupt requests. Refer to 5.9 Chip-Selects for more information. 5.8.1 Interrupt Exception Processing The CPU16 handles interrupts as a type of asynchronous exception. An exception is an event that preempts normal processing. Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception. Each exception has an assigned vector that points to an associated handler routine. These vectors are stored in a vector table located in the first 512 bytes of address bank 0. The CPU16 uses vector numbers to calculate displacement into the table. Refer to 4.13 Exceptions for more information. 5.8.2 Interrupt Priority and Recognition The CPU16 provides for seven levels of interrupt priority (1 – 7), seven automatic interrupt vectors, and 200 assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the interrupt priority (IP) field in the condition code register. There are seven interrupt request signals (IRQ[7:1]). These signals are used internally on the IMB, and there are corresponding pins for external interrupt service requests. The CPU16 treats all interrupt requests as though they come from internal modules; external interrupt requests are treated as interrupt service requests from the SIM. Each of the interrupt request signals corresponds to an interrupt priority level. IRQ1 has the lowest priority and IRQ7 the highest. The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide eight priority masks. Masks prevent an interrupt request of a priority less than or equal to the mask value (except for IRQ7) from being recognized and processed. When IP contains %000, no interrupt is masked. During exception processing, the IP field is set to the priority of the interrupt being serviced. Interrupt recognition is determined by interrupt priority level and interrupt priority (IP) mask value. The interrupt priority mask consists of three bits in the CPU16 condition code register (CCR[7:5]). Binary values %000 to %111 provide eight priority masks. Masks prevent an interrupt request of a priority less than or equal to the mask value from being recognized and processed. IRQ7, however, is always recognized, even if the mask value is %111. IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted until an interrupt acknowledge cycle corresponding to that level is detected. IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected unless a falling edge transition is detected on the IRQ7 line. This prevents redundant servicing and stack overflow. A non-maskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask is written while IRQ7 is asserted. If IRQ7 is asserted and the IP mask is written to any new value (including %111), IRQ7 will be recognized as a new IRQ7. SYSTEM INTEGRATION MODULE 5-58 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input circuitry has hysteresis. To be valid, a request signal must be asserted for at least two consecutive clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests are processed at instruction boundaries or when exception processing of higher-priority interrupts is complete. The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. If an interrupt request with a priority equal to or lower than the current IP mask value is made, the CPU16 does not recognize the occurrence of the request. If simultaneous interrupt requests of different priorities are made, and both have a priority greater than the mask value, the CPU16 recognizes the higher-level request. Freescale Semiconductor, Inc... 5.8.3 Interrupt Acknowledge and Arbitration When the CPU16 detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it places the interrupt request level on the address bus and initiates a CPU space read cycle. The request level serves two purposes: it is decoded by modules or external devices that have requested interrupt service, to determine whether the current interrupt acknowledge cycle pertains to them, and it is latched into the interrupt priority mask field in the CPU16 condition code register to preclude further interrupts of lower priority during interrupt service. Modules or external devices that have requested interrupt service must decode the IP mask value placed on the address bus during the interrupt acknowledge cycle and respond if the priority of the service request corresponds to the mask value. However, before modules or external devices respond, interrupt arbitration takes place. Arbitration is performed by means of serial contention between values stored in individual module interrupt arbitration (IARB) fields. Each module that can make an interrupt service request, including the SIM, has an IARB field in its configuration register. IARB fields can be assigned values from %0000 to %1111. In order to implement an arbitration scheme, each module that can request interrupt service must be assigned a unique, non-zero IARB field value during system initialization. Arbitration priorities range from %0001 (lowest) to %1111 (highest). If the CPU16 recognizes an interrupt service request from a source that has an IARB field value of %0000, a spurious interrupt exception is processed. WARNING Do not assign the same arbitration priority to more than one module. When two or more IARB fields have the same nonzero value, the CPU16 interprets multiple vector numbers at the same time, with unpredictable consequences. Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration between internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is %0000. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-59 Freescale Semiconductor, Inc. Although arbitration is intended to deal with simultaneous requests of the same interrupt level, it always takes place, even when a single source is requesting service. This is important for two reasons: the EBI does not transfer the interrupt acknowledge read cycle to the external bus unless the SIM wins contention, and failure to contend causes the interrupt acknowledge bus cycle to be terminated early by a bus error. When arbitration is complete, the module with both the highest asserted interrupt level and the highest arbitration priority must terminate the bus cycle. Internal modules place an interrupt vector number on the data bus and generate appropriate internal cycle termination signals. In the case of an external interrupt request, after the interrupt acknowledge cycle is transferred to the external bus, the appropriate external device must respond with a vector number, then generate data size acknowledge (DSACK) termination signals, or it must assert the autovector (AVEC) request signal. If the device does not respond in time, the SIM bus monitor, if enabled, asserts the bus error signal (BERR), and a spurious interrupt exception is taken. Chip-select logic can also be used to generate internal AVEC or DSACK signals in response to interrupt acknowledgment cycles. Refer to 5.9.3 Using Chip-Select Signals for Interrupt Acknowledge for more information. Chip-select address match logic functions only after the EBI transfers an interrupt acknowledge cycle to the external bus following IARB contention. All interrupts from internal modules have their associated IACK cycles terminated with an internal DSACK. Thus, user vectors (instead of autovectors) must always be used for interrupts generated from internal modules. If an internal module makes an interrupt request of a certain priority, and the appropriate chip-select registers are programmed to generate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level, chip-select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a vector number and generates internal cycle termination signals. For periodic timer interrupts, the PIRQ[2:0] field in the periodic interrupt control register (PICR) determines PIT priority level. A PIRQ[2:0] value of %000 means that PIT interrupts are inactive. By hardware convention, when the CPU16 receives simultaneous interrupt requests of the same level from more than one SIM source (including external devices), the periodic interrupt timer is given the highest priority, followed by the IRQ pins. 5.8.4 Interrupt Processing Summary A summary of the entire interrupt processing sequence follows. When the sequence begins, a valid interrupt service request has been detected and is pending. A. The CPU16 finishes higher priority exception processing or reaches an instruction boundary. B. Processor state is stacked, then the CCR PK extension field is cleared. C. The interrupt acknowledge cycle begins: 1. FC[2:0] are driven to %111 (CPU space) encoding. 2. The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged; and ADDR0 = %1. SYSTEM INTEGRATION MODULE 5-60 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 3. Request priority is latched into the CCR IP field from the address bus. Modules or external peripherals that have requested interrupt service decode the priority value in ADDR[3:1]. If request priority is the same as acknowledged priority, arbitration by IARB contention takes place. After arbitration, the interrupt acknowledge cycle is completed in one of the following ways: 1. When there is no contention (IARB = %0000), the spurious interrupt monitor asserts BERR, and the CPU16 generates the spurious interrupt vector number. 2. The dominant interrupt source supplies a vector number and DSACK signals appropriate to the access. The CPU16 acquires the vector number. 3. The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source or the pin can be tied low), and the CPU16 generates an autovector number corresponding to interrupt priority. 4. The bus monitor asserts BERR and the CPU16 generates the spurious interrupt vector number. The vector number is converted to a vector address. The content of the vector address is loaded into the PC and the processor transfers control to the exception handler routine. D. E. Freescale Semiconductor, Inc... F. G. 5.8.5 Interrupt Acknowledge Bus Cycles Interrupt acknowledge bus cycles are CPU space cycles that are generated during exception processing. For further information about the types of interrupt acknowledge bus cycles determined by AVEC or DSACK, refer to APPENDIX A ELECTRICAL CHARACTERISTICS and the SIM Reference Manual (SIMRM/AD). 5.9 Chip-Selects Typical microcontrollers require additional hardware to provide external chip-select signals. The MCU includes 12 programmable chip-select circuits that can provide from two to 16 clock-cycle access to external memory and peripherals. Address block sizes of 2 Kbytes to 512 Kbytes can be selected. However, because ADDR[23:20] follow the state of ADDR19, 512-Kbyte blocks are the largest usable size. Figure 5-21 is a diagram of a basic system that uses chip-selects. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-61 Freescale Semiconductor, Inc. VDD VDD VDD VDD VDD VDD 10 kΩ DSACK1 DSACK0 R/W CS3 CS4 IRQ7 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ DTACK R/W CS IACK IRQ ADDR[3:0] RS[4:1] DATA[15:8] D[7:0] VDD ADDR[17:0] DATA[15:0] Freescale Semiconductor, Inc... 10 kΩ CSBOOT1 CE OE WE ADDR[17:1] A[16:0] DATA[15:0] VDD VDD DQ[15:0] M68HC16 Z-SERIES MCU 10 kΩ CS01 CS11 10 kΩ E W ADDR[15:1] A[14:0] DATA[15:8] DQ[7:0] VDD 10 kΩ CS21 ADDR[15:1] E W A[14:0] DATA[7:0] DQ[7:0] MCM6206D MCM6206D G G NOTES: 1. ALL CHIP-SELECT LINES IN THIS EXAMPLE MUST BE CONFIGURED AS 16-BIT. HC16 SIM/SCIM BUS Figure 5-21 Basic MCU System SYSTEM INTEGRATION MODULE 5-62 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL (SRAM 32K X 8) (SRAM 32K X 8) (FLASH 64K X 16) (ASYNC BUS PERIPHERAL) MC68HC681 Freescale Semiconductor, Inc. Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. Logic can also generate DSACK and AVEC signals internally. A single DSACK generator is shared by all chipselects. Each signal can also be synchronized with the ECLK signal available on ADDR23. When a memory access occurs, chip-select logic compares address space type, address, type of access, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select signals are active low. If a chip-select function is given the same address as a microcontroller module or an internal memory array, an access to that address goes to the module or array, and the chip-select signal is not asserted. The external address and data buses do not reflect the internal access. All chip-select circuits are configured for operation out of reset. However, all chip-select signals except CSBOOT are disabled, and cannot be asserted until the BYTE[1:0] field in the corresponding option register is programmed to a non-zero value to select a transfer size. The chip-select option register must not be written until a base address has been written to a proper base address register. Alternate functions for chip-select pins are enabled if appropriate data bus pins are held low at the release of RESET. Refer to 5.7.3.1 Data Bus Mode Selection for more information. Figure 5-22 is a functional diagram of a single chip-select circuit. Freescale Semiconductor, Inc... INTERNAL SIGNALS ADDRESS BUS CONTROL BASE ADDRESS REGISTER ADDRESS COMPARATOR OPTION COMPARE OPTION REGISTER TIMING AND CONTROL PIN AVEC DSACK AVEC GENERATOR DSACK GENERATOR PIN ASSIGNMENT REGISTER PIN DATA REGISTER CHIP SEL BLOCK Figure 5-22 Chip-Select Circuit Block Diagram 5.9.1 Chip-Select Registers Each chip-select pin can have one or more functions. Chip-select pin assignment registers CSPAR[1:0] determine functions of the pins. Pin assignment registers also determine port size (8- or 16-bit) for dynamic bus allocation. A pin data register (PORTC) latches data for chip-select pins that are used for discrete output. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-63 Freescale Semiconductor, Inc. Blocks of addresses are assigned to each chip-select function. Block sizes of 2 Kbytes to 1 Mbyte can be selected by writing values to the appropriate base address register (CSBAR[10:0] and CSBARBT). However, because the logic state of ADDR20 is always the same as the state of ADDR19 in the MCU, the largest usable block size is 512 Kbytes. Multiple chip-selects assigned to the same block of addresses must have the same number of wait states. Chip-select option registers (CSORBT and CSOR[0:10]) determine timing of and conditions for assertion of chip-select signals. Eight parameters, including operating mode, access size, synchronization, and wait state insertion can be specified. Initialization software usually resides in a peripheral memory device controlled by the chip-select circuits. A set of special chip-select functions and registers (CSORBT and CSBARBT) is provided to support bootstrap operation. Freescale Semiconductor, Inc... Comprehensive address maps and register diagrams are provided in APPENDIX D REGISTER SUMMARY. 5.9.1.1 Chip-Select Pin Assignment Registers The pin assignment registers contain twelve 2-bit fields that determine the functions of the chip-select pins. Each pin has two or three possible functions, as shown in Table 5-22. Table 5-22 Chip-Select Pin Functions Chip-Select CSBOOT CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 Alternate Function CSBOOT BR BG BGACK FC0 FC1 FC2 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 Discrete Output — — — — PC0 PC1 PC2 PC3 PC4 PC5 PC6 ECLK Table 5-23 shows pin assignment field encoding. Pins that have no discrete output function must not use the %00 encoding as this will cause the alternate function to be selected. For instance, %00 for CS0/BR will cause the pin to perform the BR function. Table 5-23 Pin Assignment Field Encoding CSxPA[1:0] 00 01 10 11 Description Discrete output Alternate function Chip-select (8-bit port) Chip-select (16-bit port) SYSTEM INTEGRATION MODULE 5-64 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Port size determines the way in which bus transfers to an external address are allocated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip-select. Port size and transfer size affect how the chip-select signal is asserted. Refer to 5.9.1.3 Chip-Select Option Registers for more information. Out of reset, chip-select pin function is determined by the logic level on a corresponding data bus pin. The data bus pins have weak internal pull-up drivers, but can be held low by external devices. Refer to 5.7.3.1 Data Bus Mode Selection for more information. Either 16-bit chip-select function (%11) or alternate function (%01) can be selected during reset. All pins except the boot ROM select pin (CSBOOT) are disabled out of reset. There are twelve chip-select functions and only eight associated data bus pins. There is not a one-to-one correspondence. Refer to 5.9.4 Chip-Select Reset Operation for more detailed information. Freescale Semiconductor, Inc... The CSBOOT signal is enabled out of reset. The state of the DATA0 line during reset determines what port width CSBOOT uses. If DATA0 is held high (either by the weak internal pull-up driver or by an external pull-up device), 16-bit port size is selected. If DATA0 is held low, 8-bit port size is selected. A pin programmed as a discrete output drives an external signal to the value specified in the port C register. No discrete output function is available on CSBOOT, BR, BG, or BGACK. ADDR23 provides the ECLK output rather than a discrete output signal. When a pin is programmed for discrete output or alternate function, internal chip-select logic still functions and can be used to generate DSACK or AVEC internally on an address and control signal match. 5.9.1.2 Chip-Select Base Address Registers Each chip-select has an associated base address register. A base address is the lowest address in the block of addresses enabled by a chip-select. Block size is the extent of the address block above the base address. Block size is determined by the value contained in BLKSZ[2:0]. Multiple chip-selects assigned to the same block of addresses must have the same number of wait states. BLKSZ[2:0] determines which bits in the base address field are compared to corresponding bits on the address bus during an access. Provided other constraints determined by option register fields are also satisfied, when a match occurs, the associated chip-select signal is asserted. Table 5-24 shows BLKSZ[2:0] encoding. Table 5-24 Block Size Encoding BLKSZ[2:0] 000 001 010 011 100 101 110 111 Block Size 2 Kbytes 8 Kbytes 16 Kbytes 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes 512 Kbytes Address Lines Compared1 ADDR[23:11] ADDR[23:13] ADDR[23:14] ADDR[23:16] ADDR[23:17] ADDR[23:18] ADDR[23:19] ADDR[23:20] NOTES: 1. ADDR[23:20] are the same logic level as ADDR19 during normal operation. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-65 Freescale Semiconductor, Inc. The chip-select address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be an integer multiple of the block size. Because the logic state of ADDR[23:20] follows that of ADDR19 in the CPU16, maximum block size is 512 Kbytes, and addresses from $080000 to $F7FFFF are inaccessible. After reset, the MCU fetches the initialization routine from the address contained in the reset vector, located beginning at address $000000 of program space. To support bootstrap operation from reset, the base address field in the boot chip-select base address register (CSBARBT) has a reset value of $000, which corresponds to a base address of $000000 and a block size of 512 Kbytes. A memory device containing the reset vector and initialization routine can be automatically enabled by CSBOOT after a reset. Refer to 5.9.4 Chip-Select Reset Operation for more information. 5.9.1.3 Chip-Select Option Registers Option register fields determine timing of and conditions for assertion of chip-select signals. To assert a chip-select signal, and to provide DSACK or autovector support, other constraints set by fields in the option register and in the base address register must also be satisfied. The following paragraphs summarize option register functions. Refer to D.2.21 Chip-Select Option Registers for register and bit field information. The MODE bit determines whether chip-select assertion simulates an asynchronous bus cycle, or is synchronized to the M6800-type bus clock signal ECLK available on ADDR23. Refer to 5.3 System Clock for more information on ECLK. BYTE[1:0] controls bus allocation for chip-select transfers. Port size, set when a chipselect is enabled by a pin assignment register, affects signal assertion. When an 8-bit port is assigned, any BYTE field value other than %00 enables the chip-select signal. When a 16-bit port is assigned, however, BYTE field value determines when the chipselect is enabled. The BYTE fields for CS[10:0] are cleared during reset. However, both bits in the boot ROM chip-select option register (CSORBT) BYTE field are set (%11) when the RESET signal is released. R/W[1:0] causes a chip-select signal to be asserted only for a read, only for a write, or for both read and write. Use this field in conjunction with the STRB bit to generate asynchronous control signals for external devices. The STRB bit controls the timing of a chip-select assertion in asynchronous mode. Selecting address strobe causes a chip-select signal to be asserted synchronized with the address strobe. Selecting data strobe causes a chip-select signal to be asserted synchronized with the data strobe. This bit has no effect in synchronous mode. DSACK[3:0] specifies the source of DSACK in asynchronous mode. It also allows the user to optimize bus speed in a particular application by controlling the number of wait states that are inserted. NOTE The external DSACK pins are always active. SYSTEM INTEGRATION MODULE 5-66 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SPACE[1:0] determines the address space in which a chip-select is asserted. An access must have the space type represented by the SPACE[1:0] encoding in order for a chip-select signal to be asserted. IPL[2:0] contains an interrupt priority mask that is used when chip-select logic is set to trigger on external interrupt acknowledge cycles. When SPACE[1:0] is set to %00 (CPU space), interrupt priority (ADDR[3:1]) is compared to the IPL field. If the values are the same, and other option register constraints are satisfied, a chip-select signal is asserted. This field only affects the response of chip-selects and does not affect interrupt recognition by the CPU. Encoding %000 in the IPL field causes a chip-select signal to be asserted regardless of interrupt acknowledge cycle priority, provided all other constraints are met. Freescale Semiconductor, Inc... The AVEC bit is used to make a chip-select respond to an interrupt acknowledge cycle. If the AVEC bit is set, an autovector will be selected for the particular external interrupt being serviced. If AVEC is zero, the interrupt acknowledge cycle will be terminated with DSACK, and an external vector number must be supplied by an external device. 5.9.1.4 PORTC Data Register The PORTC data register latches data for PORTC pins programmed as discrete outputs. When a pin is assigned as a discrete output, the value in this register appears at the output. PC[6:0] correspond to CS[9:3]. Bit 7 is not used. Writing to this bit has no effect, and it always reads zero. 5.9.2 Chip-Select Operation When the MCU makes an access, enabled chip-select circuits compare the following items: • Function codes to SPACE fields, and to the IP mask if the SPACE field encoding is not for CPU space. • Appropriate address bus bits to base address fields. • Read/write status to R/W fields. • ADDR0 and/or SIZ[1:0] bits to BYTE field (16-bit ports only). • Priority of the interrupt being acknowledged (ADDR[3:1]) to IPL fields (when the access is an interrupt acknowledge cycle). When a match occurs, the chip-select signal is asserted. Assertion occurs at the same time as AS or DS assertion in asynchronous mode. Assertion is synchronized with ECLK in synchronous mode. In asynchronous mode, the value of the DSACK field determines whether DSACK is generated internally. DSACK[3:0] also determines the number of wait states inserted before internal DSACK assertion. The speed of an external device determines whether internal wait states are needed. Normally, wait states are inserted into the bus cycle during S3 until a peripheral asserts DSACK. If a peripheral does not generate DSACK, internal DSACK generation must be selected and a predetermined number of wait states can be programmed into the chip-select option register. Refer to the SIM Reference Manual (SIMRM/AD) for further information. M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-67 Freescale Semiconductor, Inc. 5.9.3 Using Chip-Select Signals for Interrupt Acknowledge Ordinary bus cycles use supervisor or user space access, but interrupt acknowledge bus cycles use CPU space access. Refer to 5.6.4 CPU Space Cycles and 5.8 Interrupts for more information. There are no differences in flow for chip selects in each type of space, but base and option registers must be properly programmed for each type of external bus cycle. During a CPU space cycle, bits [15:3] of the appropriate base register must be configured to match ADDR[23:11], as the address is compared to an address generated by the CPU. ADDR[23:20] follow the state of ADDR19 in this MCU. The states of base register bits [15:12] must match that of bit 11. Figure 5-23 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0] are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority, and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge code. The rest of the address lines are set to one. FUNCTION CODE 2 0 111 ADDRESS BUS Freescale Semiconductor, Inc... INTERRUPT ACKNOWLEDGE 0 23 19 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1 CPU SPACE TYPE FIELD CPU SPACE IACK TIM Figure 5-23 CPU Space Encoding for Interrupt Acknowledge Because address match logic functions only after the EBI transfers an interrupt acknowledge cycle to the external address bus following IARB contention, chip-select logic generates AVEC or DSACK signals only in response to interrupt requests from external IRQ pins. If an internal module makes an interrupt request of a certain priority, and the chip-select base address and option registers are programmed to generate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level, chip-select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a vector number and generates an internal DSACK signal to terminate the cycle. Perform the following operations before using a chip select to generate an interrupt acknowledge signal. 1. Program the base address field to all ones. 2. Program block size to no more than 64 Kbytes, so that the address comparator checks ADDR[19:16] against the corresponding bits in the base address register. (The CPU16 places the CPU space bus cycle type on ADDR[19:16].) 3. Set the R/W field to read only. An interrupt acknowledge cycle is performed as a read cycle. SYSTEM INTEGRATION MODULE 5-68 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 4. Set the BYTE field to lower byte when using a 16-bit port, as the external vector for a 16-bit port is fetched from the lower byte. Set the BYTE field to upper byte when using an 8-bit port. If an interrupting device does not provide a vector number, an autovector acknowledge must be generated, either by asserting the AVEC pin or by generating AVEC internally using the chip-select option register. This terminates the bus cycle. 5.9.4 Chip-Select Reset Operation The least significant bit of each of the 2-bit chip-select pin assignment fields in CSPAR0 and CSPAR1 each have a reset value of one. The reset values of the most significant bits of each field are determined by the states of DATA[7:1] during reset. There are weak internal pull-up drivers for each of the data lines so that chip-select operation is selected by default out of reset. However, the internal pull-up drivers can be overcome by bus loading effects. To ensure a particular configuration out of reset, use an active device to put the data lines in a known state during reset. The base address fields in chip-select base address registers CSBAR[0:10] and chip-select option registers CSOR[0:10] have the reset values shown in Table 5-25. The BYTE fields of CSOR[0:10] have a reset value of “disable”, so that a chip-select signal cannot be asserted until the base and option registers are initialized. Table 5-25 Chip-Select Base and Option Register Reset Values Fields Base address Block size Async/sync mode Upper/lower byte Read/write AS/DS DSACK Address space IPL Autovector Reset Values $000000 2 Kbyte Asynchronous mode Disabled Disabled AS No wait states CPU space Any level External interrupt vector Freescale Semiconductor, Inc... Following reset, the MCU fetches the initial stack pointer and program counter values from the exception vector table, beginning at $000000 in supervisor program space. The CSBOOT chip-select signal is used to select an external boot device mapped to a base address of $000000. The MSB of the CSBTPA field in CSPAR0 has a reset value of one, so that chip-select function is selected by default out of reset. The BYTE field in chip-select option register CSORBT has a reset value of “both bytes” so that the select signal is enabled out of reset. The LSB of the CSBOOT field, determined by the logic level of DATA0 during reset, selects the boot ROM port size. When DATA0 is held low during reset, port size is eight bits. When DATA0 is held high during reset, port size is 16 bits. DATA0 has a weak internal pull-up driver, so that a 16-bit port is selected by default M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-69 Freescale Semiconductor, Inc. However, the internal pull-up driver can be overcome by bus loading effects. To ensure a particular configuration out of reset, use an active device to put DATA0 in a known state during reset. The base address field in the boot chip-select base address register CSBARBT has a reset value of all zeros, so that when the initial access to address $000000 is made, an address match occurs, and the CSBOOT signal is asserted. The block size field in CSBARBT has a reset value of 512 Kbytes. Table 5-26 shows CSBOOT reset values. Table 5-26 CSBOOT Base and Option Register Reset Values Fields Base address Block size Async/sync mode Upper/lower byte Read/write AS/DS DSACK Address space IPL1 Autovector Reset Values $000000 512 Kbyte Asynchronous mode Both bytes Read/write AS 13 wait states Supervisor space Any level Interrupt vector externally Freescale Semiconductor, Inc... NOTES: 1. These fields are not used unless “Address space” is set to CPU space. 5.10 Parallel Input/Output Ports Sixteen SIM pins can be configured for general-purpose discrete input and output. Although these pins are organized into two ports, port E and port F, function assignment is by individual pin. PE3 is not connected to a pin. PE3 returns zero when read and writes have no effect. Pin assignment registers, data direction registers, and data registers are used to implement discrete I/O. 5.10.1 Pin Assignment Registers Bits in the port E and port F pin assignment registers (PEPAR and PFPAR) control the functions of the pins on each port. Any bit set to one defines the corresponding pin as a bus control signal. Any bit cleared to zero defines the corresponding pin as an I/O pin. PEPA3 returns one when read, and writes have no effect. 5.10.2 Data Direction Registers Bits in the port E and port F data direction registers (DDRE and DDRF) control the direction of the pin drivers when the pins are configured as I/O. Any bit in a register set to one configures the corresponding pin as an output. Any bit in a register cleared to zero configures the corresponding pin as an input. These registers can be read or written at any time. DDE3 returns zero when read. Writes have no effect. SYSTEM INTEGRATION MODULE 5-70 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 5.10.3 Data Registers A write to the port E and port F data registers (PORTE[0:1] and PORTF[0:1]) is stored in an internal data latch, and if any pin in the corresponding port is configured as an output, the value stored for that bit is driven out on the pin. A read of a data register returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the register. Both data registers can be accessed in two locations and can be read or written at any time. 5.11 Factory Test The test submodule supports scan-based testing of the various MCU modules. It is integrated into the SIM to support production test. Test submodule registers are intended for Freescale use only. Register names and addresses are provided in APPENDIX D REGISTER SUMMARY to show the user that these addresses are occupied. The QUOT pin is also used for factory test. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 5-71 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SYSTEM INTEGRATION MODULE 5-72 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 6 STANDBY RAM MODULE The standby RAM (SRAM) module consists of a fixed-location control register block and an array of fast (two clock) static RAM that may be mapped to a user specified location in the system memory map. Array size depends on the M68HC16, M68CK16, and M68CM16 Z-series version. Refer to Table 6-1 for appropriate SRAM array size. The SRAM is especially useful for system stacks and variable storage. Table 6-1 SRAM Configuration Freescale Semiconductor, Inc... Z-Series Device MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z4 MC68CK16Z4 MC68HC16Z2 MC68HC16Z3 Array Size 1 Kbyte 2 Kbytes 4 Kbytes The SRAM can be mapped to any address that is a multiple of the array size so long as SRAM boundaries do not overlap the module control registers (overlap makes the registers inaccessible). Data can be read/written in bytes, words or long words. SRAM is powered by VDD in normal operation. During power-down, SRAM contents can be maintained by power from the VSTBY input. Power switching between sources is automatic. 6.1 SRAM Register Block There are four SRAM control registers: the RAM module configuration register (RAMMCR), the RAM test register (RAMTST), and the RAM array base address registers (RAMBAH/RAMBAL). The module mapping bit (MM) in the SIM configuration register (SIMCR) defines the most significant bit (ADDR23) of the IMB address for each M68HC16, M68CK16, and M68CM16 Z-series module. Because ADDR[23:20] are driven to the same value as ADDR19, MM must be set to one. If MM is cleared, IMB modules are inaccessible. For more information about how the state of MM affects the system, refer to 5.2.1 Module Mapping. The SRAM control register consists of eight bytes, but not all locations are implemented. Unimplemented register addresses are read as zeros, and writes have no effect. Refer to D.3 Standby RAM Module for the register block address map and register bit/field definitions. M68HC16 Z SERIES USER’S MANUAL STANDBY RAM MODULE For More Information On This Product, Go to: www.freescale.com 6-1 Freescale Semiconductor, Inc. 6.2 SRAM Array Address Mapping Base address registers RAMBAH and RAMBAL are used to specify the SRAM array base address in the memory map. RAMBAH and RAMBAL can only be written while the SRAM is in low-power stop mode (RAMMCR STOP = 1) and the base address lock (RAMMCR RLCK = 0) is disabled. RLCK can be written once only to a value of one; subsequent writes are ignored. This prevents accidental remapping of the array. NOTE In the CPU16, ADDR[23:20] follow the logic state of ADDR19. The SRAM array must not be mapped to addresses $080000–$7FFFFF, which are inaccessible to the CPU16. If mapped to these addresses, the array remains inaccessible until a reset occurs, or it is remapped outside of this range. Freescale Semiconductor, Inc... 6.3 SRAM Array Address Space Type The RASP[1:0] in RAMMCR determine the SRAM array address space type. The SRAM module can respond to both program and data space accesses or to program space accesses only. Because the CPU16 operates in supervisor mode only, RASP1 has no effect. Table 6-2 shows RASP[1:0] encodings. Table 6-2 SRAM Array Address Space Type RASP[1:0] X0 X1 Space Program and data accesses Program access only Refer to 5.5.1.7 Function Codes for more information concerning address space types and program/data space access. Refer to 4.6 Addressing Modes for more information on addressing modes. 6.4 Normal Access The array can be accessed by byte, word, or long word. A byte or aligned word access takes one bus cycle or two system clocks. A long word or misaligned word access requires two bus cycles. Refer to 5.6 Bus Operation for more information concerning access times. 6.5 Standby and Low-Power Stop Operation Standby and low-power modes should not be confused. Standby mode maintains the RAM array when the main MCU power supply is turned off. Low-power stop mode allows the CPU16 to control MCU power consumption by disabling unused modules. Relative voltage levels of the MCU VDD and VSTBY pins determine whether the SRAM is in standby mode. SRAM circuitry switches to the standby power source when VDD drops below specified limits. If specified standby supply voltage levels are maintained during the transition, there is no loss of memory when switching occurs. The RAM array cannot be accessed while the SRAM module is powered from VSTBY. If standby operation is not desired, connect the VSTBY pin to VSS. STANDBY RAM MODULE 6-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. ISB (SRAM standby current) values may vary while VDD transitions occur. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for standby switching and power consumption specifications. 6.6 Reset Reset places the SRAM in low-power stop mode, enables program space access, and clears the base address registers and the register lock bit. These actions make it possible to write a new base address into the ROMBAH and ROMBAL registers. When a synchronous reset occurs while a byte or word SRAM access is in progress, the access is completed. If reset occurs during the first word access of a long-word operation, only the first word access is completed. If reset occurs during the second word access of a long-word operation, the entire access is completed. Data being read from or written to the RAM may be corrupted by an asynchronous reset. For more information, refer to 5.7 Reset. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL STANDBY RAM MODULE For More Information On This Product, Go to: www.freescale.com 6-3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... STANDBY RAM MODULE 6-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 7 MASKED ROM MODULE The masked ROM module (MRM) is only available with the MC68HC16Z2 and the MC68HC16Z3. The MRM consists of a fixed-location control register block and an 8Kbyte mask-programmed read-only memory array that can be mapped to any 8-Kbyte boundary in the system memory map. The MRM can be programmed to insert wait states to match slower external development memory. Access time depends upon the number of wait states specified, but can be as fast as two clock cycles. The MRM can be used for program accesses only, or for program and data accesses. Data can be read in bytes, words or long words. The MRM can be configured to support system bootstrap during reset. 7.1 MRM Register Block There are three MRM control registers: the masked ROM module configuration register (MRMCR), and the ROM array base address registers (ROMBAH and ROMBAL). In addition, the MRM register block contains the signature registers (RSIGHI and RSIGLO), and ROM bootstrap words (ROMBS[0:3]). The module mapping bit (MM) in the SIM configuration register (SIMCR) defines the most significant bit (ADDR23) of the IMB address for each M68HC16, M68CK16, and M68CM16 Z-series module. Because ADDR[23:20] are driven to the same value as ADDR19, MM must be set to one. If MM is cleared, IMB modules are inaccessible. For more information about how the state of MM affects the system, refer to 5.2.1 Module Mapping. The MRM control register block consists of 32 bytes, but not all locations are implemented. Unimplemented register addresses are read as zeros, and writes have no effect. Refer to D.4 Masked ROM Module for the register block address map and register bit/field definitions. 7.2 MRM Array Address Mapping Base address registers ROMBAH and ROMBAL are used to specify the ROM array base address in the memory map. Although the base address loaded into ROMBAH and ROMBAL during reset is mask-programmed as user-specified, these registers can be written after reset to change the default array address if the base address lock bit (LOCK in MRMCR) is not masked to a value of one. NOTE In the CPU16, ADDR[23:20] follow the logic state of ADDR19. The MRM array must not be mapped to addresses $7FF000–$7FFFFF, which are inaccessible to the CPU16. If mapped to these addresses, the array remains inaccessible until a reset occurs, or it is remapped outside of this range. M68HC16 Z SERIES USER’S MANUAL MASKED ROM MODULE For More Information On This Product, Go to: www.freescale.com 7-1 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. The MRM array can be mapped to any 8-Kbyte boundary in the memory map, but must not overlap other module control registers (overlap makes the registers inaccessible). If the array overlaps the MRM register block, addresses in the register block are accessed instead of the corresponding ROM array addresses. ROMBAH and ROMBAL can only be written while the ROM is in low-power stop mode (MRMCR STOP = 1) and the base address lock (MRMCR LOCK = 0) is disabled. LOCK can be written once only to a value of one; subsequent writes are ignored. This prevents accidental remapping of the array. 7.3 MRM Array Address Space Type ASPC[1:0] in MRMCR determines ROM array address space type. The module can respond to both program and data space accesses or to program space accesses only. The default value of ASPC[1:0] is established during mask programming, but the value can be changed after reset if the LOCK bit in the MRMCR has not been masked to a value of one. Because the CPU16 operates in supervisor mode only, ASPC1 has no effect. Table 7-1 shows ASPC[1:0] field encodings. Table 7-1 ROM Array Space Field ASPC[1:0] X0 X1 State Specified Program and data accesses Program access only Freescale Semiconductor, Inc... Refer to 5.5.1.7 Function Codes for more information concerning address space types and program/data space access. Refer to 4.6 Addressing Modes for more information on addressing modes. 7.4 Normal Access The array can be accessed by byte, word, or long word. A byte or aligned word access takes a minimum of one bus cycle (two system clocks). A long word or misaligned word access requires a minimum of two bus cycles. Access time can be optimized for a particular application by inserting wait states into each access. The number of wait states inserted is determined by the value of WAIT[1:0] in the MRMCR. Two, three, four, or five clock accesses can be specified. The default value WAIT[1:0] is established during mask programming, but field value can be changed after reset if the LOCK bit in the MRMCR has not been masked to a value of one. Table 7-2 shows WAIT[1:0] field encodings. MASKED ROM MODULE 7-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 7-2 Wait States Field WAIT[1:0] 00 01 10 11 Number of Wait States 0 1 2 –1 Clocks per Transfer 3 4 5 2 Refer to 5.6 Bus Operation for more information concerning access times. 7.5 Low-Power Stop Mode Operation Low-power stop mode minimizes MCU power consumption. Setting the STOP bit in MRMCR places the MRM in low-power stop mode. In low-power stop mode, the array cannot be accessed. The reset state of STOP is the complement of the logic state of DATA14 during reset. Low-power stop mode is exited by clearing STOP. 7.6 ROM Signature Signature registers RSIGHI and RSIGLO contain a user-specified mask-programmed signature pattern. A user-specified signature algorithm provides the capability to verify ROM array contents. 7.7 Reset The state of the MRM following reset is determined by the default values programmed into the MRMCR BOOT, LOCK, ASPC[1:0], and WAIT[1:0] bits. The default array base address is determined by the values programmed into ROMBAL and ROMBAH. When the mask programmed value of the MRMCR BOOT bit is zero, the contents of MRM bootstrap words ROMBS[0:3] are used as reset vectors. When the mask programmed value of the MRMCR BOOT bit is one, reset vectors are fetched from external memory, and system integration module chip-select logic is used to assert the boot ROM select signal CSBOOT. Refer to 5.9.4 Chip-Select Reset Operation for more information concerning external boot ROM selection. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL MASKED ROM MODULE For More Information On This Product, Go to: www.freescale.com 7-3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MASKED ROM MODULE 7-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 8 ANALOG-TO-DIGITAL CONVERTER This section is an overview of the analog-to-digital converter module (ADC). Refer to the ADC Reference Manual (ADCRM/AD) for a comprehensive discussion of ADC capabilities. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for ADC timing and electrical specifications. Refer to D.5 Analog-to-Digital Converter Module for register address mapping and bit/field definitions. 8.1 General The ADC is a unipolar, successive-approximation converter with eight modes of operation. It has selectable 8- or 10-bit resolution. Monotonicity is guaranteed in both modes. A bus interface unit handles communication between the ADC and other microcontroller modules, and supplies IMB timing signals to the ADC. Special operating modes and test functions are controlled by a module configuration register (ADCMCR) and a factory test register (ADCTST). ADC module conversion functions can be grouped into three basic subsystems: an analog front end, a digital control section, and result storage. Figure 8-1 is a functional block diagram of the ADC module. In addition to use as multiplexer inputs, the eight analog inputs can be used as a general-purpose digital input port (port ADA), provided signals are within logic level specification. A port data register (PORTADA) is used to access input data. 8.2 External Connections The ADC uses 12 pins on the MCU package. Eight pins are analog inputs (which can also be used as digital inputs), two pins are dedicated analog reference connections (VRH and VRL), and two pins are analog supply connections (VDDA and VSSA). Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-1 Freescale Semiconductor, Inc. VDDA VSSA SUPPLY VRH VRL REFERENCE RC DAC ARRAY AND COMPARATOR ANALOG MUX AND SAMPLE BUFFER AMP RESERVED RESERVED RESERVED RESERVED V RH V RL (V RH –VRL)/2 RESERVED PORT ADA DATA REGISTER SAR MODE AND TIMING CONTROL AN7/PADA7 AN6/PADA6 AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 RESULT 0 RESULT 1 RESULT 2 RESULT 3 RESULT 4 RESULT 5 RESULT 6 RESULT 7 INTERNAL CONNECTIONS Freescale Semiconductor, Inc... CLK SELECT/ PRESCALE ADC BUS INTERFACE UNIT INTERMODULE BUS (IMB) 16 ADC BLOCK 2 Figure 8-1 ADC Block Diagram 8.2.1 Analog Input Pins Each of the eight analog input pins (AN[7:0]) is connected to a multiplexer in the ADC. The multiplexer selects an analog input for conversion to digital data. Analog input pins can also be read as digital inputs, provided the applied voltage meets VIH and VIL specifications. When used as digital inputs, the pins are organized into an 8-bit port (PORTADA), and referred to as PADA[7:0]. There is no data direction register because port pins are input only. ANALOG-TO-DIGITAL CONVERTER 8-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 8.2.2 Analog Reference Pins Separate high (VRH) and low (VRL) analog reference voltages are connected to the analog reference pins. The pins permit connection of regulated and filtered supplies that allow the ADC to achieve its highest degree of accuracy. 8.2.3 Analog Supply Pins Pins VDDA and VSSA supply power to analog circuitry associated with the RC DAC. Other circuitry in the ADC is powered from the digital power bus (pins VDDI and VSSI). Dedicated analog power supplies are necessary to isolate sensitive ADC circuitry from noise on the digital power bus. 8.3 Programmer’s Model The ADC module is mapped into 32 words of address space. Five words are control/ status registers, one word is digital port data, and 24 words provide access to the results of AD conversion (eight addresses for each type of converted data). Two words are reserved for expansion. The ADC module base address is determined by the value of the MM bit in the SIM configuration register (SIMCR). The base address is normally $FFF700. Internally, the ADC has both a differential data bus and a buffered IMB data bus. Registers not directly associated with conversion functions, such as the configuration register, the test register, and the port data register, reside on the buffered bus, while conversion registers and result registers reside on the differential bus. Registers that reside on the buffered bus are updated immediately when written. However, writes to ADC control registers abort any conversion in progress. 8.4 ADC Bus Interface Unit The ADC is designed to act as a slave device on the intermodule bus. The ADC bus interface unit (ABIU) provides IMB bus cycle termination and synchronizes internal ADC signals with IMB signals. The ABIU also manages data bus routing to accommodate the three conversion data formats, and controls the interface to the module differential data bus. 8.5 Special Operating Modes Low-power stop mode and freeze mode are ADC operating modes associated with assertion of IMB signals by other microcontroller modules or by external sources. These modes are controlled by the values of bits in the ADC module configuration register (ADCMCR). 8.5.1 Low-Power Stop Mode When the STOP bit in ADCMCR is set, the IMB clock signal to the ADC is disabled. This places the module in an idle state, and power consumption is minimized. The ABIU does not shut down and ADC registers are still accessible. If a conversion is in progress when STOP is set, it is aborted. M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-3 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. STOP is set during system reset, and must be cleared before the ADC can be used. Because analog circuit bias currents are turned off during low-power stop mode, the ADC requires recovery time after STOP is cleared. Execution of the CPU16 LPSTOP command places the entire modular microcontroller in low-power stop mode. Refer to 5.3.4 Low-Power Operation for more information. 8.5.2 Freeze Mode When the CPU16 in the modular microcontroller enters background debug mode, the FREEZE signal is asserted. The type of response is determined by the value of the FRZ[1:0] field in the ADCMCR. Table 8-1 shows the different ADC responses to FREEZE assertion. Freescale Semiconductor, Inc... Table 8-1 FRZ Field Selection FRZ[1:0] 00 01 10 11 Reserved Finish conversion in process, then freeze Freeze immediately Response Ignore FREEZE, continue conversions When the ADC freezes, the ADC clock stops and all sequential activity ceases. Contents of control and status registers remain valid while frozen. When the FREEZE signal is negated, ADC activity resumes. If the ADC freezes during a conversion, activity resumes with the next step in the conversion sequence. However, capacitors in the analog conversion circuitry discharge while the ADC is frozen; as a result, the conversion will be inaccurate. Refer to 4.14.4 Background Debug Mode for more information. 8.6 Analog Subsystem The analog subsystem consists of a multiplexer, sample capacitors, a buffer amplifier, an RC DAC array, and a high-gain comparator. Comparator output sequences the successive approximation register (SAR). The interface between the comparator and the SAR is the boundary between ADC analog and digital subsystems. 8.6.1 Multiplexer The multiplexer selects one of 16 sources for conversion. Eight sources are internal and eight are external. Multiplexer operation is controlled by channel selection field CD:CA in register ADCTL1. Table 8-2 shows the different multiplexer channel sources. The multiplexer contains positive and negative stress protection circuitry. This circuitry prevents voltages on other input channels from affecting the current conversion. ANALOG-TO-DIGITAL CONVERTER 8-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 8-2 Multiplexer Channel Sources [CD:CA] Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Input Source AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH VRL (VRH – VRL) / 2 Test/Reserved Freescale Semiconductor, Inc... 1010 1011 1100 1101 1110 1111 8.6.2 Sample Capacitor and Buffer Amplifier Each of the eight external input channels is associated with a sample capacitor and share a single sample buffer amplifier. After a conversion is initiated, the multiplexer output is connected to the sample capacitor at the input of the sample buffer amplifier for the first two ADC clock cycles of the sampling period. The sample amplifier buffers the input channel from the relatively large capacitance of the RC DAC array. During the second two clock cycles of a sampling period, the sample capacitor is disconnected from the multiplexer, and the sample buffer amplifier charges the RC DAC array with the value stored in the sample capacitor. During the third portion of a sampling period, both sample capacitor and buffer amplifier are bypassed, and multiplexer input charges the DAC array directly. The length of this third portion of a sampling period is determined by the value of the STS field in ADCTL0. 8.6.3 RC DAC Array The RC DAC array consists of binary-weighted capacitors and a resistor-divider chain. The array performs two functions: it acts as a sample hold circuit during conversion, and it provides each successive digital-to-analog comparison voltage to the comparator. Conversion begins with MSB comparison and ends with LSB comparison. Array switching is controlled by the digital subsystem. M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-5 Freescale Semiconductor, Inc. 8.6.4 Comparator The comparator indicates whether each approximation output from the RC DAC array during resolution is higher or lower than the sampled input voltage. Comparator output is fed to the digital control logic, which sets or clears each bit in the successive approximation register in sequence, MSB first. 8.7 Digital Control Subsystem The digital control subsystem includes control and status registers, clock and prescaler control logic, channel and reference select logic, conversion sequence control logic, and the successive approximation register. The subsystem controls the multiplexer and the output of the RC array during sample and conversion periods, stores the results of comparison in the successive-approximation register, then transfers results to the result registers. 8.7.1 Control/Status Registers There are two control registers (ADCTL0, ADCTL1) and one status register (ADCSTAT). ADCTL0 controls conversion resolution, sample time, and clock/prescaler value. ADCTL1 controls analog input selection, conversion mode, and initiation of conversion. A write to ADCTL0 aborts the current conversion sequence and halts the ADC. Conversion must be restarted by writing to ADCTL1. A write to ADCTL1 aborts the current conversion sequence and starts a new sequence with parameters altered by the write. ADCSTAT shows conversion sequence status, conversion channel status, and conversion completion status. The following paragraphs are a general discussion of control function. D.5 Analog-toDigital Converter Module shows the ADC address map and discusses register bits and fields. 8.7.2 Clock and Prescaler Control The ADC clock is derived from the system clock by a programmable prescaler. ADC clock period is determined by the value of the PRS field in ADCTL0. The prescaler has two stages. The first stage is a 5-bit modulus counter. It divides the system clock by any value from two to 32 (PRS[4:0] = %00000 to %11111). The second stage is a divide-by-two circuit. Table 8-3 shows prescaler output values. Freescale Semiconductor, Inc... ANALOG-TO-DIGITAL CONVERTER 8-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 8-3 Prescaler Output PRS[4:0] %00000 %00001 %00010 %00011 … %11101 %11110 %11111 ADC Clock Reserved System Clock/4 System Clock/6 System Clock/8 … System Clock/60 System Clock/62 System Clock/64 Minimum System Clock — 2.0 MHz 3.0 MHz 4.0 MHz … 30.0 MHz 31.0 MHz 32.0 MHz Maximum System Clock — 8.4 MHz 12.6 MHz 16.8 MHz … — — — Freescale Semiconductor, Inc... ADC clock speed must be between 0.5 MHz and 2.1 MHz. The reset value of the PRS field is %00011, which divides a nominal 16.78 MHz system clock by eight, yielding maximum ADC clock frequency. There are a minimum of four IMB clock cycles for each ADC clock cycle. 8.7.3 Sample Time The first two portions of all sample periods require four ADC clock cycles. During the third portion of a sample period, the selected channel is connected directly to the RC DAC array for a specified number of clock cycles. The value of the STS field in ADCTL0 determines the number of cycles. Refer to Table 8-4. The number of clock cycles required for a sample period is the value specified by STS plus four. Sample time is determined by PRS value. Table 8-4 TS Field Selection STS[1:0] 00 01 10 11 Sample Time 2 A/D clock periods 4 A/D clock periods 8 A/D clock periods 16 A/D clock periods 8.7.4 Resolution ADC resolution can be either eight or ten bits. Resolution is determined by the state of the RES10 bit in ADCTL0. Both 8-bit and 10-bit conversion results are automatically aligned in the result registers. 8.7.5 Conversion Control Logic Analog-to-digital conversions are performed in sequences. Sequences are initiated by any write to ADCTL1. If a conversion sequence is already in progress, a write to either control register will abort it and reset the SCF and CCF flags in the A/D status register. There are eight conversion modes. Conversion mode is determined by ADCTL1 control bits. Each conversion mode affects the bits in status register ADCSTAT differently. Result storage differs from mode to mode. M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-7 Freescale Semiconductor, Inc. 8.7.5.1 Conversion Parameters Table 8-5 describes the conversion parameters controlled by bits in ADCTL1. Table 8-5 Conversion Parameters Controlled by ADCTL1 Conversion Parameter Conversion channel Description The value of the channel selection field (CD:CA) in ADCTL1 determines which multiplexer inputs are used in a conversion sequence. There are 16 possible inputs. Seven inputs are external pins (AN[6:0]), and nine are internal. A conversion sequence consists of either four or eight conversions. The number of conversions in a sequence is determined by the state of the S8CM bit in ADCTL1. Conversion can be limited to a single sequence or a sequence can be performed continuously. The state of the SCAN bit in ADCTL1 determines whether single or continuous conversion is performed. Conversion sequence(s) can be run on a single channel or on a block of four or eight channels. Channel conversion is controlled by the state of the MULT bit in ADCTL1. Length of sequence Single or continuous conversion Freescale Semiconductor, Inc... Single or multiple channel conversion 8.7.5.2 Conversion Modes Conversion modes are defined by the state of the SCAN, MULT, and S8CM bits in ADCTL1. Table 8-6 shows mode numbering. Table 8-6 ADC Conversion Modes SCAN 0 0 0 0 1 1 1 1 MULT 0 0 1 1 0 0 1 1 S8CM 0 1 0 1 0 1 0 1 Mode 0 1 2 3 4 5 6 7 The following paragraphs describe each type of conversion mode: Mode 0 — A single four-conversion sequence is performed on a single input channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the conversion sequence is complete. Mode 1 — A single eight-conversion sequence is performed on a single input channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the conversion sequence is complete. ANALOG-TO-DIGITAL CONVERTER 8-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Mode 2 — A single conversion is performed on each of four sequential input channels, starting with the channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the last conversion is complete. Mode 3 — A single conversion is performed on each of eight sequential input channels, starting with the channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the last conversion is complete. Mode 4 — Continuous four-conversion sequences are performed on a single input channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT3). Previous results are overwritten when a sequence repeats. The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the first four-conversion sequence is complete. Mode 5 — Continuous eight-conversion sequences are performed on a single input channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT7). Previous results are overwritten when a sequence repeats. The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the first eight-conversion sequence is complete. Mode 6 — Continuous conversions are performed on each of four sequential input channels, starting with the channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the first four-conversion sequence is complete. Mode 7 — Continuous conversions are performed on each of eight sequential input channels, starting with the channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the first eight-conversion sequence is complete. Table 8-7 is a summary of ADC operation when MULT is cleared (single-channel modes). Table 8-8 is a summary of ADC operation when MULT is set (multi-channel modes). Number of conversions per channel is determined by SCAN. Channel numbers are given in order of conversion. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-9 Freescale Semiconductor, Inc. Table 8-7 Single-Channel Conversions (MULT = 0) S8CM 0 0 0 0 0 0 0 0 0 0 CD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH VRL (VRH – VRL) / 2 Test/Reserved AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH VRL (VRH – VRL) / 2 Test/Reserved Result Register1 RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] Freescale Semiconductor, Inc... 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES: 1. Result register (RSLT) is either RJURRX, LJSRRX, or LJURRX, depending on the address read. ANALOG-TO-DIGITAL CONVERTER 8-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 8-8 Multiple-Channel Conversions (MULT = 1) S8CM 0 CD 0 CC 0 CB X CA X Input AN0 AN1 AN2 AN3 0 0 1 X X AN4 AN5 AN6 AN7 0 1 0 X X Reserved Reserved Reserved Reserved 0 1 1 X X VRH VRL (VRH – VRL) / 2 Test/Reserved 1 0 X X X AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 1 1 X X X Reserved Reserved Reserved Reserved VRH VRL (VRH – VRL) / 2 Test/Reserved Result Register1 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT4 RSLT5 RSLT6 RSLT7 RSLT0 RSLT1 RSLT2 RSLT3 RSLT4 RSLT5 RSLT6 RSLT7 Freescale Semiconductor, Inc... NOTES: 1. Result register (RSLT) is either RJURRX, LJSRRX, or LJURRX, depending on the address read. M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-11 Freescale Semiconductor, Inc. 8.7.6 Conversion Timing Total conversion time is made up of initial sample time, transfer time, final sample time, and resolution time. Initial sample time is the time during which a selected input channel is connected to the sample buffer amplifier through a sample capacitor. During transfer time, the sample capacitor is disconnected from the multiplexer, and the RC DAC array is driven by the sample buffer amp. During final sampling time, the sample capacitor and amplifier are bypassed, and the multiplexer input charges the RC DAC array directly. During resolution time, the voltage in the RC DAC array is converted to a digital value, and the value is stored in the SAR. Initial sample time and transfer time are fixed at two ADC clock cycles each. Final sample time can be 2, 4, 8, or 16 ADC clock cycles, depending on the value of the STS field in ADCTL0. Resolution time is ten cycles for 8-bit conversion and twelve cycles for 10-bit conversion. Transfer and resolution require a minimum of 16 ADC clocks (8 µs with a 2.1 MHz ADC clock) for 8-bit resolution or 18 ADC clocks (9 µs with a 2.1 MHz ADC clock) for 10-bit resolution. If maximum final sample time (16 ADC clocks) is used, total conversion time is 15 µs for an 8-bit conversion or 16 µs for a 10-bit conversion (with a 2.1 MHz ADC clock). Figures 8-2 and 8-3 illustrate the timing for 8- and 10-bit conversions, respectively. These diagrams assume a final sampling period of two ADC clocks. TRANSFER CONVERSION TO RESULT REGISTER AND SET CCF RESOLUTION TIME Freescale Semiconductor, Inc... INITIAL SAMPLE TIME TRANSFER TIME FINAL SAMPLE TIME (2 ADC CLOCKS) 1 2 CYCLES SAR7 16 1 1 1 1 1 1 1 1 CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SAR0 EOC 6 CYCLES SAMPLE AND TRANSFER PERIOD SUCCESSIVE APPROXIMATION SEQUENCE END CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 CH 8 SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 4-CHANNEL MODE SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 8-CHANNEL MODE 16 ADC 8-BIT TIM 1 Figure 8-2 8-Bit Conversion Timing ANALOG-TO-DIGITAL CONVERTER 8-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. INITIAL SAMPLE TIME TRANSFER TIME FINAL SAMPLE TIME (2 ADC CLOCKS) TRANSFER CONVERSION TO RESULT REGISTER AND SET CCF RESOLUTION TIME 1 2 CYCLES SAR9 16 1 1 1 1 1 1 1 1 1 1 CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SAR0 EOC 6 CYCLES SAMPLE AND TRANSFER PERIOD SUCCESSIVE APPROXIMATION SEQUENCE END Freescale Semiconductor, Inc... CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 CH 8 SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 4-CHANNEL MODE SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 8-CHANNEL MODE 16 ADC 10-BIT TIM Figure 8-3 10-Bit Conversion Timing 8.7.7 Successive Approximation Register The successive approximation register (SAR) accumulates the result of each conversion one bit at a time, starting with the most significant bit. At the start of the resolution period, the MSB of the SAR is set, and all less significant bits are cleared. Depending on the result of the first comparison, the MSB is either left set or cleared. Each successive bit is set or left cleared in descending order until all eight or ten bits have been resolved. When conversion is complete, the content of the SAR is transferred to the appropriate result register. Refer to APPENDIX D REGISTER SUMMARY for register mapping and configuration. 8.7.8 Result Registers Result registers are used to store data after conversion is complete. The registers can be accessed from the IMB under ABIU control. Each register can be read from three different addresses in the ADC memory map. The format of the result data depends on the address from which it is read. Table 8-9 shows the three types of formats. M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-13 Freescale Semiconductor, Inc. Table 8-9 Result Register Formats Result Data Format Unsigned right-justified format Description Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution, bits [7:0] are used for 8-bit conversion (bits [9:8] are zero). Bits [15:10] always return zero when read. Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution, bits [15:8] are used for 8-bit conversion (bits [7:6] are zero). Although the ADC is unipolar, it is assumed that the zero point is (VRH – VRL) / 2 when this format is used. The value read from the register is an offset two’s-complement number; for positive input, bit 15 equals zero, for negative input, bit 15 equals one. Bits [5:0] always return zero when read. Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolution, bits [15:8] are used for 8-bit conversion (bits [7:6] are zero). Bits [5:0] always return zero when read. Signed left-justified format Unsigned left-justified format Freescale Semiconductor, Inc... Refer to APPENDIX D REGISTER SUMMARY for register mapping and configuration. 8.8 Pin Considerations The ADC requires accurate, noise-free input signals for proper operation. The following sections discuss the design of external circuitry to maximize ADC performance. 8.8.1 Analog Reference Pins No A/D converter can be more accurate than its analog reference. Any noise in the reference can result in at least that much error in a conversion. The reference for the ADC, supplied by pins VRH and VRL, should be low-pass filtered from its source to obtain a noise-free, clean signal. In many cases, simple capacitive bypassing may suffice. In extreme cases, inductors or ferrite beads may be necessary if noise or RF energy is present. Series resistance is not advisable since there is an effective DC current requirement from the reference voltage by the internal resistor string in the RC DAC array. External resistance may introduce error in this architecture under certain conditions. Any series devices in the filter network should contain a minimum amount of DC resistance. For accurate conversion results, the analog reference voltages must be within the limits defined by VDDA and VSSA, as explained in the following subsection. 8.8.2 Analog Power Pins The analog supply pins (VDDA and VSSA) define the limits of the analog reference voltages (VRH and VRL) and of the analog multiplexer inputs. Figure 8-4 is a diagram of the analog input circuitry. ANALOG-TO-DIGITAL CONVERTER 8-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. VDDA VRH SAMPLE AMP 8 CHANNELS TOTAL1 RC DAC ARRAY COMPARATOR Freescale Semiconductor, Inc... REF 1 VSSA VRL REF 2 NOTES: 1. TWO SAMPLE AMPS EXIST ON THE ADC WITH EIGHT CHANNELS ON EACH SAMPLE AMP. ADC 8CH SAMPLE AMP Figure 8-4 Analog Input Circuitry Since the sample amplifier is powered by VDDA and VSSA, it can accurately transfer input signal levels up to but not exceeding VDDA and down to but not below VSSA. If the input signal is outside of this range, the output from the sample amplifier is clipped. In addition, VRH and VRL must be within the range defined by VDDA and VSSA. As long as VRH is less than or equal to VDDA, and VRL is greater than or equal to VSSA, and the sample amplifier has accurately transferred the input signal, resolution is ratiometric within the limits defined by VRL and VRH. If VRH is greater than VDDA, the sample amplifier can never transfer a full-scale value. If VRL is less than VSSA, the sample amplifier can never transfer a zero value. Figure 8-5 shows the results of reference voltages outside the range defined by VDDA and VSSA. At the top of the input signal range, VDDA is 10 mV lower than VRH. This results in a maximum obtainable 10-bit conversion value of 3FE. At the bottom of the signal range, VSSA is 15 mV higher than VRL, resulting in a minimum obtainable 10-bit conversion value of three. M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-15 Freescale Semiconductor, Inc. 3FF 3FE 3FD 3FC 3FB 10-BIT RESULT 3FA 8 7 6 Freescale Semiconductor, Inc... 5 4 3 2 1 0 .010 .020 .030 5.100 5.110 5.120 INPUT IN VOLTS (VRH = 5.120 V, VRL = 0 V) 5.130 ADC CLIPPING Figure 8-5 Errors Resulting from Clipping 8.8.3 Analog Supply Filtering and Grounding Two important factors influencing performance in analog integrated circuits are supply filtering and grounding. Generally, digital circuits use bypass capacitors on every VDD/ VSS pin pair. This applies to analog subsystems or submodules also. Equally important as bypassing is the distribution of power and ground. Analog supplies should be isolated from digital supplies as much as possible. This necessity stems from the higher performance requirements often associated with analog circuits. Therefore, deriving an analog supply from a local digital supply is not recommended. However, if for economic reasons digital and analog power are derived from a common regulator, filtering of the analog power is recommended in addition to the bypassing of the supplies already mentioned. For example, an RC low-pass filter could be used to isolate the digital and analog supplies when generated by a common regulator. If multiple high precision analog circuits are locally employed (such as two A/D converters), the analog supplies should be isolated from each other, as sharing supplies introduces the potential for interference between analog circuits. ANALOG-TO-DIGITAL CONVERTER 8-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Grounding is the most important factor influencing analog circuit performance in mixed signal systems (or in stand-alone analog systems). Close attention must be paid to avoid introducing additional sources of noise into the analog circuitry. Common sources of noise include ground loops, inductive coupling, and combining digital and analog grounds together inappropriately. The problem of how and when to combine digital and analog grounds arises from the large transients which the digital ground must handle. If the digital ground is not able to handle the large transients, the current from the large transients can return to ground through the analog ground. It is the excess current overflowing into the analog ground which causes performance degradation by developing a differential voltage between the true analog ground and the microcontroller’s ground pin. The end result is that the ground observed by the analog circuit is no longer true ground and often ends in skewed results. Two similar approaches designed to improve or eliminate the problems associated with grounding excess transient currents involve star-point ground systems. One approach is to star-point the different grounds at the power supply origin, thus keeping the ground isolated. Refer to Figure 8-6. Freescale Semiconductor, Inc... ANALOG POWER SUPPLY DIGITAL POWER SUPPLY +5V AGND +5V PGND +5V VSSA VDDA VSS VDD VRH VRL ADC PCB ADC POWER SCHEM Figure 8-6 Star-Ground at the Point of Power Supply Origin Another approach is to star-point the different grounds near the analog ground pin on the microcontroller by using small traces for connecting the non-analog grounds to the analog ground. The small traces are meant only to accommodate DC differences, not AC transients. M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-17 Freescale Semiconductor, Inc. NOTE This star-point scheme still requires adequate grounding for digital and analog subsystems in addition to the star-point ground. Other suggestions for PCB layout in which the ADC is employed include the following: • The analog ground must be low impedance to all analog ground points in the circuit. • Bypass capacitors should be as close to the power pins as possible. • The analog ground should be isolated from the digital ground. This can be done by cutting a separate ground plane for the analog ground. • Non-minimum traces should be utilized for connecting bypass capacitors and filters to their corresponding ground/power points. • Minimum distance for trace runs when possible. 8.8.4 Accommodating Positive/Negative Stress Conditions Positive or negative stress refers to conditions which exceed nominally defined operating limits. Examples include applying a voltage exceeding the normal limit on an input (for example, voltages outside of the suggested supply/reference ranges) or causing currents into or out of the pin which exceed normal limits. ADC specific considerations are voltages greater than VDDA, VRH or less than VSSA applied to an analog input which cause excessive currents into or out of the input. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS on exact magnitudes. Both stress conditions can potentially disrupt conversion results on neighboring inputs. Parasitic devices, associated with CMOS processes, can cause an immediate disruptive influence on neighboring pins. Common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal tied to substrate (VSSI/VSSA ground). Under stress conditions, current introduced on an adjacent pin can cause errors on adjacent channels by developing a voltage drop across the adjacent external channel source impedances. Figure 8-7 shows an active parasitic bipolar when an input pin is subjected to negative stress conditions. Positive stress conditions do not activate a similar parasitic device. NEGATIVE STRESS VOLTAGE + VDD RADJACENT Freescale Semiconductor, Inc... RSTRESS IOUT 10K IIN PIN UNDER STRESS PARASITIC DEVICE ADJACENT PINS ADC PAR STRESS CONN Figure 8-7 Input Pin Subjected to Negative Stress ANALOG-TO-DIGITAL CONVERTER 8-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. The current out of the pin (IOUT) under negative stress is determined by the following equation: V STRESS – V BE I OUT = -----------------------------------------R STRESS where: VSTRESS = Adjustable voltage source VBE = Parasitic bipolar base/emitter voltage (refer to VNEGCLAMP in APPENDIX A ELECTRICAL CHARACTERISTICS) RSTRESS = Source impedance (10K resistor in Figure 8-7 on stressed channel) Freescale Semiconductor, Inc... The current into (IIN) the neighboring pin is determined by the 1/KN (Gain) of the parasitic bipolar transistor (1/KN‹‹1). One way to minimize the impact of stress conditions on the ADC is to apply voltage limiting circuits such as diodes to supply and ground. However, leakage from such circuits and the potential influence on the sampled voltage to be converted must be considered. Refer to Figure 8-8. VDD kR EXTERNAL VOLTAGE R TO DEVICE VSS ADC NEG STRESS CONN Figure 8-8 Voltage Limiting Diodes in a Negative Stress Circuit Another method for minimizing the impact of stress conditions on the ADC is to strategically allocate ADC inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress conditions. Finally, suitable source impedances should be selected to meet design goals and minimize the effect of stress conditions. 8.8.5 Analog Input Considerations The source impedance of the analog signal to be measured and any intermediate filtering should be considered whether external multiplexing is used or not. Figure 8-9 shows the connection of eight typical analog signal sources to one ADC analog input pin through a separate multiplexer chip. Also, an example of an analog signal source connected directly to a ADC analog input channel is displayed. M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-19 Freescale Semiconductor, Inc. ANALOG SIGNAL SOURCE FILTERING AND INTERCONNECT R FILTER2 0.1 µF1 ~ ~ ~ Freescale Semiconductor, Inc... R SOURCE2 TYPICAL MUX CHIP (MC54HC4051, MC74HC4051, MC54HC4052, MC74HC4052, MC54HC4053, ETC.) INTERCONNECT ADC C SOURCE R SOURCE2 C FILTER R FILTER2 0.1 µF1 C MUXIN C SOURCE R SOURCE2 C FILTER R FILTER2 0.1 µF1 C MUXIN R MUXOUT C MUXIN C SOURCE ~ ~ ~ ~ ~ ~ R SOURCE2 C FILTER R FILTER2 0.1 µF1 C MUXOUT C MUXIN C IN C SAMPLE C SOURCE R SOURCE2 C FILTER R FILTER2 0.1 µF1 CIN = CIN + CSAMPLE C SOURCE R SOURCE2 C FILTER R FILTER2 0.1 µF1 C MUXIN C SOURCE R SOURCE2 C FILTER R FILTER2 0.1 µF1 C MUXIN C SOURCE R SOURCE2 C FILTER R FILTER2 0.1 µF1 C MUXIN C SOURCE C FILTER C MUXIN R SOURCE2 R FILTER2 0.1 µF1 C SOURCE C FILTER NOTES: 1. TYPICAL VALUE 2. RFILTER TYPICALLY 10KΩ–20KΩ. C IN C SAMPLE ADC EXT MUX EX Figure 8-9 External Multiplexing of Analog Signal Sources ANALOG-TO-DIGITAL CONVERTER 8-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 8.8.6 Analog Input Pins Analog inputs should have low AC impedance at the pins. Low AC impedance can be realized by placing a capacitor with good high frequency characteristics at the input pin of the part. Ideally, that capacitor should be as large as possible (within the practical range of capacitors that still have good high frequency characteristics). This capacitor has two effects. First, it helps attenuate any noise that may exist on the input. Second, it sources charge during the sample period when the analog signal source is a high-impedance source. Series resistance can be used with the capacitor on an input pin to implement a simple RC filter. The maximum level of filtering at the input pins is application dependent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input. Simple RC filtering at the pin may be limited by the source impedance of the transducer or circuit supplying the analog signal to be measured. Refer to 8.8.6.2 Error Resulting from Leakage. In some cases, the size of the capacitor at the pin may be very small. Figure 8-10 is a simplified model of an input channel. Refer to this model in the following discussion of the interaction between the user's external circuitry and the circuitry inside the ADC. Freescale Semiconductor, Inc... EXTERNAL CIRCUIT S1 RF INTERNAL CIRCUIT MODEL S2 AMP S3 S4 VSRC CF CS CDAC VI VSRC = SOURCE VOLTAGE RF = FILTER IMPEDANCE (SOURCE IMPEDANCE INCLUDED) CF = FILTER CAPACITOR CS = INTERNAL CAPACITANCE (FOR A BYPASSED CHANNEL, THIS IS THE CDAC CAPACITANCE) CDAC = DAC CAPACITOR ARRAY VI = INTERNAL VOLTAGE SOURCE FOR PRECHARGE (VDDA/2) ADC SAMPLE AMP MODEL Figure 8-10 Electrical Model of an A/D Input Pin M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-21 Freescale Semiconductor, Inc. In Figure 8-10, RF and CF comprise the user's external filter circuit. CS is the internal sample capacitor. Each channel has its own capacitor. CS is never precharged; it retains the value of the last sample. VI is an internal voltage source used to precharge the DAC capacitor array (CDAC) before each sample. The value of this supply is VDDA/ 2, or 2.5 volts for 5-volt operation. The following paragraphs provide a simplified description of the interaction between the ADC and the user's external circuitry. This circuitry is assumed to be a simple RC low-pass filter passing a signal from a source to the ADC input pin. The following simplifying assumptions are made: • The source impedance is included with the series resistor of the RC filter. • The external capacitor is perfect (no leakage, no significant dielectric absorption characteristics, etc.) • All parasitic capacitance associated with the input pin is included in the value of the external capacitor. • Inductance is ignored. • The “on” resistance of the internal switches is zero ohms and the “off” resistance is infinite. 8.8.6.1 Settling Time for the External Circuit The values for RF and CF in the user's external circuitry determine the length of time required to charge CF to the source voltage level (VSRC). At time t = 0, S1 in Figure 8-10 closes. S2 is open, disconnecting the internal circuitry from the external circuitry. Assume that the initial voltage across CF is zero. As CF charges, the voltage across it is determined by the following equation, where t is the total charge time: V CF = V SRC ( 1 – e –t ⁄ RF CF Freescale Semiconductor, Inc... ) When t = 0, the voltage across CF = 0. As t approaches infinity, VCF will equal VSRC. (This assumes no internal leakage.) With 10-bit resolution, 1/2 of a count is equal to 1/2048 full-scale value. Assuming worst case (VSRC = full scale), Table 8-10 shows the required time for CF to charge to within 1/2 of a count of the actual source voltage during 10-bit conversions. Table 8-10 is based on the RC network in Figure 8-10. NOTE The following times are completely independent of the A/D converter architecture (assuming the ADC is not affecting the charging). ANALOG-TO-DIGITAL CONVERTER 8-22 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 8-10 External Circuit Settling Time (10-Bit Conversions) Filter Capacitor (CF) 1 µF .1 µF .01 µF .001 µF 100 pF Source Resistance (RF) 100 Ω 760 µs 76 µs 7.6 µs 760 ns 76 ns 1 kΩ 7.6 ms 760 µs 76 µs 7.6 µs 760 ns 10 kΩ 76 ms 7.6 ms 760 µs 76 µs 7.6 µs 100 kΩ 760 ms 76 ms 7.6 ms 760 µs 76 µs The external circuit described in Table 8-10 is a low-pass filter. A user interested in measuring an AC component of the external signal must take the characteristics of this filter into account. Freescale Semiconductor, Inc... 8.8.6.2 Error Resulting from Leakage A series resistor limits the current to a pin, therefore input leakage acting through a large source impedance can degrade A/D accuracy. The maximum input leakage current is specified in APPENDIX A ELECTRICAL CHARACTERISTICS. Input leakage is greatest at high operating temperatures and as a general rule decreases by one half for each 10°C decrease in temperature. Assuming VRH – VRL = 5.12 V, 1 count (assuming 10-bit resolution) corresponds to 5 mV of input voltage. A typical input leakage of 50 nA acting through 100 kΩ of external series resistance results in an error of less than 1 count (5.0 mV). If the source impedance is 1 MΩ and a typical leakage of 50 nA is present, an error of 10 counts (50 mV) is introduced. In addition to internal junction leakage, external leakage (e.g., if external clamping diodes are used) and charge sharing effects with internal capacitors also contribute to the total leakage current. Table 8-11 illustrates the effect of different levels of total leakage on accuracy for different values of source impedance. The error is listed in terms of 10-bit counts. CAUTION Leakage from the part of 10 nA is obtainable only within a limited temperature range. Table 8-11 Error Resulting From Input Leakage (IOFF) Source Impedance 1 kΩ 10 kΩ 100 kΩ Leakage Value (10-Bit Conversions) 10 nA — — 0.2 counts 50 nA — 0.1 counts 1 count 100 nA — 0.2 counts 2 counts 1000 nA 0.2 counts 2 counts 20 counts M68HC16 Z SERIES USER’S MANUAL ANALOG-TO-DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com 8-23 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ANALOG-TO-DIGITAL CONVERTER 8-24 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 9 QUEUED SERIAL MODULE This section is an overview of the queued serial module (QSM). Refer to the QSM Reference Manual (QSMRM/AD) for complete information about the QSM. 9.1 General The QSM contains two serial interfaces: the queued serial peripheral interface (QSPI) and the serial communication interface (SCI). Figure 9-1 is a block diagram of the QSM. The QSM is present on the MC68HC16Z1, MC68CK16Z1, MC68CM16Z1, MC68HC16Z2, and MC68HC16Z3 microcontrollers. Freescale Semiconductor, Inc... QSPI MISO/PQS0 MOSI/PQS1 SCK/PQS2 PCS0/SS/PQS3 PCS1/PQS4 PCS2/PQS5 PCS3/PQS6 INTERFACE LOGIC PORT QS IMB TXD/PQS7 SCI RXD QSM BLOCK Figure 9-1 QSM Block Diagram The QSPI provides peripheral expansion or interprocessor communication through a full-duplex, synchronous, three-line bus. Four programmable peripheral chip-selects can select up to sixteen peripheral devices by using an external 1 of 16 line selector. A self-contained RAM queue allows up to sixteen serial transfers of eight to sixteen bits each or continuous transmission of up to a 256-bit data stream without CPU16 intervention. A special wrap-around mode supports continuous transmission/reception of data. M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-1 Freescale Semiconductor, Inc. The SCI provides a standard non-return to zero (NRZ) mark/space format. It operates in either full- or half-duplex mode. There are separate transmitter and receiver enable bits and dual data buffers. A modulus-type baud rate generator provides rates from 110 baud to 781 kbaud with a 25.17 MHz system clock. Word length of either eight or nine bits is software selectable. Optional parity generation and detection provide either even or odd parity check capability. Advanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. Wake-up functions allow the CPU16 to run uninterrupted until meaningful data is available. 9.2 QSM Registers and Address Map There are four types of QSM registers: QSM global registers, QSM pin control registers, QSPI registers, and SCI registers. Refer to 9.2.1 QSM Global Registers and 9.2.2 QSM Pin Control Registers for a discussion of global and pin control registers. Refer to 9.3.1 QSPI Registers and 9.4.1 SCI Registers for further information about QSPI and SCI registers. Writes to unimplemented register bits have no effect, and reads of unimplemented bits always return zero. Refer to D.6 Queued Serial Module for a QSM address map and register bit and field definitions. Refer to 5.2.1 Module Mapping for more information about how the state of MM affects the system. 9.2.1 QSM Global Registers The QSM configuration register (QSMCR) controls the interface between the QSM and the intermodule bus. The QSM test register (QTEST) is used during factory test of the QSM. The QSM interrupt level register (QILR) determines the priority of interrupts requested by the QSM and the vector used when an interrupt is acknowledged. The QSM interrupt vector register (QIVR) contains the interrupt vector for both QSM submodules. QILR and QIVR are 8-bit registers located at the same word address. 9.2.1.1 Low-Power Stop Mode Operation When the STOP bit in QSMCR is set, the system clock input to the QSM is disabled and the module enters low-power stop mode. QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is not readable in low-power stop mode. However, writes to RAM or any register are guaranteed valid while STOP is asserted. STOP can be set by the CPU16 and by reset. The QSPI and SCI must be brought to an orderly stop before asserting STOP to avoid data corruption. To accomplish this, disable QSM interrupts or set the interrupt priority level mask in the CPU16 condition code register to a value higher than the IRQ level requested by the QSM. The SCI receiver and transmitter should be disabled after transfers in progress are complete. The QSPI can be halted by setting the HALT bit in SPCR3 and then setting STOP after the HALTA flag is set. Refer to 5.3.4 Low-Power Operation for more information about low-power stop mode. Freescale Semiconductor, Inc... QUEUED SERIAL MODULE 9-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 9.2.1.2 Freeze Operation The freeze FRZ[1:0] bits in QSMCR are used to determine what action is taken by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the CPU16 enters background debug mode. At the present time, FRZ0 has no effect; setting FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE assertion. Refer to 4.14.4 Background Debug Mode for more information about background debug mode. 9.2.1.3 QSM Interrupts Both the QSPI and SCI can generate interrupt requests. Each has a separate interrupt request priority register. A single vector register is used to generate exception vector numbers. Freescale Semiconductor, Inc... The values of the ILQSPI and ILSCI fields in QILR determine the priority of QSPI and SCI interrupt requests. The values in these fields correspond to internal interrupt request signals IRQ[7:1]. A value of %111 causes IRQ7 to be asserted when a QSM interrupt request is made. Lower field values cause correspondingly lower-numbered interrupt request signals to be asserted. Setting the ILQSPI or ILSCI field values to %000 disables interrupts for the QSPI and the SCI respectively. If ILQSPI and ILSCI have the same non-zero value, and the QSPI and SCI make simultaneous interrupt requests, the QSPI has priority. When the CPU16 acknowledges an interrupt request, it places the value in the condition code register interrupt priority (IP) mask on ADDR[3:1]. The QSM compares the IP mask value to the priority of the interrupt request to determine whether it should contend for arbitration. QSM arbitration priority is determined by the value of the IARB field in QSMCR. Each module that can generate interrupt requests must have a nonzero IARB value, otherwise the CPU16 will identify any such interrupt requests as spurious and take a spurious interrupt exception. Arbitration is performed by means of serial contention between values stored in individual module IARB fields. When the QSM wins interrupt arbitration, it responds to the CPU16 interrupt acknowledge cycle by placing an interrupt vector number on the data bus. The vector number is used to calculate displacement into the CPU16 exception vector table. SCI and QSPI vector numbers are generated from the value in the QIVR INTV field. The values of bits INTV[7:1] are the same for both the QSPI and the SCI. The value of INTV0 is supplied by the QSM when an interrupt request is made. INTV0 = 0 for SCI interrupt requests; INTV0 = 1 for QSPI interrupt requests. At reset, INTV[7:0] is initialized to $0F, the uninitialized interrupt vector number. To enable interrupt-driven serial communication, a user-defined vector number must be written to QIVR, and interrupt handler routines must be located at the addresses pointed to by the corresponding vector. Writes to INTV0 have no effect. Reads of INTV0 return a value of one. Refer to SECTION 4 CENTRAL PROCESSOR UNIT and SECTION 5 SYSTEM INTEGRATION MODULE for more information about exceptions and interrupts. M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-3 Freescale Semiconductor, Inc. 9.2.2 QSM Pin Control Registers The QSM uses nine pins. Eight of the pins can be used for serial communication or for parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI. The port QS data direction register (DDRQS) determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function. DDQS7 determines the direction of the TXD pin only when the SCI transmitter is disabled. When the SCI transmitter is enabled, the TXD pin is an output. The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins defined as outputs. PORTQS reads return data present on the pins. To avoid driving undefined data, first write PORTQS, then configure DDRQS. PQSPAR and DDRQS are 8-bit registers located at the same word address. Refer to Table 9-1 for a summary of QSM pin functions. Table 9-1 Effect of DDRQS on QSM Pin Function QSM Pin MISO QSPI Mode Master Slave MOSI Master Slave SCK1 PCS0/SS Master Slave Master Slave PCS[1:3] Master Slave TXD2 RXD — — DDQS7 None DDQS[4:6] DDQS2 DDQS3 DDQS1 DDRQS Bit DDQS0 Bit State 0 1 0 1 0 1 0 1 — — 0 1 0 1 0 1 0 1 X NA Pin Function Serial data input to QSPI Disables data input Disables data output Serial data output from QSPI Disables data output Serial data output from QSPI Serial data input to QSPI Disables data input Clock output from QSPI Clock input to QSPI Assertion causes mode fault Chip-select output QSPI slave select input Disables slave select input Disables chip-select output Chip-select output Inactive Inactive Serial data output from SCI Serial data input to SCI Freescale Semiconductor, Inc... NOTES: 1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which case it becomes the QSPI serial clock SCK. 2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE set in SCCR1), in which case it becomes the SCI serial data output TXD. QUEUED SERIAL MODULE 9-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 9.3 Queued Serial Peripheral Interface The queued serial peripheral interface (QSPI) is used to communicate with external devices through a synchronous serial bus. The QSPI is fully compatible with SPI systems found on other Freescale products, but has enhanced capabilities. The QSPI can perform full duplex three-wire or half duplex two-wire transfers. A variety of transfer rates, clocking, and interrupt-driven communication options is available. Figure 9-2 displays a block diagram of the QSPI. QUEUE CONTROL BLOCK QUEUE POINTER 4 Freescale Semiconductor, Inc... COMPARATOR DONE 4 END QUEUE POINTER A D D R E S S R E G I S T E R 80-BYTE QSPI RAM CONTROL LOGIC STATUS REGISTER CONTROL REGISTERS 4 DELAY COUNTER 4 CHIP SELECT COMMAND MSB LSB 8/16-BIT SHIFT REGISTER PROGRAMMABLE LOGIC ARRAY Rx/Tx DATA REGISTER M S M S MOSI MISO PCS0/SS 2 BAUD RATE GENERATOR PCS[2:1] SCK QSPI BLOCK Figure 9-2 QSPI Block Diagram M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-5 Freescale Semiconductor, Inc. The serial transfer length is programmable from eight to sixteen bits, inclusive. An inter-transfer delay of 17 to 8192 system clocks can be specified (default is 17 system clocks). A dedicated 80-byte RAM is used to store received data, data to be transmitted, and a queue of commands. The CPU16 can access these locations directly. The command queue allows the QSPI to perform up to 16 serial transfers without CPU16 intervention. Each queue entry contains all the information needed by the QSPI to independently complete one serial transfer. A pointer identifies the queue location containing the data and command for the next serial transfer. Normally, the pointer address is incremented after each serial transfer, but the CPU16 can change the pointer value at any time. Support for multiple-tasks can be provided by segmenting the queue. The QSPI has four peripheral chip-select pins. The chip-select signals simplify interfacing by reducing CPU16 intervention. If the chip-select signals are externally decoded, 16 independent select signals can be generated. Wrap-around mode allows continuous execution of queued commands. In wraparound mode, newly received data replaces previously received data in the receive RAM. Wrap-around mode can simplify the interface with A/D converters by continuously updating conversion values stored in the RAM. Continuous transfer mode allows an uninterrupted bit stream of eight to 256 bits in length to be transferred without CPU16 intervention. Longer transfers are possible, but minimal intervention is required to prevent loss of data. A standard delay of 17 system clocks is inserted between the transfer of each queue entry. 9.3.1 QSPI Registers The programmer’s model for the QSPI consists of the QSM global and pin control registers, four QSPI control registers (SPCR[0:3]), the status register (SPSR), and the 80byte QSPI RAM. Registers and RAM can be read and written by the CPU16. Refer to D.6 Queued Serial Module for register bit and field definitions. 9.3.1.1 Control Registers Control registers contain parameters for configuring the QSPI and enabling various modes of operation. The CPU16 has read and write access to all control registers. The QSM has read access only to all bits except the SPE bit in SPCR1. Control registers must be initialized before the QSPI is enabled to ensure proper operation. SPCR1 must be written last because it contains the QSPI enable bit (SPE). Writing a new value to any control register except SPCR2 while the QSPI is enabled disrupts operation. SPCR2 is buffered. New SPCR2 values become effective after completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location. Reads of SPCR2 return the current value of the register, not of the buffer. Writing the same value into any control register except SPCR2 while the QSPI is enabled has no effect on QSPI operation. QUEUED SERIAL MODULE 9-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 9.3.1.2 Status Register SPSR contains information concerning the current serial transmission. Only the QSPI can set the bits in this register. The CPU16 reads SPSR to obtain QSPI status information and writes SPSR to clear status flags. 9.3.2 QSPI RAM The QSPI contains an 80-byte block of dual-ported static RAM that can be accessed by both the QSPI and the CPU16. The RAM is divided into three segments: receive data RAM, transmit data RAM, and command data RAM. Receive data is information received from a serial device external to the MCU. Transmit data is information stored for transmission to an external device. Command control data defines transfer parameters. Refer to Figure 9-3, which shows RAM organization. Freescale Semiconductor, Inc... 500 RR0 RR1 RR2 RECEIVE RAM RRD RRE RRF WORD 520 TR0 TR1 TR2 TRANSMIT RAM TRD TRE TRF WORD 540 CR0 CR1 CR2 COMMAND RAM CRD CRE CRF BYTE 51E 53E 54F QSPI RAM MAP Figure 9-3 QSPI RAM 9.3.2.1 Receive RAM Data received by the QSPI is stored in this segment to be read by the CPU16. Data stored in the receive RAM is right-justified. Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry. The CPU16 can access the data using byte, word, or long-word transfers. The CPTQP value in SPSR shows which queue entries have been executed. The CPU16 can use this information to determine which locations in receive RAM contain valid data before reading them. 9.3.2.2 Transmit RAM Data that is to be transmitted by the QSPI is stored in this segment and must be written by the CPU16 in right-justified form. The QSPI cannot modify information in the transmit RAM. The QSPI copies the information to its data serializer for transmission. Information remains in the transmit RAM until overwritten. M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-7 Freescale Semiconductor, Inc. 9.3.2.3 Command RAM Command RAM is used by the QSPI in master mode. The CPU16 writes one byte of control information to this segment for each QSPI command to be executed. The QSPI cannot modify information in command RAM. Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer. The command control field provides transfer options. A maximum of 16 commands can be in the queue. Queue execution by the QSPI proceeds from the address in NEWQP through the address in ENDQP (both of these fields are in SPCR2). 9.3.3 QSPI Pins The QSPI uses seven pins. These pins can be configured for general-purpose I/O when not needed for QSPI application. Table 9-2 shows QSPI input and output pins and their functions. Table 9-2 QSPI Pins Pin Names Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Slave Select Mnemonics MISO MOSI SCK PCS[3:1] PCS0/SS Mode Master Slave Master Slave Master Slave Master Master Master Slave Function Serial data input to QSPI Serial data output from QSPI Serial data output from QSPI Serial data input to QSPI Clock output from QSPI Clock input to QSPI Select peripherals Selects peripherals Causes mode fault Initiates serial transfer Freescale Semiconductor, Inc... 9.3.4 QSPI Operation The QSPI uses a dedicated 80-byte block of static RAM accessible by both the QSPI and the CPU16 to perform queued operations. The RAM is divided into three segments. There are 16 command bytes, 16 transmit data words, and 16 receive data words. QSPI RAM is organized so that one byte of command data, one word of transmit data, and one word of receive data correspond to one queue entry, $0–$F. The CPU16 initiates QSPI operation by setting up a queue of QSPI commands in command RAM, writing transmit data into transmit RAM, then enabling the QSPI. The QSPI executes the queued commands, sets a completion flag (SPIF), and then either interrupts the CPU16 or waits for intervention. There are four queue pointers. The CPU16 can access three of them through fields in QSPI registers. The new queue pointer (NEWQP), contained in SPCR2, points to the first command in the queue. An internal queue pointer points to the command currently being executed. The completed queue pointer (CPTQP), contained in SPSR, points to the last command executed. The end queue pointer (ENDQP), contained in SPCR2, points to the final command in the queue. QUEUED SERIAL MODULE 9-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. The internal pointer is initialized to the same value as NEWQP. During normal operation, the command pointed to by the internal pointer is executed, the value in the internal pointer is copied into CPTQP, the internal pointer is incremented, and then the sequence repeats. Execution continues at the internal pointer address unless the NEWQP value is changed. After each command is executed, ENDQP and CPTQP are compared. When a match occurs, the SPIF flag is set and the QSPI stops and clears SPE, unless wrap-around mode is enabled. At reset, NEWQP is initialized to $0. When the QSPI is enabled, execution begins at queue address $0 unless another value has been written into NEWQP. ENDQP is initialized to $0 at reset, but should be changed to show the last queue entry before the QSPI is enabled. NEWQP and ENDQP can be written at any time. When NEWQP changes, the internal pointer value also changes. However, if NEWQP is written while a transfer is in progress, the transfer is completed normally. Leaving NEWQP and ENDQP set to $0 transfers only the data in transmit RAM location $0. 9.3.5 QSPI Operating Modes The QSPI operates in either master or slave mode. Master mode is used when the MCU initiates data transfers. Slave mode is used when an external device initiates transfers. Switching between these modes is controlled by MSTR in SPCR0. Before entering either mode, the appropriate QSM and QSPI registers must be initialized properly. In master mode, the QSPI executes a queue of commands defined by control bits in each command RAM queue entry. Chip-select pins are activated, data is transmitted from the transmit RAM and received by the receive RAM. In slave mode, operation proceeds in response to SS pin activation by an external SPI bus master. Operation is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred is controlled in a different manner. When the QSPI is selected, it automatically executes the next queue transfer to exchange data with the external device correctly. Although the QSPI inherently supports multi-master operation, no special arbitration mechanism is provided. A mode fault flag (MODF) indicates a request for SPI master arbitration. System software must provide arbitration. Note that unlike previous SPI systems, MSTR is not cleared by a mode fault being set nor are the QSPI pin output drivers disabled. The QSPI and associated output drivers must be disabled by clearing SPE in SPCR1. Figure 9-4 shows QSPI initialization. Figures 9-5 through 9-9 show QSPI master and slave operation. The CPU16 must initialize the QSM global and pin registers and the QSPI control registers before enabling the QSPI for either mode of operation. The command queue must be written before the QSPI is enabled for master mode operation. Any data to be transmitted should be written into transmit RAM before the QSPI is enabled. During wrap-around operation, data for subsequent transmissions can be written at any time. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-9 Freescale Semiconductor, Inc. BEGIN INITIALIZE QSM GLOBAL REGISTERS INITIALIZE PQSPAR, PORTQS, AND DDRQS IN THIS ORDER Freescale Semiconductor, Inc... QSPI INITIALIZATION INITIALIZE QSPI CONTROL REGISTERS INITIALIZE QSPI RAM ENABLE QSPI Y MSTR = 1 ? N A2 A1 QSPI FLOW 1 Figure 9-4 Flowchart of QSPI Initialization Operation QUEUED SERIAL MODULE 9-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (MASTER MODE) A1 IS QSPI DISABLED N Y HAS NEWQP BEEN WRITTEN Y WORKING QUEUE POINTER CHANGED TO NEWQP Freescale Semiconductor, Inc... N READ COMMAND CONTROL AND TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS ASSERT PERIPHERAL CHIP-SELECT(S) IS PCS TO SCK DELAY PROGRAMMED N Y EXECUTE PROGRAMMED DELAY EXECUTE STANDARD DELAY EXECUTE SERIAL TRANSFER STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS B1 QSPI FLOW 2 Figure 9-5 Flowchart of QSPI Master Operation (Part 1) M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-11 Freescale Semiconductor, Inc. B1 WRITE QUEUE POINTER TO CPTQP STATUS BITS IS CONTINUE BIT ASSERTED N Y Freescale Semiconductor, Inc... NEGATE PERIPHERAL CHIP-SELECT(S) IS DELAY AFTER TRANSFER ASSERTED N EXECUTE STANDARD DELAY Y EXECUTE PROGRAMMED DELAY C1 QSPI MSTR2 FLOW 3 Figure 9-6 Flowchart of QSPI Master Operation (Part 2) QUEUED SERIAL MODULE 9-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. C1 IS THIS THE LAST COMMAND IN THE QUEUE N Y ASSERT SPIF STATUS FLAG IS INTERRUPT ENABLE BIT SPIFIE ASSERTED N Y REQUEST INTERRUPT Freescale Semiconductor, Inc... INCREMENT WORKING QUEUE POINTER IS WRAP ENABLE BIT ASSERTED N DISABLE QSPI Y RESET WORKING QUEUE POINTER TO NEWQP OR $0000 A1 IS HALT OR FREEZE ASSERTED N Y HALT QSPI AND ASSERT HALTA IS INTERRUPT ENABLE BIT HMIE ASSERTED N Y REQUEST INTERRUPT IS HALT OR FREEZE ASSERTED N A1 Y QSPI MSTR3 FLOW 4 Figure 9-7 Flowchart of QSPI Master Operation (Part 3) M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-13 Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (SLAVE MODE) A2 IS QSPI DISABLED N Y HAS NEWQP BEEN WRITTEN Y QUEUE POINTER CHANGED TO NEWQP Freescale Semiconductor, Inc... N READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS IS SLAVE SELECT PIN ASSERTED N Y EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS WRITE QUEUE POINTER TO CPTQP STATUS BITS B2 QSPI SLV1 FLOW 5 Figure 9-8 Flowchart of QSPI Slave Operation (Part 1) QUEUED SERIAL MODULE 9-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. C2 IS THIS THE LAST COMMAND IN THE QUEUE N Y ASSERT SPIF STATUS FLAG IS INTERRUPT ENABLE BIT SPIFIE ASSERTED N Y REQUEST INTERRUPT Freescale Semiconductor, Inc... INCREMENT WORKING QUEUE POINTER IS WRAP ENABLE BIT ASSERTED N DISABLE QSPI Y RESET WORKING QUEUE POINTER TO NEWQP OR $0000 A2 IS HALT OR FREEZE ASSERTED N Y HALT QSPI AND ASSERT HALTA IS INTERRUPT ENABLE BIT HMIE ASSERTED N Y REQUEST INTERRUPT IS HALT OR FREEZE ASSERTED N A2 Y QSPI SLV2 FLOW 6 Figure 9-9 Flowchart of QSPI Slave Operation (Part 2) M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-15 Freescale Semiconductor, Inc. Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus master supplies the clock signal SCK to time the transfer of data. Four possible combinations of clock phase and polarity can be specified by the CPHA and CPOL bits in SPCR0. Data is transferred with the most significant bit first. The number of bits transferred per command defaults to eight, but can be set to any value from eight to sixteen bits inclusive by writing a value into the BITS[3:0] field in SPCR0 and setting BITSE in the command RAM. Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the system. If needed, the WOMQ bit in SPCR0 can be set to provide wired-OR, opendrain outputs. An external pull-up resistor should be used on each output line. WOMQ affects all QSPI pins regardless of whether they are assigned to the QSPI or used as general-purpose I/O. 9.3.5.1 Master Mode Setting the MSTR bit in SPCR0 selects master mode operation. In master mode, the QSPI can initiate serial transfers, but cannot respond to externally initiated transfers. When the slave select input of a device configured for master mode is asserted, a mode fault occurs. Before QSPI operation begins, QSM register PQSPAR must be written to assign the necessary pins to the QSPI. The pins necessary for master mode operation are MISO, MOSI, SCK, and one or more of the chip-select pins. MISO is used for serial data input in master mode, and MOSI is used for serial data output. Either or both may be necessary, depending on the particular application. SCK is the serial clock output in master mode and must be assigned to the QSPI for proper operation. The PORTQS data register must next be written with values that make the PQS2/SCK and PQS[6:3]/PCS[3:0] outputs inactive when the QSPI completes a series of transfers. Pins allocated to the QSPI by PQSPAR are controlled by PORTQS when the QSPI is inactive. PORTQS I/O pins driven to states opposite those of the inactive QSPI signals can generate glitches that momentarily enable or partially clock a slave device. For example, if a slave device operates with an inactive SCK state of logic one (CPOL = 1) and uses active low peripheral chip-select PCS0, the PQS[3:2] bits in PORTQS must be set to %11. If PQS[3:2] = %00, falling edges will appear on PQS2/SCK and PQS3/PCS0 as the QSPI relinquishes control of these pins and PORTQS drives them to logic zero from the inactive SCK and PCS0 states of logic one. Before master mode operation is initiated, QSM register DDRQS is written last to direct the data flow on the QSPI pins used. Configure the SCK, MOSI and appropriate chip-select pins PCS[3:0] as outputs. The MISO pin must be configured as an input. After pins are assigned and configured, write appropriate data to the command queue. If data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers as appropriate. QUEUED SERIAL MODULE 9-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Data transfer is synchronized with the internally-generated serial clock SCK. Control bits, CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of CPHA and CPOL determine upon which SCK edge to drive outgoing data from the MOSI pin and to latch incoming data from the MISO pin. Baud rate is selected by writing a value from two to 255 into SPBR[7:0] in SPCR0. The QSPI uses a modulus counter to derive the SCK baud rate from the MCU system clock. The following expressions apply to the SCK baud rate: f sys SCK Baud Rate = -----------------------------------2 × SPBR[7:0] Freescale Semiconductor, Inc... or f sys SPBR[7:0] = ------------------------------------------------------------------------2 × SCK Baud Rate Desired Giving SPBR[7:0] a value of zero or one disables the baud rate generator and SCK assumes its inactive state. The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or user-specified (DSCK = 1) delay from chip-select assertion until the leading edge of the serial clock. The DSCKL field in SPCR1 determines the length of the user-defined delay before the assertion of SCK. The following expression determines the actual delay before SCK: DSCKL[6:0] PCS to SCK Delay = -----------------------------f sys where DSCKL[6:0] equals {1, 2, 3,..., 127}. When DSCK equals zero, DSCKL[6:0] is not used. Instead, the PCS valid-to-SCK transition is one-half the SCK period. There are two transfer length options. The user can choose a default value of eight bits, or a programmed value from eight to sixteen bits, inclusive. The programmed value must be written into BITS[3:0] in SPCR0. The BITSE bit in each command RAM byte determines whether the default value (BITSE = 0) or the BITS[3:0] value (BITSE = 1) is used. Table 9-3 shows BITS[3:0] encoding. M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-17 Freescale Semiconductor, Inc. Table 9-3 Bits Per Transfer BITS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 8 9 10 11 12 13 14 15 Freescale Semiconductor, Inc... Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. Writing a value to DTL[7:0] in SPCR1 specifies a delay period. The DT bit in each command RAM byte determines whether the standard delay period (DT = 0) or the user-specified delay period (DT = 1) is used. The following expression is used to calculate the delay: 32 × DTL[7:0] Delay after Transfer = ----------------------------------- if DT = 1 f sys where DTL equals {1, 2, 3,..., 255}. A zero value for DTL[7:0] causes a delay-after-transfer value of 8192/fsys. 17 Standard Delay after Transfer = -------- if DT = 0 f sys Adequate delay between transfers must be specified for long data streams because the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay between successive transfers. If the system clock is operating at a slower rate, the delay between transfers must be increased proportionately. QUEUED SERIAL MODULE 9-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. QSPI operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set, the QSPI executes the command at the command RAM address pointed to by NEWQP. Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is simultaneously received is stored at the pointer address in receive RAM. When the proper number of bits have been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working queue pointer, and loads the next data for transfer from transmit RAM. The command pointed to by the incremented working queue pointer is executed next, unless a new value has been written to NEWQP. If a new queue pointer value is written while a transfer is in progress, that transfer is completed normally. Freescale Semiconductor, Inc... When the CONT bit in a command RAM byte is set, PCS pins are continuously driven to specified states during and between transfers. If the chip-select pattern changes during or between transfers, the original pattern is driven until execution of the following transfer begins. When CONT is cleared, the data in register PORTQS is driven between transfers. The data in PORTQS must match the inactive states of SCK and any peripheral chip-selects used. When the QSPI reaches the end of the queue, it sets the SPIF flag. SPIF is set during the final transfer before it is complete. If the SPIFIE bit in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wrap-around mode is enabled. 9.3.5.2 Master Wrap-Around Mode Wrap-around mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address $0 or to the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2. In wrap-around mode, the QSPI cycles through the queue continuously, even while the QSPI is requesting interrupt service. SPE is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in receive RAM. Each time the end of the queue is reached, the SPIF flag is set. SPIF is not automatically reset. If interrupt-driven QSPI service is used, the service routine must clear the SPIF bit to end the current interrupt request. Additional interrupt requests during servicing can be prevented by clearing SPIFIE, but SPIFIE is buffered. Clearing it does not end the current request. Wrap-around mode is exited by clearing the WREN bit or by setting the HALT bit in SPCR3. Exiting wrap-around mode by clearing SPE is not recommended, as clearing SPE may abort a serial transfer in progress. The QSPI sets SPIF, clears SPE, and stops the first time it reaches the end of the queue after WREN is cleared. After HALT is set, the QSPI finishes the current transfer, then stops executing commands. After the QSPI stops, SPE can be cleared. M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-19 Freescale Semiconductor, Inc. 9.3.5.3 Slave Mode Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the QSPI is unable to initiate serial transfers. Transfers are initiated by an external SPI bus master. Slave mode is typically used on a multi-master SPI bus. Only one device can be bus master (operate in master mode) at any given time. Before QSPI operation is initiated, QSM register PQSPAR must be written to assign necessary pins to the QSPI. The pins necessary for slave mode operation are MISO, MOSI, SCK, and PCS0/SS. MISO is used for serial data output in slave mode, and MOSI is used for serial data input. Either or both may be necessary, depending on the particular application. SCK is the serial clock input in slave mode and must be assigned to the QSPI for proper operation. Assertion of the active-low slave select signal (SS) initiates slave mode operation. Freescale Semiconductor, Inc... Before slave mode operation is initiated, DDRQS must be written to direct data flow on the QSPI pins used. Configure the MOSI, SCK and PCS0/SS pins as inputs. The MISO pin must be configured as an output. After pins are assigned and configured, write data to be transmitted into transmit RAM. Command RAM is not used in slave mode, and does not need to be initialized. Set the queue pointers, as appropriate. When SPE is set and MSTR is clear, a low state on the slave select PCS0/SS pin begins slave mode operation at the address indicated by NEWQP. Data that is received is stored at the pointer address in receive RAM. Data is simultaneously loaded into the data serializer from the pointer address in transmit RAM and transmitted. Transfer is synchronized with the externally generated SCK. The CPHA and CPOL bits determine upon which SCK edge to latch incoming data from the MISO pin and to drive outgoing data from the MOSI pin. Because the command RAM is not used in slave mode, the CONT, BITSE, DT, DSCK, and peripheral chip-select bits have no effect. The PCS0/SS pin is used only as an input. The SPBR, DT and DSCKL fields in SPCR0 and SPCR1 bits are not used in slave mode. The QSPI drives neither the clock nor the chip-select pins and thus cannot control clock rate or transfer delay. Because the BITSE option is not available in slave mode, the BITS field in SPCR0 specifies the number of bits to be transferred for all transfers in the queue. When the number of bits designated by BITS[3:0] has been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working queue pointer, and loads new transmit data from transmit RAM into the data serializer. The working queue pointer address is used the next time PCS0/SS is asserted, unless the CPU16 writes to NEWQP first. The QSPI shifts one bit for each pulse of SCK until the slave select input goes high. If SS goes high before the number of bits specified by the BITS field is transferred, the QSPI resumes operation at the same pointer address the next time SS is asserted. The maximum value that the BITS field can have is 16. If more than 16 bits are transmitted before SS is negated, pointers are incremented and operation continues. QUEUED SERIAL MODULE 9-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. The QSPI transmits as many bits as it receives at each queue address, until the BITS[3:0] value is reached or SS is negated. SS does not need to go high between transfers as the QSPI transfers data until reaching the end of the queue, whether SS remains low or is toggled between transfers. When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wrap-around mode is enabled. 9.3.5.4 Slave Wrap-Around Mode Slave wrap-around mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address $0 or to the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2. Slave wrap-around operation is identical to master wrap-around operation. 9.3.6 Peripheral Chip Selects Peripheral chip-select signals are used to select an external device for serial data transfer. Chip-select signals are asserted when a command in the queue is executed. Signals are asserted at a logic level corresponding to the value of the PCS[3:0] bits in each command byte. More than one chip-select signal can be asserted at a time, and more than one external device can be connected to each PCS pin, provided proper fanout is observed. PCS0 shares a pin with the slave select (SS) signal, which initiates slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault occurs. To configure a peripheral chip-select, set the appropriate bit in PQSPAR, then configure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value of the bit in PORTQS that corresponds to the chip-select pin determines the base state of the chip-select signal. If base state is zero, chip-select assertion must be active high (PCS bit in command RAM must be set); if base state is one, assertion must be active low (PCS bit in command RAM must be cleared). PORTQS bits are cleared during reset. If no new data is written to PORTQS before pin assignment and configuration as an output, the base state of chip-select signals is zero and chip-select pins should thus be driven active-high. 9.4 Serial Communication Interface The serial communication interface (SCI) communicates with external devices through an asynchronous serial bus. The SCI uses a standard non-return to zero (NRZ) transmission format. The SCI is fully compatible with other Freescale SCI systems, such as those on M68HC11 and M68HC05 devices. Figure 9-10 is a block diagram of the SCI transmitter. Figure 9-11 is a block diagram of the SCI receiver. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-21 Freescale Semiconductor, Inc. (WRITE-ONLY) SCDR Tx BUFFER TRANSMITTER BAUD RATE CLOCK START STOP DDRQS (D7) 10 (11)-BIT Tx SHIFT REGISTER 6 5 4 3 2 1 0 H (8) 7 L PIN BUFFER AND CONTROL OPEN DRAIN OUTPUT MODE ENABLE FORCE PIN DIRECTION (OUT) TxD TRANSFER Tx BUFFER SHIFT ENABLE SIZE 8/9 BREAK—JAM 0's PARITY GENERATOR Freescale Semiconductor, Inc... TRANSMITTER CONTROL LOGIC LOOPS WOMS WAKE PREAMBLE—JAM 1's JAM ENABLE RDRF RWU TCIE TDRE IDLE SBK RAF ILIE RIE TIE OR ILT RE PE TC NF PT TE FE 15 SCCR1 CONTROL REGISTER 1 TIE TCIE 0 15 SCSR STATUS REGISTER PF 0 INTERNAL DATA BUS 16/32 SCI TX BLOCK M TDRE TC SCI Rx REQUESTS SCI INTERRUPT REQUEST Figure 9-10 SCI Transmitter Block Diagram QUEUED SERIAL MODULE 9-22 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. RECEIVER BAUD RATE CLOCK RxD PIN BUFFER DATA RECOVERY STOP 16 10 (11)-BIT Rx SHIFT REGISTER 6 5 4 MSB 3 2 1 0 H (8) 7 ALL ONES PARITY DETECT Freescale Semiconductor, Inc... WAKE-UP LOGIC LOOPS WOMS WAKE RWU TCIE 15 SBK ILIE RIE TIE ILT RE PE PT TE M 0 SCCR1 CONTROL REGISTER 1 0 SCDR Rx BUFFER (READ-ONLY) RDRF RAF TDRE TC IDLE OR NF FE PF 15 SCSR STATUS REGISTER 0 SCI Tx REQUESTS SCI INTERRUPT REQUEST INTERNAL DATA BUS 16/32 SCI RX BLOCK Figure 9-11 SCI Receiver Block Diagram M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-23 START L Freescale Semiconductor, Inc. 9.4.1 SCI Registers The SCI programming model includes the QSM global and pin control registers, and four SCI registers. There are two SCI control registers (SCCR0 and SCCR1), one status register (SCSR), and one data register (SCDR). Refer to D.6 Queued Serial Module for register bit and field definitions. 9.4.1.1 Control Registers SCCR0 contains the baud rate selection field. Baud rate must be set before the SCI is enabled. This register can be read or written. SCCR1 contains a number of SCI configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. This register can be read or written at any time. The SCI can modify the RWU bit under certain circumstances. Changing the value of SCI control bits during a transfer may disrupt operation. Before changing register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter. 9.4.1.2 Status Register SCSR contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware or by reading SCSR, then reading or writing SCDR. A long-word read can consecutively access both SCSR and SCDR. This action clears receiver status flag bits that were set at the time of the read, but does not clear TDRE or TC flags. If an internal SCI signal for setting a status bit comes after reading the asserted status bits, but before reading or writing SCDR, the newly set status bit is not cleared. SCSR must be read again with the bit set, and SCDR must be read or written before the status bit is cleared. Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit already set in either byte is cleared on a subsequent read or write of SCDR. 9.4.1.3 Data Register SCDR contains two data registers at the same address. The receive data register (RDR) is a read-only register that contains data received by the SCI. Data enters the receive serial shifter and is transferred to RDR. The transmit data register (TDR) is a write-only register that contains data to be transmitted. Data is first written to TDR, then transferred to the transmit serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/ T8 are used when the SCI is configured for 9-bit operation. When the SCI is configured for 8-bit operation, they have no meaning or effect. Freescale Semiconductor, Inc... QUEUED SERIAL MODULE 9-24 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 9.4.2 SCI Pins Two unidirectional pins, TXD (transmit data) and RXD (receive data), are associated with the SCI. TXD can be used by the SCI or for general-purpose I/O. TXD function is controlled by PQSPA7 in the port QS pin assignment register (PQSPAR) and TE in SCI control register 1 (SCCR1). The receive data (RXD) pin is dedicated to the SCI. 9.4.3 SCI Operation The SCI can operate in polled or interrupt-driven mode. Status flags in SCSR reflect SCI conditions regardless of the operating mode chosen. The TIE, TCIE, RIE, and ILIE bits in SCCR1 enable interrupts for the conditions indicated by the TDRE, TC, RDRF, and IDLE bits in SCSR, respectively. Freescale Semiconductor, Inc... 9.4.3.1 Definition of Terms • Bit-Time — The time required to transmit or receive one bit of data, which is equal to one cycle of the baud frequency. • Start Bit — One bit-time of logic zero that indicates the beginning of a data frame. A start bit must begin with a one-to-zero transition and be preceded by at least three receive time samples of logic one. • Stop Bit — One bit-time of logic one that indicates the end of a data frame. • Frame — A complete unit of serial information. The SCI can use 10-bit or 11-bit frames. • Data Frame — A start bit, a specified number of data or information bits, and at least one stop bit. • Idle Frame — A frame that consists of consecutive ones. An idle frame has no start bit. • Break Frame — A frame that consists of consecutive zeros. A break frame has no stop bits. 9.4.3.2 Serial Formats All data frames must have a start bit and at least one stop bit. Receiving and transmitting devices must use the same data frame format. The SCI provides hardware support for both 10-bit and 11-bit frames. The M bit in SCCR1 specifies the number of bits per frame. The most common data frame format for NRZ serial interfaces is one start bit, eight data bits (LSB first), and one stop bit; a total of ten bits. The most common 11-bit data frame contains one start bit, eight data bits, a parity or control bit, and one stop bit. Ten-bit and 11-bit frames are shown in Table 9-4. M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-25 Freescale Semiconductor, Inc. Table 9-4 Serial Frame Formats Start 1 1 1 Start 1 1 10-Bit Frames Data Parity/Control 7 — 7 1 8 — 11-Bit Frames Data Parity/Control 7 1 8 1 Stop 2 1 1 Stop 2 1 Freescale Semiconductor, Inc... 9.4.3.3 Baud Clock The SCI baud rate is programmed by writing a 13-bit value to the SCBR field in SCI control register 0 (SCCR0). The baud rate is derived from the MCU system clock by a modulus counter. Writing a value of zero to SCBR[12:0] disables the baud rate generator. Baud rate is calculated as follows: f sys SCI Baud Rate = ------------------------------------------32 × SCBR[12:0] or f sys SCBR[12:0] = -------------------------------------------------------------------------32 × SCI Baud Rate Desired where SCBR[12:0] is in the range {1, 2, 3, ..., 8191}. The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an incoming data stream. The SCI baud rate generator produces a receive time sampling clock with a frequency 16 times that of the SCI baud rate. The SCI determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period. 9.4.3.4 Parity Checking The PT bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects received and transmitted data. The PE bit in SCCR1 determines whether parity checking is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data in a frame is used for the parity function. For transmitted data, a parity bit is generated; for received data, the parity bit is checked. When parity checking is enabled, the PF bit in the SCI status register (SCSR) is set if a parity error is detected. Enabling parity affects the number of data bits in a frame, which can in turn affect frame size. Table 9-5 shows possible data and parity formats. QUEUED SERIAL MODULE 9-26 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 9-5 Effect of Parity Checking on Data Size M 0 0 1 1 PE 0 1 0 1 Result 8 data bits 7 data bits, 1 parity bit 9 data bits 8 data bits, 1 parity bit Freescale Semiconductor, Inc... 9.4.3.5 Transmitter Operation The transmitter consists of a serial shifter and a parallel data register (TDR) located in the SCI data register (SCDR). The serial shifter cannot be directly accessed by the CPU16. The transmitter is double-buffered, which means that data can be loaded into TDR while other data is shifted out. The TE bit in SCCR1 enables (TE = 1) and disables (TE = 0) the transmitter. The shifter output is connected to the TXD pin while the transmitter is operating (TE = 1, or TE = 0 and transmission in progress). Wired-OR operation should be specified when more than one transmitter is used on the same SCI bus. The WOMS bit in SCCR1 determines whether TXD is an open-drain (wired-OR) output or a normal CMOS output. An external pull-up resistor on TXD is necessary for wired-OR operation. WOMS controls TXD function whether the pin is used by the SCI or as a generalpurpose I/O pin. Data to be transmitted is written to SCDR, then transferred to the serial shifter. The transmit data register empty (TDRE) flag in SCSR shows the status of TDR. When TDRE = 0, TDR contains data that has not been transferred to the shifter. Writing to SCDR again overwrites the data. TDRE is set when the data in TDR is transferred to the shifter. Before new data can be written to SCDR, however, the processor must clear TDRE by writing to SCSR. If new data is written to SCDR without first clearing TDRE, the data will not be transmitted. The transmission complete (TC) flag in SCSR shows transmitter shifter state. When TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is not automatically cleared. The processor must clear it by first reading SCSR while TC is set, then writing new data to SCDR. The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame is transmitted as a preamble to the following data frame. If TC = 0, the current operation continues until the final bit in the frame is sent, then the preamble is transmitted. The TC bit is set at the end of preamble transmission. The SBK bit in SCCR1 is used to insert break frames in a transmission. A non-zero integer number of break frames is transmitted while SBK is set. Break transmission begins when SBK is set, and ends with the transmission in progress at the time either SBK or TE is cleared. If SBK is set while a transmission is in progress, that transmission finishes normally before the break begins. To assure the minimum break time, toggle SBK quickly to one and back to zero. The TC bit is set at the end of break transmission. After break transmission, at least one bit-time of logic level one (mark idle) is transmitted to ensure that a subsequent start bit can be detected. M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-27 Freescale Semiconductor, Inc. If TE remains set, after all pending idle, data and break frames are shifted out, TDRE and TC are set and TXD is held at logic level one (mark). When TE is cleared, the transmitter is disabled after all pending idle, data, and break frames are transmitted. The TC flag is set, and control of the TXD pin reverts to PQSPAR and DDRQS. Buffered data is not transmitted after TE is cleared. To avoid losing data in the buffer, do not clear TE until TDRE is set. Some serial communication systems require a mark on the TXD pin even when the transmitter is disabled. Configure the TXD pin as an output, then write a one to PQS7. When the transmitter releases control of the TXD pin, it will revert to driving a logic one output. To insert a delimiter between two messages, to place non-listening receivers in wakeup mode between transmissions, or to signal a retransmission by forcing an idle line, clear and then set TE before data in the serial shifter has shifted out. The transmitter finishes the transmission, then sends a preamble. After the preamble is transmitted, if TDRE is set, the transmitter will mark idle. Otherwise, normal transmission of the next sequence will begin. Both TDRE and TC have associated interrupts. The interrupts are enabled by the transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits in SCCR1. Service routines can load the last byte of data in a sequence into SCDR, then terminate the transmission when a TDRE interrupt occurs. 9.4.3.6 Receiver Operation The RE bit in SCCR1 enables (RE = 1) and disables (RE = 0) the receiver. The receiver contains a receive serial shifter and a parallel receive data register (RDR) located in the SCI data register (SCDR). The serial shifter cannot be directly accessed by the CPU16. The receiver is double-buffered, allowing data to be held in RDR while other data is shifted in. Receiver bit processor logic drives a state machine that determines the logic level for each bit-time. This state machine controls when the bit processor logic is to sample the RXD pin and also controls when data is to be passed to the receive serial shifter. A receive time clock is used to control sampling and synchronization. Data is shifted into the receive serial shifter according to the most recent synchronization of the receive time clock with the incoming data stream. From this point on, data movement is synchronized with the MCU system clock. Operation of the receiver state machine is detailed in the QSM Reference Manual (QSMRM/AD). The number of bits shifted in by the receiver depends on the serial format. However, all frames must end with at least one stop bit. When the stop bit is received, the frame is considered to be complete, and the received data in the serial shifter is transferred to RDR. The receiver data register flag (RDRF) is set when the data is transferred. Noise errors, parity errors, and framing errors can be detected while a data stream is being received. Although error conditions are detected as bits are received, the noise flag (NF), the parity flag (PF), and the framing error (FE) flag in SCSR are not set until data is transferred from the serial shifter to RDR. QUEUED SERIAL MODULE 9-28 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. RDRF must be cleared before the next transfer from the shifter can take place. If RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR) flag in SCSR is set. OR indicates that RDR needs to be serviced faster. When OR is set, the data in RDR is preserved, but the data in the serial shifter is lost. Because framing, noise, and parity errors are detected while data is in the serial shifter, FE, NF, and PF cannot occur at the same time as OR. When the CPU16 reads SCSR and SCDR in sequence, it acquires status and data, and also clears the status flags. Reading SCSR acquires status and arms the clearing mechanism. Reading SCDR acquires data and clears SCSR. When RIE in SCCR1 is set, an interrupt request is generated whenever RDRF is set. Because receiver status flags are set at the same time as RDRF, they do not have separate interrupt enables. Freescale Semiconductor, Inc... 9.4.3.7 Idle-Line Detection During a typical serial transmission, frames are transmitted isochronally and no idle time occurs between frames. Even when all the data bits in a frame are logic ones, the start bit provides one logic zero bit-time during the frame. An idle line is a sequence of contiguous ones equal to the current frame size. Frame size is determined by the state of the M bit in SCCR1. The SCI receiver has both short and long idle-line detection capability. Idle-line detection is always enabled. The idle line type (ILT) bit in SCCR1 determines which type of detection is used. When an idle line condition is detected, the IDLE flag in SCSR is set. For short idle-line detection, the receiver bit processor counts contiguous logic one bittimes whenever they occur. Short detection provides the earliest possible recognition of an idle line condition, because the stop bit and contiguous logic ones before and after it are counted. For long idle-line detection, the receiver counts logic ones after the stop bit is received. Only a complete idle frame causes the IDLE flag to be set. In some applications, software overhead can cause a bit-time of logic level one to occur between frames. This bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled, the receiver flags an idle line. When the ILIE bit in SCCR1 is set, an interrupt request is generated when the IDLE flag is set. The flag is cleared by reading SCSR and SCDR in sequence. IDLE is not set again until after at least one frame has been received (RDRF = 1). This prevents an extended idle interval from causing more than one interrupt. 9.4.3.8 Receiver Wake-Up The receiver wake-up function allows a transmitting device to direct a transmission to a single receiver or to a group of receivers by sending an address frame at the start of a message. Hardware activates each receiver in a system under certain conditions. Resident software must process address information and enable or disable receiver operation. M68HC16 Z SERIES USER’S MANUAL QUEUED SERIAL MODULE For More Information On This Product, Go to: www.freescale.com 9-29 Freescale Semiconductor, Inc. A receiver is placed in wake-up mode by setting the RWU bit in SCCR1. While RWU is set, receiver status flags and interrupts are disabled. Although the CPU16 can clear RWU, it is normally cleared by hardware during wake-up. The WAKE bit in SCCR1 determines which type of wake-up is used. When WAKE = 0, idle-line wake-up is selected. When WAKE = 1, address-mark wake-up is selected. Both types require a software-based device addressing and recognition scheme. Idle-line wake-up allows a receiver to sleep until an idle line is detected. When an idleline is detected, the receiver clears RWU and wakes up. The receiver waits for the first frame of the next transmission. The byte is received normally, transferred to RDR, and the RDRF flag is set. If software does not recognize the address, it can set RWU and put the receiver back to sleep. For idle-line wake-up to work, there must be a minimum of one frame of idle line between transmissions. There must be no idle time between frames within a transmission. Address-mark wake-up uses a special frame format to wake up the receiver. When the MSB of an address-mark frame is set, that frame contains address information. The first frame of each transmission must be an address frame. When the MSB of a frame is set, the receiver clears RWU and wakes up. The byte is received normally, transferred to the RDR, and the RDRF flag is set. If software does not recognize the address, it can set RWU and put the receiver back to sleep. Address-mark wake-up allows idle time between frames and eliminates idle time between transmissions. However, there is a loss of efficiency because of an additional bit-time per frame. 9.4.3.9 Internal Loop Mode The LOOPS bit in SCCR1 controls a feedback path in the data serial shifter. When LOOPS is set, the SCI transmitter output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver must be enabled before entering loop mode. Freescale Semiconductor, Inc... QUEUED SERIAL MODULE 9-30 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 10 MULTICHANNEL COMMUNICATION INTERFACE This section is an overview of the multichannel communication interface (MCCI) module. Refer to the MCCI Reference Manual (MCCIRM/AD) for more information on MCCI capabilities. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for MCCI timing and electrical specifications. Refer to D.7 Multichannel Communication Interface Module for register address mapping and bit/field definitions. 10.1 General The MCCI contains three serial interfaces: a serial peripheral interface (SPI) and two serial communication interfaces (SCI). Figure 10-1 is a block diagram of the MCCI. The MCCI is present only on MC68HC16Z4 and MC68CK16Z4 microcontrollers. INTERMODULE BUS (IMB) Freescale Semiconductor, Inc... BUS INTERFACE UNIT PMC0/MISO PMC1/MOSI PMC2/SCK PMC3/SS PORT MCCI PMC4/RXDB PMC5/TXDB PMC6/RXDA PMC7/TXDA MCCI BLOCK SERIAL PERIPHERAL INTERFACE (SPI) SERIAL COMMUNICATION INTERFACE (SCIB) SERIAL COMMUNICATION INTERFACE (SCIA) Figure 10-1 MCCI Block Diagram The SPI provides easy peripheral expansion or interprocessor communication via a full-duplex, synchronous, three-line bus: data in, data out, and a serial clock. Serial transfer of eight or sixteen bits can begin with the most significant bit (MSB) or least significant bit (LSB). The MCCI module can be configured as a master or slave device. Clock control logic allows a selection of clock polarity and a choice of two clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of 254 different bit rates for the serial clock. M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-1 Freescale Semiconductor, Inc. The SCI is a universal asynchronous receiver transmitter (UART) serial interface with a standard non-return to zero (NRZ) mark/space format. It operates in either full- or half-duplex mode. It also contains separate transmit and receive enable bits and a double-transmit buffer. A modulus-type baud rate generator provides rates from 64 baud to 524 kbaud with a 16.78-MHz system clock. Word length of either eight or nine bits is software selectable. Optional parity generation and detection provide either even or odd parity check capability. Advanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. Wakeup functions allow the CPU to run uninterrupted until meaningful data is received. 10.2 MCCI Registers and Address Map The MCCI address map occupies 64 bytes from address $YFFC00 to $YFFC3F. It consists of MCCI global registers and SPI and SCI control, status, and data registers. Writes to unimplemented register bits have no effect, and reads of unimplemented bits always return zero. The MM bit in the system integration module configuration register (SIMCR) defines the most significant bit (ADDR23) of the IMB address for each module. Because ADDR[23:20] are driven to the same bit as ADDR19, MM must be set to one. If MM is cleared, IMB modules are inaccessible. Refer to 5.2.1 Module Mapping for more information about how the state of MM affects the system. 10.2.1 MCCI Global Registers The MCCI module configuration register (MMCR) contains bits and fields to place the MCCI in low-power operation, establish the privilege level required to access MCCI registers, and establish the priority of the MCCI during interrupt arbitration. The MCCI test register (MTEST) is used only during factory test of the MCCI. The SCI interrupt level register (ILSCI) determines the level of interrupts requested by each SCI. Separate fields hold the interrupt-request levels for SCIA and SCIB. The MCCI interrupt vector register (MIVR) determines which three vectors in the exception vector table are to be used for MCCI interrupts. The SPI and both SCI interfaces have separate interrupt vectors adjacent to one another. The SPI interrupt level register (ILSPI) determines the priority level of interrupts requested by the SPI. The MCCI port data registers (PORTMC and PORTMCP) are used to configure port MCCI for generalpurpose I/O. The MCCI pin assignment register (MPAR) determines which of the SPI pins (with the exception of SCK) are used by the SPI, and which pins are available for general-purpose I/O. The MCCI data direction register (MDDR) configures each pin as an input or output. 10.2.1.1 Low-Power Stop Mode When the STOP bit in the MMCR is set, the IMB clock signal to most of the MCCI module is disabled. This places the module in an idle state and minimizes power consumption. Freescale Semiconductor, Inc... MULTICHANNEL COMMUNICATION INTERFACE 10-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. To ensure that the MCCI stops in a known state, assert the STOP bit before executing the CPU LPSTOP instruction. Before asserting the STOP bit, disable the SPI (clear the SPE bit) and disable the SCI receivers and transmitters (clear the RE and TE bits). Complete transfers in progress before disabling the SPI and SCI interfaces. Once the STOP bit is asserted, it can be cleared by system software or by reset. 10.2.1.2 Privilege Levels The supervisor bit (SUPV) in the MMCR has no effect since the CPU16 operates only in the supervisor mode. 10.2.1.3 MCCI Interrupts The interrupt request level of each of the three MCCI interfaces can be programmed to a value of zero (interrupts disabled) through seven (highest priority). These levels are selected by the ILSCIA and ILSCIB fields in the SCI interrupt level register (ILSCI) and the ILSPI field in the SPI interrupt level register (ILSPI). In case two or more MCCI submodules request an interrupt simultaneously and are assigned the same interrupt request level, the SPI submodule is given the highest priority and SCIB is given the lowest. When an interrupt is requested which is at a higher level than the interrupt mask in the CPU status register, the CPU initiates an interrupt acknowledge cycle. During this cycle, the MCCI compares its interrupt request level to the level recognized by the CPU. If a match occurs, arbitration with other modules begins. Interrupting modules present their arbitration number on the IMB, and the module with the highest number wins. The arbitration number for the MCCI is programmed into the interrupt arbitration (IARB) field of the MMCR. Each module should be assigned a unique arbitration number. The reset value of the IARB field is $0, which prevents the MCCI from arbitrating during an interrupt acknowledge cycle. The IARB field should be initialized by system software to a value from $F (highest priority) through $1 (lowest priority). Otherwise, the CPU identifies any interrupts generated as spurious and takes a spurious-interrupt exception. If the MCCI wins the arbitration, it generates an interrupt vector that uniquely identifies the interrupting serial interface. The six MSBs are read from the interrupt vector (INTV) field in the MCCI interrupt vector register (MIVR). The two LSBs are assigned by the MCCI according to the interrupting serial interface, as indicated in Table 10-1. Table 10-1 MCCI Interrupt Vectors Interface SCIA SCIB SPI INTV[1:0] 00 01 10 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-3 Freescale Semiconductor, Inc. Select a value for INTV so that each MCCI interrupt vector corresponds to one of the user-defined vectors ($40–$FF). Refer to the CPU16 Reference Manual (CPU16RM/ AD) for additional information on interrupt vectors. 10.2.2 Pin Control and General-Purpose I/O The eight pins used by the SPI and SCI subsystems have alternate functions as general-purpose I/O pins. Configuring the MCCI submodule includes programming each pin for either general-purpose I/O or its serial interface function. In either function, each pin must also be programmed as input or output. The MCCI data direction register (MDDR) assigns each MCCI pin as either input or output. The MCCI pin assignment register (MPAR) assigns the MOSI, MISO, and SS pins as either SPI pins or general-purpose I/O. (The fourth pin, SCK, is automatically assigned to the SPI whenever the SPI is enabled, for example, when the SPE bit in the SPI control register is set.) The receiver enable (RE) and transmitter enable (TE) bits in the SCI control registers (SCCR0A, SCCR0B) automatically assign the associated pin as an SCI pin when set or general-purpose I/O when cleared. Table 10-2 summarizes how pin function and direction are assigned. Table 10-2 Pin Assignments Pin TXDA/PMC7 RXDA/PMC6 TXDB/PMC5 RXDB/PMC4 SS/PMC3 SCK/PMC2 MOSI/PMC1 MISO/PMC0 Function Assigned By TE bit in SCCR0A RE bit in SCCR0A TE bit in SCCR0B RE bit in SCCR0B SS bit in MPAR SPE bit in SPCR MOSI bit in MPAR MISO bit in MPAR Direction Assigned By MMDR7 MMDR6 MMDR5 MMDR4 MMDR3 MMDR2 MMDR1 MMDR0 Freescale Semiconductor, Inc... 10.3 Serial Peripheral Interface (SPI) The SPI submodule communicates with external peripherals and other MCUs via a synchronous serial bus. The SPI is fully compatible with the serial peripheral interface systems found on othe Freescale devices, such as the M68HC11 and M68HC05 families. The SPI can perform full duplex three-wire or half duplex two-wire transfers. Serial transfer of eight or sixteen bits can begin with the MSB or LSB. The system can be configured as a master or slave device. Figure 10-2 shows a block diagram of the SPI. MULTICHANNEL COMMUNICATION INTERFACE 10-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. INTERNAL MCU CLOCK S M MISO PMC0 8/16-BIT SHIFT REGISTER READ DATA BUFFER S CLOCK SPI CLOCK (MASTER) SELECT CLOCK LOGIC M S PRINT CONTROL LOGIC MODULUS COUNTER MSB LSB M MOSI PMC1 SCK PMC2 Freescale Semiconductor, Inc... BAUD SS PMC3 SHIFT CONTROL LOGIC MSTR SPE SPI CONTROL MSTR SPE WOMP WCOL MODF MSTR CPHA SPI STATUS REGISTER SPI CONTROL REGISTER SPI INTERRUPT REQUEST INTERNAL DATA BUS BAUD CPOL LSBF SPIE SIZE SPIF SPE WOMP MCCI SPI BLOCK Figure 10-2 SPI Block Diagram Clock control logic allows a selection of clock polarity and a choice of two clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of 254 different bit rates for the serial clock. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave-select line allows individual selection of a slave SPI device. Slave devices which are not selected do not interfere with SPI bus activities. On a master SPI device the slave-select line can optionally be used to indicate a multiple-master bus contention. M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-5 Freescale Semiconductor, Inc. Error-detection logic is included to support interprocessor interfacing. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers if more than one MCU simultaneously attempts to become bus master. 10.3.1 SPI Registers SPI control registers include the SPI control register (SPCR), the SPI status register (SPSR), and the SPI data register (SPDR). Refer to D.7.13 SPI Control Register, D.7.14 SPI Status Register, and D.7.15 SPI Data Register for register bit and field definitions. 10.3.1.1 SPI Control Register (SPCR) The SPCR contains parameters for configuring the SPI. The register can be read or written at any time. 10.3.1.2 SPI Status Register (SPSR) The SPSR contains SPI status information. Only the SPI can set the bits in this register. The CPU reads the register to obtain status information. 10.3.1.3 SPI Data Register (SPDR) The SPDR is used to transmit and receive data on the serial bus. A write to this register in the master device initiates transmission or reception of another byte or word. After a byte or word of data is transmitted, the SPIF status bit is set in both the master and slave devices. A read of the SPDR actually reads a buffer. If the first SPIF is not cleared by the time a second transfer of data from the shift register to the read buffer is initiated, an overrun condition occurs. In cases of overrun the byte or word causing the overrun is lost. A write to the SPDR is not buffered and places data directly into the shift register for transmission. 10.3.2 SPI Pins Four bidirectional pins are associated with the SPI. The MPAR configures each pin for either SPI function or general-purpose I/O. The MDDR assigns each pin as either input or output. The WOMP bit in the SPI control register (SPCR) determines whether each SPI pin that is configured for output functions as an open-drain output or a normal CMOS output. The MDDR and WOMP assignments are valid regardless of whether the pins are configured for SPI use or general-purpose I/O. The operation of pins configured for SCI use depends on whether the SCI is operating as a master or a slave, determined by the MSTR bit in the SPCR. Table 10-3 shows SPI pins and their functions. Freescale Semiconductor, Inc... MULTICHANNEL COMMUNICATION INTERFACE 10-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 10-3 SPI Pin Functions Pin Name Master in, slave out (MISO) Master out, slave in (MOSI) Serial clock (SCK) Slave select (SS) Mode Master Slave Master Slave Master Slave Master Slave Function Provides serial data input to the SPI Provides serial data output from the SPI Provides serial output from the SPI Provides serial input to the SPI Provides clock output from the SPI Provides clock input to the SPI Detects bus-master mode fault Selects the SPI for an externally-initiated serial transfer Freescale Semiconductor, Inc... 10.3.3 SPI Operating Modes The SPI operates in either master or slave mode. Master mode is used when the MCU originates data transfers. Slave mode is used when an external device initiates serial transfers to the MCU. The MSTR bit in SPCR selects master or slave operation. 10.3.3.1 Master Mode Setting the MSTR bit in SPCR selects master mode operation. In master mode, the SPI can initiate serial transfers but cannot respond to externally initiated transfers. When the slave-select input of a device configured for master mode is asserted, a mode fault occurs. When using the SPI in master mode, include the following steps: 1. Write to the MMCR, MIVR, and ILSPI. Refer to 10.5 MCCI Initialization for more information. 2. Write to the MPAR to assign the following pins to the SPI: MISO, MOSI, and (optionally) SS. MISO is used for serial data input in master mode, and MOSI is used for serial data output. Either or both may be necessary, depending on the particular application. SS is used to generate a mode fault in master mode. If this SPI is the only possible master in the system, the SS pin may be used for general-purpose I/O. 3. Write to the MDDR to direct the data flow on SPI pins. Configure the SCK (serial clock) and MOSI pins as outputs. Configure MISO and (optionally) SS as inputs. 4. Write to the SPCR to assign values for BAUD, CPHA, CPOL, SIZE, LSBF, WOMP, and SPIE. Set the MSTR bit to select master operation. Set the SPE bit to enable the SPI. 5. Enable the slave device. 6. Write appropriate data to the SPI data register to initiate the transfer. When the SPI reaches the end of the transmission, it sets the SPIF flag in the SPSR. If the SPIE bit in the SPCR is set, an interrupt request is generated when SPIF is asserted. After the SPSR is read with SPIF set, and then the SPDR is read or written to, the SPIF flag is automatically cleared. M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-7 Freescale Semiconductor, Inc. Data transfer is synchronized with the internally-generated serial clock (SCK). Control bits CPHA and CPOL in SPCR control clock phase and polarity. Combinations of CPHA and CPOL determine the SCK edge on which the master MCU drives outgoing data from the MOSI pin and latches incoming data from the MISO pin. 10.3.3.2 Slave Mode Clearing the MSTR bit in SPCR selects slave mode operation. In slave mode, the SPI is unable to initiate serial transfers. Transfers are initiated by an external bus master. Slave mode is typically used on a multimaster SPI bus. Only one device can be bus master (operate in master mode) at any given time. When using the SPI in slave mode, include the following steps: Freescale Semiconductor, Inc... 1. Write to the MMCR and interrupt registers. Refer to 10.5 MCCI Initialization for more information. 2. Write to the MPAR to assign the following pins to the SPI: MISO, MOSI, and SS. MISO is used for serial data output in slave mode, and MOSI is used for serial data input. Either or both may be necessary, depending on the particular application. SCK is the input serial clock. SS selects the SPI when asserted. 3. Write to the MDDR to direct the data flow on SPI pins. Configure the SCK, MOSI, and SS pins as inputs. Configure MISO as an output. 4. Write to the SPCR to assign values for CPHA, CPOL, SIZE, LSBF, WOMP, and SPIE. Set the MSTR bit to select master operation. Set the SPE bit to enable the SPI. (The BAUD field in the SPCR of the slave device has no effect on SPI operation.) When SPE is set and MSTR is clear, a low state on the SS pin initiates slave mode operation. The SS pin is used only as an input. After a byte or word of data is transmitted, the SPI sets the SPIF flag. If the SPIE bit in SPCR is set, an interrupt request is generated when SPIF is asserted. Transfer is synchronized with the externally generated SCK. The CPHA and CPOL bits determine the SCK edge on which the slave MCU latches incoming data from the MOSI pin and drives outgoing data from the MISO pin. 10.3.4 SPI Clock Phase and Polarity Controls Two bits in the SPCR determine SCK phase and polarity. The clock polarity (CPOL) bit selects clock polarity (high true or low true clock). The clock phase control bit (CPHA) selects one of two transfer formats and affects the timing of the transfer. The clock phase and polarity should be the same for the master and slave devices. In some cases, the phase and polarity may be changed between transfers to allow a master device to communicate with slave devices with different requirements. The flexibility of the SPI system allows it to be directly interfaced to almost any existing synchronous serial peripheral. MULTICHANNEL COMMUNICATION INTERFACE 10-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 10.3.4.1 CPHA = 0 Transfer Format Figure 10-3 is a timing diagram of an 8-bit, MSB-first SPI transfer in which CPHA equals zero. Two waveforms are shown for SCK: one for CPOL equal to zero and another for CPOL equal to one. The diagram may be interpreted as a master or slave timing diagram since the SCK, MISO and MOSI pins are directly connected between the master and the slave. The MISO signal shown is the output from the slave and the MOSI signal shown is the output from the master. The SS line is the chip-select input to the slave. SCK CYCLE # (FOR REFERENCE) 1 2 3 4 5 6 7 8 Freescale Semiconductor, Inc... SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MSB 6 5 4 3 2 1 LSB MISO (FROM SLAVE) SS (TO SLAVE) MSB 6 5 4 3 2 1 LSB CPHA = 0 SPI TRANSFER Figure 10-3 CPHA = 0 SPI Transfer Format For a master, writing to the SPDR initiates the transfer. For a slave, the falling edge of SS indicates the start of a transfer. The SCK signal remains inactive for the first half of the first SCK cycle. Data is latched on the first and each succeeding odd clock edge, and the SPI shift register is left-shifted on the second and succeeding even clock edges. SPIF is set at the end of the eighth SCK cycle. When CPHA equals zero, the SS line must be negated and reasserted between each successive serial byte. If the slave writes data to the SPI data register while SS is asserted (low), a write collision error results. To avoid this problem, the slave should read bit three of PORTMCP, which indicates the state of the SS pin, before writing to the SPDR again. M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-9 Freescale Semiconductor, Inc. 10.3.4.2 CPHA = 1 Transfer Format Figure 10-4 is a timing diagram of an 8-bit, MSB-first SPI transfer in which CPHA equals one. Two waveforms are shown for SCK, one for CPOL equal to zero and another for CPOL equal to one. The diagram may be interpreted as a master or slave timing diagram since the SCK, MISO and MOSI pins are directly connected between the master and the slave. The MISO signal shown is the output from the slave and the MOSI signal shown is the output from the master. The SS line is the slave select input to the slave. SCK CYCLE # (FOR REFERENCE) 1 2 3 4 5 6 7 8 Freescale Semiconductor, Inc... SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MSB 6 5 4 3 2 1 LSB MISO (FROM SLAVE) * MSB 6 5 4 3 2 1 LSB SS (TO SLAVE) * NOT DEFINED BUT NORMALLY LSB OF PREVIOUSLY TRANSMITTED CHARACTER CPHA = 1 SPI TRANSFER Figure 10-4 CPHA = 1 SPI Transfer Format For a master, writing to the SPDR initiates the transfer. For a slave, the first edge of SCK indicates the start of a transfer. The SPI is left-shifted on the first and each succeeding odd clock edge, and data is latched on the second and succeeding even clock edges. SCK is inactive for the last half of the eighth SCK cycle. For a master, SPIF is set at the end of the eighth SCK cycle (after the seventeenth SCK edge). Since the last SCK edge occurs in the middle of the eighth SCK cycle, however, the slave has no way of knowing when the end of the last SCK cycle occurs. The slave therefore considers the transfer complete after the last bit of serial data has been sampled, which corresponds to the middle of the eighth SCK cycle. When CPHA is one, the SS line may remain at its active low level between transfers. This format is sometimes preferred in systems having a single fixed master and only one slave that needs to drive the MISO data line. MULTICHANNEL COMMUNICATION INTERFACE 10-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 10.3.5 SPI Serial Clock Baud Rate Baud rate is selected by writing a value from two to 255 into SPBR[7:0] in the SPCR of the master MCU. Writing an SPBR[7:0] value into the SPCR of the slave device has no effect. The SPI uses a modulus counter to derive SCK baud rate from the MCU system clock. The following expressions apply to SCK baud rate: f sys SCK Baud Rate = -----------------------------------2 × SPBR[7:0] or Freescale Semiconductor, Inc... f sys SPBR[7:0] = ------------------------------------------------------------------------2 × SCK Baud Rate Desired Giving SPBR[7:0] a value of zero or one disables the baud rate generator. SCK is disabled and assumes its inactive state value. SPBR[7:0] has 254 active values. Table 10-4 lists several possible baud values and the corresponding SCK frequency based on a 16.78-MHz system clock. Table 10-4 SCK Frequencies System Clock Frequency 16.78 MHz Required Division Ratio 4 8 16 34 168 510 Value of SPBR Actual SCK Frequency 2 4 8 17 84 255 4.19 MHz 2.10 MHz 1.05 MHz 493 kHz 100 kHz 33 kHz 10.3.6 Wired-OR Open-Drain Outputs Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the system. If needed, the WOMP bit in SPCR can be set to provide wired-OR, open-drain outputs. An external pull-up resistor should be used on each output line. WOMP affects all SPI pins regardless of whether they are assigned to the SPI or used as general-purpose I/O. 10.3.7 Transfer Size and Direction The SIZE bit in the SPCR selects a transfer size of eight (SIZE = 0) or sixteen (SIZE = 1) bits. The LSBF bit in the SPCR determines whether serial shifting to and from the data register begins with the LSB (LSBF = 1) or MSB (LSBF = 0). M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-11 Freescale Semiconductor, Inc. 10.3.8 Write Collision A write collision occurs if an attempt is made to write the SPDR while a transfer is in progress. Since the SPDR is not double buffered in the transmit direction, a successful write to SPDR would cause data to be written directly into the SPI shift register. Because this would corrupt any transfer in progress, a write collision error is generated instead. The transfer continues undisturbed, the data that caused the error is not written to the shifter, and the WCOL bit in SPSR is set. No SPI interrupt is generated. A write collision is normally a slave error because a slave has no control over when a master initiates a transfer. Since a master is in control of the transfer, software can avoid a write collision error generated by the master. The SPI logic can, however, detect a write collision in a master as well as in a slave. Freescale Semiconductor, Inc... What constitutes a transfer in progress depends on the SPI configuration. For a master, a transfer starts when data is written to the SPDR and ends when SPIF is set. For a slave, the beginning and ending points of a transfer depend on the value of CPHA. When CPHA = 0, the transfer begins when SS is asserted and ends when it is negated. When CPHA = 1, a transfer begins at the edge of the first SCK cycle and ends when SPIF is set. Refer to 10.3.4 SPI Clock Phase and Polarity Controls for more information on transfer periods and on avoiding write collision errors. When a write collision occurs, the WCOL bit in the SPSR is set. To clear WCOL, read the SPSR while WCOL is set, and then either read the SPDR (either before or after SPIF is set) or write the SPDR after SPIF is set. (Writing the SPDR before SPIF is set results in a second write collision error.) This process clears SPIF as well as WCOL. 10.3.9 Mode Fault When the SPI system is configured as a master and the SS input line is asserted, a mode fault error occurs, and the MODF bit in the SPSR is set. Only an SPI master can experience a mode fault error, caused when a second SPI device becomes a master and selects this device as if it were a slave. To avoid latchup caused by contention between two pin drivers, the MCU does the following when it detects a mode fault error: Forces the MSTR control bit to zero to reconfigure the SPI as a slave. Forces the SPE control bit to zero to disable the SPI system. Sets the MODF status flag and generates an SPI interrupt if SPIE = 1. Clears the appropriate bits in the MDDR to configure all SPI pins except the SS pin as inputs. After correcting the problems that led to the mode fault, clear MODF by reading the SPSR while MODF is set and then writing to the SPCR. Control bits SPE and MSTR may be restored to their original set state during this clearing sequence or after the MODF bit has been cleared. Hardware does not allow the user to set the SPE and MSTR bits while MODF is a logic one except during the proper clearing sequence. 1. 2. 3. 4. MULTICHANNEL COMMUNICATION INTERFACE 10-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 10.4 Serial Communication Interface (SCI) The SCI submodule contains two independent SCI systems. Each is a full-duplex universal asynchronous receiver transmitter (UART). This SCI system is fully compatible with SCI systems found on other Freescale devices, such as the M68HC11 and M68HC05 families. The SCI uses a standard non-return to zero (NRZ) transmission format. An on-chip baud-rate generator derives standard baud-rate frequencies from the MCU oscillator. Both the transmitter and the receiver are double buffered, so that back-to-back characters can be handled easily even if the CPU is delayed in responding to the completion of an individual character. The SCI transmitter and receiver are functionally independent but use the same data format and baud rate. Freescale Semiconductor, Inc... Figure 10-5 shows a block diagram of the SCI transmitter. Figure 10-6 shows a block diagram of the SCI receiver. The two independent SCI systems are called SCIA and SCIB. These SCIs are identical in register set and hardware configuration, providing an application with full flexibility in using the dual SCI system. References to SCI registers in this section do not always distinguish between the two SCI systems. A reference to SCCR1, for example, applies to both SCCR1A (SCIA control register 1) and SCCR1B (SCIB control register 1). 10.4.1 SCI Registers The SCI programming model includes the MCCI global and pin control registers and eight SCI registers. Each of the two SCI units contains two SCI control registers, one status register, and one data register. Refer to D.7.9 SCI Control Register 0, D.7.11 SCI Status Register, and D.7.12 SCI Data Register for register bit and field definitions. All registers may be read or written at any time by the CPU. Rewriting the same value to any SCI register does not disrupt operation; however, writing a different value into an SCI register when the SCI is running may disrupt operation. To change register values, the receiver and transmitter should be disabled with the transmitter allowed to finish first. The status flags in the SCSR may be cleared at any time. When initializing the SCI, set the transmitter enable (TE) and receiver enable (RE) bits in SCCR1 last. A single word write to SCCR1 can be used to initialize the SCI and enable the transmitter and receiver. 10.4.1.1 SCI Control Registers SCCR0 contains the baud rate selection field. The baud rate must be set before the SCI is enabled. The CPU16 can read and write this register at any time. M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-13 Freescale Semiconductor, Inc. TRANSMITTER BAUD RATE CLOCK SCDR TX BUFFER (WRITE ONLY) MDDR7 MDDR5 TXD 10 (11) - BIT TX SHIFT REGISTER (8) 7 6 5 4 3 2 1 0 START STOP H L PIN BUFFER AND CONTROL TRANSFER TX BUFFER PARITY GENERATOR Freescale Semiconductor, Inc... TRANSMITTER CONTROL LOGIC FORCE PIN DIRECTION (OUT) LOOPS WOMS WAKE RDRF TDRE RWU TCIE IDLE SBK RAF ILIE RIE TIE OR ILT RE PE TC NF TE FE PT 15 SCCR1 (CONTROL REGISTER 1) 0 15 SCSR (STATUS REGISTER) PF M 0 0 TIE TDRE TCIE TC SCI RX REQUESTS SCI INTERRUPT REQUEST INTERNAL DATA BUS MCCI SCI TX BLOCK Figure 10-5 SCI Transmitter Block Diagram MULTICHANNEL COMMUNICATION INTERFACE 10-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL OPEN DRAIN OUTPUT MODE ENABLE SIZE 8/9 PREAMBLE — JAM 1’S BREAK — JAM 0’S SHIFT ENABLE JAM ENABLE Freescale Semiconductor, Inc. 10 (11) - BIT RX SHIFT REGISTER (8) 7 6 5 4 3 2 1 0 RXD PIN BUFFER DATA RECOVERY H MSB ALL ONES PARITY DETECT WAKE-UP LOGIC Freescale Semiconductor, Inc... LOOPS WOMS WAKE RWU TCIE 15 SCCR1 (CONTROL REGISTER 1) SBK ILIE RIE TIE ILT RE PE TE PT M 0 0 SCDR RX BUFFER (READ ONLY) RDRF TDRE IDLE RAF OR TC NF FE 15 SCSR (STATUS REGISTER) PF 0 SCI TX REQUESTS SCI INTERRUPT REQUEST INTERNAL DATA BUS MCCI SCI RX BLOCK Figure 10-6 SCI Receiver Block Diagram M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-15 START L STOP RECEIVER BAUD RATE CLOCK ÷ 16 Freescale Semiconductor, Inc. SCCR1 contains a number of SCI configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. The CPU16 can read and write this register at any time. The SCI can modify the RWU bit under certain circumstances. Changing the value of SCI control bits during a transfer may disrupt operation. Before changing register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter. 10.4.1.2 SCI Status Register The SCSR contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware or by a read/write sequence. To clear SCI transmitter flags, read the SCSR and then write to the SCDR. To clear SCI receiver flags, read the SCSR and then read the SCDR. A long-word read can consecutively access both the SCSR and the SCDR. This action clears receiver status flag bits that were set at the time of the read, but does not clear TDRE or TC flags. If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits, but before the CPU has written or read the SCDR, the newly set status bit is not cleared. The SCSR must be read again with the bit set, and the SCDR must be written to or read before the status bit is cleared. Reading either byte of the SCSR causes all 16 bits to be accessed, and any status bit already set in either byte will be cleared on a subsequent read or write of the SCDR. 10.4.1.3 SCI Data Register The SCDR contains two data registers at the same address. The RDR is a read-only register that contains data received by the SCI serial interface. The data comes into the receive serial shifter and is transferred to the RDR. The TDR is a write-only register that contains data to be transmitted. The data is first written to the TDR, then transferred to the transmit serial shifter, where additional format bits are added before transmission. 10.4.2 SCI Pins Four pins are associated with the SCI: TXDA, TXDB, RXDA, and RXDB. The state of the TE or RE bit in SCI control register 1 of each SCI submodule (SCCR1A, SCCR1B) determines whether the associated pin is configured for SCI operation or general-purpose I/O. The MDDR assigns each pin as either input or output. The WOMC bit in SCCR1A or SCCR1B determines whether the associated RXD and TXD pins, when configured as outputs, function as open-drain output pins or normal CMOS outputs. The MDDR and WOMC assignments are valid regardless of whether the pins are configured for SPI use or general-purpose I/O. SCI pins are listed in Table 10-5. Freescale Semiconductor, Inc... MULTICHANNEL COMMUNICATION INTERFACE 10-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 10-5 SCI Pins Pin Transmit data Receive data Mode TXDA TXDB RXDA RXDB SCI Function Serial data output from SCIA (TE = 1) Serial data output from SCIB (TE = 1) Serial data input to SCIA (RE = 1) Serial data input to SCIB (RE = 1) Port I/O Signal PMC7 PMC5 PMC6 PMC4 Freescale Semiconductor, Inc... 10.4.3 Receive Data Pins (RXDA, RXDB) RXDA and RXDB are the serial data inputs to the SCIA and SCIB interfaces, respectively. Each pin is also available as a general-purpose I/O pin when the RE bit in SCCR1 of the associated SCI submodule is cleared. When used for general-purpose I/O, RXDA and RXDB may be configured either as input or output as determined by the RXDA and RXDB bits in the MDDR. 10.4.4 Transmit Data Pins (TXDA, TXDB) When used for general-purpose I/O, TXDA and TXDB can be configured either as input or output as determined by the TXDA and TXDB bits in the MDDR. The TXDA and TXDB pins are enabled for SCI use by setting the TE bit in SCCR1 of each SCI interface. 10.4.5 SCI Operation SCI operation can be polled by means of status flags in the SCSR, or interrupt-driven operation can be employed by means of the interrupt-enable bits in SCCR1. 10.4.5.1 Definition of Terms Data can be transmitted and received in a number of formats. The following terms concerning data format are used in this section: • Bit-Time — The time required to transmit or receive one bit of data, which is equal to one cycle of the baud frequency. • Start Bit — One bit-time of logic zero that indicates the beginning of a data frame. A start bit must begin with a one-to-zero transition and be preceded by at least three receive time samples of logic one. • Stop Bit — One bit-time of logic one that indicates the end of a data frame. • Frame — A complete unit of serial information. The SCI can use 10-bit or 11-bit frames. • Data Frame — A start bit, a specified number of data or information bits, and at least one stop bit. • Idle Frame — A frame that consists of consecutive ones. An idle frame has no start bit. • Break Frame — A frame that consists of consecutive zeros. A break frame has no stop bits. M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-17 Freescale Semiconductor, Inc. 10.4.5.2 Serial Formats All data frames must have a start bit and at least one stop bit. Receiving and transmitting devices must use the same data frame format. The SCI provides hardware support for both 10-bit and 11-bit frames. The M bit in SCCR1 specifies the number of bits per frame. The most common data frame format for NRZ serial interfaces is one start bit, eight data bits (LSB first), and one stop bit; a total of ten bits. The most common 11-bit data frame contains one start bit, eight data bits, a parity or control bit, and one stop bit. Ten-bit and eleven-bit frames are shown in Table 10-6. Table 10-6 Serial Frame Formats Freescale Semiconductor, Inc... Start 1 1 1 Start 1 1 10-Bit Frames Data Parity/Control 7 — 7 1 8 — 11-Bit Frames Data Parity/Control 7 1 8 1 Stop 2 1 1 Stop 2 1 10.4.5.3 Baud Clock The SCI baud rate is programmed by writing a 13-bit value to the SCBR field in SCI control register zero (SCCR0). The baud rate is derived from the MCU system clock by a modulus counter. Writing a value of zero to SCBR[12:0] disables the baud rate generator. Baud rate is calculated as follows: f sys SCI Baud Rate = ------------------------------------------32 × SCBR[12:0] or f sys SCBR[12:0] = -------------------------------------------------------------------------32 × SCI Baud Rate Desired where SCBR[12:0] is in the range {1, 2, 3, ..., 8191}. The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an incoming data stream. The SCI baud rate generator produces a receive time sampling clock with a frequency 16 times that of the SCI baud rate. The SCI determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period. MULTICHANNEL COMMUNICATION INTERFACE 10-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 10.4.5.4 Parity Checking The PT bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects received and transmitted data. The PE bit in SCCR1 determines whether parity checking is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data in a frame is used for the parity function. For transmitted data, a parity bit is generated for received data; the parity bit is checked. When parity checking is enabled, the PF bit in the SCI status register (SCSR) is set if a parity error is detected. Enabling parity affects the number of data bits in a frame, which can in turn affect frame size. Table 10-7 shows possible data and parity formats. Table 10-7 Effect of Parity Checking on Data Size Freescale Semiconductor, Inc... M 0 0 1 1 PE 0 1 0 1 Result 8 data bits 7 data bits, 1 parity bit 9 data bits 8 data bits, 1 parity bit 10.4.5.5 Transmitter Operation The transmitter consists of a serial shifter and a parallel data register (TDR) located in the SCI data register (SCDR). The serial shifter cannot be directly accessed by the CPU16. The transmitter is double-buffered, which means that data can be loaded into the TDR while other data is shifted out. The TE bit in SCCR1 enables (TE = 1) and disables (TE = 0) the transmitter. Shifter output is connected to the TXD pin while the transmitter is operating (TE = 1, or TE = 0 and transmission in progress). Wired-OR operation should be specified when more than one transmitter is used on the same SCI bus. The WOMS bit in SCCR1 determines whether TXD is an open-drain (wired-OR) output or a normal CMOS output. An external pull-up resistor on TXD is necessary for wired-OR operation. WOMS controls TXD function whether the pin is used by the SCI or as a generalpurpose I/O pin. Data to be transmitted is written to SCDR, then transferred to the serial shifter. The transmit data register empty (TDRE) flag in SCSR shows the status of TDR. When TDRE = 0, the TDR contains data that has not been transferred to the shifter. Writing to SCDR again overwrites the data. TDRE is set when the data in the TDR is transferred to the shifter. Before new data can be written to the SCDR, however, the processor must clear TDRE by writing to SCSR. If new data is written to the SCDR without first clearing TDRE, the data will not be transmitted. The transmission complete (TC) flag in SCSR shows transmitter shifter state. When TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is not automatically cleared. The processor must clear it by first reading SCSR while TC is set, then writing new data to SCDR. M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-19 Freescale Semiconductor, Inc. The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame is transmitted as a preamble to the following data frame. If TC = 0, the current operation continues until the final bit in the frame is sent, then the preamble is transmitted. The TC bit is set at the end of preamble transmission. The SBK bit in SCCR1 is used to insert break frames in a transmission. A non-zero integer number of break frames is transmitted while SBK is set. Break transmission begins when SBK is set, and ends with the transmission in progress at the time either SBK or TE is cleared. If SBK is set while a transmission is in progress, that transmission finishes normally before the break begins. To assure the minimum break time, toggle SBK quickly to one and back to zero. The TC bit is set at the end of break transmission. After break transmission, at least one bit-time of logic level one (mark idle) is transmitted to ensure that a subsequent start bit can be detected. Freescale Semiconductor, Inc... If TE remains set, after all pending idle, data and break frames are shifted out, TDRE and TC are set and TXD is held at logic level one (mark). When TE is cleared, the transmitter is disabled after all pending idle, data, and break frames are transmitted. The TC flag is set, and control of the TXD pin reverts to MPAR and MDDR. Buffered data is not transmitted after TE is cleared. To avoid losing data in the buffer, do not clear TE until TDRE is set. Some serial communication systems require a mark on the TXD pin even when the transmitter is disabled. Configure the TXD pin as an output, then write a one to PQS7. When the transmitter releases control of the TXD pin, it reverts to driving a logic one output. To insert a delimiter between two messages, to place non-listening receivers in wakeup mode between transmissions, or to signal a retransmission by forcing an idle line, clear and then set TE before data in the serial shifter has shifted out. The transmitter finishes the transmission, then sends a preamble. After the preamble is transmitted, if TDRE is set, the transmitter will mark idle. Otherwise, normal transmission of the next sequence will begin. Both TDRE and TC have associated interrupts. The interrupts are enabled by the transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits in SCCR1. Service routines can load the last byte of data in a sequence into SCDR, then terminate the transmission when a TDRE interrupt occurs. 10.4.5.6 Receiver Operation The RE bit in SCCR1 enables (RE = 1) and disables (RE = 0) the receiver. The receiver contains a receive serial shifter and a parallel receive data register (RDR) located in the SCI data register (SCDR). The serial shifter cannot be directly accessed by the CPU16. The receiver is double-buffered, allowing data to be held in the RDR while other data is shifted in. Receiver bit processor logic drives a state machine that determines the logic level for each bit-time. This state machine controls when the bit processor logic is to sample the RXD pin and also controls when data is to be passed to the receive serial shifter. MULTICHANNEL COMMUNICATION INTERFACE 10-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. A receive time clock is used to control sampling and synchronization. Data is shifted into the receive serial shifter according to the most recent synchronization of the receive time clock with the incoming data stream. From this point on, data movement is synchronized with the MCU system clock. The number of bits shifted in by the receiver depends on the serial format. However, all frames must end with at least one stop bit. When the stop bit is received, the frame is considered to be complete, and the received data in the serial shifter is transferred to the RDR. The receiver data register flag (RDRF) is set when the data is transferred. Noise errors, parity errors, and framing errors can be detected while a data stream is being received. Although error conditions are detected as bits are received, the noise flag (NF), the parity flag (PF), and the framing error flag (FE) in SCSR are not set until data is transferred from the serial shifter to the RDR. Freescale Semiconductor, Inc... RDRF must be cleared before the next transfer from the shifter can take place. If RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR) flag in SCSR is set. OR indicates that the RDR needs to be serviced faster. When OR is set, the data in the RDR is preserved, but the data in the serial shifter is lost. Because framing, noise, and parity errors are detected while data is in the serial shifter, FE, NF, and PF cannot occur at the same time as OR. When the CPU16 reads SCSR and SCDR in sequence, it acquires status and data, and also clears the status flags. Reading SCSR acquires status and arms the clearing mechanism. Reading SCDR acquires data and clears SCSR. When RIE in SCCR1 is set, an interrupt request is generated whenever RDRF is set. Because receiver status flags are set at the same time as RDRF, they do not have separate interrupt enables. 10.4.5.7 Idle-Line Detection During a typical serial transmission, frames are transmitted isochronally and no idle time occurs between frames. Even when all the data bits in a frame are logic ones, the start bit provides one logic zero bit-time during the frame. An idle line is a sequence of contiguous ones equal to the current frame size. Frame size is determined by the state of the M bit in SCCR1. The SCI receiver has both short and long idle-line detection capability. Idle-line detection is always enabled. The idle line type (ILT) bit in SCCR1 determines which type of detection is used. When an idle line condition is detected, the IDLE flag in SCSR is set. For short idle-line detection, the receiver bit processor counts contiguous logic one bittimes whenever they occur. Short detection provides the earliest possible recognition of an idle line condition, because the stop bit and contiguous logic ones before and after it are counted. For long idle-line detection, the receiver counts logic ones after the stop bit is received. Only a complete idle frame causes the IDLE flag to be set. M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-21 Freescale Semiconductor, Inc. In some applications, software overhead can cause a bit-time of logic level one to occur between frames. This bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled, the receiver flags an idle line. When the ILIE bit in SCCR1 is set, an interrupt request is generated when the IDLE flag is set. The flag is cleared by reading SCSR and SCDR in sequence. IDLE is not set again until after at least one frame has been received (RDRF = 1). This prevents an extended idle interval from causing more than one interrupt. 10.4.5.8 Receiver Wake-Up The receiver wake-up function allows a transmitting device to direct a transmission to a single receiver or to a group of receivers by sending an address frame at the start of a message. Hardware activates each receiver in a system under certain conditions. Resident software must process address information and enable or disable receiver operation. A receiver is placed in wake-up mode by setting the RWU bit in SCCR1. While RWU is set, receiver status flags and interrupts are disabled. Although the CPU32 can clear RWU, it is normally cleared by hardware during wake-up. The WAKE bit in SCCR1 determines which type of wake-up is used. When WAKE = 0, idle-line wake-up is selected. When WAKE = 1, address-mark wake-up is selected. Both types require a software-based device addressing and recognition scheme. Idle-line wake-up allows a receiver to sleep until an idle line is detected. When an idleline is detected, the receiver clears RWU and wakes up. The receiver waits for the first frame of the next transmission. The byte is received normally, transferred to the RDR, and the RDRF flag is set. If software does not recognize the address, it can set RWU and put the receiver back to sleep. For idle-line wake-up to work, there must be a minimum of one frame of idle line between transmissions. There must be no idle time between frames within a transmission. Address-mark wake-up uses a special frame format to wake up the receiver. When the MSB of an address-mark frame is set, that frame contains address information. The first frame of each transmission must be an address frame. When the MSB of a frame is set, the receiver clears RWU and wakes up. The byte is received normally, transferred to the RDR, and the RDRF flag is set. If software does not recognize the address, it can set RWU and put the receiver back to sleep. Address-mark wake-up allows idle time between frames and eliminates idle time between transmissions. However, there is a loss of efficiency because of an additional bit-time per frame. 10.4.5.9 Internal Loop The LOOPS bit in SCCR1 controls a feedback path in the data serial shifter. When LOOPS is set, the SCI transmitter output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver must be enabled before entering loop mode. Freescale Semiconductor, Inc... MULTICHANNEL COMMUNICATION INTERFACE 10-22 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 10.5 MCCI Initialization After reset, the MCCI remains in an idle state. Several registers must be initialized before serial operations begin. A general sequence guide for initialization follows. A. Global 1. Configure MMCR a. Write an interrupt arbitration number greater than zero into the IARB field. b. Clear the STOP bit if it is not already cleared. 2. Interrupt vector and interrupt level registers (MIVR, ILSPI, and ILSCI) a. Write the SPI/SCI interrupt vector into MIVR. b. Write the SPI interrupt request level into the ILSPI and the interrupt request levels for the two SCI interfaces into the ILSCI. 3. Port data register a. Write a data word to PORTMC. b. Read a port pin state from PORTMCP. 4. Pin control registers a. Establish the direction of MCCI pins by writing to the MDDR. b. Assign pin functions by writing to the MPAR. B. Serial Peripheral Interface 1. Configure SPCR a. Write a transfer rate value into the BAUD field. b. Determine clock phase (CPHA) and clock polarity (CPOL). c. Specify an 8- or 16-bit transfer (SIZE) and MSB- or LSB-first transfer mode (LSBF). d. Select master or slave operating mode (MSTR). e. Enable or disable wired-OR operation (WOMP). f. Enable or disable SPI interrupts (SPIE). g. Enable the SPI by setting the SPE bit. C. Serial Communication Interface (SCIA/SCIB) 1. To transmit, read the SCSR, and then write transmit data to the SCDR. This clears the TDRE and TC indicators in the SCSR. a. SCI control register 0 (SCCR0) b. Write a baud rate value into the BR field. 2. Configure SCCR1 a. Select 8- or 9-bit frame format (M). b. Determine use (PE) and type (PT) of parity generation or detection. c. To receive, set the RE and RIE bits in SCCR1. Select use (RWU) and type (WAKE) of receiver wakeup. Select idle-line detection type (ILT) and enable or disable idle-line interrupt (ILIE). d. To transmit, set TE and TIE bits in SCCR1, and enable or disable WOMC and TCIE bits. Disable break transmission (SBK) for normal operation. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL MULTICHANNEL COMMUNICATION INTERFACE For More Information On This Product, Go to: www.freescale.com 10-23 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MULTICHANNEL COMMUNICATION INTERFACE 10-24 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SECTION 11 GENERAL-PURPOSE TIMER This section is an overview of the general-purpose timer (GPT) function. Refer to the GPT Reference Manual (GPTRM/AD) for complete information about the GPT module. 11.1 General The 11-channel general-purpose timer (GPT) is used in systems where a moderate level of CPU control is required. The GPT consists of a capture/compare unit, a pulse accumulator, and two pulse-width modulators. A bus interface unit connects the GPT to the intermodule bus (IMB). Figure 11-1 is a block diagram of the GPT. The capture/compare unit features three input capture channels, four output compare channels, and one channel that can be selected as input capture or output compare. These channels share a 16-bit free-running counter (TCNT) that derives its clock from a nine-stage prescaler or from the external clock input signal, PCLK. Pulse accumulator channel logic includes an 8-bit counter. The pulse accumulator can operate in either event counting mode or gated time accumulation mode. Pulse-width modulator outputs are periodic waveforms whose duty cycles can be independently selected and modified by user software. The PWM circuits share a 16-bit free-running counter that can be clocked by the same nine-stage prescaler used by the capture/compare unit or by the PCLK input. All GPT pins can also be used for general-purpose input/output. The input capture and output compare pins form a bidirectional 8-bit parallel port (port GP). PWM pins are outputs only. PAI and PCLK pins are inputs only. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-1 Freescale Semiconductor, Inc. IC1/PGP0 IC2/PGP1 IC3/PGP2 CAPTURE/COMPARE UNIT OC1/PGP3 OC2/OC1/PGP4 OC3/OC1/PGP5 OC4/OC1/PGP6 IC4/OC5/OC1/PGP7 PAI PULSE ACCUMULATOR PRESCALER PCLK PWM UNIT PWMA PWMB Freescale Semiconductor, Inc... BUS INTERFACE IMB GPT BLOCK Figure 11-1 GPT Block Diagram 11.2 GPT Registers and Address Map The GPT programming model consists of a configuration register (GPTMCR), parallel I/O registers (DDRGP, PORTGP), capture/compare registers (TCNT, TCTL1, TCTL2, TIC[1:3], TOC[1:4], TI4/O5, CFORC), pulse accumulator registers (PACNT, PACTL), pulse-width modulation registers (PWMA, PWMB, PWMC, PWMCNT, PWMBUFA, PWMBUFB), status registers (TFLG1, TFLG2) and interrupt control registers (TMSK1, TMSK2). Functions of the module configuration register are discussed in 11.3 Special Modes of Operation and 11.4 Polled and Interrupt-Driven Operation. Other register functions are discussed in the appropriate sections. All registers can be accessed using byte or word operations. Certain capture/compare registers and pulse-width modulation registers must be accessed by word operations to ensure coherency. If byte accesses are used to read a register such as the timer counter register (TCNT), there is a possibility that data in the byte not being accessed will change while the other byte is read. Both bytes must be accessed at the same time. The modmap (MM) bit in the system integration module configuration register (SIMCR) defines the most significant bit (ADDR23) of the IMB address for each register in the MCU. Because the CPU16 drives ADDR[23:20] to the same logic state as ADDR[19:0], MM must equal one. GENERAL-PURPOSE TIMER 11-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Refer to D.8 General-Purpose Timer for a GPT address map and register bit/field descriptions. Refer to 5.2.1 Module Mapping for more information about how the state of MM affects the system. 11.3 Special Modes of Operation The GPT module configuration register (GPTMCR) is used to control special GPT operating modes. These include low-power stop mode, freeze mode, single-step mode, and test mode. Normal GPT operation can be polled or interrupt-driven. Refer to 11.4 Polled and Interrupt-Driven Operation for more information. 11.3.1 Low-Power Stop Mode Low-power stop operation is initiated by setting the STOP bit in GPTMCR. In stop mode the system clock to the module is turned off. The clock remains off until STOP is negated or a reset occurs. All counters and prescalers within the timer stop counting while the STOP bit is set. Only the module configuration register (GPTMCR) and the interrupt configuration register (ICR) should be accessed while in the stop mode. Accesses to other GPT registers cause unpredictable behavior. Low-power stop can also be used to disable module operation during debugging. 11.3.2 Freeze Mode The freeze (FRZ[1:0]) bits in GPTMCR are used to determine what action is taken by the GPT when the IMB FREEZE signal is asserted. FREEZE is asserted when the CPU enters background debug mode. At the present time, FRZ1 is not implemented; FRZ0 causes the GPT to enter freeze mode. Refer to 4.14.4 Background Debug Mode for more information. Freeze mode freezes the current state of the timer. The prescaler and the pulse accumulator do not increment and changes to the pins are ignored (input pin synchronizers are not clocked). All of the other timer functions that are controlled by the CPU operate normally. For example, registers can be written to change pin directions, force output compares, and read or write I/O pins. While the FREEZE signal is asserted, the CPU has write access to registers and bits that are normally read-only or write-once. The write-once bits can be written to as often as needed. The prescaler and the pulse accumulator remain stopped and the input pins are ignored until the FREEZE signal is negated (the CPU is no longer in BDM), the FRZ0 bit is cleared, or the MCU is reset. Activities that are in progress before FREEZE assertion are completed. For example, if an input edge on an input capture pin is detected just as the FREEZE signal is asserted, the capture occurs and the corresponding interrupt flag is set. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-3 Freescale Semiconductor, Inc. 11.3.3 Single-Step Mode Two bits in GPTMCR support GPT debugging without using BDM. When the STOPP bit is asserted, the prescaler and the pulse accumulator stop counting and changes at input pins are ignored. Reads of the GPT pins return the state of the pin when STOPP was set. After STOPP is set, the INCP bit can be set to increment the prescaler and clock the input synchronizers once. The INCP bit is self-negating after the prescaler is incremented. INCP can be set repeatedly. The INCP bit has no effect when the STOPP bit is not set. 11.3.4 Test Mode Test mode is used during Freescale factory testing. The GPT has no dedicated testmode control register; all GPT testing is done under control of the system integration module. 11.4 Polled and Interrupt-Driven Operation Normal GPT function can be polled or interrupt-driven. All GPT functions have an associated status flag and an associated interrupt. The timer interrupt flag registers (TFLG1 and TFLG2) contain status flags used for polled and interrupt-driven operation. The timer mask registers (TMSK1 and TMSK2) contain interrupt control bits. Control routines can monitor GPT operation by polling the status registers. When an event occurs, the control routine transfers control to a service routine that handles that event. If interrupts are enabled for an event, the GPT requests interrupt service when the event occurs. Using interrupts does not require continuously polling the status flags to see if an event has taken place. However, to disable the interrupt request, status flags must be cleared after an interrupt is serviced. 11.4.1 Polled Operation When an event occurs in the GPT, that event sets a status flag in TFLG1 or TFLG2. The GPT sets the flags; they cannot be set by the CPU. TFLG1 and TFLG2 are 8-bit registers that can be accessed individually or as one 16-bit register. The registers are initialized to zero at reset. Table 11-1 shows status flag assignment. Freescale Semiconductor, Inc... GENERAL-PURPOSE TIMER 11-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table 11-1 GPT Status Flags Flag Mnemonic IC1F IC2F IC3F OC1F OC2F OC3F OC4F I4/O5F TOF Register Assignment TFLG1 TFLG1 TFLG1 TFLG1 TFLG1 TFLG1 TFLG1 TFLG1 TFLG2 TFLG2 TFLG2 Source Input capture 1 Input capture 2 Input capture 3 Output compare 1 Output compare 2 Output compare 3 Output compare 4 Input capture 4/output compare 5 Timer overflow Pulse accumulator overflow Pulse accumulator input Freescale Semiconductor, Inc... PAOVF PAIF For each bit in TFLG1 and TFLG2 there is a corresponding bit in TMSK1 and TMSK2 in the same bit position. If a mask bit is set and an associated event occurs, a hardware interrupt request is generated. In order to re-enable a status flag after an event occurs, the status flags must be cleared. Status registers are cleared in a particular sequence. The register must first be read for set flags, then zeros must be written to the flags that are to be cleared. If a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared. 11.4.2 GPT Interrupts The GPT has 11 internal sources that can cause it to request interrupt service (refer to Table 11-2). Setting bits in TMSK1 and TMSK2 enables specific interrupt sources. TMSK1 and TMSK2 are 8-bit registers that can be addressed individually or as one 16-bit register. The registers are initialized to zero at reset. For each bit in TMSK1 and TMSK2 there is a corresponding bit in TFLG1 and TFLG2 in the same bit position. TMSK2 also controls the operation of the timer prescaler. Refer to 11.7 Prescaler for more information. The value of the interrupt priority level (IPL[2:0]) field in the interrupt control register (ICR) determines the priority of GPT interrupt requests. IPL[2:0] values correspond to MCU interrupt request signals IRQ[7:1]. IRQ7 is the highest priority interrupt request signal; IRQ1 is the lowest-priority signal. A value of %111 causes IRQ7 to be asserted when a GPT interrupt request is made; lower field values cause corresponding lowerpriority interrupt request signals to be asserted. Setting field value to %000 disables interrupts. M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-5 Freescale Semiconductor, Inc. Table 11-2 GPT Interrupt Sources Name — IC1 IC2 IC3 OC1 OC2 OC3 OC4 IC4/OC5 TO PAOV PAI Source Number 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Source Adjusted channel Input capture 1 Input capture 2 Input capture 3 Output compare 1 Output compare 2 Output compare 3 Output compare 4 Input capture 4/output compare 5 Timer overflow Pulse accumulator overflow Pulse accumulator input Vector Number IVBA : 0000 IVBA : 0001 IVBA : 0010 IVBA : 0011 IVBA : 0100 IVBA : 0101 IVBA : 0110 IVBA : 0111 IVBA : 1000 IVBA : 1001 IVBA : 1010 IVBA : 1011 Freescale Semiconductor, Inc... The CPU16 recognizes only interrupt request signals of a priority greater than the condition code register interrupt priority (IP) mask value. When the CPU acknowledges an interrupt request, the priority of the acknowledged request is written to the IP mask and driven out on the IMB address lines. When the IP mask value driven out on the address lines is the same as the IRL value, the GPT contends for arbitration priority. GPT arbitration priority is determined by the value of IARB[3:0] in GPTMCR. Each MCU module that can make interrupt requests must be assigned a non-zero IARB value to implement an arbitration scheme. Arbitration is performed by serial assertion of IARB[3:0] bit values. When the GPT wins interrupt arbitration, it responds to the CPU interrupt acknowledge cycle by placing an interrupt vector number on the data bus. The vector number is used to calculate displacement into the CPU16 exception vector table. Vector numbers are formed by concatenating the value in ICR IVBA[3:0] with a 4-bit value supplied by the GPT when an interrupt request is made. Hardware prevents the vector number from changing while it is being driven out on the IMB. Vector number assignment is shown in Table 11-2. At reset, IVBA[3:0] is initialized to $0. To enable interrupt-driven timer operation, the upper nibble of a user-defined vector number ($40 – $FF) must be written to IVBA, and interrupt handler routines must be located at the addresses pointed to by the corresponding vector. NOTE IVBA[3:0] must be written before GPT interrupts are enabled, or the GPT could supply a vector number ($00 to $0F) that corresponds to an assigned or reserved exception vector. The internal GPT interrupt priority hierarchy is shown in Table 11-2. The lower the interrupt source number, the higher the priority. A single GPT interrupt source can be given priority over all other GPT interrupt sources by assigning the priority adjust field (IPA[3:0]) in the ICR a value equal to its source number. GENERAL-PURPOSE TIMER 11-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Interrupt requests are asserted until associated status flags are cleared. Status flags must be cleared in a particular sequence. The status register must first be read for set flags, then zeros must be written to the flags that are to be cleared. If a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared. For more information on interrupts, refer to 5.8 Interrupts. For more information on exceptions, refer to 4.13.4 Types of Exceptions. 11.5 Pin Descriptions The GPT uses 12 of the MCU pins. Each pin can perform more than one function. Descriptions of GPT pins divided into functional groups follow. Freescale Semiconductor, Inc... 11.5.1 Input Capture Pins Each input capture pin is associated with a single GPT input capture function. Each pin has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored. Each pin has an associated 16-bit capture register that holds the captured counter value. These pins can also be used for general-purpose I/O. Refer to 11.8.2 Input Capture Functions for more information. 11.5.2 Input Capture/Output Compare Pin The input capture/output compare pin can be configured for use by either an input capture or an output compare function. It has an associated 16-bit register that is used for holding either the input capture value or the output match value. When used for input capture the pin has the same hysteresis as other input capture pins. The pin can be used for general-purpose I/O. Refer to 11.8.2 Input Capture Functions and 11.8.3 Output Compare Functions for more information. 11.5.3 Output Compare Pins Output compare pins are used for GPT output compare functions. Each pin has an associated 16-bit compare register and a 16-bit comparator. Pins OC2, OC3, and OC4 are associated with a specific output compare function. The OC1 function can affect the output of all compare pins. If the OC1 pin is not needed for an output compare function it can be used to output the clock selected for the timer counter register. Any of these pins can also be used for general-purpose I/O. Refer to 11.8.3 Output Compare Functions for more information. 11.5.4 Pulse Accumulator Input Pin The pulse accumulator input (PAI) pin connects a discrete signal to the pulse accumulator for timed or gated pulse accumulation. PAI has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored. It can be used as a general-purpose input pin. Refer to 11.10 Pulse Accumulator for more information. M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-7 Freescale Semiconductor, Inc. 11.5.5 Pulse-Width Modulation Pulse-width modulation (PWMA/B) pins carry pulse-width modulator outputs. The modulators can be programmed to generate a periodic waveform of variable frequency and duty cycle. PWMA can be used to output the clock selected as the input to the PWM counter. These pins can also be used for general-purpose output. Refer to 11.11 Pulse-Width Modulation Unit for more information. 11.5.6 Auxiliary Timer Clock Input The auxiliary timer clock input (PCLK) pin connects an external clock to the GPT. The external clock can be used as the clock source for the capture/compare unit or the PWM unit in place of one of the prescaler outputs. PCLK has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored. This pin can also be used as a general-purpose input pin. Refer to 11.7 Prescaler for more information. 11.6 General-Purpose I/O Any GPT pin can be used for general-purpose I/O when it is not used for another purpose. Capture/compare pins are bidirectional, others can be used only for output or input. I/O direction is controlled by a data direction bit in the port GP data direction register (DDRGP). Parallel data is read from and written to the port GP data register (PORTGP). Pin data can be read even when pins are configured for a timer function. Data read from PORTGP always reflects the state of the external pin, while data written to PORTGP may not always affect the external pin. Data written to PORTGP does not immediately affect pins used for output compare functions, but the data is latched. When an output compare function is disabled, the last data written to PORTGP is driven out on the associated pin if it is configured as an output. Data written to PORTGP can cause input captures if the corresponding pin is configured for input capture function. The pulse accumulator input (PAI) and the external clock input (PCLK) pins provide general-purpose input. The state of these pins can be read by accessing the PAIS and PCLKS bits in the pulse accumulator control register (PACTL). Pulse-width modulation A and B (PWMA/B) output pins can serve as general-purpose outputs. The force PWM value (FPWMx) and the force logic one (F1x) bits in the compare force (CFORC) and PWM control (PWMC) registers, respectively, control their operation. 11.7 Prescaler Capture/compare and PWM units have independent 16-bit free-running counters as a main timing component. These counters derive their clocks from the prescaler or from the PCLK input. Figure 11-2 is a prescaler block diagram. Freescale Semiconductor, Inc... GENERAL-PURPOSE TIMER 11-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SYSTEM CLOCK DIVIDER 128 256 512 512 EXT. TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR 16 32 64 2 4 8 CPR2 CPR1 CPR0 Freescale Semiconductor, Inc... 256 128 64 32 16 8 4 EXT. SELECT TO CAPTURE/ COMPARE TIMER 128 64 32 16 8 4 2 EXT. SELECT TO PWM UNIT PCLK PIN SYNCHRONIZER AND DIGITAL FILTER PPR2 PPR1 PPR0 GPT PRE BLOCK Figure 11-2 Prescaler Block Diagram In the prescaler, the system clock is divided by a nine-stage divider chain. Prescaler outputs equal to system clock divided by 2, 4, 8, 16, 32, 64, 128, 256 and 512 are provided. Connected to these outputs are two multiplexers, one for the capture/compare unit, the other for the PWM unit. Multiplexers can each select one of seven prescaler taps or an external input from the PCLK pin. Multiplexer output for the timer counter (TCNT) is selected by bits CPR[2:0] in timer interrupt mask register 2 (TMSK2). Multiplexer output for the PWM counter (PWMCNT) is selected by bits PPR[2:0] in PWM control register C (PWMC). After reset, the GPT is configured to use system clock divided by four for TCNT and system clock divided by two for PWMCNT. Initialization software can change the division factor. The PPR bits can be written at any time, but the CPR bits can only be written once after reset, unless the GPT is in test or freeze mode. M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-9 Freescale Semiconductor, Inc. The prescaler can be read at any time. In freeze mode the prescaler can also be written. Word accesses must be used to ensure coherency. If coherency is not needed byte accesses can be used. The prescaler value is contained in bits [8:0] while bits [15:9] are unimplemented and are read as zeros. Multiplexer outputs (including the PCLK signal) can be connected to external pins. The CPROUT bit in the TMSK2 register configures the OC1pin to output the TCNT clock and the PPROUT bit in the PWMC register configures the PWMA pin to output the PWMC clock. CPROUT and PPROUT can be written at any time. Clock signals on OC1 and PWMA do not have a 50% duty cycle. They have the period of the selected clock but are high for only one system clock time. The prescaler also supplies three clock signals to the pulse accumulator clock select mux. These are the system clock divided by 512, the external clock signal from the PCLK pin and the capture/compare clock signal. 11.8 Capture/Compare Unit The capture/compare unit contains the timer counter (TCNT), the input capture (IC) functions and the output compare (OC) functions. Figure 11-3 is a block diagram of the capture/compare unit. 11.8.1 Timer Counter The timer counter (TCNT) is the key timing component in the capture/compare unit. The timer counter is a 16-bit free-running counter that starts counting after the processor comes out of reset. The counter cannot be stopped during normal operation. After reset, the GPT is configured to use the system clock divided by four as the input to the counter. The prescaler divides the system clock and provides selectable input frequencies. User software can configure the system to use one of seven prescaler outputs or an external clock. The counter can be read any time without affecting its value. Because the GPT is interfaced to the IMB, and the IMB supports a 16-bit bus, a word read gives a coherent value. If coherency is not needed, byte accesses can be made. The counter is set to $0000 during reset and is normally a read-only register. In test mode and freeze mode, any value can be written to the timer counter. When the counter rolls over from $FFFF to $0000, the timer overflow flag (TOF) in timer interrupt flag register 2 (TFLG2) is set. An interrupt can be enabled by setting the corresponding interrupt enable bit (TOI) in timer interrupt mask register 2 (TMSK2). Refer to 11.4.2 GPT Interrupts for more information. 11.8.2 Input Capture Functions All GPT input capture functions use the same 16-bit timer counter (TCNT). Each input capture pin has a dedicated 16-bit latch and input edge-detection/selection logic. Each input capture function has an associated status flag, and can cause the GPT to make an interrupt service request. When a selected edge transition occurs on an input capture pin, the associated 16-bit latch captures the content of TCNT and sets the appropriate status flag. An interrupt request can be generated when the transition is detected. GENERAL-PURPOSE TIMER 11-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. PCLK SYSTEM CLOCK PRESCALER – DIVIDE BY 4, 8, 16, 32, 64, 128, 256 1 OF 8 SELECT CPR2 CPR1 CPR0 TCNT (HI) TCNT (LO) TOI 9 TOF 16-BIT FREE RUNNING COUNTER INTERRUPT REQUESTS 16-BIT TIMER BUS IC1I 16-BIT LATCH CLK TIC1 (HI) TIC1 (LO) IC2F IC3I IC3F OC1I 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) OC1F FOC1 OC2I 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) OC2F FOC2 OC3I 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) OC3F FOC3 OC4I 16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO) OC4F FOC4 I4/O5I 16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH CLK I4/O5 TFLG1 STATUS FLAGS 16/32 CC BLOCK PIN FUNCTIONS 1 BIT 0 PGP0 IC1 PGP1 IC2 PGP2 IC3 IC1F IC2I 2 Freescale Semiconductor, Inc... 16-BIT LATCH CLK TIC2 (HI) TIC2 (LO) BIT 1 3 BIT 2 4 BIT 3 5 BIT 4 6 BIT 5 7 BIT 6 8 BIT 7 16-BIT LATCH CLK TIC3 (HI) TIC3 (LO) PGP3 OC1 PGP4 OC2/OC1 PGP5 OC3/OC1 PGP6 OC4/OC1 OC5 I4/O5F IC4 CFORC FORCE OUTPUT COMPARE FOC5 PGP7 IC4/OC5/ OC1 TMSK1 INTERRUPT ENABLES PARALLEL PORT PIN CONTROL Figure 11-3 Capture/Compare Unit Block Diagram M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-11 Freescale Semiconductor, Inc. Edge-detection logic consists of control bits that enable edge detection and select a transition to detect. The EDGExA/B bits in timer control register 2 (TCTL2) determine whether the input capture functions detect rising edges only, falling edges only, or both rising and falling edges. Clearing both bits disables the input capture function. Input capture functions operate independently of each other and can capture the same TCNT value if individual input edges are detected within the same timer count cycle. Input capture interrupt logic includes a status flag, which indicates that an edge has been detected, and an interrupt enable bit. An input capture event sets the ICxF bit in the timer interrupt flag register 1 (TFLG1) and causes the GPT to make an interrupt request if the corresponding ICxI bit is set in the timer interrupt mask register 1 (TMSK1). If the ICxI bit is cleared, software must poll the status flag to determine that an event has occurred. Refer to 11.4 Polled and Interrupt-Driven Operation for more information. Input capture events are generally asynchronous to the timer counter. Because of this, input capture signals are conditioned by a synchronizer and digital filter. Events are synchronized with the system clock and digital filter. Events are synchronized with the system clock so that latching of TCNT content and counter incrementation occur on opposite half-cycles of the system clock. Inputs have hysteresis. Capture of any transition longer than two system clocks is guaranteed; any transition shorter than one system clock has no effect. Figure 11-4 shows the relationship of system clock to synchronizer output. The value latched into the capture register is the value of the counter several system clock cycles after the transition that triggers the edge detection logic. There can be up to one clock cycle of uncertainty in latching of the input transition. Maximum time is determined by the system clock frequency. The input capture register is a 16-bit register. A word access is required to ensure coherency. If coherency is not required, byte accesses can be used to read the register. Input capture registers can be read at any time without affecting their values. Freescale Semiconductor, Inc... GENERAL-PURPOSE TIMER 11-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. F clock (PHI1)1 CAPTURE/COMPARE CLOCK TCNT $0101 $0102 EXTERNAL PIN SYNCHRONIZER OUTPUT Freescale Semiconductor, Inc... CAPTURE REGISTER $0102 ICxF FLAG NOTES: PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 16/32 IC TIM Figure 11-4 Input Capture Timing Example An input capture occurs every time a selected edge is detected, even when the input capture status flag is set. This means that the value read from the input capture register corresponds to the most recent edge detected, which may not be the edge that caused the status flag to be set. 11.8.3 Output Compare Functions Each GPT output compare pin has an associated 16-bit compare register and a 16-bit comparator. Each output compare function has an associated status flag, and can cause the GPT to make an interrupt service request. Output compare logic is designed to prevent false compares during data transition times. When the programmed content of an output compare register matches the value in TCNT, an output compare status flag (OCxF) bit in TFLG1 is set. If the appropriate interrupt enable bit (OCxI) in TMSK1 is set, an interrupt request is made when a match occurs. Refer to 11.4.2 GPT Interrupts for more information. Operation of output compare 1 differs from that of the other output compare functions. OC1 control logic can be programmed to make state changes on other OC pins when an OC1 match occurs. Control bits in the timer compare force register (CFORC) allow for early forced compares. M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-13 Freescale Semiconductor, Inc. 11.8.3.1 Output Compare 1 Output compare 1 can affect any or all of OC[5:1] when an output match occurs. In addition to allowing generation of multiple control signals from a single comparison operation, this function makes it possible for two or more output compare functions to control the state of a single OC pin. Output pulses as short as one timer count can be generated in this way. The OC1 action mask register (OC1M) and the OC1 action data register (OC1D) control OC1 function. Setting a bit in OC1M selects a corresponding bit in the GPT parallel data port. Bits in OC1D determine whether selected bits are to be set or cleared when an OC1 match occurs. Pins must be configured as outputs in order for the data in the register to be driven out on the corresponding pin. If an OC1 match and another output match occur at the same time and both attempt to alter the same pin, the OC1 function controls the state of the pin. 11.8.3.2 Forced Output Compare Timer compare force register (CFORC) is used to make forced compares. The action taken as a result of a forced compare is the same as when an output compare match occurs, except that status flags are not set. Forced channels take programmed actions immediately after the write to CFORC. The CFORC register is implemented as the upper byte of a 16-bit register which also contains the PWM control register C (PWMC). It can be accessed as eight bits or a word access can be used. Reads of force compare bits (FOC) have no meaning and always return zeros. These bits are self-negating. 11.9 Input Capture 4/Output Compare 5 The IC4/OC5 pin can be used for input capture, output compare, or general-purpose I/O. A function enable bit (I4/O5) in the pulse accumulator control register (PACTL) configures the pin for input capture (IC4) or output compare function (OC5). Both bits are cleared during reset, configuring the pin as an input, but also enabling the OC5 function. IC4/OC5 I/O functions are controlled by DDGP7 in the port GP data direction register (DDRGP). The 16-bit register (TI4/O5) used with the IC4/OC5 function acts as an input capture register or as an output compare register depending on which function is selected. When used as the input capture 4 register, it cannot be written to except in test or freeze mode. 11.10 Pulse Accumulator The pulse accumulator counter (PACNT) is an 8-bit read/write up-counter. PACNT can operate in external event counting or gated time accumulation modes. Figure 11-5 is a block diagram of the pulse accumulator. Freescale Semiconductor, Inc... GENERAL-PURPOSE TIMER 11-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 10 INTERRUPT REQUESTS 11 PAOVF EDGE DETECT LOGIC 2:1 MUX PAOVI TMSK2 Freescale Semiconductor, Inc... PAI SYNCHRONIZER & DIGITAL FILTER OVERFLOW PACNT 8-BIT COUNTER ENABLE PAMOD PACTL PACLK1 PACLK0 PCLKS PEDGE PAEN PAIS PCLK TCNT OVERFLOW CAPTURE/COMPARE CLK PRESCALER 512 MUX INTERNAL DATA BUS PAIF TFLG2 PAII 16/32 PULSE ACC BLOCK Figure 11-5 Pulse Accumulator Block Diagram In event counting mode, the counter increments each time a selected transition of the pulse accumulator input (PAI) pin is detected. The maximum clocking rate is the system clock divided by four. In gated time accumulation mode a clock increments PACNT while the PAI pin is in the active state. There are four possible clock sources. Two bits in the TFLG2 register show pulse accumulator status. The pulse accumulator flag (PAIF) indicates that a selected edge has been detected at the PAI pin. The pulse accumulator overflow flag (PAOVF) indicates that the pulse accumulator count has rolled over from $FF to $00. This can be used to extend the range of the counter beyond eight bits. M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-15 Freescale Semiconductor, Inc. An interrupt request can be made when each of the status flags is set. However, operation of the PAI interrupt depends on operating mode. In event counting mode, an interrupt is requested when the edge being counted is detected. In gated mode, the request is made when the PAI input changes from active to inactive state. Interrupt requests are enabled by the PAOVI and PAII bits in the TMSK2 register. Bits in the pulse accumulator control register (PACTL) control the operation of PACNT. The PAMOD bit selects event counting or gated operation. In event counting mode, the PEDGE control bit determines whether a rising or falling edge is detected. In gated mode, PEDGE specifies the active state of the gate signal. Bits PACLK[1:0] select the clock source used in gated mode. PACTL and PACNT are implemented as one 16-bit register, but can be accessed with byte or word access cycles. Both registers are cleared at reset, but the PAIS and PCLKS bits show the state of the PAI and PCLK pins. The PAI pin can also be used for general-purpose input. The logic state of the PAIS bit in PACTL shows the state of the pin. 11.11 Pulse-Width Modulation Unit The pulse-width modulation (PWM) unit has two output channels, PWMA and PWMB. A single clock output from the prescaler multiplexer drives a 16-bit counter that is used to control both channels. Figure 11-6 is a block diagram of the pulse-width modulation unit. Freescale Semiconductor, Inc... GENERAL-PURPOSE TIMER 11-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 16-BIT DATA BUS PWMA REGISTER PWMB REGISTER PWMBUFA REGISTER PWMBUFB REGISTER Freescale Semiconductor, Inc... "A" COMPARATOR "B" COMPARATOR PWMA PIN R LATCH S 8-BIT 8-BIT R LATCH S PWMB PIN F1A BIT ZERO DETECTOR ZERO DETECTOR F1B BIT SFA BIT "A" MULTIPLEXER "B" MULTIPLEXER SFB BIT 16-BIT COUNTER [14:0] FROM PRESCALER CLOCK 16/32 PWM BLOCK Figure 11-6 PWM Block Diagram The PWM unit has two operational modes. Fast mode uses a clocking rate that equals 1/256 of the prescaler output rate; slow mode uses a rate equal to 1/32768 of the prescaler output rate. The duty cycle ratios of the two PWM channels can be individually controlled by software. The PWMA pin can also output the clock that drives the PWM counter. PWM pins can also be used as output pins. M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-17 Freescale Semiconductor, Inc. 11.11.1 PWM Counter The 16-bit counter in the PWM unit is similar to the timer counter in the capture/compare unit. During reset, the GPT is configured to use the system clock divided by two to drive the counter. Initialization software can reconfigure the counter to use one of seven prescaler outputs or an external clock input from the PCLK pin. The PWM count register (PWMCNT) can be read at any time without affecting its value. A read must be a word access to ensure coherence, but byte accesses can be made if coherence is not needed. The counter is cleared to $0000 during reset and is a read-only register except in freeze or test mode. Fifteen of the sixteen counter bits are output to multiplexers A and B. The multiplexers provide the fast and slow modes of the PWM unit. Mode for PWMA is selected by the SFA bit in the PWM control register C (PWMC). Mode for PWMB is selected by the SFB bit in the same register. PWMA, PWMB, and PPR[2:0] bits in PWMC control PWM output frequency. In fast mode, bits [7:0] of PWMCNT are used to clock the PWM logic; in slow mode, bits [14:7] are used. The period of a PWM output in slow mode is 128 times longer than the fast mode period. Table 11-3 shows a range of PWM output frequencies using 16.78 MHz, 20.97 MHz, and 25.17 MHz system clocks. Table 11-3 PWM Frequency Ranges PPR [2:0] 000 001 010 011 100 101 110 111 Prescaler Tap 16.78 MHz Div 2 = 8.39 MHz Div 4 = 4.19 MHz Div 8 = 2.10 MHz 20.97 MHz Div 2 = 10.5 MHz Div 4 = 5.25 MHz Div 8 = 2.62 MHz 25.17 MHz Div 2 = 12.6 MHz Div 4 = 6.29 MHz Div 8 = 3.15 MHz SFA/B = 0 16.78 MHz 20.97 MHz 25.17 MHz 32.8 kHz 16.4 kHz 8.19 kHz 4.09 kHz 2.05 kHz 1.02 kHz 512 Hz PCLK/256 41 kHz 20.5 kHz 10.2 kHz 5.15 kHz 2.56 kHz 1.28 kHz 641 Hz PCLK/256 49.2 kHz 24.6 kHz 12.3 kHz 6.13 kHz 3.07 kHz 1.54 kHz 770 Hz PCLK/256 16.78 MHz 256 Hz 128 Hz 64.0 Hz 32.0 Hz 16.0 Hz 8.0 Hz 4.0 Hz PCLK/ 32768 SFA/B = 1 20.97 MHz 320 Hz 160 Hz 80.0 Hz 40.0 Hz 20.0 Hz 10.0 Hz 5.0 Hz PCLK/ 32768 25.17 MHz 384 Hz 192 Hz 96 Hz 48 Hz 24 Hz 12 Hz 6 Hz PCLK/ 32768 Freescale Semiconductor, Inc... Div 16 = 1.05 MHz Div 16 = 1.31 MHz Div 16 = 1.57 MHz Div 32 = 524 kHz Div 64 = 262 kHz Div 128 = 131 kHz PCLK Div 32 = 655 kHz Div 64 = 328 kHz Div 128 = 164 kHz PCLK Div 32 = 787 kHz Div 64 = 393 kHz Div 128 = 197 kHz PCLK 11.11.2 PWM Function The pulse width values of the PWM outputs are determined by control registers PWMA and PWMB. PWMA and PWMB are 8-bit registers implemented as two bytes of a 16bit register. PWMA and PWMB can be accessed as separate bytes or as one 16-bit register. A value of $00 loaded into either register causes the corresponding output pin to output a continuous logic level zero signal. A value of $80 causes the corresponding output signal to have a 50% duty cycle, and so on, to the maximum value of $FF, which corresponds to an output which is at logic level one for 255/256 of the cycle. Setting the F1A (for PWMA) or F1B (for PWMB) bits in the CFORC register causes the corresponding pin to output a continuous logic level one signal. The logic level of the associated pin does not change until the end of the current cycle. F1A and F1B are the lower two bits of CFORC, but can be accessed at the same word address as PWMC. GENERAL-PURPOSE TIMER 11-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Data written to PWMA and PWMB is not used until the end of a complete cycle. This prevents spurious short or long pulses when register values are changed. The current duty cycle value is stored in the appropriate PWM buffer register (PWMBUFA or PWMBUFB). The new value is transferred from the PWM register to the buffer register at the end of the current cycle. Registers PWMA, PWMB, and PWMC are reset to $00 during reset. These registers may be written or read at any time. PWMC is implemented as the lower byte of a 16bit register. The upper byte is the CFORC register. The buffer registers, PWMBUFA and PWMBUFB, are read-only at all times and may be accessed as separate bytes or as one 16-bit register. Pins PWMA and PWMB can also be used for general-purpose output. The values of the F1A and F1B bits in PWMC are driven out on the corresponding PWM pins when normal PWM operation is disabled. When read, the F1A and F1B bits reflect the states of the PWMA and PWMB pins. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL GENERAL-PURPOSE TIMER For More Information On This Product, Go to: www.freescale.com 11-19 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... GENERAL-PURPOSE TIMER 11-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. APPENDIX A ELECTRICAL CHARACTERISTICS Table A-1 Maximum Ratings Num 1 2 3 Supply Voltage Rating 1, 2, 3 Symbol VDD VIN ID Value – 0.3 to +6.5 – 0.3 to +6.5 25 Unit V V mA Input Voltage 1, 2, 3, 4, 5, 7 Instantaneous Maximum Current Single Pin Limit (applies to all pins)1, 3, 5, 6 Operating Maximum Current Digital Input Disruptive Current3, 5, 6, 7, 8 VNEGCLAMP ≈ –0.3 V VPOSCLAMP ≈ VDD + 0.3 V Operating Temperature Range “C” Suffix “V” Suffix “M” Suffix Storage Temperature Range 4 IiD – 500 to +500 µA Freescale Semiconductor, Inc... 5 TA Tstg TL to TH – 40 to +85 – 40 to +105 – 40 to +125 – 55 to +150 °C °C 6 NOTES: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3. This parameter is periodically sampled rather than 100% tested. 4. All pins except TSC. 5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current. 7. All functional non-supply pins are internally clamped to VSS. All functional pins except EXTAL, TSC, and XFC are internally clamped to VDD. 8. Total input current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-1 Freescale Semiconductor, Inc. Table A-2 Typical Ratings, 2.7 to 3.6V, 16.78-MHz Operation Num 1 2 Supply Voltage Operating Temperature VDD Supply Current RUN LPSTOP, VCO off LPSTOP, External clock, max fsys Clock Synthesizer Operating Voltage VDDSYN Supply Current 4.194 MHz VCO on, maximum fsys 32.768 kHz VCO on, maximum fsys 4.194 MHz External Clock, maximum fsys 32.768 kHz External Clock, maximum fsys 4.194 MHz LPSTOP, VCO off 32.768 kHz LPSTOP, VCO off 4.194 MHz VDD powered down 32.768 kHz VDD powered down RAM Standby Voltage RAM Standby Current Normal RAM operation Standby operation Power Dissipation Rating Symbol VDD TA Value 3.0 25 38 70 1 3.0 TBD 200 TBD 1 TBD 20 TBD 10 3 3 3 120 Unit V °C mA µA mA V mA µA µA mA mA µA µA µA V µA µA mW 3 IDD 4 VDDSYN Freescale Semiconductor, Inc... 5 IDDSYN 6 7 8 VSB ISB PD ELECTRICAL CHARACTERISTICS A-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-3 Typical Ratings, 5V, 16.78-MHz Operation Num 1 2 Supply Voltage Operating Temperature VDD Supply Current RUN LPSTOP, VCO off LPSTOP, External clock, maximum fsys Clock Synthesizer Operating Voltage VDDSYN Supply Current VCO on, maximum fsys External Clock, maximum fsys LPSTOP, VCO off VDD powered down RAM Standby Voltage RAM Standby Current Normal RAM operation Standby operation Power Dissipation Rating Symbol VDD TA Value 5.0 25 65 125 3 5.0 1.0 3.0 100 50 5.0 1.0 1.0 380 Unit V °C mA µA mA V mA mA µA µA V µA µA mW 3 IDD 4 VDDSYN 5 IDDSYN Freescale Semiconductor, Inc... 6 7 8 VSB ISB PD Table A-4 Typical Ratings, 20.97-MHz Operation Num 1 2 Supply Voltage Operating Temperature VDD Supply Current RUN LPSTOP, VCO off LPSTOP, External clock, maximum fsys Clock Synthesizer Operating Voltage VDDSYN Supply Current VCO on, maximum fsys External Clock, maximum fsys LPSTOP, VCO off VDD powered down RAM Standby Voltage RAM Standby Current Normal RAM operation Standby operation Power Dissipation Rating Symbol VDD TA Value 5.0 25 95 125 3.75 5.0 1.0 4.0 100 50 5.0 1.0 1.0 480 Unit V °C mA µA mA V mA mA µA µA V µA µA mW 3 IDD 4 VDDSYN 5 IDDSYN 6 7 8 VSB ISB PD M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-3 Freescale Semiconductor, Inc. Table A-5 Typical Ratings, 25.17-MHz Num 1 2 Supply Voltage Operating Temperature VDD Supply Current RUN LPSTOP, VCO off LPSTOP, External clock, max fsys Clock Synthesizer Operating Voltage VDDSYN Supply Current VCO on, maximum fsys External Clock, maximum fsys LPSTOP, VCO off VDD powered down RAM Standby Voltage RAM Standby Current Normal RAM operation Standby operation Power Dissipation Rating Symbol VDD TA Value 5.0 25 110 125 3.75 5.0 1.0 5.0 100 50 5.0 1.0 1.0 555 Unit V °C mA µA mA V mA mA µA µA V µA µA mW 3 IDD VDDSYN 4 5 IDDSYN Freescale Semiconductor, Inc... 6 7 8 VSB ISB PD ELECTRICAL CHARACTERISTICS A-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-6 Thermal Characteristics Num 1 Characteristic Thermal Resistance Plastic 132-Pin Surface Mount Plastic 144-Pin Surface Mount Symbol ΘJA Value 38 49 Unit °C/W The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D × Θ JA ) (1) where: TA= Ambient Temperature, °C ΘJA= Package Thermal Resistance, Junction-to-Ambient, °C/W PD= PINT + PI/O PINT= IDD × VDD, Watts — Chip Internal Power PI/O= Power Dissipation on Input and Output Pins — User Determined For most applications PI/O < PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: Freescale Semiconductor, Inc... P D = K ÷ ( T J + 273 ° C ) (2) Solving equations 1 and 2 for K gives: K = P D × ( T A + 273 ° C ) + Θ JA × P D 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-5 Freescale Semiconductor, Inc. Table A-7 Low Voltage Clock Control Timing (VDD and VDDSYN = 2.7 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH) Num 1 Characteristic PLL Reference Frequency Range MC68CM16Z1 1 Symbol fref fref Min 3.2 20 20 dc Max 4.2 50 50 16.78 16.78 16.78 16.78 Unit MHz kHz kHz 2 PLL Reference Frequency Range MC68CK16Z1 MC68CK16Z4 1 3 System Frequency2 On-Chip PLL System Frequency Slow On-Chip PLL System Frequency Fast On-Chip PLL System Frequency External Clock Operation PLL Lock Time1, 7, 8, 9 Changing W or Y in SYNCR or exiting from LPSTOP3 Warm Start-Up4 Cold Start-Up (fast reference option only)5 VCO Frequency6 Limp Mode Clock Frequency SYNCR X bit = 0 SYNCR X bit = 1 CLKOUT Jitter1, 7, 8, 9, 10 Short term (5 µs interval) Long term (500 µs interval) fsys 4 (fref) 4 (fref) /128 dc MHz Freescale Semiconductor, Inc... 4 tlpll — 20 50 75 2 (fsys max) fsys max /2 fsys max 0.5 0.05 ms 5 6 fVCO flimp — — — –0.5 –0.05 ms MHz 7 Jclk % NOTES: 1. Refer to notes in Table A-10. ELECTRICAL CHARACTERISTICS A-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-8 16.78-MHz Clock Control Timing (VDD and VDDSYN = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH) Num Characteristic PLL Reference Frequency Range MC68HC16Z1 MC68HC16Z2 MC68HC16Z3 1 Symbol Minimum 25 3.2 3.2 dc Maximum 50 4.2 4.2 16.78 16.78 16.78 16.78 Unit kHz MHz MHz 1 fref 2 System Frequency2 On-Chip PLL System Frequency Slow On-Chip PLL System Frequency Fast On-Chip PLL System Frequency External Clock Operation PLL Lock Time1, 7, 8, 9 Changing W or Y in SYNCR or exiting from LPSTOP3 Warm Start-Up4 Cold Start-Up (fast reference option only)5 VCO Frequency6 Limp Mode Clock Frequency SYNCR X bit = 0 SYNCR X bit = 1 CLKOUT Jitter1, 7, 8, 9, 10 Short term (5 µs interval) Long term (500 µs interval) fsys 4 (fref) 4 (fref) /128 dc MHz Freescale Semiconductor, Inc... 3 tlpll — 20 50 75 2 (fsys max) fsys max /2 fsys max 0.5 0.05 ms 4 5 fVCO flimp — — — –0.5 –0.05 ms MHz 6 Jclk % NOTES: 1. Refer to notes in Table A-10. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-7 Freescale Semiconductor, Inc. Table A-9 20.97-MHz Clock Control Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH) Num Characteristic PLL Reference Frequency Range MC68HC16Z1 MC68HC16Z2 MC68HC16Z3 1 Symbol Minimum 20 3.2 3.2 dc Maximum 50 5.2 5.2 20.97 20.97 20.97 20.97 Unit kHz MHz MHz 1 fref 2 System Frequency2 On-Chip PLL System Frequency Slow On-Chip PLL System Frequency Fast On-Chip PLL System Frequency External Clock Operation PLL Lock Time1, 7, 8, 9 Changing W or Y in SYNCR or exiting from LPSTOP3 Warm Start-Up4 Cold Start-Up (fast reference option only)5 VCO Frequency6 Limp Mode Clock Frequency SYNCR X bit = 0 SYNCR X bit = 1 CLKOUT Jitter1, 7, 8, 9, 10 Short term (5 µs interval) Long term (500 µs interval) fsys 4 (fref) 4 (fref) /128 dc MHz Freescale Semiconductor, Inc... 3 tlpll — 20 50 75 2 (fsys max) fsys max /2 fsys max 1.0 0.5 ms 4 5 fVCO flimp — — — –1.0 –0.5 MHz MHz 6 Jclk % NOTES: 1. Refer to notes in Table A-10 ELECTRICAL CHARACTERISTICS A-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-10 25.17-MHz Clock Control Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH) Num Characteristic PLL Reference Frequency Range MC68HC16Z1 MC68HC16Z2 MC68HC16Z3 1 Symbol Min 20 3.2 3.2 dc Max 50 5.2 5.2 25.17 25.17 25.17 25.17 Unit kHz MHz MHz 1 fref 2 System Frequency2 On-Chip PLL System Frequency Slow On-Chip PLL System Frequency Fast On-Chip PLL System Frequency External Clock Operation PLL Lock Time1, 7, 8, 9 Changing W or Y in SYNCR or exiting from LPSTOP3 Warm Start-Up4 Cold Start-Up (fast reference option only)5 VCO Frequency6 Limp Mode Clock Frequency SYNCR X bit = 0 SYNCR X bit = 1 CLKOUT Jitter1, 7, 8, 9, 10 Short term (5 µs interval) Long term (500 µs interval) fsys 4 (fref) 4 (fref) /128 dc MHz Freescale Semiconductor, Inc... 3 tlpll — — — — — — –1.0 –0.05 20 50 75 2 (fsys max) fsys max/2 fsys max 1.0 0.5 ms 4 5 fVCO flimp MHz MHz 6 Jclk % NOTES: 1. The base configuration of the MC68HC16Z1, MC68CK16Z1, MC68HC16Z4, and the MC68CK16Z4 requires a 32.768 kHz crystal reference. The base configuration of the MC68CM16Z1, M68HC16Z2, and the MC68HC16Z3 requires a 4.194 MHz crystal reference. 2. All internal registers retain data at 0 Hz. 3. Assumes that VDDSYN and VDD are stable, that an external filter is attached to the XFC pin, and that the crystal oscillator is stable. 4. Assumes that VDDSYN is stable, that an external filter is attached to the XFC pin, and that the crystal oscillator is stable, followed by VDD ramp-up. Lock time is measured from VDD at specified minimum to RESET negated. 5. Cold start is measured from VDDSYN and VDD at specified minimum to RESET negated. 6. Internal VCO frequency (fVCO) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and fsys = fVCO ÷ 4. When X = 1, the divider is disabled, and fsys = fVCO ÷ 2. X must equal one when operating at maximum specified fsys. 7. This parameter is periodically sampled rather than 100% tested. 8. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total external resistance from the XFC pin due to external leakage must be greater than 15 MΩ to guarantee this specification. Filter network geometry can vary depending upon operating environment. 9. Proper layout procedures must be followed to achieve specifications. 10. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSS and variation in crystal oscillator frequency increase the Jclk percentage for a given interval. When jitter is a critical constraint on control system operation, this parameter should be measured during functional testing of the final system. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-9 Freescale Semiconductor, Inc. Table A-11 Low Voltage 16.78-MHz DC Characteristics (VDD and VDDSYN = 2.7 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH) Num 1 2 3 4 5 6 Input High Voltage Input Low Voltage Input Hysteresis 1 2 Characteristic Symbol VIH VIL VHYS Iin IOZ VOH VOL VOH Min 0.7 (VDD) VSS – 0.3 0.5 –2.5 –2.5 VDD –0.2 — VDD –0.5 Max VDD + 0.3 0.2 (VDD) — 2.5 2.5 — 0.2 — Unit V V V µA µA V V V Input Leakage Current Vin = VDD or VSS Input-only pins High Impedance (Off-State) Leakage Current2 Vin = VDD or VSS All input/output and output pins CMOS Output High Voltage2, 3 IOH = –10.0 µA Group 1, 2, 4 input/output and output pins CMOS Output Low Voltage2 IOL = 10.0 µA Group 1, 2, 4 input/output and output pins Output High Voltage2, 3 IOH = –0.4 mA Group 1, 2, 4 input/output and output pins Output Low Voltage2 IOL = 0.8 mA Group 1 I/O pins, CLKOUT, FREEZE/QUOT, IPIPE0 IOL = 2.6 mA Group 2 and group 4 I/O pins, CSBOOT, BG/CS IOL = 6 mA Group 3 Three State Control Input High Voltage Data Bus Mode Select Pull-up Current Vin = VIL Vin = VIH 4 Freescale Semiconductor, Inc... 7 8 9 VOL — — — 7.2 — –8 0.4 0.4 0.4 9.1 –95 — 50 2 260 3.0 23 3.6 2 2.5 2 2 655 2.5 150 70 VDD 3.6 V 10 11 VIHTSC IMSP IDD SIDD SIDD SIDD WIDD VDDSYN V µA 12 VDD Supply Current5 Run6 LPSTOP, 4.194 MHz crystal, VCO Off (STSIM = 0)7 LPSTOP, 32.768 kHz crystal, VCO Off (STSIM = 0)7 LPSTOP, external clock input frequency = max fsys WAIT8 Clock Synthesizer Operating Voltage MC68CM16Z1VDDSYN Supply Current4 VCO on, crystal reference, maximum fsys7 External clock, maximum fsys LPSTOP, 4.194 MHz crystal reference, VCO off (STSIM = 0)7 VDD powered down — — — — 2.7 — — — — — — — — 0.0 2.7 mA mA µA mA mA V mA mA mA mA µA mA µA µA V 13 14 IDDSYN MC68CK16Z1/Z4 VDDSYN Supply Current4 VCO on, crystal reference, maximum fsys7 14A External clock, maximum fsys LPSTOP, 32.768 kHz crystal reference, VCO off (STSIM = 0)7 32.768 kHz, VDD powered down 15 RAM Standby Voltage9 Specified VDD applied VDD = VSS MC68CK16Z1/Z4 RAM Standby Current4, 9, 10 Normal RAM operation VDD > VSB – 0.5 V Transient condition Standby operation VDD < VSS + 0.5 V IDDSYN VSB 16 VSB – 0.5 V ≥ VDD ≥ VSS + 0.5 V ISB — — — 10 3 50 µA mA µA ELECTRICAL CHARACTERISTICS A-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-11 Low Voltage 16.78-MHz DC Characteristics (Continued) (VDD and VDDSYN = 2.7 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH) Num 17 18 MC68CM16Z1/Z4 Power Input Capacitance All input-only pins All input/output pins Load Capacitance2 Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0 Group 2 I/O Pins and CSBOOT, BG/CS Group 3 I/O Pins Group 4 I/O Pins 2, 7 Characteristic Dissipation11 Symbol PD Cin Min — — — — — — — Max 191 10 20 90 100 100 100 Unit mW pF 19 CL pF NOTES: 1. Applies to: Port ADA [7:0] — AN[7:0] Port E [7:4] — SIZ[1:0], AS, DS Port F [7:0] — IRQ[7:1], MODCLK Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1 Port MCCI[7:0] — TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO BKPT/DSCLK, DSI/IPIPE1, PAI, PCLK, RESET, RXD, TSC 2. Input-Only Pins: EXTAL, TSC, BKPT/DSCLK, PAI, PCLK, RXD Output-Only Pins: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, DSO/IPIPE0, PWMA, PWMB Input/Output Pins: Group 1: Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1, DATA[15:0], DSI/IPIPE1 Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3] Port E[7:0] — SIZ[1:0], AS, DS, AVEC, DSACK[1:0] Port F[7:0] — IRQ[7:1], MODCLK Port MCCI[7:3] — TXD, PCS[3:1], PCS0/SS, ADDR23/CS10/ECLK Group 3: HALT, RESET Group 4: MISO, MOSI, SCK 3. Does not apply to HALT and RESET because they are open drain pins. Does not apply to port MCCI[7:0] (TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode. 4. Use of an active pulldown device is recommended. 5. Total operating current is the sum of the appropriate IDD, IDDSYN, ISB, and IDDA. 6. Current measured with system clock frequency of 16.78 MHz, all modules active. 7. This parameter is periodically sampled rather than 100% tested. 8. CPU16 in WAIT, all other modules inactive. 9. The RAM module will not switch into standby mode as long as VSB does not exceed VDD by more than 0.5 Volt. The RAM array cannot be accessed while the module is in standby mode. 10. When VDD is transitioning during a power up or power down sequence, and VSB is applied, current flows between the VSTBY and VDD pins, which causes standby current to increase toward the maximum transient condition specification. System noise on the VDD and VSTBY pins can contribute to this condition. 11. Power dissipation measured at specified system clock frequency, all modules active. Power dissipation can be calculated using the expression: PD = Maximum VDD (IDD + IDDSYN + ISB) + Maximum VDDA (IDDA) IDD includes supply currents for all device modules powered by VDD pins. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-11 Freescale Semiconductor, Inc. Table A-12 16.78-MHz DC Characteristics (VDD and VDDSYN = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH) Num 1 2 3 4 5 6 Input High Voltage Input Low Voltage Input Hysteresis1, 2 3, 4 Characteristic Symbol VIH VIL VHYS IIN IOZ VOH VOL VOH Min Max Unit V V V µA µA V V V 0.7 (VDD) VDD + 0.3 VSS – 0.3 0.2 (VDD) 0.5 –2.5 –2.5 VDD –0.2 — VDD –0.8 — 2.5 2.5 — 0.2 — Input Leakage Current Vin = VDD or VSS High Impedance (Off-State) Leakage Current 4, 5 Vin = VDD or VSS CMOS Output High Voltage 4, 6, 7 IOH = –10.0 µA CMOS Output Low Voltage 4, 8 IOL = 10.0 µA Output High Voltage 4, 6, 7 IOH = –0.8 mA Output Low Voltage4, 8 IOL = 1.6 mA IOL = 5.3 mA IOL = 12 mA Three State Control Input High Voltage Data Bus Mode Select Pull-Up Current Vin = VIL Vin = VIH 9, 10 Freescale Semiconductor, Inc... 7 8 9 VOL VIIHTSC IMSP — — — 1.6 (VDD) — –15 — — — — — — 4.5 — — — — — — — — 0.0 3.0 0.4 0.4 0.4 9.1 –120 — 110 350 5 113 2 10 5.5 1 5 150 100 2 7 2 2 5.5 5.5 V 10 11 V µA 12 MC68HC16Z1 VDD Supply Current11, 12, 13 Run LPSTOP, crystal, VCO Off (STSIM = 0) LPSTOP, external clock input frequency = maximum fsys IDD mA µA mA mA mA mA V mA mA µA µA mA mA mA mA V MC68HC16Z2/Z3 VDD Supply Current11, 12, 13 Run 12A LPSTOP, crystal, VCO Off (STSIM = 0) LPSTOP, external clock input frequency = maximum fsys 13 Clock Synthesizer Operating Voltage MC68HC16Z1 VDDSYN Supply Current VCO on, crystal reference, maximum fsys External clock, maximum fsys LPSTOP, crystal reference, VCO off (STSIM = 0) VDD powered down 11, 13 IDD VDDSYN 14 IDDSYN MC68HC16Z2/Z3 VDDSYN Supply Current11, 13 VCO on, crystal reference, maximum fsys 14A External clock, maximum fsys LPSTOP, crystal reference, VCO off (STSIM = 0) VDD powered down 15 RAM Standby Voltage14 Specified VDD applied VDD = VSS IDDSYN VSB ELECTRICAL CHARACTERISTICS A-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-12 16.78-MHz DC Characteristics (Continued) (VDD and VDDSYN = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH) Num Characteristic MC68HC16Z1 RAM Standby Current Normal RAM operation15 VDD > VSB – 0.5 V Transient condition VSB − 0.5 V ≥ VDD ≥ VSS + 0.5 V Standby operation14 VDD < VSS + 0.5 V 12 Symbol Min — — — — — — — — — — Max TBD 2.5 50 TBD 2.5 100 639 666 10 20 Unit µA mA µA µA mA µA mW mW pF 16 ISB MC68HC16Z2/Z3 RAM Standby Current12 Normal RAM operation15 VDD > VSB – 0.5 V 16A Transient condition VSB − 0.5 V ≥ VDD ≥ VSS + 0.5 V Standby operation14 VDD < VSS + 0.5 V 17 17A MC68HC16Z1 Power Dissipation16 MC68HC16Z2/Z3 Power Dissipation 3, 7, 13 16 ISB PD PD CIN Freescale Semiconductor, Inc... 18 Input Capacitance All input-only pins except ADC pins All input/output pins Load Capacitance4 Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0 Group 2 I/O Pins and CSBOOT, BG/CS Group 3 I/O Pins Group 4 I/O Pins 19 CL — — — — 90 100 130 200 pF NOTES: 1. Refer to notes in Table A-14. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-13 Freescale Semiconductor, Inc. Table A-13 20.97-MHz DC Characteristics (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH) Num 1 2 3 4 5 6 Input High Voltage Input Low Voltage Input Hysteresis 1, 2 3, 4 Characteristic Symbol VIH VIL VHYS IIN IOZ VOH VOL VOH Min Max Unit V V V µA µA V V V 0.7 (VDD) VDD + 0.3 VSS – 0.3 0.2 (VDD) 0.5 –2.5 –2.5 VDD –0.2 — VDD –0.8 — — — 1.6 (VDD) — –15 — — — — — — 4.75 — — — — — — — — 0.0 3.0 — 2.5 2.5 — 0.2 — Input Leakage Current Vin = VDD or VSS High Impedance (Off-State) Leakage Current4, 5 Vin = VDD or VSS CMOS Output High Voltage4, 6, 7 IOH = –10.0 µA CMOS Output Low Voltage4, 8 IOL = 10.0 µA Output High Voltage4, 6, 7 IOH = –0.8 mA Output Low Voltage4, 8 IOL = 1.6 mA IOL = 5.3 mA IOL = 12 mA Three State Control Input High Voltage Data Bus Mode Select Pull-Up Current Vin = VIL Vin = VIH 9, 10 Freescale Semiconductor, Inc... 7 8 9 VOL VIIHTSC IMSP 0.4 0.4 0.4 9.1 –120 — 140 350 5 140 2 10 5.25 2 6 150 100 2.5 8.75 2 2 5.25 5.25 V 10 11 V µA 12 MC68HC16Z1 VDD Supply Current11, 12, 13 Run LPSTOP, crystal, VCO Off (STSIM = 0) LPSTOP, external clock input frequency = maximum fsys IDD mA µA mA mA mA mA V mA mA µA µA mA mA mA mA V MC68HC16Z2/Z3 VDD Supply Current11, 12, 13 Run 12A LPSTOP, crystal, VCO Off (STSIM = 0) LPSTOP, external clock input frequency = maximum fsys 13 Clock Synthesizer Operating Voltage MC68HC16Z1 VDDSYN Supply Current VCO on, crystal reference, maximum fsys External clock, maximum fsys LPSTOP, crystal reference, VCO off (STSIM = 0) VDD powered down 11, 13 IDD VDDSYN 14 IDDSYN MC68HC16Z2/Z3 VDDSYN Supply Current11, 13 VCO on, crystal reference, maximum fsys 14A External clock, maximum fsys LPSTOP, crystal reference, VCO off (STSIM = 0) VDD powered down 15 RAM Standby Voltage14 Specified VDD applied VDD = VSS IDDSYN VSB ELECTRICAL CHARACTERISTICS A-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-13 20.97-MHz DC Characteristics (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH) Num Characteristic MC68HC16Z1 RAM Standby Current Normal RAM operation15 VDD > VSB – 0.5 V Transient condition VSB − 0.5 V ≥ VDD ≥ VSS + 0.5 V Standby operation14 VDD < VSS + 0.5 V 12 Symbol Min — — — — — — — — — — Max 10 3 50 10 3 100 772 787 10 20 Unit µA mA µA µA mA µA mW mW pF 16 ISB MC68HC16Z2/Z3 RAM Standby Current12 Normal RAM operation15 VDD > VSB – 0.5 V 16A Transient condition VSB − 0.5 V ≥ VDD ≥ VSS + 0.5 V Standby operation14 VDD < VSS + 0.5 V 17 MC68HC16Z1 Power Dissipation16 16 3, 7, 13 ISB PD PD CIN 17A MC68HC16Z2/Z3 Power Dissipation Freescale Semiconductor, Inc... 18 Input Capacitance All input-only pins except ADC pins All input/output pins Load Capacitance4 Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0 Group 2 I/O Pins and CSBOOT, BG/CS Group 3 I/O Pins Group 4 I/O Pins 19 CL — — — — 90 100 130 200 pF NOTES: 1. Refer to notes in Table A-14. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-15 Freescale Semiconductor, Inc. Table A-14 25.17-MHz DC Characteristics (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH) Num 1 2 3 4 5 6 Input High Voltage Input Low Voltage Input Hysteresis 1, 2 3, 4 Characteristic Symbol VIH VIL VHYS IIN 4, 5 Min Max Unit V V V µA µA V V V 0.7 (VDD) VDD + 0.3 VSS – 0.3 0.2 (VDD) 0.5 –2.5 –2.5 VDD –0.2 — VDD –0.8 — — — 1.6 (VDD) — –15 — — — — — — 4.75 — — — — — — — — 0.0 3.0 — 2.5 2.5 — 0.2 — Input Leakage Current Vin = VDD or VSS High Impedance (Off-State) Leakage Current Vin = VDD or VSS CMOS Output High Voltage4, 6, 7 IOH = –10.0 µA CMOS Output Low Voltage4, 8 IOL = 10.0 µA Output High Voltage4, 6, 7 IOH = –0.8 mA Output Low Voltage4, 8 IOL = 1.6 mA IOL = 5.3 mA IOL = 12 mA Three State Control Input High Voltage Data Bus Mode Select Pull-Up Current Vin = VIL Vin = VIH 9, 10 IOZ VOH VOL VOH Freescale Semiconductor, Inc... 7 8 9 VOL VIIHTSC IMSP 0.4 0.4 0.4 9.1 –120 — 140 350 5 140 2 10 5.25 2 7 150 100 2.5 8.75 2 2 5.25 5.25 V 10 11 V µA 12 MC68HC16Z1 VDD Supply Current11, 12, 13 Run LPSTOP, crystal, VCO Off (STSIM = 0) LPSTOP, external clock input frequency = maximum fsys IDD mA µA mA mA mA mA V mA mA µA µA mA mA mA mA V MC68HC16Z2/Z3 VDD Supply Current 11, 12, 13 Run 12A LPSTOP, crystal, VCO Off (STSIM = 0) LPSTOP, external clock input frequency = maximum fsys 13 Clock Synthesizer Operating Voltage MC68HC16Z1 VDDSYN Supply Current VCO on, crystal reference, maximum fsys External clock, maximum fsys LPSTOP, crystal reference, VCO off (STSIM = 0) VDD powered down 11, 13 IDD VDDSYN 14 IDDSYN MC68HC16Z2/Z3 VDDSYN Supply Current11, 13 VCO on, crystal reference, maximum fsys 14A External clock, maximum fsys LPSTOP, crystal reference, VCO off (STSIM = 0) VDD powered down 15 RAM Standby Voltage14 Specified VDD applied VDD = VSS IDDSYN VSB ELECTRICAL CHARACTERISTICS A-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-14 25.17-MHz DC Characteristics (Continued) (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH) Num Characteristic MC68HC16Z1 RAM Standby Current Normal RAM operation15 VDD > VSB – 0.5 V Transient condition VSB − 0.5 V ≥ VDD ≥ VSS + 0.5 V Standby operation14 VDD < VSS + 0.5 V 12 Symbol Min — — — — — — — — — — Max 10 3 50 10 3 100 777 787 10 20 Unit µA mA µA µA mA µA mW mW pF 16 ISB MC68HC16Z2/Z3 RAM Standby Current12 Normal RAM operation15 VDD > VSB – 0.5 V 16A Transient condition VSB − 0.5 V ≥ VDD ≥ VSS + 0.5 V Standby operation14 VDD < VSS + 0.5 V 17 17A MC68HC16Z1 Power Dissipation16 MC68HC16Z2/Z3 Power Dissipation 3, 7, 13 16 ISB PD PD CIN Freescale Semiconductor, Inc... 18 Input Capacitance All input-only pins except ADC pins All input/output pins Load Capacitance4 Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0 Group 2 I/O Pins and CSBOOT, BG/CS Group 3 I/O Pins Group 4 I/O Pins 19 CL — — — — 90 100 130 200 pF NOTES: 1. Applies to : Port ADA[7:0] — AN[7:0] Port E[7:4] — SIZ[1:0], AS, DS Port F[7:0] — IRQ[7:1], MODCLK Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1 Port QS[7:0] — TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO BKPT/DSCLK, DSI/IPIPE1, PAI, PCLK, RESET, RXD, TSC EXTAL (when PLL enabled) 2. This parameter is periodically sampled rather than 100% tested. 3. Applies to all input-only pins except ADC pins. 4. Input-Only Pins: EXTAL, TSC, BKPT/DSCLK, PAI, PCLK, RXD Input/Output: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, DSO/IPIPE0, PWMA, PWMB Output-Only Pins: Group 1: Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1, DATA[15:0], DSI/IPIPE1 Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3], Port E[7:0] — SIZ[1:0], AS, DS, AVEC, DSACK[1:0] Port F[7:0] — IRQ[7:1], MODCLK Port QS[7:3] — TXD, PCS[3:1], PCS0/SS ADDR23/CS10/ECLK, ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2 Group 3: HALT, RESET Group 3: MISO, MOSI, SCK 5. Applies to all input/output and output pins. 6. Does not apply to HALT and RESET because they are open drain pins. Does not apply to port QS[7:0] (TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode. 7. Applies to Group 1, 2, 4 input/output and all output pins. 8. Applies to Group 1, 2, 3, 4 input/output pins, BG/CS, CLKOUT, CSBOOT, FREEZE/QUOT, and IPIPE0. 9. Applies to DATA[15:0]. 10. Use of an active pulldown device is recommended. 11. Total operating current is the sum of the appropriate IDD, IDDSYN, ISB, and IDDA. 12. Current measured at maximum system clock frequency, all modules active. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-17 Freescale Semiconductor, Inc. 13. The base configuration of the MC68HC16Z1, MC68CK16Z1, MC68HC16Z4, and the MC68CK16Z4 requires a 32.768 kHz crystal reference. The base configuration of the MC68CM16Z1, MC68HC16Z2, and the MC68HC16Z3 requires a 4.194 MHz crystal reference. 14. The RAM module will not switch into standby mode as long as VSB does not exceed VDD by more than 0.5 volts. The RAM array cannot be accessed while the module is in standby mode. 15. When VSB is more than 0.3 V greater than VDD, current flows between the VSTBY and VDD pins, which causes standby current to increase toward the maximum transient condition specification. System noise on the VDD and VSTBY pin can contribute to this condition. 16. Power dissipation is measured with the appropriate system clock frequency, all modules active. Power dissipation can be calculated using the following expression: PD = Maximum VDD (IDD + IDDSYN + ISB) + Maximum VDDA (IDDA) IDD includes supply currents for all device modules powered by VDD pins. Freescale Semiconductor, Inc... ELECTRICAL CHARACTERISTICS A-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-15 Low Voltage 16.78-MHz AC Timing (VDD and VDDSYN = 2.7 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH)1 Num F1 1 1A 1B 2, 3 Frequency of Operation Clock Period ECLK Period External Clock Input Period2 Clock Pulse Width3 Characteristic Symbol f tcyc tEcyc tXcyc tCW tECW tXCHL tCrf trf tXCrf tCHAV tCHAZx tCHAZn tCLSA tSTSA tAVSA tCLSN tSNAI tSWA tSWAW tSWDW tSN tCHSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO tDVASN tSNDOI tDVSA tDICL tBELCL tSNDN tSNDI tSHDI Min — 59.6 476 64 24 236 32 — 0 0 0 2 0 2 –15 15 2 15 110 45 40 40 0 15 0 0 15 70 — 15 15 15 5 20 0 0 — Max Unit 16.78 MHz — — — — — — 9 8 5 35 59 — 25 15 — 29 — — — — — 59 — 30 30 — — 30 — — — — — 80 — 55 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2A, 3A ECLK Pulse Width 2B, 3B External Clock Input High/Low Time2 4, 5 CLKOUT Rise and Fall Time Freescale Semiconductor, Inc... 4A, 5A Rise and Fall Time (All outputs except CLKOUT) 4B, 5B External Clock Input Rise and Fall Time3 6 7 8 9 9A 11 12 13 14 14A 14B 15 16 17 18 20 21 22 23 24 25 26 27 27A 28 29 29A Clock High to ADDR, FC, SIZ Valid4 Clock High to ADDR, Data, FC, SIZ High Impedance Clock High to ADDR, FC, SIZ Invalid Clock Low to AS, DS, CS Asserted4 AS to DS or CS Asserted (Read)5 ADDR, FC, SIZ Valid to AS, CS, (and DS Read) Asserted Clock Low to AS, DS, CS Negated AS, DS, CS Negated to ADDR, FC, SIZ Invalid (Address Hold) AS, CS (and DS Read) Width Asserted DS, CS Width Asserted (Write) AS, CS (and DS Read) Width Asserted (Fast Cycle) AS, DS, CS Width Negated6 Clock High to AS, DS, R/W High Impedance AS, DS, CS Negated to R/W High Clock High to R/W High Clock High to R/W Low R/W High to AS, CS Asserted R/W Low to DS, CS Asserted (Write) Clock High to Data Out Valid Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) DS, CS Negated to Data Out Invalid (Data Out Hold) Data Out Valid to DS, CS Asserted (Write) Data In Valid to Clock Low (Data Setup)4 Late BERR, HALT Asserted to Clock Low (Setup Time) AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated DS, CS Negated to Data In Invalid (Data In Hold)7 DS, CS Negated to Data In High Impedance7, 8 M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-19 Freescale Semiconductor, Inc. Table A-15 Low Voltage 16.78-MHz AC Timing (Continued) (VDD and VDDSYN = 2.7 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH)1 Num 30 30A 31 33 35 37 39 39A Characteristic CLKOUT Low to Data In Invalid (Fast Cycle Hold) CLKOUT Low to Data In High Impedance DSACK[1:0] Asserted to Data In Valid Clock Low to BG Asserted/Negated BR Asserted to BG Asserted 10 9 7 7 Symbol tCLDI tCLDH tDADI tCLBAN tBRAGA tGAGN tGH tGA tRWA tRWAS tAIST tAIHT 12 Min 15 — — — 1 1 2 1 150 90 15 15 — 0 — 40 0 15 10 20 15 20 0 4 — 3 3 10 10 10 10 Max — 90 50 30 — 2 — — — — — — 30 — 28 — 30 — — — — — — — 10 40 40 — — — — Unit ns ns ns ns tcyc tcyc tcyc tcyc ns ns ns ns ns ns ns ns ns ns ns ns ns tcyc ns tcyc tcyc ns ns ns ns ns ns BGACK Asserted to BG Negated BG Width Negated BG Width Asserted R/W Width Asserted (Write or Read) R/W Width Asserted (Fast Write or Read Cycle) Asynchronous Input Setup Time BR, BGACK, DSACK[1:0], BERR, AVEC, HALT Asynchronous Input Hold Time DSACK[1:0] Asserted to BERR, HALT Asserted Data Out Hold from Clock High Clock High to Data Out High Impedance R/W Asserted to Data Bus Impedance Change Clock Low to Data Bus Driven (Show Cycle) Data Setup Time to Clock Low (Show Cycle) Data Hold from Clock Low (Show Cycle) BKPT Input Setup Time BKPT Input Hold Time Mode Select Setup Time, DATA[15:0], MODCLK, BKPT pins Mode Select Hold Time, DATA[15:0], MODCLK, BKPT pins RESET Assertion Time RESET Rise Time 13 14 14 14 12 Freescale Semiconductor, Inc... 46 46A 47A 47B 48 53 54 55 70 71 72 73 74 75 76 77 78 100 101 102 103 104 105 tDABA tDOCH tCHDH tRADC tSCLDD tSCLDS tSCLDH tBKST tBKHT tMSS tMSH tRSTA tRSTR tCHP1A tCHP2A tP1VSN tP2VSN tSAP1N CLKOUT High to Phase 1 Asserted CLKOUT High to Phase 2 Asserted Phase 1 Valid to AS or DS Asserted Phase 2 Valid to AS or DS Negated 14 14 14 AS or DS Valid to Phase 1 Negated AS or DS Negated to Phase 2 Negated tSNP2N NOTES: 1. Refer to notes in Table A-18. ELECTRICAL CHARACTERISTICS A-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-16 16.78-MHz AC Timing (VDD and VDDSYN = 5.0 Vdc ± 10 %, VSS = 0 Vdc, TA = TL to TH)1 Num F1 1 1A 1B 2, 3 Frequency of Operation Clock Period ECLK Period External Clock Input Period2 Clock Pulse Width3 Characteristic Symbol f tcyc tEcyc tXcyc tCW tECW tXCHL tCrf trf tXCrf tCHAV tCHAZx tCHAZn tCLSA tSTSA tAVSA tCLSN tSNAI tSWA tSWAW tSWDW tSN tCHSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO tDVASN tSNDOI tDVSA tDICL tBELCL tSNDN tSNDI tSHDI Min — 59.6 476 59.6 24 236 29.8 — — — 0 0 0 2 -15 15 2 15 100 45 40 40 — 15 0 0 15 70 — 15 15 15 5 20 0 0 — Max 16.78 — — — — — — 5 8 5 29 59 — 24 15 — 29 — — — — — 59 — 29 29 — — 29 — — — — — 80 — 55 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2A, 3A ECLK Pulse Width 2B, 3B External Clock Input High/Low Time2 4, 5 CLKOUT Rise and Fall Time Freescale Semiconductor, Inc... 4A, 5A Rise and Fall Time (All Outputs except CLKOUT) 4B, 5B External Clock Input Rise and Fall Time3 6 7 8 9 9A 11 12 13 14 14A 14B 15 16 17 18 20 21 22 23 24 25 26 27 27A 28 29 29A Clock High to ADDR, FC, SIZE Valid4 Clock High to ADDR, Data, FC, SIZE, High Impedance Clock High to ADDR, FC, SIZE, Invalid Clock Low to AS, DS, CS Asserted4 AS to DS or CS Asserted (Read)5 ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted Clock Low to AS, DS, CS Negated AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold) AS, CS (and DS Read) Width Asserted DS, CS Width Asserted (Write) AS, CS (and DS Read) Width Asserted (Fast Cycle) AS, DS, CS Width Negated6 Clock High to AS, DS, R/W High Impedance AS, DS, CS Negated to R/W High Clock High to R/W High Clock High to R/W Low R/W High to AS, CS Asserted R/W Low to DS, CS Asserted (Write) Clock High to Data Out Valid Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) DS, CS Negated to Data Out Invalid (Data Out Hold) Data Out Valid to DS, CS Asserted (Write) Data In Valid to Clock Low (Data Setup)4 Late BERR, HALT Asserted to Clock Low (Setup Time) AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated DS, CS Negated to Data In Invalid (Data In Hold)7 DS, CS Negated to Data In High Impedance7, 8 M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-21 Freescale Semiconductor, Inc. Table A-16 16.78-MHz AC Timing (Continued) (VDD and VDDSYN = 5.0 Vdc ± 10 %, VSS = 0 Vdc, TA = TL to TH)1 Num 30 30A 31 33 35 37 39 39A Characteristic CLKOUT Low to Data In Invalid (Fast Cycle Hold) CLKOUT Low to Data In High Impedance DSACK[1:0] Asserted to Data In Valid Clock Low to BG Asserted/Negated BR Asserted to BG Asserted 10 9 7 7 Symbol tCLDI tCLDH tDADI tCLBAN tBRAGA tGAGN tGH tGA tRWA tRWAS tAIST tAIHT 11 Min 15 — — — 1 1 2 1 150 90 5 15 — 0 — 40 0 15 10 15 10 20 0 4 — 3 3 10 10 10 10 Max — 90 50 29 — 2 — — — — — — 30 — 28 — 29 — — — — — — — 10 40 40 — — — — Unit ns ns ns ns tcyc tcyc tcyc tcyc ns ns ns ns ns ns ns ns ns ns ns ns ns tcyc ns tcyc tcyc ns ns ns ns ns ns BGACK Asserted to BG Negated BG Width Negated BG Width Asserted R/W Width Asserted (Write or Read) R/W Width Asserted (Fast Write or Read Cycle) Asynchronous Input Setup Time BR, BGACK, DSACK[1:0], BERR, AVEC, HALT Asynchronous Input Hold Time DSACK[1:0] Asserted to BERR, HALT Asserted Data Out Hold from Clock High Clock High to Data Out High Impedance R/W Asserted to Data Bus Impedance Change Clock Low to Data Bus Driven (Show Cycle) Data Setup Time to Clock Low (Show Cycle) Data Hold from Clock Low (Show Cycle) BKPT Input Setup Time BKPT Input Hold Time Mode Select Setup Time, DATA[15:0], MODCLK, BKPT pins Mode Select Hold Time, DATA[15:0], MODCLK, BKPT pins RESET Assertion Time RESET Rise Time 13 14 14 14 14 12 Freescale Semiconductor, Inc... 46 46A 47A 47B 48 53 54 55 70 71 72 73 74 75 76 77 78 100 101 102 103 104 105 tDABA tDOCH tCHDH tRADC tSCLDD tSCLDS tSCLDH tBKST tBKHT tMSS tMSH tRSTA tRSTR tCHP1A tCHP2A tP1VSA tP2VSN tSAP1N CLKOUT High to Phase 1 Asserted CLKOUT High to Phase 2 Asserted Phase 1 Valid to AS or DS Asserted Phase 2 Valid to AS or DS Asserted AS or DS Valid to Phase 1 Negated 14 14 AS or DS Negated to Phase 2 Negated tSNP2N NOTES: 1. Refer to notes in Table A-18. ELECTRICAL CHARACTERISTICS A-22 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-17 20.97-MHz AC Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1 Num F1 1 1A 1B 2, 3 Frequency of Operation Clock Period ECLK Period External Clock Input Period2 Clock Pulse Width3 Characteristic Symbol f tcyc tEcyc tXcyc tCW tECW tXCHL tCrf trf tXCrf tCHAV tCHAZx tCHAZn tCLSA tSTSA tAVSA tCLSN tSNAI tSWA tSWAW tSWDW tSN tCHSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO tDVASN tSNDOI tDVSA tDICL tBELCL tSNDN tSNDI tSHDI Min — 47.7 381 47.7 18.8 183 23.8 — — — 0 0 0 0 -10 10 2 10 80 36 32 32 — 10 0 0 10 54 — 10 10 10 5 15 0 0 — Max 20.97 — — — — — — 5 8 5 23 47 — 23 10 — 23 — — — — — 47 — 23 23 — — 23 — — — — — 60 — 48 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2A, 3A ECLK Pulse Width 2B, 3B External Clock Input High/Low Time2 4, 5 CLKOUT Rise and Fall Time Freescale Semiconductor, Inc... 4A, 5A Rise and Fall Time (All Outputs except CLKOUT) 4B, 5B External Clock Input Rise and Fall Time3 6 7 8 9 9A 11 12 13 14 14A 14B 15 16 17 18 20 21 22 23 24 25 26 27 27A 28 29 29A Clock High to ADDR, FC, SIZE Valid4 Clock High to ADDR, Data, FC, SIZE, High Impedance Clock High to ADDR, FC, SIZE, Invalid Clock Low to AS, DS, CS Asserted4 AS to DS or CS Asserted (Read)5 ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted Clock Low to AS, DS, CS Negated AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold) AS, CS (and DS Read) Width Asserted DS, CS Width Asserted (Write) AS, CS (and DS Read) Width Asserted (Fast Cycle) AS, DS, CS Width Negated6 Clock High to AS, DS, R/W High Impedance AS, DS, CS Negated to R/W High Clock High to R/W High Clock High to R/W Low R/W High to AS, CS Asserted R/W Low to DS, CS Asserted (Write) Clock High to Data Out Valid Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) DS, CS Negated to Data Out Invalid (Data Out Hold) Data Out Valid to DS, CS Asserted (Write) Data In Valid to Clock Low (Data Setup)4 Late BERR, HALT Asserted to Clock Low (Setup Time) AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated DS, CS Negated to Data In Invalid (Data In Hold)7 DS, CS Negated to Data In High Impedance7, 8 M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-23 Freescale Semiconductor, Inc. Table A-17 20.97-MHz AC Timing (Continued) (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1 Num 30 30A 31 33 35 37 39 39A Characteristic CLKOUT Low to Data In Invalid (Fast Cycle Hold) CLKOUT Low to Data In High Impedance DSACK[1:0] Asserted to Data In Valid Clock Low to BG Asserted/Negated BR Asserted to BG Asserted 10 9 7 7 Symbol tCLDI tCLDH tDADI tCLBAN tBRAGA tGAGN tGH tGA tRWA tRWAS tAIST tAIHT 11 Min 10 — — — 1 1 2 1 115 70 5 12 — 0 — 32 0 10 10 10 10 20 0 4 — 3 3 10 10 10 10 Max — 72 46 23 — 2 — — — — — — 30 — 23 — 23 — — — — — — — 10 40 40 — — — — Unit ns ns ns ns tcyc tcyc tcyc tcyc ns ns ns ns ns ns ns ns ns ns ns ns ns tcyc ns tcyc tcyc ns ns ns ns ns ns BGACK Asserted to BG Negated BG Width Negated BG Width Asserted R/W Width Asserted (Write or Read) R/W Width Asserted (Fast Write or Read Cycle) Asynchronous Input Setup Time BR, BGACK, DSACK[1:0], BERR, AVEC, HALT Asynchronous Input Hold Time DSACK[1:0] Asserted to BERR, HALT Asserted Data Out Hold from Clock High Clock High to Data Out High Impedance R/W Asserted to Data Bus Impedance Change Clock Low to Data Bus Driven (Show Cycle) Data Setup Time to Clock Low (Show Cycle) Data Hold from Clock Low (Show Cycle) BKPT Input Setup Time BKPT Input Hold Time Mode Select Setup Time, DATA[15:0], MODCLK, BKPT pins Mode Select Hold Time, DATA[15:0], MODCLK, BKPT pins RESET Assertion Time RESET Rise Time 13 14 14 14 14 12 Freescale Semiconductor, Inc... 46 46A 47A 47B 48 53 54 55 70 71 72 73 74 75 76 77 78 100 101 102 103 104 105 tDABA tDOCH tCHDH tRADC tSCLDD tSCLDS tSCLDH tBKST tBKHT tMSS tMSH tRSTA tRSTR tCHP1A tCHP2A tP1VSA tP2VSN tSAP1N CLKOUT High to Phase 1 Asserted CLKOUT High to Phase 2 Asserted Phase 1 Valid to AS or DS Asserted Phase 2 Valid to AS or DS Asserted AS or DS Valid to Phase 1 Negated 14 14 AS or DS Negated to Phase 2 Negated tSNP2N NOTES: 1. Refer to notes in Table A-18. ELECTRICAL CHARACTERISTICS A-24 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-18 25.17-MHz AC Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1 Num F1 1 1A 1B 2, 3 Frequency of Operation Clock Period ECLK Period External Clock Input Period2 Clock Pulse Width3 Characteristic Symbol f tcyc tEcyc tXcyc tCW tECW tXCHL tCrf trf tXCrf tCHAV tCHAZx tCHAZn tCLSA tSTSA tAVSA tCLSN tSNAI tSWA tSWAW tSWDW tSN tCHSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO tDVASN tSNDOI tDVSA tDICL tBELCL tSNDN tSNDI tSHDI Min — 39.7 318 39.7 15 155 19.8 — — — 0 0 0 2 –10 8 2 8 65 25 22 22 — 10 0 0 10 40 — 7 5 8 5 10 0 0 — Max 25.166 — — — — — — 5 8 4 19 39 — 19 15 — 19 — — — — — 39 — 19 19 — — 19 — — — — — 50 — 45 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2A, 3A ECLK Pulse Width 2B, 3B External Clock Input High/Low Time2 4, 5 CLKOUT Rise and Fall Time Freescale Semiconductor, Inc... 4A, 5A Rise and Fall Time (All Outputs except CLKOUT) 4B, 5B External Clock Input Rise and Fall Time3 6 7 8 9 9A 11 12 13 14 14A 14B 15 16 17 18 20 21 22 23 24 25 26 27 27A 28 29 29A Clock High to ADDR, FC, SIZ Valid4 Clock High to ADDR, Data, FC, SIZ, High Impedance Clock High to ADDR, FC, SIZ, Invalid Clock Low to AS, DS, CS Asserted4 AS to DS or CS Asserted (Read)5 ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted Clock Low to AS, DS, CS Negated AS, DS, CS Negated to ADDR, FC, SIZ Invalid (Address Hold) AS, CS (and DS Read) Width Asserted DS, CS Width Asserted (Write) AS, CS (and DS Read) Width Asserted (Fast Cycle) AS, DS, CS Width Negated6 Clock High to AS, DS, R/W High Impedance AS, DS, CS Negated to R/W High Clock High to R/W High Clock High to R/W Low R/W High to AS, CS Asserted R/W Low to DS, CS Asserted (Write) Clock High to Data Out Valid Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) DS, CS Negated to Data Out Invalid (Data Out Hold) Data Out Valid to DS, CS Asserted (Write) Data In Valid to Clock Low (Data Setup)4 Late BERR, HALT Asserted to Clock Low (Setup Time) AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated DS, CS Negated to Data In Invalid (Data In Hold)7 DS, CS Negated to Data In High Impedance7, 8 M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-25 Freescale Semiconductor, Inc. Table A-18 25.17-MHz AC Timing (Continued) (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1 Num 30 30A 31 33 35 37 39 39A Characteristic CLKOUT Low to Data In Invalid (Fast Cycle Hold) CLKOUT Low to Data In High Impedance DSACK[1:0] Asserted to Data In Valid Clock Low to BG Asserted/Negated BR Asserted to BG Asserted 10 9 7 7 Symbol tCLDI tCLDH tDADI tCLBAN tBRAGA tGAGN tGH tGA tRWA tRWAS tAIST tAIHT 11 Min 8 — — — 1 1 2 1 90 55 5 10 — 0 — 25 0 8 8 10 10 20 0 4 — 3 3 9 9 9 9 Max — 60 35 19 — 2 — — — — — — 27 — 23 — 19 — — — — — — — 10 34 34 — — — — Unit ns ns ns ns tcyc tcyc tcyc tcyc ns ns ns ns ns ns ns ns ns ns ns ns ns tcyc ns tcyc tcyc ns ns ns ns ns ns BGACK Asserted to BG Negated BG Width Negated BG Width Asserted R/W Width Asserted (Write or Read) R/W Width Asserted (Fast Write or Read Cycle) Asynchronous Input Setup Time BR, BGACK, DSACK[1:0], BERR, AVEC, HALT Asynchronous Input Hold Time DSACK[1:0] Asserted to BERR, HALT Asserted Data Out Hold from Clock High Clock High to Data Out High Impedance R/W Asserted to Data Bus Impedance Change Clock Low to Data Bus Driven (Show Cycle) Data Setup Time to Clock Low (Show Cycle) Data Hold from Clock Low (Show Cycle) BKPT Input Setup Time BKPT Input Hold Time Mode Select Setup Time (DATA[15:0], MODCLK, BKPT) Mode Select Hold Time (DATA[15:0], MODCLK, BKPT) RESET Assertion Time RESET Rise Time 13 14 14 14 14 12 Freescale Semiconductor, Inc... 46 46A 47A 47B 48 53 54 55 70 71 72 73 74 75 76 77 78 100 101 102 103 104 105 tDABA tDOCH tCHDH tRADC tSCLDD tSCLDS tSCLDH tBKST tBKHT tMSS tMSH tRSTA tRSTR tCHP1A tCHP2A tP1VSA tP2VSN tSAP1N CLKOUT High to Phase 1 Asserted CLKOUT High to Phase 2 Asserted Phase 1 Valid to AS or DS Asserted Phase 2 Valid to AS or DS Asserted AS or DS Valid to Phase 1 Negated 14 14 AS or DS Negated to Phase 2 Negated tSNP2N NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. 2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable tXcyc period is reduced when the duty cycle of the external clock varies. The relationship between external clock input duty cycle and minimum tXcyc is expressed: Minimum tXcyc period = minimum tXCHL / (50% – external clock input duty cycle tolerance). ELECTRICAL CHARACTERISTICS A-26 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 3. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during reset) do not pertain to an external reference applied while the PLL is enabled (MODCLK pin held high during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical. 4. Address access time = (2.5 + WS) tcyc – tCHAV – tDICL Chip select access time = (2 + WS) tcyc – tCLSA – tDICL Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1. 5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside the limits shown in specification 9. 6. If multiple-chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip-select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip-selects does not apply to chip selects being used for synchronous ECLK cycles. 7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads. The user is free to use either hold time. 8. Maximum value is equal to (tcyc / 2) + 25 ns. 9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle. 10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles of the current operand transfer are complete. 11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification 47A). 12. After external RESET negation is detected, a short transition period (approximately 2 tcyc) elapses, then the SIM drives RESET low for 512 tcyc. 13. External logic must pull RESET high during this period in order for normal MCU operation to begin. 14. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-27 Freescale Semiconductor, Inc. 1 4 CLKOUT 2 3 5 16 CLKOUT TIM Figure A-1 CLKOUT Output Timing Diagram Freescale Semiconductor, Inc... 1B 4B EXTAL 2B 3B 5B NOTE: TIMING SHOWN WITH RESPECT TO VIH/VIL LEVELS. PULSE WIDTH SHOWN WITH RESPECT TO 50% VDD. 16 EXT CLK INPUT TIM Figure A-2 External Clock Input Timing Diagram 1A 4A ECLK 2A 3A 5A NOTE: TIMING SHOWN WITH RESPECT TO VIH/VILLEVELS. 16 ECLK OUTPUT TIM Figure A-3 ECLK Output Timing Diagram ELECTRICAL CHARACTERISTICS A-28 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. S0 CLKOUT 6 ADDR[23:0] S1 S2 S3 S4 S5 8 FC[2:0] SIZ[1:0] 11 AS 9 13 14 15 Freescale Semiconductor, Inc... DS 9A CS 18 R/W 46 21 20 12 DSACK0 47A DSACK1 31 DATA[15:0] 27 29A BERR 48 27A HALT 74 73 BKPT 47A ASYNCHRONOUS INPUTS 100 IPIPE0 PHASE 1 IPIPE1 102 104 103 PHASE 2 101 105 47B 29 28 16 RD CYC TIM Figure A-4 Read Cycle Timing Diagram M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-29 Freescale Semiconductor, Inc. S0 CLKOUT 6 ADDR[23:20] S1 S2 S3 S4 S5 8 FC[2:0] SIZ[1:0] 11 AS 9 14 15 13 Freescale Semiconductor, Inc... DS 21 9 12 CS 20 R/W 46 DSACK0 47A DSACK1 55 DATA[15:0] 23 BERR 48 27A HALT 74 73 BKPT 100 IPIPE0 PHASE 1 IPIPE1 102 104 103 16 WR CYC TIM 22 14A 17 28 25 26 54 53 101 PHASE 2 105 Figure A-5 Write Cycle Timing Diagram ELECTRICAL CHARACTERISTICS A-30 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. S0 CLKOUT 6 ADDR[23:0] S1 S4 S5 S0 8 FC[2:0] SIZ[1:0] 14B AS 9 12 Freescale Semiconductor, Inc... DS CS 20 18 R/W 46A 27 30 30A DATA[15:0] 73 29A 29 BKPT 74 100 IPIPE0 PHASE 1 IPIPE1 102 104 103 105 16 FAST RD CYC TIM 101 PHASE 2 Figure A-6 Fast Termination Read Cycle Timing Diagram M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-31 Freescale Semiconductor, Inc. S0 CLKOUT 6 ADDR[23:0] 8 S1 S4 S5 S0 FC[1:0] SIZ[1:0] 14B AS 9 DS 12 Freescale Semiconductor, Inc... CS 20 46A R/W 23 DATA[15:0] 73 BKPT 100 IPIPE0 PHASE 1 IPIPE1 102 104 103 16 FAST WR CYC TIM 24 18 25 101 105 PHASE 2 Figure A-7 Fast Termination Write Cycle Timing Diagram ELECTRICAL CHARACTERISTICS A-32 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. S0 CLKOUT S1 S2 S3 S4 S5 S98 A5 A5 A2 ADDR[23:0] 7 DATA[15:0] AS 16 DS Freescale Semiconductor, Inc... R/W DSACK0 DSACK1 47A BR 35 BG 33 33 BGACK 100 IPIPE0 PHASE 1 IPIPE1 102 104 103 105 16 BUS ARB TIM 39A 101 PHASE 2 37 Figure A-8 Bus Arbitration Timing Diagram — Active Bus Case M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-33 Freescale Semiconductor, Inc. A0 CLKOUT A5 A5 A2 A3 A0 ADDR[23:0] DATA[15:0] AS 47A 47A BR Freescale Semiconductor, Inc... 35 BG 33 37 33 47A BGACK 16 BUS ARB TIM IDLE Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case ELECTRICAL CHARACTERISTICS A-34 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. S0 CLKOUT 6 ADDR[23:0] 18 R/W 20 AS 8 S41 S42 S43 S0 S1 S2 9 12 15 DS 71 70 72 Freescale Semiconductor, Inc... DATA[15:0] 73 74 BKPT 100 IPIPE0 PHASE 1 IPIPE1 102 104 103 105 START OF EXTERNAL CYCLE SHOW CYCLE PHASE 2 PHASE 1 PHASE 2 101 NOTE: SHOW CYCLES CAN STRETCH DURING CLOCK PHASE S42 WHEN BUS ACCESSES TAKE LONGER THAN TWO CYCLES DUE TO IMB MODULE WAIT-STATE INSERTION. 16 SHW CYC TIM Figure A-10 Show Cycle Timing Diagram M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-35 Freescale Semiconductor, Inc. S0 CLKOUT 6 ADDR[23:0] S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 6 8 FC[2:0] SIZ[1:0] 11 AS 9 9 9 14 11 14 13 15 Freescale Semiconductor, Inc... DS 12 CS 18 R/W 46 29 DATA[15:0] 27 17 21 12 17 20 46 55 14A 18 25 29A 23 53 54 16 CHIP SEL TIM Figure A-11 Chip-Select Timing Diagram 77 RESET 75 DATA[15:0], MODCLK, BKPT 78 76 16 RST/MODE SEL TIM Figure A-12 Reset and Mode Select Timing Diagram ELECTRICAL CHARACTERISTICS A-36 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-19 Low Voltage 16.78-MHz Background Debug Mode Timing (VDD and VDDSYN = 2.7 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH)1 Num B0 B1 B2 B3 B4 B5 B6 B7 DSI Input Setup Time DSI Input Hold Time DSCLK Setup Time DSCLK Hold Time DSO Delay Time DSCLK Cycle Time CLKOUT High to FREEZE Asserted/Negated CLKOUT High to IPIPE1 High Impedance CLKOUT High to IPIPE1 Valid DSCLK Low Time IPIPE1 High Impedance to FREEZE Asserted FREEZE Negated to IPIPE[0:1] Active Characteristic Symbol tDSISU tDSIH tDSCSU tDSCH tDSOD tDSCCYC tFRZAN tIFZ tIF tDSCLO tIPFA tFRIP Min 15 15 15 15 — 2 — — — 1 TBD TBD Max — — — — 35 — 50 50 50 — — — Unit ns ns ns ns ns tcyc ns ns ns tcyc tcyc tcyc Freescale Semiconductor, Inc... B8 B9 B10 B11 NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. Table A-20 16.78-MHz Background Debug Mode Timing (VDD and VDDSYN = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)1 Num B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 DSI Input Setup Time DSI Input Hold Time DSCLK Setup Time DSCLK Hold Time DSO Delay Time DSCLK Cycle Time CLKOUT High to FREEZE Asserted/Negated CLKOUT High to IPIPE1 High Impedance CLKOUT High to IPIPE1 Valid DSCLK Low Time IPIPE1 High Impedance to FREEZE Asserted FREEZE Negated to IPIPE[0:1] Active Characteristic Symbol tDSISU tDSIH tDSCSU tDSCH tDSOD tDSCCYC tFRZAN tIFZ tIF tDSCLO tIPFA tFRIP Min 15 10 15 10 — 2 — — — 1 TBD TBD Max — — — — 25 — 50 TBD TBD — — — Unit ns ns ns ns ns tcyc ns ns ns tcyc tcyc tcyc NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-37 Freescale Semiconductor, Inc. Table A-21 20.97-MHz Background Debug Mode Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1 Num B0 B1 B2 B3 B4 B5 B6 B7 DSI Input Setup Time DSI Input Hold Time DSCLK Setup Time DSCLK Hold Time DSO Delay Time DSCLK Cycle Time CLKOUT High to FREEZE Asserted/Negated CLKOUT High to IPIPE1 High Impedance CLKOUT High to IPIPE1 Valid DSCLK Low Time IPIPE1 High Impedance to FREEZE Asserted FREEZE Negated to IPIPE[0:1] Active Characteristic Symbol tDSISU tDSIH tDSCSU tDSCH tDSOD tDSCCYC tFRZAN tIFZ tIF tDSCLO tIPFA tFRIP Min 15 10 15 10 — 2 — — — 1 TBD TBD Max — — — — 25 — 50 50 50 — — — Unit ns ns ns ns ns tcyc ns ns ns tcyc tcyc tcyc Freescale Semiconductor, Inc... B8 B9 B10 B11 NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. Table A-22 25.17-MHz Background Debug Mode Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1 Num B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 DSI Input Setup Time DSI Input Hold Time DSCLK Setup Time DSCLK Hold Time DSO Delay Time DSCLK Cycle Time CLKOUT High to FREEZE Asserted/Negated CLKOUT High to IPIPE1 High Impedance CLKOUT High to IPIPE1 Valid DSCLK Low Time IPIPE1 High Impedance to FREEZE Asserted FREEZE Negated to IPIPE[0:1] Active Characteristic Symbol tDSISU tDSIH tDSCSU tDSCH tDSOD tDSCCYC tFRZAN tIFZ tIF tDSCLO tIPFA tFRIP Min 10 5 10 5 — 2 — — — 1 TBD TBD Max — — — — 20 — 20 20 20 — — — Unit ns ns ns ns ns tcyc ns ns ns tcyc tcyc tcyc NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. ELECTRICAL CHARACTERISTICS A-38 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. CLKOUT FREEZE B2 BKPT/DSCLK B3 B9 B5 B1 B0 IPIPE1/DSI B4 IPIPE0/DSO Freescale Semiconductor, Inc... 16 BDM SER COM TIM Figure A-13 Background Debug Mode Timing Diagram (Serial Communication) CLKOUT B6 B6 FREEZE B7 IPIPE1/DSI B8 16 BDM FRZ TIM B10 B11 Figure A-14 Background Debug Mode Timing Diagram (Freeze Assertion) M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-39 Freescale Semiconductor, Inc. Table A-23 Low Voltage ECLK Bus Timing (VDD and VDDSYN = 2.7 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH)1 Num E1 E2 E3 E4 E5 E6 E7 E8 Characteristic ECLK Low to Address Valid2 ECLK Low to Address Hold ECLK Low to CS Valid (CS Delay) ECLK Low to CS Hold CS Negated Width Read Data Setup Time Read Data Hold Time ECLK Low to Data High Impedance CS Negated to Data Hold (Read) CS Negated to Data High Impedance ECLK Low to Data Valid (Write) ECLK Low to Data Hold (Write) CS Negated to Data Hold (Write) Address Access Time (Read)3 Chip-Select Access Time (Read)4 Address Setup Time Symbol tEAD tEAH tECSD tECSH tECSN tEDSR tEDHR tEDHZ tECDH tECDZ tEDDW tEDHW tECHW tEACC tEACS tEAS Min — 10 — 15 30 30 15 — 0 — — 5 0 386 296 — Max 60 — 150 — — — — 60 — 1 2 — — — — 1/2 Unit ns ns ns ns ns ns ns ns ns tcyc tcyc ns ns ns ns tcyc Freescale Semiconductor, Inc... E9 E10 E11 E12 E13 E14 E15 E16 NOTES: 1. Refer to notes in Table A-26. ELECTRICAL CHARACTERISTICS A-40 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-24 16.78-MHz ECLK Bus Timing (VDD and VDDSYN = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)1 Num E1 E2 E3 E4 E5 E6 E7 E8 Characteristic ECLK Low to Address Valid2 ECLK Low to Address Hold ECLK Low to CS Valid (CS Delay) ECLK Low to CS Hold CS Negated Width Read Data Setup Time Read Data Hold Time ECLK Low to Data High Impedance CS Negated to Data Hold (Read) CS Negated to Data High Impedance ECLK Low to Data Valid (Write) ECLK Low to Data Hold (Write) CS Negated to Data Hold (Write) Address Access Time (Read)3 Chip-Select Access Time (Read)4 Address Setup Time Symbol tEAD tEAH tECSD tECSH tECSN tEDSR tEDHR tEDHZ tECDH tECDZ tEDDW tEDHW tECHW tEACC tEACS tEAS Min — 10 — 15 30 30 15 — 0 — — 5 0 386 296 — Max 60 — 150 — — — — 60 — 1 2 — — — — 1/2 Unit ns ns ns ns ns ns ns ns ns tcyc tcyc ns ns ns ns tcyc Freescale Semiconductor, Inc... E9 E10 E11 E12 E13 E14 E15 E16 NOTES: 1. Refer to notes in Table A-26. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-41 Freescale Semiconductor, Inc. Table A-25 20.97-MHz ECLK Bus Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1 Num E1 E2 E3 E4 E5 E6 E7 E8 Characteristic ECLK Low to Address Valid2 ECLK Low to Address Hold ECLK Low to CS Valid (CS Delay) ECLK Low to CS Hold CS Negated Width Read Data Setup Time Read Data Hold Time ECLK Low to Data High Impedance CS Negated to Data Hold (Read) CS Negated to Data High Impedance ECLK Low to Data Valid (Write) ECLK Low to Data Hold (Write) CS Negated to Data Hold (Write) Address Access Time (Read)3 Chip-Select Access Time (Read)4 Address Setup Time Symbol tEAD tEAH tECSD tECSH tECSN tEDSR tEDHR tEDHZ tECDH tECDZ tEDDW tEDHW tECHW tEACC tEACS tEAS Min — 10 — 10 25 25 5 — 0 — — 10 0 308 236 1/2 Max 48 — 120 — — — — 48 — 1 2 — — — — — Unit ns ns ns ns ns ns ns ns ns tcyc tcyc ns ns ns ns tcyc Freescale Semiconductor, Inc... E9 E10 E11 E12 E13 E14 E15 E16 NOTES: 1. Refer to notes in Table A-26. ELECTRICAL CHARACTERISTICS A-42 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-26 25.17-MHz ECLK Bus Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1 Num E1 E2 E3 E4 E5 E6 E7 E8 Characteristic ECLK Low to Address Valid2 ECLK Low to Address Hold ECLK Low to CS Valid (CS Delay) ECLK Low to CS Hold CS Negated Width Read Data Setup Time Read Data Hold Time ECLK Low to Data High Impedance CS Negated to Data Hold (Read) CS Negated to Data High Impedance ECLK Low to Data Valid (Write) ECLK Low to Data Hold (Write) CS Negated to Data Hold (Write) Address Access Time (Read)3 Chip-Select Access Time (Read)4 Address Setup Time Symbol tEAD tEAH tECSD tECSH tECSN tEDSR tEDHR tEDHZ tECDH tECDZ tEDDW tEDHW tECHW tEACC tEACS tEAS Min — 10 — 10 20 25 5 — 0 — — 5 0 255 195 — Max 40 — 100 — — — — 40 — 1 2 — — — — 1/2 Unit ns ns ns ns ns ns ns ns ns tcyc tcyc ns ns ns ns tcyc Freescale Semiconductor, Inc... E9 E10 E11 E12 E13 E14 E15 E16 NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. 2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low. 3. Address access time = tEcyc – tEAD – tEDSR. 4. Chip select access time = tEcyc – tECSD – tEDSR. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-43 Freescale Semiconductor, Inc. CLKOUT 2A ECLK 1A 3A R/W E1 ADDR[23:0] E3 CS E15 E6 E16 E14 DATA[15:0] READ E7 E8 E11 E13 DATA[15:0] WRITE E12 HC16 E CYCLE TIM E2 E4 E5 Freescale Semiconductor, Inc... E9 WRITE E10 Figure A-15 ECLK Timing Diagram ELECTRICAL CHARACTERISTICS A-44 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-27 Low Voltage QSPI Timing (VDD and VDDSYN = 2.7 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH)1 Num 1 Function Operating Frequency Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock (SCK) High or Low Time Master Slave2 Sequential Transfer Delay Master Slave (Does Not Require Deselect) Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Slave Access Time Slave MISO Disable Time Data Valid (after SCK Edge) Master Slave Data Hold Time (Outputs) Master Slave Rise Time Input Output Fall Time Input Output Symbol fop Min DC DC 4 4 2 2 — 2 2 tcyc – 60 2 tcyc – n 17 13 20 20 30 20 — — — — 0 0 — — — — Max 1/4 1/4 510 — 128 — 1/2 — 255 tcyc — 8192 — — — — — 1 2 50 50 — — 2 30 2 30 Unit fsys fsys tcyc tcyc tcyc tcyc SCK tcyc ns ns tcyc tcyc ns ns ns ns tcyc tcyc ns ns ns ns µs ns µs ns 2 tqcyc 3 tlead Freescale Semiconductor, Inc... 4 tlag 5 tsw 6 ttd 7 tsu 8 9 10 11 thi ta tdis tv 12 tho 13 tri tro tfi tfo 14 NOTES: 1. Refer to notes in Table A-28. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-45 Freescale Semiconductor, Inc. Table A-28 QSPI Timing (VDD and VDDSYN = 5.0 Vdc ± 5% for 16.78 MHz, 10% for 20/25 MHz, VSS = 0 Vdc, TA = TL to TH)1 Num 1 Function Operating Frequency Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock (SCK) High or Low Time Master Slave2 Sequential Transfer Delay Master Slave (Does Not Require Deselect) Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Slave Access Time Slave MISO Disable Time Data Valid (after SCK Edge) Master Slave Data Hold Time (Outputs) Master Slave Rise Time Input Output Fall Time Input Output Symbol fop Min DC DC 4 4 2 2 — 2 2 tcyc – 60 2 tcyc – n 17 13 30 20 0 20 — — — — 0 0 — — — — Max 1/4 1/4 510 — 128 — 1/2 — 255 tcyc — 8192 — — — — — 1 2 50 50 — — 2 30 2 30 Unit fsys fsys tcyc tcyc tcyc tcyc SCK tcyc ns ns tcyc tcyc ns ns ns ns tcyc tcyc ns ns ns ns µs ns µs ns 2 tqcyc 3 tlead Freescale Semiconductor, Inc... 4 tlag 5 tsw 6 ttd 7 tsu 8 9 10 11 thi ta tdis tv 12 tho 13 tri tro tfi tfo 14 NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. 2. For high time, n = External SCK rise time; for low time, n = External SCK fall time. ELECTRICAL CHARACTERISTICS A-46 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 3 PCS[3:0] OUTPUT 13 12 SCK CPOL=0 OUTPUT 4 SCK CPOL=1 OUTPUT 6 7 MISO INPUT MSB IN DATA LSB IN 4 12 13 1 5 2 MSB IN Freescale Semiconductor, Inc... 11 MOSI OUTPUT 10 DATA LSB OUT PORT DATA 12 16 QSPI MAST CPHA0 PD 13 MSB OUT MSB OUT Figure A-16 QSPI Timing — Master, CPHA = 0 3 PCS[3:0] OUTPUT 13 1 SCK CPOL=0 OUTPUT 4 SCK CPOL=1 OUTPUT 4 12 13 6 MISO INPUT MSB IN DATA LSB IN 1 7 12 5 2 MSB 11 MOSI OUTPUT 10 DATA LSB OUT PORT DATA 12 16 QSPI MAST CPHA1 PORT DATA 13 MSB OUT MSB Figure A-17 QSPI Timing — Master, CPHA = 1 M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-47 Freescale Semiconductor, Inc. 3 SS INPUT 13 12 SCK CPOL=0 INPUT 4 SCK CPOL=1 INPUT 4 8 MISO OUTPUT MSB OUT 7 6 MOSI INPUT MSB IN DATA LSB IN 11 DATA 12 13 10 LSB OUT 11 9 PD 13 1 5 2 MSB OUT Freescale Semiconductor, Inc... MSB IN 16 QSPI SLV CPHA0 Figure A-18 QSPI Timing — Slave, CPHA = 0 SS INPUT 5 1 4 SCK CPOL=0 INPUT 2 SCK CPOL=1 INPUT 12 10 8 MISO OUTPUT PD MSB OUT 7 6 MOSI INPUT MSB IN DATA LSB IN 10 DATA 13 11 SLAVE LSB OUT 12 9 4 3 12 13 PD 16 QSPI SLV CPHA1 Figure A-19 QSPI Timing — Slave, CPHA = 1 ELECTRICAL CHARACTERISTICS A-48 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-29 Low Voltage SPI Timing (VDD and VDDSYN = 2.7 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH)1 Num 1 Function Operating Frequency Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock (SCK) High or Low Time Master Slave2 Sequential Transfer Delay Master Slave (Does Not Require Deselect) Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Slave Access Time Slave MISO Disable Time Data Valid (after SCK Edge) Master Slave Data Hold Time (Outputs) Master Slave Rise Time Input Output Fall Time Input Output Symbol fop Min DC DC 4 4 2 2 — 2 2 tcyc – 60 2 tcyc – n 17 13 20 20 30 20 — — — — 0 0 — — — — Max 1/4 1/4 510 — 128 — 1/2 — 255 tcyc — 8192 — — — — — 1 2 50 50 — — 2 30 2 30 Unit fsys fsys tcyc tcyc tcyc tcyc SCK tcyc ns ns tcyc tcyc ns ns ns ns tcyc tcyc ns ns ns ns µs ns µs ns 2 tqcyc 3 tlead Freescale Semiconductor, Inc... 4 tlag 5 tsw 6 ttd 7 tsu 8 9 10 11 thi ta tdis tv 12 tho 13 tri tro tfi tfo 14 NOTES: 1. Refer to notes in Table A-30. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-49 Freescale Semiconductor, Inc. Table A-30 SPI Timing (VDD and VDDSYN = 5.0 Vdc ± 10% for 16.78 MHz, 5% for 20/25 MHz, VSS = 0 Vdc, TA = TL to TH)1 Num 1 Function Operating Frequency Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock (SCK) High or Low Time Master Slave2 Sequential Transfer Delay Master Slave (Does Not Require Deselect) Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Slave Access Time Slave MISO Disable Time Data Valid (after SCK Edge) Master Slave Data Hold Time (Outputs) Master Slave Rise Time Input Output Fall Time Input Output Symbol fop Min DC DC 4 4 2 2 — 2 2 tcyc – 60 2 tcyc – n 17 13 30 20 0 20 — — — — 0 0 — — — — Max 1/4 1/4 510 — 128 — 1/2 — 255 tcyc — 8192 — — — — — 1 2 50 50 — — 2 30 2 30 Unit fsys fsys tcyc tcyc tcyc tcyc SCK tcyc ns ns tcyc tcyc ns ns ns ns tcyc tcyc ns ns ns ns µs ns µs ns 2 tqcyc 3 tlead Freescale Semiconductor, Inc... 4 tlag 5 tsw 6 ttd 7 tsu 8 9 10 11 thi ta tdis tv 12 tho 13 tri tro tfi tfo 14 NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. 2. For high time, n = External SCK rise time; for low time, n = External SCK fall time. ELECTRICAL CHARACTERISTICS A-50 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 13 12 SCK CPOL=0 OUTPUT 4 SCK CPOL=1 OUTPUT 6 7 MISO INPUT MSB IN DATA LSB IN MSB IN 4 12 13 1 11 MOSI OUTPUT 10 DATA LSB OUT PORT DATA 12 16 MCCI MAST CPHA0 Freescale Semiconductor, Inc... PD 13 MSB OUT MSB OUT Figure A-20 SPI Timing — Master, CPHA = 0 13 1 SCK CPOL=0 OUTPUT 4 SCK CPOL=1 OUTPUT 4 12 13 6 MISO INPUT MSB IN DATA LSB IN MSB 1 7 12 11 MOSI OUTPUT 10 DATA LSB OUT PORT DATA 12 16 MCCI MAST CPHA1 PORT DATA 13 MSB OUT MSB Figure A-21 SPI Timing — Master, CPHA = 1 M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-51 Freescale Semiconductor, Inc. 3 SS INPUT 13 12 SCK CPOL=0 INPUT 4 SCK CPOL=1 INPUT 4 8 MISO OUTPUT MSB OUT 7 6 MOSI INPUT MSB IN DATA LSB IN 11 DATA 12 13 10 LSB OUT 12 11 9 PD 13 1 5 2 MSB OUT Freescale Semiconductor, Inc... MSB IN 16 MCCI SLV CPHA0 Figure A-22 SPI Timing — Slave, CPHA = 0 SS INPUT 5 1 4 SCK CPOL=0 INPUT 2 SCK CPOL=1 INPUT 12 10 8 MISO OUTPUT PD MSB OUT 7 6 MOSI INPUT MSB IN DATA LSB IN 10 DATA 13 11 SLAVE LSB OUT 12 9 4 3 12 13 PD 16 MCCI SLV CPHA1 Figure A-23 SPI Timing — Slave, CPHA = 1 ELECTRICAL CHARACTERISTICS A-52 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-31 General-Purpose Timer AC Characteristics Num 1 2 3 4 5 6 7 8 Parameter Operating Frequency PCLK Frequency Pulse Width Input Capture PWM Resolution IC/OC Resolution PCLK Width (PWM) PCLK Width (IC/OC) PAI Pulse Width Symbol Fclock Fpclk PWtim — — — — — Min 0 0 2/Fclock 2/Fclock 4/Fclock 4/Fclock 4/Fclock 2/Fclock Max 16.78 1/4 Fclock — — — — — — Unit MHz MHz — — — — — — Freescale Semiconductor, Inc... PHI11 EXT PIN A2 B3 NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. A = INPUT SIGNAL AFTER THE SYNCHRONIZER. 3. B = “A” AFTER THE DIGITAL FILTER. INPUT SIG CONDITIONER TIM Figure A-24 Input Signal Conditioner Timing M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-53 Freescale Semiconductor, Inc. PHI11 PAEN EXT PIN (PAI) A2 Freescale Semiconductor, Inc... B3 PACNT $FF $00 PAIF4 PAOVF5 NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. A = PAI SIGNAL AFTER THE SYNCHRONIZER. 3. B = “A” AFTER THE DIGITAL FILTER. 4. THE EXTERNAL LEADING EDGE CAUSES THE PULSE ACCUMULATOR TO INCREMENT AND THE PAIF FLAG TO BE SET. 5. THE COUNTER TRANSITION FROM $FF TO $00 CAUSES THE PAOVF FLAG TO BE SET. PULSE ACCUM ECM LEAD EDGE Figure A-25 Pulse Accumulator — Event Counting Mode (Leading Edge) ELECTRICAL CHARACTERISTICS A-54 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. PHI11 PHI1/42 PAEN EXT PIN (PAI) Freescale Semiconductor, Inc... A3 B4 PACNT $77 $78 PAIF5 NOTES: 1. PHI1 HAS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. PHI1/4 CLOCKS PACNT WHEN GT-PAIF IS ASSERTED. 3. A = PAI SIGNAL AFTER THE SYNCHRONIZER. 4. B = “A” AFTER THE DIGITAL FILTER. 5. PAIF IS ASSERTED WHEN PAI IS NEGATED. PULSE ACCUM GATED MODE Figure A-26 Pulse Accumulator — Gated Mode (Count While Pin High) M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-55 Freescale Semiconductor, Inc. PHI11 PHI1/42 EXT PIN (PAI) TCNT $FFFE $FFFF $0000 Freescale Semiconductor, Inc... PACNT $77 $78 NOTES: 1. PHI1 HAS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. TCNT COUNTS AS A RESULT OF PHI1/4; PACNT COUNTS WHEN TCNT OVERFLOWS FROM $FFFF TO $0000 AND THE CONDITIONED PAI SIGNAL IS ASSERTED. PULSE ACCUM TOF GATED MODE Figure A-27 Pulse Accumulator — Using TOF as Gated Mode Clock PHI11 PHI1/21 PWMCNT[7:0]2 $FF $00 $01 $02 EXT PIN (PMWx) NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. WHEN THE COUNTER ROLLS OVER FROM $FF TO $00, THE PWM PIN IS SET TO LOGIC LEVEL ONE. WHEN THE COUNTER EQUALS THE PWM REGISTER, THE PWM PIN IS CLEARED TO A LOGIC LEVEL ZERO. PWMx FAST MODE Figure A-28 PWMx (PWMx Register = 01, Fast Mode) ELECTRICAL CHARACTERISTICS A-56 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. PHI11 COMPARE/CAPTURE CLOCK OCx COMPARE REGISTER $0102 TCNT2 $0101 $0102 $0103 Freescale Semiconductor, Inc... OCx MATCH OCxF EXT PIN (OCx) NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. WHEN THE TCNT MATCHES THE OCx COMPARE REGISTER, THE OCx FLAG IS SET FOLLOWED BY THE OCx PIN CHANGING STATE. OUTPUT COMPARE Figure A-29 Output Compare (Toggle Pin State) M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-57 Freescale Semiconductor, Inc. PHI11 COMPARE/CAPTURE CLOCK TCNT $0101 $0102 ICx EXTERNAL PIN Freescale Semiconductor, Inc... CONDITIONED INPUT2 ICx CAPTURE REGISTER $0102 ICxF NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. THE CONDITIONED INPUT SIGNAL CAUSES THE CURRENT VALUE OF THE TCNT TO BE LATCHED BY THE ICx CAPTURE REGISTER. THE ICxF FLAG IS SET AT THE SAME TIME. INPUT CAPTURE Figure A-30 Input Capture (Capture on Rising Edge) ELECTRICAL CHARACTERISTICS A-58 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. BUS STATES PHI11 PDDRx EXTERNAL PIN (INPUT) CONDITIONED INPUT Freescale Semiconductor, Inc... PDRx INTERNAL DATA BUS NEW DATA IMB READ CYCLE (READ BIT AS 1) IMB READ CYCLE (READ BIT AS 1) IMB READ CYCLE (READ BIT AS 0) NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. GENERAL PURPOSE INPUT Figure A-31 General-Purpose Input M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-59 Freescale Semiconductor, Inc. BUS STATES PHI11 B1 B2 B3 B4 B1 B2 B3 B4 B1 B2 B3 B4 B1 B2 B3 B4 INTERNAL DATA BUS PDR PDRx2 Freescale Semiconductor, Inc... EXTERNAL PIN (OUTPUT) CONDITIONED INPUT ICx COMPARE REGISTER $0102 PDDRX 0 TCNT IMB WRITE CYCLE $0101 IMB WRITE CYCLE $0102 NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. 2. WHEN THE BIT VALUE IS DRIVEN ON THE PIN, THE INPUT CIRCUIT SEES THE SIGNAL. AFTER IT IS CONDITIONED, IT CAUSES THE CONTENTS OF THE TCNT TO BE LATCHED INTO THE ICx COMPARE REGISTER. GENERAL PURPOSE OUTPUT Figure A-32 General-Purpose Output (Causes Input Capture) ELECTRICAL CHARACTERISTICS A-60 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. BUS STATES PHI11 B1 B2 B3 B4 B1 B2 B3 B4 B1 B2 B3 B4 B1 B2 B3 B4 COMPARE/ COMPARE CLOCK TCNT $0101 $0102 $0103 TOCx $AOF3 Freescale Semiconductor, Inc... FOCx OCxF (NOT SET) EXTERNAL PIN (OCx) IMB WRITE CYCLE NOTES: 1. PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING. FORCE COMPARE Figure A-33 Force Compare (CLEAR) M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-61 Freescale Semiconductor, Inc. Table A-32 ADC Maximum Ratings Num 1 2 3 4 5 6 7 8 9 10 11 12 Analog Supply Internal Digital Supply, with reference to VSSI Reference Supply, with reference to VSSI VSS Differential Voltage VDD Differential Voltage VREF Differential Voltage VRH to VDDA Differential Voltage VRL to VSSA Differential Voltage Disruptive Input Current VNEGCLAMP ≅ –0.3 V VPOSCLAMP ≅ 8 V 1, 2, 3, 4, 5, 6, 7 Parameter Symbol VDDA VDDI VRH, VRL VSSI –VSSA VDDI –VDDA VRH –VRL VRH –VDDA VRL –VSSA INA KP KN IMA Min –0.3 –0.3 –0.3 –0.1 –6.5 –6.5 –6.5 –6.5 –500 2000 500 –25 Max 6.5 6.5 6.5 0.1 6.5 6.5 6.5 6.5 500 — — 25 Unit V V V V V V V V µA — — mA Freescale Semiconductor, Inc... Positive Overvoltage Current Coupling Ratio1,5,6,8 Negative Overvoltage Current Coupling Ratio Maximum Input Current VNEGCLAMP ≅ –0.3 V VPOSCLAMP ≅ 8 V 3,4,6 1,5,6,8 NOTES: 1. Below disruptive current conditions, a stressed channel will store the maximum conversion value for analog inputs greater than VRH and the minimum conversion value for inputs less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample amplifier. Other channels are not affected by nondisruptive conditions. 2. Input signals with large slew rates or high frequency noise components cannot be converted accurately. These signals also interfere with conversion of other channels. 3. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 4. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using positive and negative clamp values, then use the larger of the calculated values. 5. This parameter is periodically sampled rather than 100% tested. 6. Applies to single pin only. 7. The values of external system components can change the maximum input current value, and affect operation. A voltage drop may occur across the external source impedances of the adjacent pins, impacting conversions on these adjacent pins. The actual maximum may need to be determined by testing the complete design. 8. Current coupling is the ratio of the current induced from overvoltage (positive or negative, through an external series coupling resistor), divided by the current induced on adjacent pins. A voltage drop may occur across the external source impedances of the adjacent pins, impacting conversions on these adjacent pins. ELECTRICAL CHARACTERISTICS A-62 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-33 Low Voltage ADC DC Electrical Characteristics (Operating) (VSS = 0 Vdc, ADCLK = 1.05 MHz, TA within operating temperature range) Num 1 2 3 4 5 6 7 8 Analog Supply 1 1 Parameter Symbol VDDA VDDI VSSI – VSSA VDDI – VDDA Min 2.7 2.7 – 1.0 – 0.6 VSSA VDDA / 2 2.7 VSSA 0.7 (VDDA) VSSA – 0.3 — — — — — — Max 3.6 3.6 1.0 0.6 VDDA / 2 VDDA 3.6 VDDA VDDA + 0.3 0.2 (VDDA) 1.0 200 120 150 10 15 Unit V V mV V V V V V V V mA µA µA nA pF pF Internal Digital Supply VSS Differential Voltage VDD Differential Voltage Reference Voltage Low 2, 3 2, 3 VRL VRH VRH – VRL VINDC VIH VIL IDDA IREF Reference Voltage High VREF Differential Input Voltage 2 Voltage3 Freescale Semiconductor, Inc... 9 10 11 12 13 14 15 Input High, Port ADA Input Low, Port ADA Analog Supply Current Normal Operation4 Low-Power Stop Reference Supply Current Input Current, Off Channel 5 IOFF CINN CINS Total Input Capacitance, Not Sampling Total Input Capacitance, Sampling NOTES: 1. Refers to operation over full temperature and frequency range. 2. To obtain full-scale, full-range results, VSSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA. 3. Accuracy tested and guaranteed at VRH – VRL = 2.7 V ± 3.6 Vdc. 4. Current measured at maximum system clock frequency with ADC active. 5. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 10°C decrease from maximum temperature. Table A-34 Low Voltage ADC AC Characteristics (Operating) (VDD and VDDA = 2.7 to 3.6 Vdc, VSS = 0 Vdc, TA within operating temperature range) Num 1 2 3 4 Parameter ADC Clock Frequency 8-Bit Conversion Time fADCLK = 1.05 MHz 1 Symbol fADCLK tCONV tCONV tSR Min 0.5 15.2 17.1 — Max 1.05 — — 50 Unit MHz µs µs µs 10-Bit Conversion Time1 fADCLK = 1.05 MHz Stop Recovery Time NOTES: 1. Conversion accuracy varies with fADCLK rate. Reduced conversion accuracy occurs at maximum. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-63 Freescale Semiconductor, Inc. Table A-35 5V ADC DC Electrical Characteristics (Operating) (VSS = 0 Vdc, ADCLK = 2.1 MHz, TA = TL to TH) Num 1 2 3 4 5 6 7 8 Analog Supply 1 1 Parameter Symbol VDDA VDDI VSSI – VSSA VDDI – VDDA Min 4.5 4.5 – 1.0 – 1.0 VSSA VDDA / 2 4.5 VSSA 0.7 (VDDA) VSSA – 0.3 — — — — — — Max 5.5 5.5 1.0 1.0 VDDA / 2 VDDA 5.5 VDDA VDDA + 0.3 0.2 (VDDA) 1.0 200 250 150 10 15 Unit V V mV V V V V V V V mA µA µA nA pF pF Internal Digital Supply VSS Differential Voltage VDD Differential Voltage Reference Voltage Low 2,3 2,3 VRL VRH VRH – VRL VINDC VIH VIL IDDA IREF 5 Reference Voltage High VREF Differential Input Voltage 2 Voltage3 Freescale Semiconductor, Inc... 9 10 11 12 13 14 15 Input High, Port ADA Input Low, Port ADA Analog Supply Current Normal Operation4 Low-Power Stop Reference Supply Current Input Current, Off Channel IOFF CINN CINS Total Input Capacitance, Not Sampling Total Input Capacitance, Sampling NOTES: 1. Refers to operation over full temperature and frequency range. 2. To obtain full-scale, full-range results, VSSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA. 3. Accuracy tested and guaranteed at VRH – VRL = 5.0 V ± 5% for 20/25 MHz, ± 10% for 16 MHz. 4. Current measured at maximum system clock frequency with ADC active. 5. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 10°C decrease from maximum temperature. ELECTRICAL CHARACTERISTICS A-64 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-36 ADC AC Characteristics (Operating) (VDD and VDDA = 5.0 Vdc ± 5% for 20/25 MHz, ± 10% for 16 MHz, VSS = 0 Vdc, TA within operating temperature range) Num 1 2 Parameter ADC Clock Frequency 8-Bit Conversion Time1 fADCLK = 1.0 MHz fADCLK = 2.1 MHz 10-Bit Conversion Time1 fADCLK = 1.0 MHz fADCLK = 2.1 MHz Stop Recovery Time Symbol fADCLK tCONV Min 0.5 15.2 7.6 17.1 8.6 — Max 2.1 — Unit MHz µs 3 4 tCONV tSR — 10 µs µs Freescale Semiconductor, Inc... NOTES: 1. Conversion accuracy varies with fADCLK rate. Reduced conversion accuracy occurs at maximum. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-65 Freescale Semiconductor, Inc. Table A-37 Low Voltage ADC Conversion Characteristics (Operating) (VDD and VDDA = 2.7 to 3.6 Vdc , VSS = 0 Vdc, TA = TL to TH, fADCLK = 1.05 MHz) Num 1 2 3 4 5 6 7 8 Parameter 8-Bit Resolution 1 Symbol 1 Count DNL INL AE 1 Count 3 Min — –0.5 –1.0 –1.5 — –1 –2.0 –4 — Typical 12 — — — 3 — — — 20 Max — 0.5 1.0 1.5 — 1 2.0 4.0 — Unit mV Counts Counts Counts mV Counts Counts Counts kΩ 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error 10-Bit Resolution 1 2 10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute Error 3,4 3 DNL INL AE RS Freescale Semiconductor, Inc... 9 Source Impedance at Input5 NOTES: 1. At VRH – VRL= 3.072 V, one 10-bit count = 3 mV and one 8-bit count = 12 mV. 2. 8-bit absolute error of 1.5 counts (18 mV) includes 1/2 count (6 mV) inherent quantization error and 1 count (12 mV) circuit (differential, integral, and offset) error. 3. Conversion accuracy varies with fADCLK rate. Reduced conversion accuracy occurs at maximum fADCLK. Assumes that minimum sample time (2 ADC clocks) is selected. 4. 10-bit absolute error of 4.0 counts (12 mV) includes 1/2 count (1.5 mV) inherent quantization error and 3.5 counts (10.5 mV) circuit (differential, integral, and offset) error. 5. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result value due to junction leakage is expressed in voltage (VERRJ): V ERRJ = R S × I OFF where IOFF is a function of operating temperature, as shown in Table A-35. Charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage between successive conversions, and the size of the decoupling capacitor used. Error levels are best determined empirically. In general, continuous conversion of the same channel may not be compatible with high source impedance. ELECTRICAL CHARACTERISTICS A-66 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table A-38 ADC Conversion Characteristics (Operating) (VDD and VDDA = 5.0 Vdc ± 5% for 20/25 MHz, ± 10% for 16 MHz, VSS = 0 Vdc, TA = TL to TH, 0.5 MHz ≤ fADCLK ≤ 1.0 MHz, 2 clock input sample time) Num 1 2 3 4 5 6 7 Parameter 8-Bit Resolution 1 Symbol 1 Count DNL INL AE 1 Count 3 Min — –0.5 –1 –1 — –1 –2.0 –2.5 — Typical 20 — — — 5 — — — 20 Max — 0.5 1 1 — 1 2.0 2.5 — Unit mV Counts Counts Counts mV Counts Counts Counts kΩ 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error 10-Bit Resolution 1 2 10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity3 3,4 DNL INL AE RS Freescale Semiconductor, Inc... 8 9 10-Bit Absolute Error Source Impedance at Input5 NOTES: 1. At VRH – VRL= 5.12 V, one 10-bit count = 5 mV and one 8-bit count = 20 mV. 2. 8-bit absolute error of 1 count (20 mV) includes 1/2 count (10 mV) inherent quantization error and 1/2 count (10 mV) circuit (differential, integral, and offset) error. 3. Conversion accuracy varies with fADCLK rate. Reduced conversion accuracy occurs at maximum fADCLK. Assumes that minimum sample time (2 ADC clocks) is selected. 4. 10-bit absolute error of 2.5 counts (12.5 mV) includes 1/2 count (2.5 mV) inherent quantization error and 2 counts (10 mV) circuit (differential, integral, and offset) error. 5. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result value due to junction leakage is expressed in voltage (VERRJ): V ERRJ = R S × I OFF where IOFF is a function of operating temperature, as shown in Table A-35. Charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage between successive conversions, and the size of the decoupling capacitor used. Error levels are best determined empirically. In general, continuous conversion of the same channel may not be compatible with high source impedance. M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-67 Freescale Semiconductor, Inc. ER RO R BO UN DA RY DIGITAL OUTPUT 8- BI T AB SO L UT E IDEAL TRANSFER CURVE A UT E Freescale Semiconductor, Inc... 8-BIT TRANSFER CURVE (NO CIRCUIT ERROR) 0 20 -1 B 8m V 8- BI T C AB SO L 40 INPUT IN mV, VRH – VRL = 3.072 V ER RO R BO UN DA RY +1 8 mV 60 A – +1/2 COUNT (6 mV) INHERENT QUANTIZATION ERROR B – CIRCUIT-CONTRIBUTED +12 mV ERROR C – +18 mV ABSOLUTE ERROR (1.5 8-BIT COUNTS) ADC 8-BIT ACCURACY LV Figure A-34 Low Voltage 8-Bit ADC Conversion Accuracy ELECTRICAL CHARACTERISTICS A-68 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. ER RO R BO UN DA RY IDEAL TRANSFER CURVE AB SO L UT E 8-BIT TRANSFER CURVE (NO CIRCUIT ERROR) DIGITAL OUTPUT +2 0 mV 8- BI T A C BO UN DA RY Freescale Semiconductor, Inc... 0 20 -2 0m V 8- BI T AB SO L 40 INPUT IN mV, VRH – VRL = 5.120 V UT E ER RO R B 60 A – +1/2 COUNT (10 mV) INHERENT QUANTIZATION ERROR B – CIRCUIT-CONTRIBUTED +10mV ERROR C – + 20 mV ABSOLUTE ERROR (ONE 8-BIT COUNT) ADC 8-BIT ACCURACY Figure A-35 8-Bit ADC Conversion Accuracy M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-69 Freescale Semiconductor, Inc. BO UN DA RY IDEAL TRANSFER CURVE 10-BIT TRANSFER CURVE (NO CIRCUIT ERROR) UT E ER RO R DIGITAL OUTPUT AB SO L C BO UN DA RY +1 2 mV 10 -B IT A AB SO L Freescale Semiconductor, Inc... 0 20 -1 2m V 10 -B IT UT E 40 INPUT IN mV, VRH – VRL = 3.072 V ER RO R B 60 A – +.5 COUNT (1.5 mV) INHERENT QUANTIZATION ERROR B – CIRCUIT-CONTRIBUTED +10.5 mV ERROR C – +12 mV ABSOLUTE ERROR (4 10-BIT COUNTS) ADC 10-BIT ACCURACY LV Figure A-36 Low Voltage 10-Bit ADC Conversion Accuracy ELECTRICAL CHARACTERISTICS A-70 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. BO UN DA RY IDEAL TRANSFER CURVE 10-BIT TRANSFER CURVE (NO CIRCUIT ERROR) UT E DIGITAL OUTPUT AB SO L ER RO R C BO UN DA RY +1 2 .5 mV 10 -B IT B A AB SO L Freescale Semiconductor, Inc... 0 20 -1 2.5 mV 10 -B IT 40 INPUT IN mV, VRH – VRL = 5.120 V UT E ER RO R 60 A – +.5 COUNT (2.5 mV) INHERENT QUANTIZATION ERROR B – CIRCUIT-CONTRIBUTED +10 mV ERROR C – +12.5 mV ABSOLUTE ERROR (2.5 10-BIT COUNTS) ADC 10-BIT ACCURACY Figure A-37 10-Bit ADC Conversion Accuracy M68HC16 Z SERIES USER’S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product, Go to: www.freescale.com A-71 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ELECTRICAL CHARACTERISTICS A-72 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION M68HC16 Z-series microcontrollers are available in both 132- and 144-pin packages. This appendix provides package pin assignment drawings, dimensional drawings, and ordering information. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com B-1 Freescale Semiconductor, Inc. RXD PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS/PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 VSS VDD IC1/PGP0 IC2/PGP1 IC3/PGP2 OC1/PGP3 OC2/OC1/PGP4 VSS VDD OC3/OC1/PGP5 OC4/OC1/PGP6 IC4/OC5/OC1/PGP7 PAI PWMA PWMB PCLK VSS VDD ADDR23/CS10/ECLK ADDR22/CS9/PC6 ADDR21/CS8/PC5 ADDR20/CS7/PC4 ADDR19/CS6/PC3 BGACK/CS2 BG/CS1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 Freescale Semiconductor, Inc... TXD/PQS7 ADDR1 ADDR2 VDD VSS ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 VSS ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 VDD VSS VDDA VSSA AN0/PADA0 AN1/PADA1 AN2/PADA2 AN3/PADA3 AN4/PADA4 AN5/PADA5 VRH 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 MC68HC16Z3 MMMMM1 ATWLYYWW2 BR/CS0 FC2/CS5/PC2 FC1/CS4/PC1 VDD VSS FC0/CS3/PC0 CSBOOT DATA0 DATA1 DATA2 DATA3 VSS DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 VDD VSS DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ADDR0 DSACK0/PE0 DSACK1/PE1 AVEC/PE2 DS/PE4 AS/PE5 VDD NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK Figure B-1 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package B-2 VRL AN6/PADA6 AN7/PADA7 VSTBY XTAL VDDSYN EXTAL VSS VDD XFC VDD VSS CLKOUT FREEZE/QUOT TSC BKPT/DSCLK IPIPE0/DSO IPIPE1/DSI RESET HALT BERR IRQ7/PF7 IRQ6/PF6 IRQ5/PF5 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 MODCLK/PF0 R/W SIZ1/PE7 SIZ0/PE6 VSS HC16Z1/CKZ1/CMZ1/Z2/Z3 132-PIN QFP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. NC RXDA/PMC6 TXDB/PMC5 RXDB/PMC4 SS/PMC3 SCK/PMC2 MOSI/PMC1 MISO/PMC0 VSS VDD IC1/PGP0 IC2/PGP1 IC3/PGP2 OC1/PGP3 OC2/OC1/PGP4 VSS VDD OC3/OC1/PGP5 OC4/OC1/PGP6 IC4/OC5/OC1/PGP7 PAI PWMA PWMB PCLK VSS VDD ADDR23/CS10/ECLK ADDR22/CS9/PC6 ADDR21/CS8/PC5 ADDR20/CS7/PC4 ADDR19/CS6/PC3 BGACK/CS2 BG/CS1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 Freescale Semiconductor, Inc... TXDA/PMC7 ADDR1 ADDR2 VDD VSS ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 VSS ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 VDD VSS VDDA VSSA AN0/PADA0 AN1/PADA1 AN2/PADA2 AN3/PADA3 AN4/PADA4 AN5/PADA5 VRH 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MC68HC16Z4 MC68CK16Z4 MMMMM1 ATWLYYWW2 BR/CS0 FC2/CS5/PC2 FC1/CS4/PC1 VDD VSS FC0/CS3/PC0 CSBOOT DATA0 DATA1 DATA2 DATA3 VSS DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 VDD VSS DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ADDR0 DSACK0/PE0 DSACK1/PE1 AVEC/PE2 DS/PE4 AS/PE5 VDD NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK VRL AN6/PADA6 AN7/PADA7 VSTBY XTAL VDDSYN EXTAL VSS VDD XFC VDD VSS CLKOUT FREEZE/QUOT TSC BKPT/DSCLK IPIPE0/DSO IPIPE1/DSI RESET HALT BERR IRQ7/PF7 IRQ6/PF6 IRQ5/PF5 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 MODCLK/PF0 R/W SIZ1/PE7 SIZ0/PE6 VSS HC16Z4/CK16Z4 132-PIN QFP Figure B-2 MC68HC16Z4/CKZ4 Pin Assignments for 132-Pin Package M68HC16 Z SERIES USER’S MANUAL 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com B-3 Freescale Semiconductor, Inc. A A1 S S1 J 1 17 18 PIN 1 IDENT 128X G AC AC X X=L, M, OR N J1 N 117 116 VIEW AB V1 M P V AA P1 B1 BASE METAL C L VIEW AB B E Freescale Semiconductor, Inc... L AA 50 51 83 84 0.016 H L–M N 0.010 T L–M N 0.012 H L–M N 0.002 N 2X 0.002 L–M 4X 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1982. 2. DIMENSIONS IN INCHES. 3. DIMENSIONS A, B, J, AND P DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION FOR DIMENSIONS A AND B IS 0.007, FOR DIMENSIONS J AND P IS 0.010. 4. DATUM PLANE H IS LOCATED AT THE UNDERSIDE OF LEADS WHERE LEADS EXIT PACKAGE BODY. 5. DATUMS L, M, AND N TO BE DETERMINED WHERE CENTER LEADS EXIT PACKAGE BODY AT DATUM H. 6. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 7. DIMENSIONS A, B, J, AND P TO BE DETERMINED AT DATUM PLANE H. 8. DIMENSION F DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.019. INCHES MIN MAX 1.100 BSC 0.550 BSC 1.100 BSC 0.550 BSC 0.160 0.180 0.020 0.040 0.135 0.145 0.008 0.012 0.012 0.016 0.008 0.011 0.006 0.008 0.005 0.007 0.014 0.014 0.025 BSC 0.950 BSC 0.475 BSC 0.034 0.044 0.010 BSC 0.950 BSC 0.475 BSC 0.013 REF 1.080 BSC 0.540 BSC 0.025 REF 1.080 BSC 0.540 BSC 0.006 0.008 0_ 8_ 4X 33 TIPS 4X C C2 0.004 T SEATING PLANE 132X C1 132X T D1 M 0.008 T L–M N R R1 H K1 GAGE PLANE U 132X D 0.008 M K T L–M N SECTION AA–AA W q DIM A A1 B B1 C C1 C2 D D1 D2 E E1 F G J J1 K K1 P P1 R1 S S1 U V V1 W q Figure B-3 Case 831A-01 — 132-Pin Package Dimensions MECHANICAL DATA AND ORDERING INFORMATION B-4 For More Information On This Product, Go to: www.freescale.com ÍÍÍÍ ÇÇÇ ÍÍÍÍ ÇÇÇ ÍÍÍÍ D2 (D) E1 PLATING SECTION AC–AC M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VSS SIZ0/PE6 SIZ1/PE7 R/W MODCLK/PF0 IRQ1/PF1 IRQ2/PF2 IRQ3/PF3 IRQ4/PF4 IRQ5/PF5 IRQ6/PF6 IRQ7/PF7 BERR HALT RESET IPIPE1/DSI IPIPE0/DSO BKPT/DSCLK NC TSC FREEZE/QUOT CLKOUT VSS VDD XFC NC VDD VSS EXTAL VDDSYN XTAL VSTBY AN7/PADA7 AN6/PADA6 VRLP NC Freescale Semiconductor, Inc... VDD AS/PE5 DS/PE4 AVEC/PE2 DSACK1/PE1 DSACK0/PE0 ADDR0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 VSS NC VDD DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 NC VSS NC DATA3 DATA2 DATA1 DATA0 CSBOOT FC0/CS3/PC0 VSS VDD FC1/CS4/PC1 FC2/CS5/PC2 BR/CS0 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 MC68HC16Z3 MMMMM1 ATWLYYWW2 VRHP AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 VSSA VDDA VSS VDD ADDR18 ADDR17 ADDR16 ADDR15 NC ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 NC VSS NC ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 VSS VDD ADDR2 ADDR1 TXD/PQS7 NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK Figure B-4 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 144-Pin Package M68HC16 Z SERIES USER’S MANUAL NC BG/CS1 BGACK/CS2 ADDR19/CS6/PC5 ADDR20/CS7/PC4 ADDR21/CS8/PC5 ADDR22/CS9/PC6 ADDR23/CS10 VDD VSS PCLK PWMB PWMA PAI IC4/OC5/OC1/PGP7 OC4/OC1/PGP6 OC3/OC1/PCP5 NC VDD VSS OC2/PGP4 OC1/PGP3 IC3/PGP2 IC2/PGP1 IC1/PGP0 VDD VSS MISO/PQS0 MOSI/PQS1 SCK/PQS2 PCS0/SS/PQS3 PCS1/PQS4 PCS2/PQS5 PCS3/PQS6 RXD NC HC16Z1/CKZ1/CMZ1/Z2/Z3 144-PIN QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com B-5 Freescale Semiconductor, Inc. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VSS SIZ0/PE6 SIZ1/PE7 R/W MODCLK/PF0 IRQ1/PF1 IRQ2/PF2 IRQ3/PF3 IRQ4/PF4 IRQ5/PF5 IRQ6/PF6 IRQ7/PF7 BERR HALT RESET IPIPE1/DSI IPIPE0/DSO BKPT/DSCLK NC TSC FREEZE/QUOT CLKOUT VSS VDD XFC NC VDD VSS EXTAL VDDSYN XTAL VSTBY AN7/PADA7 AN6/PADA6 VRLP NC Freescale Semiconductor, Inc... VDD AS/PE5 DS/PE4 AVEC/PE2 DSACK1/PE1 DSACK0/PE0 ADDR0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 VSS NC VDD DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 NC VSS NC DATA3 DATA2 DATA1 DATA0 CSBOOT FC0/CS3/PC0 VSS VDD FC1/CS4/PC1 FC2/CS5/PC2 BR/CS0 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 MC68HC16Z4 MC68CK16Z4 MMMMM1 ATWLYYWW2 VRHP AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 VSSA VDDA VSS VDD ADDR18 ADDR17 ADDR16 ADDR15 NC ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 NC VSS NC ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 VSS VDD ADDR2 ADDR1 TXDA/PMC7 NOTES: 1. MMMMM = MASK OPTION NUMBER 2. ATWLYYWW = ASSEMBLY TEST LOCATION/YEAR, WEEK NC BG/CS1 BGACK/CS2 ADDR19/CS6/PC5 ADDR20/CS7/PC4 ADDR21/CS8/PC5 ADDR22/CS9/PC6 ADDR23/CS10 VDD VSS PCLK PWMB PWMA PAI IC4/OC5/OC1/PGP7 OC4/OC1/PGP6 OC3/OC1/PCP5 NC VDD VSS OC2/PGP4 OC1/PGP3 IC3/PGP2 IC2/PGP1 IC1/PGP0 VDD VSS MISO/PMC0 MOSI/PMC1 SCK/PMC2 SS/PMC3 RXDB/PMC4 TXDB/PMC5 NC RXDA/PMC6 NC HC16Z4/CK16Z4 144-PIN QFP Figure B-5 MC68HC16Z4/CKZ4 Pin Assignments for 144-Pin Package B-6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. 4X 0.20 T L–M N 4X 36 TIPS 0.20 T L–M N PIN 1 IDENT 1 144 109 108 J1 J1 L M B V 140X 4X P C L X X=L, M OR N G Freescale Semiconductor, Inc... VIEW Y 36 73 B1 V1 VIEW Y 37 72 N A1 S1 A S VIEW AB C NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.35. MILLIMETERS MIN MAX 20.00 BSC 10.00 BSC 20.00 BSC 10.00 BSC 1.40 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.45 0.75 0.17 0.23 0.50 BSC 0.09 0.20 0.50 REF 0.25 BSC 0.13 0.20 0.13 0.20 22.00 BSC 11.00 BSC 22.00 BSC 11.00 BSC 0.25 REF 1.00 REF 0.09 0.16 0_ 0_ 7_ 11_ 13 _ q2 q2 T 0.1 T 144X DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA SEATING PLANE PLATING J F AA C2 0.05 0.08 SECTION J1–J1 (ROTATED 90 _ ) 144 PL M68HC16 Z SERIES USER’S MANUAL É Ç ÉÉÉ ÇÇÇ ÉÉ ÇÇ ÉÉÉ ÇÇÇ D M q R2 R1 BASE METAL 0.25 GAGE PLANE T L–M N (K) C1 (Y) VIEW AB (Z) E q q1 q2 q1 Figure B-6 Case 918 — 144-Pin Package Dimensions MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com B-7 Freescale Semiconductor, Inc. B.1 Obtaining Updated M68HC16 Z-Series MCU Mechanical Information Although all devices manufactured by Freescale conform to current JEDEC standards, complete mechanical information regarding M68HC16 Z-series microcontrollers is available through Motorola’s Design-Net. To download updated package specifications, perform the following steps: 1. Visit the Design-Net case outline database search engine at http://design-net.com/cgi-bin/cases. 2. Enter the case outline number, located in Figure B-3 without the revision code (for example, 831A, not 831A-01) in the field next to the search button. 3. Download the file with the new package diagram. Freescale Semiconductor, Inc... B.2 Ordering Information Use the information in Table B-1 to specify the appropriate device when placing an order. Table B-1 M68HC16 Z-Series Ordering Information (Shaded cells indicate preliminary part numbers) Device MC68HC16Z1 Crystal Input 32 kHz Operating Voltage 5V Package Type 132-Pin PQFP Temperature –40 to +85°C Frequency (MHz) 16 MHz Package Order Quantity 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +105°C 16 MHz 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 Order Number SPMCK16Z1CFC16 MCK68HC16Z1CFC16 MCK16Z1CFC16B1 SPMCK16Z1CFC20 MCK68HC16Z1CFC20 MCK16Z1CFC20B1 SPMCK16Z1CFC25 MCK68HC16Z1CFC25 MCK16Z1CFC25B1 SPMCK16Z1VFC16 MCK68HC16Z1VFC16 MCK16Z1VFC16B1 SPMCK16Z1VFC20 MCK68HC16Z1VFC20 MCK16Z1VFC20B1 SPMCK16Z1VFC25 MCK68HC16Z1VFC25 MCK16Z1VFC25B1 MECHANICAL DATA AND ORDERING INFORMATION B-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Device MC68HC16Z1 Crystal Input 32 kHz Operating Voltage 5V Package Type 132-Pin PQFP Temperature –40 to +125°C Frequency (MHz) 16 MHz Package Order Quantity 2 36 180 20 MHz 2 36 180 MC68HC16Z1 32 kHz 5V 144-Pin TQFP –40 to +85°C 16 MHz 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +105°C 16 MHz 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +125°C 16 MHz 2 60 300 20 MHz 2 60 300 MC68HC16Z1 32 kHz 2.7 V 132-Pin PQFP –40 to +85°C 16 MHz 2 36 180 144-Pin TQFP –40 to +85°C 16 MHz 2 60 300 MC68HC16Z1 4 MHz 2.7 V 132-Pin PQFP –40 to +85°C 16 MHz 2 36 180 Order Number SPMCK16Z1MFC16 MCK68HC16Z1MFC16 MCK16Z1MFC16B1 SPMCK16Z1MFC20 MCK68HC16Z1MFC20 MCK16Z1MFC20B1 SPMCK16Z1CPV16 MCK68HC16Z1CPV16 MCK16Z1CPV16B1 SPMCK16Z1CPV20 MCK68HC16Z1CPV20 MCK16Z1CPV20B1 SPMCK16Z1CPV25 MCK68HC16Z1CPV25 MCK16Z1CPV25B1 SPMCK16Z1VPV16 MCK68HC16Z1VPV16 MCK16Z1VPV16B1 SPMCK16Z1VPV20 MCK68HC16Z1VPV20 MCK16Z1VPV20B1 SPMCK16Z1VPV25 MCK68HC16Z1VPV25 MCK16Z1VPV25B1 SPMCK16Z1MPV16 MCK68HC16Z1MPV16 MCK16Z1MPV16B1 SPMCK16Z1MPV20 MCK68HC16Z1MPV20 MCK16Z1MPV20B1 SPMCCK16Z1CFC16 MC68CK16Z1CFC16 MCCK16Z1CFC16B1 SPMCCK16Z1CPV16 MC68CK16Z1CPV16 MCCK16Z1CPV16B1 SPMCCM16Z1CFC16 MC68CM16Z1CFC16 MCCM16Z1CFC16B1 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com B-9 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Device MC68HC16Z1 Crystal Input 4 MHz Operating Voltage 2.7 V Package Type 144-Pin TQFP Temperature –40 to +85°C Frequency (MHz) 16 MHz Package Order Quantity 2 60 300 MC68HC16Z2 (ROM) 4 MHz or 32 kHz 5V 132-Pin PQFP –40 to +85°C 16 MHz 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +105°C 16 MHz 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +125°C 16 MHz 2 36 180 20 MHz 2 36 180 144-Pin TQFP –40 to +85°C 16 MHz 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 Order Number SPMCCM16Z1CPV16 MC68CM16Z1CPV16 MCCM16Z1CPV16B1 NA MC68HC16Z2CFC16 NA NA MC68HC16Z2CFC20 NA NA MC68HC16Z2CFC25 NA NA MC68HC16Z2VFC16 NA NA MC68HC16Z2VFC20 NA NA MC68HC16Z2VFC25 NA NA MC68HC16Z2MFC16 NA NA MC68HC16Z2MFC20 NA NA MC68HC16Z2CPV16 NA NA MC68HC16Z2CPV20 NA NA MC68HC16Z2CPV25 NA Freescale Semiconductor, Inc... MECHANICAL DATA AND ORDERING INFORMATION B-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Device MC68HC16Z2 (ROM) Crystal Input 4 MHz or 32 kHz Operating Voltage 5V Package Type 144-Pin TQFP Temperature –40 to +105°C Frequency (MHz) 16 MHz Package Order Quantity 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +125°C 16 MHz 2 60 300 20 MHz 2 60 300 MC68HC16Z2 (No ROM) 4 MHz 5V 132-Pin PQFP –40 to +85°C 16 MHz 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +105°C 16 MHz 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +125°C 16 MHz 2 36 180 20 MHz 2 36 180 Order Number NA MC68HC16Z2VPV16 NA NA MC68HC16Z2VPV20 NA NA MC68HC16Z2VPV25 NA NA MC68HC16Z2MPV16 NA NA MC68HC16Z2MPV20 NA SPMCM16Z2BCFC16 MCM16Z2BCFC16 MCM16Z2BCFC16B1 SPMCM16Z2BCFC20 MCM16Z2BCFC20 MCM16Z2BCFC20B1 SPMCM16Z2BCFC25 MCM16Z2BCFC25 MCM16Z2BCFC25B1 SPMCM16Z2BVFC16 MCM16Z2BVFC16 MCM16Z2BVFC16B1 SPMCM16Z2BVFC20 MCM16Z2BVFC20 MCM16Z2BVFC20B1 SPMCM16Z2BVFC25 MCM16Z2BVFC25 MCM16Z2BVFC25B1 SPMCM16Z2BMFC16 MCM16Z2BMFC16 MCM16Z2BMFC16B1 SPMCM16Z2BMFC20 MCM16Z2BMFC20 MCM16Z2BMFC20B1 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com B-11 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Device MC68HC16Z2 (No ROM) Crystal Input 4 MHz Operating Voltage 5V Package Type 144-Pin TQFP Temperature –40 to +85°C Frequency (MHz) 16 MHz Package Order Quantity 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +105°C 16 MHz 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +125°C 16 MHz 2 60 300 20 MHz 2 60 300 MC68HC16Z3 (ROM) 4 MHz or 32 kHz 5V 132-Pin PQFP –40 to +85°C 16 MHz 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 Order Number SPMCM16Z2BCPV16 MCM16Z2BCPV16 MCM16Z2BCPV16B1 SPMCM16Z2BCPV20 MCM16Z2BCPV20 MCM16Z2BCPV20B1 SPMCM16Z2BCPV25 MCM16Z2BCPV25 MCM16Z2BCPV25B1 SPMCM16Z2BVPV16 MCM16Z2BVPV16 MCM16Z2BVPV16B1 SPMCM16Z2BVPV20 MCM16Z2BVPV20 MCM16Z2BVPV20B1 SPMCM16Z2BVPV25 MCM16Z2BVPV25 MCM16Z2BVPV25B1 SPMCM16Z2BMPV16 MCM16Z2BMPV16 MCM16Z2BMPV16B1 SPMCM16Z2BMPV20 MCM16Z2BMPV20 MCM16Z2BMPV20B1 NA MC68HC16Z3CFC16 NA NA MC68HC16Z3CFC20 NA NA MC68HC16Z3CFC25 NA Freescale Semiconductor, Inc... MECHANICAL DATA AND ORDERING INFORMATION B-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Device MC68HC16Z3 (ROM) Crystal Input 4 MHz or 32 kHz Operating Voltage 5V Package Type 132-Pin PQFP Temperature –40 to +105°C Frequency (MHz) 16 MHz Package Order Quantity 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +125°C 16 MHz 2 36 180 20 MHz 2 36 180 144-Pin TQFP –40 to +85°C 16 MHz 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +105°C 16 MHz 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +125°C 16 MHz 2 60 300 20 MHz 2 60 300 Order Number NA MC68HC16Z3CFC16 NA NA MC68HC16Z3VFC20 NA NA MC68HC16Z3VFC25 NA NA MC68HC16Z3MFC16 NA NA MC68HC16Z3MFC20 NA NA MC68HC16Z3CPV16 NA NA MC68HC16Z3CPV20 NA NA MC68HC16Z3CPV25 NA NA MC68HC16Z3VPV16 NA NA MC68HC16Z3VPV20 NA NA MC68HC16Z3VPV25 NA NA MC68HC16Z3MPV16 NA NA MC68HC16Z3MPV20 NA Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com B-13 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Device MC68HC16Z3 (RTOS) Crystal Input 4 MHz Operating Voltage 5V Package Type 132-Pin PQFP Temperature –40 to +85°C Frequency (MHz) 16 MHz Package Order Quantity 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +105°C 16 MHz 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +125°C 16 MHz 2 36 180 20 MHz 2 36 180 144-Pin TQFP –40 to +85°C 16 MHz 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 Order Number SPMCM16Z3RCFC16 MCM16Z3RCFC16 MCM16Z3RCFC16B1 SPMCM16Z3RCFC20 MCM16Z3RCFC20 MCM16Z3RCFC20B1 SPMCM16Z3RCFC25 MCM16Z3RCFC25 MCM16Z3RCFC25B1 SPMCM16Z3RVFC16 MCM16Z3RVFC16 MCM16Z3RVFC16B1 SPMCM16Z3RVFC20 MCM16Z3RVFC20 MCM16Z3RVFC20B1 SPMCM16Z3RVFC25 MCM16Z3RVFC25 MCM16Z3RVFC25B1 SPMCM16Z3RMFC16 MCM16Z3RMFC16 MCM16Z3RMFC16B1 SPMCM16Z3RMFC20 MCM16Z3RMFC20 MCM16Z3RMFC20B1 SPMCM16Z3RCPV16 MCM16Z3RCPV16 MCM16Z3RCPV16B1 SPMCM16Z3RCPV20 MCM16Z3RCPV20 MCM16Z3RCPV20B1 SPMCM16Z3RCPV25 MCM16Z3RCPV25 MCM16Z3RCPV25B1 Freescale Semiconductor, Inc... MECHANICAL DATA AND ORDERING INFORMATION B-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Device MC68HC16Z3 (RTOS) Crystal Input 4 MHz Operating Voltage 5V Package Type 144-Pin TQFP Temperature –40 to +105°C Frequency (MHz) 16 MHz Package Order Quantity 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +125°C 16 MHz 2 60 300 20 MHz 2 60 300 MC68HC16Z4 32 kHz 5V 132-Pin PQFP –40 to +85°C 16 MHz 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +105°C 16 MHz 2 36 180 20 MHz 2 36 180 25 MHz 2 36 180 –40 to +125°C 16 MHz 2 36 180 20 MHz 2 36 180 Order Number SPMCM16Z3RVPV16 MCM16Z3RVPV16 MCM16Z3RVPV16B1 SPMCM16Z3RVPV20 MCM16Z3RVPV20 MCM16Z3RVPV20B1 SPMCM16Z3RVPV25 MCM16Z3RVPV25 MCM16Z3RVPV25B1 SPMCM16Z3RMPV16 MCM16Z3RMPV16 MCM16Z3RMPV16B1 SPMCM16Z3RMPV20 MCM16Z3RMPV20 MCM16Z3RMPV20B1 SPMCK16Z4CFC16 MCK68HC16Z4CFC16 MCK16Z4CFC16B1 SPMCK16Z4CFC20 MCK68HC16Z4CFC20 MCK16Z4CFC20B1 SPMCK16Z4CFC25 MCK68HC16Z4CFC25 MCK16Z4CFC25B1 SPMCK16Z4VFC16 MCK68HC16Z4VFC16 MCK16Z4VFC16B1 SPMCK16Z4VFC20 MCK68HC16Z4VFC20 MCK16Z1VFC20B1 SPMCK16Z4VFC25 MCK68HC16Z4VFC25 MCK16Z4VFC25B1 SPMCK16Z4MFC16 MCK68HC16Z4MFC16 MCK16Z4MFC16B1 SPMCK16Z4MFC20 MCK68HC16Z4MFC20 MCK16Z4MFC20B1 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product, Go to: www.freescale.com B-15 Freescale Semiconductor, Inc. Table B-1 M68HC16 Z-Series Ordering Information (Continued) (Shaded cells indicate preliminary part numbers) Device MC68HC16Z4 Crystal Input 32 kHz Operating Voltage 5V Package Type 144-Pin TQFP Temperature –40 to +85°C Frequency (MHz) 16 MHz Package Order Quantity 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +105°C 16 MHz 2 60 300 20 MHz 2 60 300 25 MHz 2 60 300 –40 to +125°C 16 MHz 2 60 300 20 MHz 2 60 300 2.7 V 132-Pin PQFP –40 to +85°C 16 MHz 2 36 180 144-Pin TQFP –40 to +85°C 16 MHz 2 60 300 Order Number SPMCK16Z4CPV16 MCK68HC16Z4CPV16 MCK16Z4CPV16B1 SPMCK16Z4CPV20 MCK68HC16Z4CPV20 MCK16Z4CPV20B1 SPMCK16Z4CPV25 MCK68HC16Z4CPV25 MCK16Z4CPV25B1 SPMCK16Z4VPV16 MCK68HC16Z4VPV16 MCK16Z4VPV16B1 SPMCK16Z4VPV20 MCK68HC16Z4VPV20 MCK16Z4VPV20B1 SPMCK16Z4VPV25 MCK68HC16Z4VPV25 MCK16Z4VPV25B1 SPMCK16Z4MPV16 MCK68HC16Z4MPV16 MCK16Z4MPV16B1 SPMCK16Z4MPV20 MCK68HC16Z4MPV20 MCK16Z4MPV20B1 SPMCCK16Z4CFC16 MC68CK16Z4CFC16 MCCK16Z4CFC16B1 SPMCCK16Z4CPV16 MC68CK16Z4CPV16 MCCK16Z4CPV16B1 Freescale Semiconductor, Inc... MECHANICAL DATA AND ORDERING INFORMATION B-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. APPENDIX C DEVELOPMENT SUPPORT This section serves as a brief reference to Freescale development tools for M68HC16 Z-series microcontrollers. Information provided is complete as of the time of publication, but new systems and software are continually being developed. In addition, there is a growing number of third-party tools available. The FreescaleMicrocontroller Development Tools Directory (MCUDEVTLDIR/D Revision. 3) provides an up-to-date list of development tools. Contact your Freescale representative for further information. C.1 M68MMDS1632 Modular Development System The M68MMDS1632 Freescale modular development system (MMDS) is a development tool for evaluating M68HC16 and M68300 MCU-based systems. The MMDS1632 is an in-circuit emulator, which includes a station module and active probe. A separately purchased MPB and PPB completes MMDS functionality with regard to a particular MCU or MCU family. The many MPBs and PPBs available let the MMDS emulate a variety of different MCUs. Contact your Freescale sales representative, who will assist you in selecting and configuring the modular system that fits your needs. A full-featured development system, the MMDS provides both in-circuit emulation and bus analysis capabilities, including: • Real-time in-circuit emulation at maximum speed of 16 MHz • Built-in emulation memory — 1-Mbyte main emulation memory (three-clock bus cycle) — 256-Kbyte fast termination (two-clock bus cycle) — 4-Kbyte dual-port emulation memory (three-clock bus cycle) • Real-time bus analysis — Instruction disassembly — State-machine-controlled triggering • Four hardware breakpoints; bitwise masking • Analog/digital emulation • Synchronized signal output • Built-in AC power supply, 90 – 264 V, 50 – 60 Hz, FCC and EC EMI compliant • RS-232 connection to host capable of communicating at 1200, 2400, 4800, 9600, 19200, 38400, or 57600 baud Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL DEVELOPMENT SUPPORT For More Information On This Product, Go to: www.freescale.com C-1 Freescale Semiconductor, Inc. C.2 M68MEVB1632 Modular Evaluation Board The M68MEVB1632 Modular Evaluation Board (MEVB) is a development tool for evaluating M68HC16 and M68300 MCU-based systems. The MEVB consists of the M68MPFB1632 modular platform board, an MCU personality board (MPB), an in-circuit debugger (ICD16 or ICD32), and development software. MEVB features include: • An economical means of evaluating target systems incorporating M68HC16 and M68300 HCMOS MCU devices • Expansion memory sockets for installing RAM, EPROM, or EEPROM — Data RAM: 32K x 16, 128K x 16, or 512K x 16 — EPROM/EEPROM: 32K x 16, 64K x 16, 128K x 16, 256K x 16, or 512K x 16 — Fast RAM: 32K x 16 or 128K x 16 • Background-mode operation, for detailed operation from a personal computer platform without an on-board monitor • Integrated assembly/editing/evaluation/programming environment for easy development • As many as seven software breakpoints • Re-usable ICD hardware for your target application debug or control • Two RS-232C terminal input/output (I/O) ports for user evaluation of the serial communication interface • Logic analyzer pod connectors • Port replacement unit (PRU) to rebuild I/O ports lost to address/data/control • On-board VPP (+12 VDC) generation for MCU and flash EEPROM programming. • On-board wire-wrap area NOTE The MC68HC16Z1 and the MC68HC16Z2/Z3 both utilize the M68HC16MPFB, however, each MCU uses a different personality board (M68MPB16Z1 on the MC68HC16Z1; M68MPB16Z2/Z3 on the MC68HC16Z2/Z3). Freescale Semiconductor, Inc... DEVELOPMENT SUPPORT C-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. APPENDIX D REGISTER SUMMARY This appendix contains address maps, register diagrams, and bit/field definitions for M68HC16 Z-series MCUs. More detailed information about register function is provided in the appropriate sections of the manual. Except for central processing unit resources, information is presented in the intermodule bus address order shown in Table D-1. Freescale Semiconductor, Inc... Table D-1 Module Address Map Module SIM SRAM MRM (MC68HC16Z2/MC68HC16Z3 only) ADC QSM MCCI (MC68HC16Z4, MC68CK16Z4 only) GPT Size (Bytes) 128 8 32 64 512 64 64 Base Address $YFFA00 $YFFB00 $YFF820 $YFF700 $YFFC00 $YFFC00 $YFF900 Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping (MM) bit in the SIM module configuration register (SIMCR) determines where the control registers block is located in the system memory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when MM = 1, register addresses range from $FFF000 to $FFFFFF. With the CPU16, ADDR[23:20] follow the logic state of ADDR19 unless driven externally. MM corresponds to IMB ADDR23. If it is cleared, the SIM maps IMB modules into address space $7FF000 – $7FFFFF, which is inaccessible to the CPU16. Modules remain inaccessible until reset occurs. The reset state of MM is one, but the bit is can be written once. Initialization software should make certain it remains set. D.1 Central Processing Unit CPU16 registers are not part of the module address map. Figure D-1 is a functional representation of CPU resources. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-1 Freescale Semiconductor, Inc. 20 16 15 87 0 BIT POSITION A D B ACCUMULATORS A AND B ACCUMULATOR D (A:B) E ACCUMULATOR E XK IX INDEX REGISTER X Freescale Semiconductor, Inc... YK IY INDEX REGISTER Y ZK IZ INDEX REGISTER Z SK SP STACK POINTER SP PK PC PROGRAM COUNTER PC CCR PK CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK EK XK K YK ZK ADDRESS EXTENSION REGISTER K SK STACK EXTENSION FIELD SK HR MAC MULTIPLIER REGISTER HR IR MAC MULTIPLICAND REGISTER IR AM AM MAC ACCUMULATOR MSB[35:16] AM MAC ACCUMULATOR LSB[15:0] AM XMSK YMSK MAC XY MASK REGISTER CPU16 REGISTER MODEL Figure D-1 CPU16 Register Model REGISTER SUMMARY D-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.1.1 Condition Code Register CCR — Condition Code Register 15 S 14 MV 13 H 12 EV 11 N 10 Z 9 V 8 C 7 6 IP[2:0] 5 4 SM 3 2 PK[3:0] 1 0 The CCR contains processor status flags, the interrupt priority field, and the program counter address extension field. The CPU16 has a special set of instructions that manipulate the CCR. S — STOP Enable 0 = Stop CPU16 clocks when LPSTOP instruction is executed. 1 = Perform NOPs when LPSTOP instruction is executed. Freescale Semiconductor, Inc... MV — Accumulator M overflow flag Set when overflow into AM35 has occurred. H — Half Carry Flag Set when a carry from A3 or B3 occurs during BCD addition. EV — Accumulator M Extension Overflow Flag EV is set when an overflow into AM31 has occurred. N — Negative Flag N is set under the following conditions: • When the MSB is set in the operand of a read operation. • When the MSB is set in the result of a logic or arithmetic operation. Z — Zero Flag Z is set under the following conditions: • When all bits are zero in the operand of a read operation. • When all bits are zero in the result of a logic or arithmetic operation. V — Overflow Flag Set when two’s complement overflow occurs as the result of an operation. C — Carry Flag Set when carry or borrow occurs during arithmetic operation. Also used during shifts and rotates. IP[2:0] — Interrupt Priority Field The priority value in this field (0 to 7) is used to mask low priority interrupts. SM — Saturate Mode Bit When SM is set, if either EV or MV is set, data read from AM using TMER or TMET is given maximum positive or negative value, depending on the state of the AM sign bit before overflow. PK[3:0] — Program Counter Address Extension Field This field is concatenated with the program counter to form a 20-bit address. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-3 Freescale Semiconductor, Inc. D.2 System Integration Module Table D-2 shows the SIM address map. Table D-2 SIM Address Map Address1 $YFFA00 $YFFA02 $YFFA04 $YFFA06 $YFFA08 $YFFA0A $YFFA0C Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used 15 87 SIM Module Configuration Register (SIMCR) SIM Test Register (SIMTR) Clock Synthesizer Control Register (SYNCR) Reset Status Register (RSR) SIM Test Register E (SIMTRE) Not Used Not Used Not Used Port E Data Register 0 (PORTE0) Port E Data Register 1(PORTE1) Port E Data Direction Register (DDRE) Port E Pin Assignment Register (PEPAR) Port F Data Register 0 (PORTF0) Port F Data Register 1 (PORTF1) Port F Data Direction Register (DDRF) Port F Pin Assignment Register (PFPAR) System Protection Control Register (SYPCR) Periodic Interrupt Timer Register (PITR) Not Used Software Watchdog Service Register (SWSR) Not Used Not Used Not Used Not Used Test Module Master Shift A Register (TSTMSRA) Test Module Master Shift B Register (TSTMSRB) Test Module Shift Count Register (TSTSC) Test Module Repetition Counter Register (TSTRC) Test Module Control Register (CREG) Test Module Distributed Register (DREG) Not Used Not Used Not Used Not Used Port C Data Register (PORTC) Not Used 0 Freescale Semiconductor, Inc... $YFFA0E $YFFA10 $YFFA12 $YFFA14 $YFFA16 $YFFA18 $YFFA1A $YFFA1C $YFFA1E $YFFA20 $YFFA22 $YFFA24 $YFFA26 $YFFA28 $YFFA2A $YFFA2C $YFFA2E $YFFA30 $YFFA32 $YFFA34 $YFFA36 $YFFA38 $YFFA3A $YFFA3C $YFFA3E $YFFA40 $YFFA42 $YFFA44 $YFFA46 $YFFA48 $YFFA4A Periodic Interrupt Control Register (PICR) Chip-Select Pin Assignment Register 0 (CSPAR0) Chip-Select Pin Assignment Register 1 (CSPAR1) Chip-Select Base Address Register Boot (CSBARBT) Chip-Select Option Register Boot (CSORBT) Chip-Select Base Address Register 0 (CSBAR0) REGISTER SUMMARY D-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table D-2 SIM Address Map (Continued) Address1 $YFFA4E $YFFA50 $YFFA52 $YFFA54 $YFFA56 $YFFA58 $YFFA5A $YFFA5C $YFFA5E $YFFA60 $YFFA62 $YFFA64 $YFFA66 $YFFA68 $YFFA6A $YFFA6C $YFFA6E $YFFA70 $YFFA72 $YFFA74 $YFFA76 $YFFA78 $YFFA7A $YFFA7C $YFFA7E 15 87 Chip-Select Option Address Register 0 (CSOR0) Chip-Select Base Address Register 1 (CSBAR1) Chip-Select Option Address Register 1 (CSOR1) Chip-Select Base Address Register 2 (CSBAR2) Chip-Select Option Address Register 2 (CSOR2) Chip-Select Base Address Register 3 (CSBAR3) Chip-Select Option Address Register 3 (CSOR3) Chip-Select Base Address Register 4 (CSBAR4) Chip-Select Option Address Register 4 (CSOR4) Chip-Select Base Address Register 5 (CSBAR5) Chip-Select Option Address Register 5 (CSOR5) Chip-Select Base Address Register 6 (CSBAR6) Chip-Select Option Address Register 6 (CSOR6) Chip-Select Base Address Register 7 (CSBAR7) Chip-Select Option Address Register 7 (CSOR7) Chip-Select Base Address Register 8 (CSBAR8) Chip-Select Option Address Register 8 (CSOR8) Chip-Select Base Address Register 9 (CSBAR9) Chip-Select Option Address Register 9 (CSOR9) Chip-Select Base Address Register 10 (CSBAR10) Chip-Select Option Address Register 10 (CSOR10) Not Used Not Used Not Used Not Used 0 Freescale Semiconductor, Inc... NOTES: 1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-5 Freescale Semiconductor, Inc. D.2.1 SIM Module Configuration Register SIMCR — SIM Module Configuration Register 15 14 13 12 0 11 RSVD 1 $YFFA00 7 6 MM 5 0 4 0 3 2 1 0 IARB[3:0] 10 0 9 8 EXOFF FRZSW FRZBM RESET: 0 1 1 SHEN[1:0] SUPV 0 DATA11 0 0 0 1 1 0 0 1 1 1 1 NOTES: 1. This bit must be left at zero. Pulling DATA11 high during reset ensures this bit remains zero. A one in this bit could allow the MCU to enter an unsupported operating mode. SIMCR controls system configuration. SIMCR can be read or written at any time, except for the module mapping (MM) bit, which can only be written once after reset, and the reserved bit, which is read-only. Write has no effect. Freescale Semiconductor, Inc... EXOFF — External Clock Off 0 = The CLKOUT pin is driven during normal operation. 1 = The CLKOUT pin is placed in a high-impedance state. FRZSW — Freeze Software Enable 0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer continue to operate, allowing interrupts during background debug mode. 1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer are disabled, preventing interrupts during background debug mode. FRZBM — Freeze Bus Monitor Enable 0 = When FREEZE is asserted, the bus monitor continues to operate. 1 = When FREEZE is asserted, the bus monitor is disabled. SHEN[1:0] — Show Cycle Enable The SHEN field determines how the external bus is driven during internal transfer operations. A show cycle allows internal transfers to be monitored externally. Table D-3 indicates whether show cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict, external devices must not be selected during show cycles. Table D-3 Show Cycle Enable Bits SHEN[1:0] 00 01 10 11 Action Show cycles disabled, external arbitration enabled Show cycles enabled, external arbitration disabled Show cycles enabled, external arbitration enabled Show cycles enabled, external arbitration enabled; internal activity is halted by a bus grant SUPV — Supervisor/User Data Space This bit has no effect because the CPU16 always operates in the supervisor mode. REGISTER SUMMARY D-6 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. MM — Module Mapping 0 = Internal modules are addressed from $7FF000 – $7FFFFF. 1 = Internal modules are addressed from $FFF000 – $FFFFFF. The logic state of the MM determines the value of ADDR23 for IMB module addresses. Because ADDR[23:20] are driven to the same state as ADDR19, MM must be set to one. If MM is cleared, IMB modules are inaccessible to the CPU16. This bit can be written only once after reset. IARB[3:0] — Interrupt Arbitration ID Each module that can generate interrupts, including the SIM, has an IARB field. Each IARB field can be assigned a value from $0 to $F. During an interrupt acknowledge cycle, IARB permits arbitration among simultaneous interrupts of the same priority level. The reset value of the SIM IARB field is $F, the highest priority. This prevents SIM interrupts from being discarded during system initialization. D.2.2 System Integration Test Register SIMTR — System Integration Test Register Used for factory test only. D.2.3 Clock Synthesizer Control Register SYNCR — Clock Synthesizer Control Register 15 W RESET: 0 0 1 1 1 1 1 1 0 0 0 0 U 0 0 0 14 X 13 12 11 Y[5:0] 10 9 8 7 EDIV 6 0 5 0 4 RSVD1 3 SLOCK 2 RSVD1 Freescale Semiconductor, Inc... $YFFA02 $YFFA04 1 STSIM 0 STEXT NOTES: 1. Ensure that the software does not change the value of these bits. They should always be zero. This register determines system clock operating frequency and operation during lowpower stop mode. With a slow reference frequency between 25 and 50 kHz (typically a 32.768-kHz crystal), the clock frequency is determined by the following equation: f sys = f ref [ 4 ( Y + 1 ) ( 2 ( 2W + X ) )] With a fast reference frequency between 1 and 6 MHz (typically a 4.194-MHz crystal), the reference frequency is divided by 128 before it is passed to the PLL system. The clock frequency is determined by the following equation: f ref ( 2W + X ) )] f sys = --------- [ 4 ( Y + 1 ) ( 2 128 M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-7 Freescale Semiconductor, Inc. W — Frequency Control (VCO) This bit controls a prescaler tap in the synthesizer feedback loop. Setting this bit increases the VCO speed by a factor of four. VCO relock delay is required. X — Frequency Control (Prescaler) This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting the bit doubles clock speed without changing the VCO speed. No VCO relock delay is required. Y[5:0] — Frequency Control (Counter) The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by a value of Y + 1. VCO relock delay is required. EDIV — E Clock Divide Rate 0 = ECLK frequency is system clock divided by eight. 1 = ECLK frequency is system clock divided by sixteen. SLOCK — Synthesizer Lock Flag 0 = VCO is enabled, but has not locked. 1 = VCO has locked on the desired frequency or VCO is disabled. The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate synthesizer lock status until after the user first writes to SYNCR. STSIM — Stop Mode SIM Clock 0 = When LPSTOP is executed, the SIM clock is driven from the external crystal oscillator and the VCO is turned off to conserve power. 1 = When LPSTOP is executed, the SIM clock is driven from the internal VCO. STEXT — Stop Mode External Clock 0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power. 1 = When LPSTOP is executed and EXOFF 1 in SIMCR, the CLKOUT signal is driven from the SIM clock, as determined by the state of the STSIM bit. D.2.4 Reset Status Register RSR — Reset Status Register 15 NOT USED 8 7 EXT 6 POW 5 SW 4 HLT 3 0 2 RSVD Freescale Semiconductor, Inc... $YFFA06 1 SYS 0 TST RSR contains a status bit for each reset source in the MCU. RSR is updated when the MCU comes out of reset. A set bit indicates what type of reset occurred. If multiple sources assert reset signals at the same time, more than one bit in RSR may be set. This register can be read at any time; a write has no effect. Bits [15:8] are unimplemented and always read zero. EXT — External Reset Reset caused by the RESET pin. REGISTER SUMMARY D-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. POW — Power-Up Reset Reset caused by the power-up reset circuit. SW — Software Watchdog Reset Reset caused by the software watchdog circuit. HLT — Halt Monitor Reset Reset caused by the halt monitor. SYS — System Reset The CPU16 does not support this function. This bit will never be set. TST — Test Submodule Reset Reset caused by the test submodule. Used during factory test reserved operating mode only. D.2.5 System Integration Test Register E SIMTRE — System Integration Test Register E Used for factory test only. D.2.6 Port E Data Register PORTE0 — Port E0 Data Register PORTE1 — Port E1 Data Register 15 NOT USED RESET: U U U U U U U U 8 7 PE7 6 PE6 5 PE5 4 PE4 3 PE3 2 PE2 Freescale Semiconductor, Inc... $YFFA08 $YFFA10 $YFFA12 1 PE1 0 PE0 This register can be accessed in two locations and can be read or written at any time. A write to this register is stored in an internal data latch, and if any pin in the corresponding port is configured as an output, the value stored for that bit is driven out on the pin. A read of this data register returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the register. Bits [15:8] are unimplemented and will always read zero. D.2.7 Port E Data Direction Register DDRE — Port E Data Direction Register 15 NOT USED RESET: 0 0 0 0 0 0 0 0 8 7 DDE7 6 DDE6 5 DDE5 4 DDE4 3 DDE3 2 DDE2 $YFFA14 1 DDE1 0 DDE0 Bits in this register control the direction of the port E pin drivers when pins are configured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input. This register can be read or written at any time. Bits [15:8] are unimplemented and will always read zero. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-9 Freescale Semiconductor, Inc. NOTE When changing a port E pin from an output to an input, the pin will drive high for approximately four milliseconds. This ensures that the shared bus control signal will be in a negated state before the pin becomes an input. D.2.8 Port E Pin Assignment Register PEPAR — Port E Pin Assignment 15 NOT USED RESET: DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 8 7 PEPA7 6 PEPA6 5 PEPA5 4 PEPA4 3 PEPA3 2 PEPA2 $YFFA16 1 PEPA1 0 PEPA0 Freescale Semiconductor, Inc... This register determines the function of port E pins. Setting a bit assigns the corresponding pin to a bus control signal; clearing a bit assigns the pin to I/O port E. PE3 is not connected to a pin. PEPA3 can be read and written, but has no function. Bits [15:8] are unimplemented and will always read zero. Table D-4 displays port E pin assignments. Table D-4 Port E Pin Assignments PEPAR Bit PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0 Port E Signal PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Bus Control Signal SIZ1 SIZ0 AS DS —1 AVEC DSACK1 DSACK0 NOTES: 1. The CPU16 does not support the RMC function for this pin. This bit is not connected to a pin for I/O usage. D.2.9 Port F Data Register PORTF0 — Port F Data Register 0 PORTF1 — Port F Data Register 1 15 NOT USED RESET: U U U U U U U U 8 7 PF7 6 PF6 5 PF5 4 PF4 3 PF3 2 PF2 $YFFA18 $YFFA1A 1 PF1 0 PF0 This register can be accessed in two locations and can be read or written at any time. A write to this register is stored in an internal data latch, and if any pin in the corre- REGISTER SUMMARY D-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. sponding port is configured as an output, the value stored for that bit is driven out on the pin. A read of this data register returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the register. Bits [15:8] are unimplemented and will always read zero. D.2.10 Port F Data Direction Register DDRF — Port F Data Direction Register 15 NOT USED RESET: 0 0 0 0 0 0 0 0 8 7 DDF7 6 DDF6 5 DDF5 4 DDF4 3 DDF3 2 DDF2 $YFFA1C 1 DDF1 0 DDF0 Freescale Semiconductor, Inc... This register controls the direction of the port F pin drivers when pins are configured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input. This register can be read or written at any time. Bits [15:8] are unimplemented and will always read zero. D.2.11 Port F Pin Assignment Register PFPAR — Port F Pin Assignment Register 15 NOT USED RESET: DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 8 7 PFPA7 6 PFPA6 5 PFPA5 4 PFPA4 3 PFPA3 2 PFPA2 $YFFA1E 1 PFPA1 0 PFPA0 This register determines the function of port F pins. Setting a bit assigns the corresponding pin to a control signal; clearing a bit assigns the pin to port F. Bits [15:8] are unimplemented and will always read zero. Refer to Table D-5. Table D-5 Port F Pin Assignments PFPAR Field PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0 Port F Signal PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Alternate Signal IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MODCLK M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-11 Freescale Semiconductor, Inc. D.2.12 System Protection Control Register SYPCR — System Protection Control Register 15 NOT USED RESET: 1 MODCLK 0 0 0 0 0 0 8 7 SWE 6 SWP 5 4 3 HME 2 BME SWT[1:0] $YFFA20 1 0 BMT[1:0] This register controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. This register can be written once following power-on or reset. Bits [15:8] are unimplemented and will always read zero. SWE — Software Watchdog Enable 0 = Software watchdog is disabled. 1 = Software watchdog is enabled. SWP — Software Watchdog Prescaler This bit controls the value of the software watchdog prescaler. 0 = Software watchdog clock is not prescaled. 1 = Software watchdog clock is prescaled by 512. The reset value of SWP is the complement of the state of the MODCLK pin during reset. SWT[1:0] — Software Watchdog Timing This field selects the divide ratio used to establish the software watchdog time-out period. Refer to Table D-6. Table D-6 Software Watchdog Divide Ratio SWP 0 0 0 0 1 1 1 1 SWT[1:0] 00 01 10 11 00 01 10 11 Divide Ratio 29 211 213 215 218 220 222 224 Freescale Semiconductor, Inc... The following equation calculates the time-out period for a slow reference frequency, where fref is equal to the EXTAL crystal frequency. Divide Ratio Specified by SWP and SWT[1:0] Time-out Period = ----------------------------------------------------------------------------------------------------------------------f ref The following equation calculates the time-out period for a fast reference frequency, where fref is equal to the EXTAL crystal frequency. REGISTER SUMMARY D-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. ( 128 ) ( Divide Ratio Specified by SWP and SWT[1:0] ) Time-out Period = -----------------------------------------------------------------------------------------------------------------------------------------f ref The following equation calculates the time-out period for an externally input clock frequency on both slow and fast reference frequency devices, when fsys is equal to the system clock frequency. Divide Ratio Specified by SWP and SWT[1:0] Time-out Period = ----------------------------------------------------------------------------------------------------------------------f sys HME — Halt Monitor Enable 0 = Halt monitor is disabled. 1 = Halt monitor is enabled. BME — Bus Monitor External Enable 0 = Disable bus monitor for external bus cycles. 1 = Enable bus monitor for external bus cycles. BMT[1:0] — Bus Monitor Timing This field selects the bus monitor time-out period. Refer to Table D-7. Table D-7 Bus Monitor Time-Out Period BMT[1:0] 00 01 10 11 Bus Monitor Time-Out Period 64 system clocks 32 system clocks 16 system clocks 8 system clocks Freescale Semiconductor, Inc... D.2.13 Periodic Interrupt Control Register PICR — Periodic Interrupt Control Register 15 0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 14 0 13 0 12 0 11 0 10 9 PIRQL[2:0] 8 7 6 5 4 PIV[7:0] 3 2 $YFFA22 1 0 PICR sets the interrupt level and vector number for the periodic interrupt timer (PIT). Bits [10:0] can be read or written at any time. Bits [15:11] are unimplemented and always read zero. PIRQL[2:0] — Periodic Interrupt Request Level This field determines the priority of periodic interrupt requests. A value of %000 disables PIT interrupts. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-13 Freescale Semiconductor, Inc. PIV[7:0] — Periodic Interrupt Vector This field specifies the periodic interrupt vector number supplied by the SIM when the CPU16 acknowledges an interrupt request. D.2.14 Periodic Interrupt Timer Register PITR — Periodic Interrupt Timer Register 15 0 RESET: 0 0 0 0 0 0 0 MODCLK 0 0 0 0 0 0 0 0 14 0 13 0 12 0 11 0 10 0 9 0 8 PTP 7 6 5 4 3 2 PITM[7:0] $YFFA24 1 0 Freescale Semiconductor, Inc... Contains the count value for the periodic timer. This register can be read or written at any time. PTP — Periodic Timer Prescaler 0 = Periodic timer clock not prescaled. 1 = Periodic timer clock prescaled by a value of 512. PITM[7:0] — Periodic Interrupt Timing Modulus This field determines the periodic interrupt rate. Use the following equations to calculate timer period. The following equation calculates the PIT period when a slow reference frequency is used: ( PITM[7:0] ) ( 1 if PTP = 0, 512 if PTP = 1 ) ( 4 ) PIT Period = -------------------------------------------------------------------------------------------------------------------f ref The following equation calculates the PIT period when a fast reference frequency is used: ( 128 ) ( PITM[7:0] ) ( 1 if PTP = 0, 512 if PTP = 1 ) ( 4 ) ----PIT Period = ------------------------------------------------------------------------------------------------------------------------------f ref The following equation calculates the PIT period for an externally input clock frequency on both slow and fast reference frequency devices. ( PITM[7:0] ) ( 1 if PTP = 0, 512 if PTP = 1 ) ( 4 ) PIT Period = -------------------------------------------------------------------------------------------------------------------f sys REGISTER SUMMARY D-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.2.15 Software Watchdog Service Register SWSR — Software Watchdog Service Register1 15 NOT USED RESET: 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 SWSR[7:0] $YFFA26 1 0 NOTES: 1. This register is shown with a read value. This register can be read or written at any time. Bits [15:8] are unimplemented and will always read zero. To reset the software watchdog: Freescale Semiconductor, Inc... 1. Write $55 to SWSR. 2. Write $AA to SWSR. Both writes must occur in the order specified before the software watchdog times out, but any number of instructions can occur between the two writes. D.2.16 Port C Data Register PORTC — Port C Data Register 15 NOT USED RESET: 0 1 1 1 1 1 1 1 8 7 0 6 PC6 5 PC5 4 PC4 3 PC3 2 PC2 $YFFA40 1 PC1 0 PC0 This register latches data for chip-select pins configured as discrete outputs. This register can be read or written at any time. Bits [15:8] are unimplemented and will always read zero. D.2.17 Chip-Select Pin Assignment Registers CSPAR0 — Chip-Select Pin Assignment Register 0 15 0 RESET: 0 0 DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1 1 DATA0 14 0 13 12 11 10 9 8 7 6 5 4 3 2 CS5PA[1:0] CS4PA[1:0] CS3PA[1:0] CS2PA[1:0] CS1PA[1:0] CS0PA[1:0] $YFFA44 1 0 CSBTPA[1:0] Chip-select pin assignment registers configure the chip-select pins for discrete I/O, an alternate function, or as an 8-bit or 16-bit chip-select. The possible encodings for each 2-bit field in CSPAR[0:1] (except for CSBTPA[1:0]) are shown in Table D-8. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-15 Freescale Semiconductor, Inc. Table D-8 Pin Assignment Field Encoding CSxPA[1:0] 00 01 10 11 Description Discrete output1 Alternate function1 Chip-select (8-bit port) Chip-select (16-bit port) NOTES: 1. Does not apply to the CSBOOT field. Freescale Semiconductor, Inc... This register contains seven 2-bit fields that determine the function of corresponding chip-select pins. Bits [15:14] are not used. These bits always read zero; writes have no effect. CSPAR0 bit 1 always reads one; writes to CSPAR0 bit 1 have no effect. The alternate functions can be enabled by data bus mode selection during reset. This register may be read or written at any time. After reset, software may enable one or more pins as discrete outputs. Table D-9 shows CSPAR0 pin assignments. Table D-9 CSPAR0 Pin Assignments CSPAR0 Field CS5PA[1:0] CS4PA[1:0] CS3PA[1:0] CS2PA[1:0] CS1PA[1:0] CS0PA[1:0] CSBTPA[1:0] Chip-Select Signal CS5 CS4 CS3 CS2 CS1 CS0 CSBOOT Alternate Signal FC2 FC1 FC0 BGACK BG BR — Discrete Output PC2 PC1 PC0 — — — — CSPAR1 — Chip-Select Pin Assignment Register 1 15 0 RESET: 0 0 0 0 0 0 DATA71 1 DATA [7:6]1 1 DATA [7:5]1 1 DATA [7:4]1 1 14 0 13 0 12 0 11 0 10 0 9 8 7 6 5 4 3 2 CS10PA[1:0] CS9PA[1:0] CS8PA[1:0] CS7PA[1:0] $YFFA46 1 0 CS6PA[1:0] DATA [7:3]1 1 NOTES: 1. Refer to Table D-11 for CSPAR1 reset state information. CSPAR1 contains five 2-bit fields that determine the functions of corresponding chipselect pins. Bits [15:10] are not used. These bits always read zero; writes have no effect. Table D-10 shows CSPAR1 pin assignments, including alternate functions that can be enabled by data bus mode selection during reset. REGISTER SUMMARY D-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table D-10 CSPAR1 Pin Assignments CSPAR1 Field CS10PA[1:0] CS9PA[1:0] CS8PA[1:0] CS7PA[1:0] CS6PA[1:0] Chip-Select Signal CS10 CS9 CS8 CS7 CS6 Alternate Signal ADDR231 ADDR221 ADDR211 ADDR201 ADDR19 Discrete Output ECLK PC6 PC5 PC4 PC3 NOTES: 1. On the CPU16, ADDR[23:20] follow the logic state of ADDR19 unless externally driven. Freescale Semiconductor, Inc... The reset state of DATA[7:3] determines whether pins controlled by CSPAR1 are initially configured as high-order address lines or chip-selects. Table D-11 shows the correspondence between DATA[7:3] and the reset configuration of CS[10:6]/ ADDR[23:19]. This register may be read or written at any time. After reset, software may enable one or more pins as discrete outputs. Table D-11 Reset Pin Function of CS[10:6] Data Bus Pins at Reset DATA7 1 1 1 1 1 0 DATA6 1 1 1 1 0 X DATA5 1 1 1 0 X X DATA4 1 1 0 X X X DATA3 1 0 X X X X Chip-Select/Address Bus Pin Function CS10/ CS9/ CS8/ CS7/ CS6/ ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 CS10 CS10 CS10 CS10 CS10 CS9 CS9 CS9 CS9 CS8 CS8 CS8 CS7 CS7 CS6 ADDR19 ADDR20 ADDR19 ADDR21 ADDR20 ADDR19 ADDR22 ADDR21 ADDR20 ADDR19 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 D.2.18 Chip-Select Base Address Register Boot CSBARBT — Chip-Select Base Address Register Boot 15 ADDR 23 14 ADDR 22 13 ADDR 21 12 ADDR 20 11 ADDR 19 10 ADDR 18 9 ADDR 17 8 ADDR 16 7 ADDR 15 6 ADDR 14 5 ADDR 13 4 ADDR 12 3 ADDR 11 2 $YFFA48 1 BLKSZ[2:0] 0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D.2.19 Chip-Select Base Address Registers CSBAR[0:10] — Chip-Select Base Address Registers 15 ADDR 23 14 ADDR 22 13 ADDR 21 12 ADDR 20 11 ADDR 19 10 ADDR 18 9 ADDR 17 8 ADDR 16 7 ADDR 15 6 ADDR 14 5 ADDR 13 4 ADDR 12 $YFFA4C–$YFFA74 3 ADDR 11 2 1 BLKSZ[2:0] 0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-17 Freescale Semiconductor, Inc. Each chip-select pin has an associated base address register. A base address is the lowest address in the block of addresses enabled by a chip select. CSBARBT contains the base address for selection of a boot memory device. Bit and field definitions for CSBARBT and CSBAR[0:10] are the same, but reset block sizes differ. These registers may be read or written at any time. ADDR[23:11] — Base Address This field sets the starting address of a particular chip-select’s address space. The address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be an integer multiple of the block size. Base address register diagrams show how base register bits correspond to address lines. Freescale Semiconductor, Inc... BLKSZ[2:0] — Block Size Field This field determines the size of the block that is enabled by the chip-select. Table D-12 shows bit encoding for the base address registers block size field. Table D-12 Block Size Field Bit Encoding BLKSZ[2:0] 000 001 010 011 100 101 110 111 Block Size 2 Kbytes 8 Kbytes 16 Kbytes 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes 512 Kbytes Address Lines Compared1 ADDR[23:11] ADDR[23:13] ADDR[23:14] ADDR[23:16] ADDR[23:17] ADDR[23:18] ADDR[23:19] ADDR[23:20] NOTES: 1. ADDR[23:20] are the same logic level as ADDR19 during normal operation. D.2.20 Chip-Select Option Register Boot CSORBT — Chip-Select Option Register Boot 15 MODE RESET: 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 14 13 12 11 10 STRB 9 8 7 6 5 4 3 2 IPL[2:0] BYTE[1:0] R/W[1:0] DSACK[3:0] SPACE[1:0] $YFFA4A 1 0 AVEC D.2.21 Chip-Select Option Registers CSOR[0:10] — Chip-Select Option Registers 15 MODE RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 STRB 9 8 7 6 5 4 BYTE[1:0] R/W[1:0] DSACK[3:0] SPACE[1:0] $YFFA4E–YFFA76 3 2 IPL[2:0] 1 0 AVEC REGISTER SUMMARY D-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. CSORBT and CSOR[0:10] contain parameters that support operations from external memory devices. Bit and field definitions for CSORBT and CSOR[0:10] are the same. MODE — Asynchronous/Synchronous Mode 0 = Asynchronous mode is selected. 1 = Synchronous mode is selected, and used with ECLK peripherals. In asynchronous mode, chip-select assertion is synchronized with AS and DS. In synchronous mode, the chip-select signal is asserted with ECLK. BYTE[1:0] — Upper/Lower Byte Option This field is used only when the chip-select 16-bit port option is selected in the pin assignment register. This allows the usage of two external 8-bit memory devices to be concatenated to form a 16-bit memory. Table D-13 shows upper/lower byte options. Freescale Semiconductor, Inc... Table D-13 BYTE Field Bit Encoding BYTE[1:0] 00 01 10 11 Description Disable Lower byte Upper byte Both bytes R/W[1:0]— Read/Write This field causes a chip-select to be asserted only for a read, only for a write, or for both read and write. Table D-14 shows the options. Table D-14 Read/Write Field Bit Encoding R/W[1:0] 00 01 10 11 Description Disable Read only Write only Read/Write STRB — Address Strobe/Data Strobe This bit controls the timing for assertion of a chip-select in asynchronous mode only. Selecting address strobe causes the chip-select to be asserted synchronized with address strobe. Selecting data strobe causes the chip-select to be asserted synchronized with data strobe. Data strobe timing is used to create a write strobe when needed. 0 = Address strobe 1 = Data strobe DSACK[3:0] — Data Strobe Acknowledge This field specifies the source of DSACK in asynchronous mode as internally generated or externally supplied. It also allows the user to adjust bus timing with internal DSACK generation by controlling the number of wait states that are inserted to optimize bus speed in a particular application. Table D-15 shows the DSACK[3:0] field encoding. The fast termination encoding (%1110) effectively corresponds to –1 wait states. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-19 Freescale Semiconductor, Inc. Table D-15 DSACK Field Encoding DSACK[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 Clock Cycles Required Per Access 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 — Wait States Inserted Per Access 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Fast Termination External DSACK Freescale Semiconductor, Inc... 1001 1010 1011 1100 1101 1110 1111 External memories are purchased with guaranteed access times on speed (in nanoseconds). Table D-16 relates wait states selected by DSACK[3:0] to the memory device access time. NOTE Table D-16 assumes a system configuration that minimizes power consumption and the number of chip-selects employed. Other access techniques can provide the same access times with slower memory devices, but require more chip-selects to be used and will subsequently increase system power consumption. Table D-16 Memory Access Times at 16.78, 20.97, and 25.17 MHz Speed 16.78 MHz 20.97 MHz 25.17 MHz tcyc 62.5 ns 50.0 ns 40.0 ns Fast Termination Access Time 30.0 ns 20.0 ns 15.0 ns 0 Wait State 95.0 ns 70.0 ns 55.0 ns 1 Wait State 155.0 ns 120.0 ns 95.0 ns REGISTER SUMMARY D-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SPACE[1:0] — Address Space Select Use this option field to select an address space for chip-select assertion or to configure a chip-select as an interrupt acknowledge strobe for an external device. The CPU16 normally operates in supervisor mode only, but interrupt acknowledge cycles take place in CPU space. Table D-17 shows address space bit encodings. Table D-17 Address Space Bit Encodings SPACE[1:0] 00 01 10 11 Address Space CPU Space User Space Supervisor Space Supervisor/User Space Freescale Semiconductor, Inc... IPL[2:0] — Interrupt Priority Level When SPACE[1:0] is set for CPU space (%00), chip-select logic can be used as an interrupt acknowledge strobe for an external device. During an interrupt acknowledge cycle, the interrupt priority level is driven on address lines ADDR[3:1] and is then compared to the value in IPL[2:0]. If the values match, an interrupt acknowledge strobe will be generated on the particular chip-select pin, provided other option register conditions are met. Table D-18 shows IPL[2:0] field encoding. Table D-18 Interrupt Priority Level Field Encoding IPL[2:0] 000 001 010 011 100 101 110 111 Interrupt Priority Level Any Level1 1 2 3 4 5 6 7 NOTES: 1. Any level means that chip-select is asserted regardless of the level of the interrupt acknowledge cycle. AVEC — Autovector Enable This field selects one of two methods of acquiring an interrupt vector during an interrupt acknowledge cycle. This field is not applicable when SPACE[1:0] = %00. 0 = External interrupt vector enabled 1 = Autovector enabled If the chip select is configured to trigger on an interrupt acknowledge cycle (SPACE[1:0] = %00) and the AVEC field is set to one, the chip-select automatically generates AVEC and completes the interrupt acknowledge cycle. Otherwise, the vector must be supplied by the requesting external device to complete the IACK read cycle. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-21 Freescale Semiconductor, Inc. D.2.22 Master Shift Registers TSTMSRA — Test Module Master Shift Register A Used for factory test only. TSTMSRB — Test Module Master Shift Register B Used for factory test only. D.2.23 Test Module Shift Count Register TSTSC — Test Module Shift Count Used for factory test only. $YFFA34 $YFFA30 $YFFA32 Freescale Semiconductor, Inc... D.2.24 Test Module Repetition Count Register TSTRC — Test Module Repetition Count Used for factory test only. D.2.25 Test Module Control Register CREG — Test Module Control Register Used for factory test only. D.2.26 Test Module Distributed Register DREG — Test Module Distributed Register Used for factory test only. $YFFA3A $YFFA38 $YFFA36 REGISTER SUMMARY D-22 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.3 Standby RAM Module Table D-19 shows the SRAM address map. Table D-19 SRAM Address Map Address1 $YFFB00 $YFFB02 $YFFB04 $YFFB06 15 RAM Module Configuration Register (RAMMCR) RAM Test Register (RAMTST) RAM Array Base Address Register High (RAMBAH) RAM Array Base Address Register Low (RAMBAL) 0 NOTES: 1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR. Freescale Semiconductor, Inc... D.3.1 RAM Module Configuration Register RAMMCR — RAM Module Configuration Register 15 STOP RESET: 1 0 0 0 0 0 1 1 0 0 0 11 RLCK 0 9 8 NOT USED RASP[1:0] $YFFB00 0 STOP — Low-Power Stop Mode Enable 0 = SRAM operates normally. 1 = SRAM enters low-power stop mode. This bit controls whether SRAM operates normally or enters low-power stop mode. In low-power stop mode, the array retains its contents, but cannot be read or written. This bit can be read or written at any time. RLCK — RAM Base Address Lock 0 = SRAM base address registers can be written. 1 = SRAM base address registers are locked and cannot be modified. RLCK defaults to zero on reset; it can be written once to a one, and may be read at any time. RASP[1:0] — RAM Array Space The RASP field limits access to the SRAM array in microcontrollers that support separate user and supervisor operating modes. RASP1 has no effect because the CPU16 operates in supervisor mode only. This bit may be read or written at any time. Refer to Table D-20. Table D-20 SRAM Array Address Space Type RASP[1:0] X0 X1 Space Program and data accesses Program access only M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-23 Freescale Semiconductor, Inc. D.3.2 RAM Test Register RAMTST — RAM Test Register Used for factory test only. D.3.3 Array Base Address Register High RAMBAH — Array Base Address Register High (Z1, Z2, Z3, and Z4) 15 NOT USED RESET: 0 0 0 0 0 0 0 0 8 7 ADDR 23 6 ADDR 22 5 ADDR 21 4 ADDR 20 3 ADDR 19 2 ADDR 18 $YFFB02 $YFFB04 1 ADDR 17 0 ADDR 16 Freescale Semiconductor, Inc... D.3.4 Array Base Address Register Low RAMBAL — Array Base Address Register Low (1K SRAM — Z1/Z4) 15 ADDR 15 RESET: 0 0 0 0 0 0 14 ADDR 14 13 ADDR 13 12 ADDR 12 11 ADDR 11 10 ADDR 10 9 ADDR 9 8 ADDR 8 7 ADDR 7 6 ADDR 6 5 ADDR 5 4 ADDR 4 3 ADDR 3 2 ADDR 2 $YFFB06 1 ADDR 1 0 ADDR 0 RAMBAL — Array Base Address Register Low (2K SRAM — Z2) 15 ADDR 15 RESET: 0 0 0 0 0 14 ADDR 14 13 ADDR 13 12 ADDR 12 11 ADDR 11 10 ADDR 10 9 ADDR 9 8 ADDR 8 7 ADDR 7 6 ADDR 6 5 ADDR 5 4 ADDR 4 3 ADDR 3 2 ADDR 2 $YFFB06 1 ADDR 1 0 ADDR 0 RAMBAL — Array Base Address Register Low (4K SRAM — Z3) 15 ADDR 15 RESET: 0 0 0 0 14 ADDR 14 13 ADDR 13 12 ADDR 12 11 ADDR 11 10 ADDR 10 9 ADDR 9 8 ADDR 8 7 ADDR 7 6 ADDR 6 5 ADDR 5 4 ADDR 4 3 ADDR 3 2 ADDR 2 $YFFB06 1 ADDR 1 0 ADDR 0 RAMBAH and RAMBAL specify the SRAM array base address in the system memory map. They can only be written while the SRAM is in low-power stop mode (STOP = 1, the default out of reset) and the base address lock is disabled (RLCK = 0, the default out of reset). This prevents accidental remapping of the array. Because the CPU16 drives ADDR[23:20] to the same logic level as ADDR19, the values of RAMBAH ADDR[23:20] must match the value of ADDR19 for the array to be accessible. These registers may be read at any time. RAMBAH[15:8] are unimplemented and will always read zero. REGISTER SUMMARY D-24 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.4 Masked ROM Module The MRM is used only in the MC68HC16Z2 and the MC68HC16Z3. Table D-21 shows the MRM address map. The reset states shown for the MRM registers are for the generic (blank ROM) versions of the device. Several MRM register bit fields can be user-specified on a custom masked ROM device. Contact a Freescale sales representative for information on ordering a custom ROM device. Table D-21 MRM Address Map Address $YFF820 $YFF822 $YFF824 $YFF826 $YFF828 $YFF82A $YFF82C $YFF82E $YFF830 $YFF832 $YFF834 $YFF836 $YFF838 $YFF83A $YFF83C $YFF83E 15 Masked ROM Module Configuration Register (MRMCR) Not Used ROM Array Base Address Register High (ROMBAH) ROM Array Base Address Register Low (ROMBAL) Signature Register High (SIGHI) Signature Register Low (SIGLO) Not Used Not Used ROM Bootstrap Word 0 (ROMBS0) ROM Bootstrap Word 1 (ROMBS1) ROM Bootstrap Word 2 (ROMBS2) ROM Bootstrap Word 3 (ROMBS3) Not Used Not Used Not Used Not Used 0 Freescale Semiconductor, Inc... D.4.1 Masked ROM Module Configuration Register MRMCR — Masked ROM Module Configuration Register 15 STOP RESET: DATA14 0 0 1 0 0 1 1 1 1 14 0 13 0 12 BOOT 11 LOCK 10 EMUL 9 8 7 6 5 4 3 2 ASPC[1:0] WAIT[1:0] NOT USED $YFF820 1 0 STOP — Low-Power Stop Mode Enable The reset state of the STOP bit is the complement of DATA14 state during reset. The ROM array base address cannot be changed unless the STOP bit is set. 0 = ROM array operates normally. 1 = ROM array operates in low-power stop mode. The ROM array cannot be read in this mode. This bit may be read or written at any time. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-25 Freescale Semiconductor, Inc. BOOT — Boot ROM Control Reset state of BOOT is specified at mask time. This is a read-only bit. 0 = ROM responds to bootstrap word locations during reset vector fetch. 1 = ROM does not respond to bootstrap word locations during reset vector fetch. Bootstrap operation is overridden if STOP = 1 at reset. LOCK — Lock Registers The reset state of LOCK is specified at mask time. If the reset state of the LOCK is zero, it can be set once after reset to allow protection of the registers after initialization. Once the LOCK bit is set, it cannot be cleared again until after a reset. LOCK protects the ASPC and WAIT fields, as well as the ROMBAL and ROMBAH registers. ASPC, ROMBAL and ROMBAH are also protected by the STOP bit. 0 = Write lock disabled. Protected registers and fields can be written. 1 = Write lock enabled. Protected registers and fields cannot be written. EMUL — Emulation Mode Control 0 = Normal ROM operation 1 = Accesses to the ROM array are forced external, allowing memory selected by the CSM pin to respond to the access. Because the MC68HC16Z2 and the MC68HC16Z3 do not support ROM emulation mode, this bit should never be set. ASPC[1:0] — ROM Array Space The ASPC field limits access to the SRAM array in microcontrollers that support separate user and supervisor operating modes. ASPC1 has no effect because the CPU16 operates in supervisor mode only. This bit may be read or written at any time. The reset state of ASPC[1:0] is specified at mask time. Table D-22 shows ASPC[1:0] encoding. Table D-22 ROM Array Space Field ASPC[1:0] X0 X1 State Specified Program and data accesses Program access only Freescale Semiconductor, Inc... WAIT[1:0] — Wait States Field WAIT[1:0] specifies the number of wait states inserted by the MRM during ROM array accesses. The reset state of WAIT[1:0] is user specified. The field can be written only if LOCK = 0 and STOP = 1. Table D-23 shows the wait states field. Table D-23 Wait States Field WAIT[1:0] 00 01 10 11 Number of Wait States 0 1 2 –1 Clocks per Transfer 3 4 5 2 REGISTER SUMMARY D-26 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.4.2 ROM Array Base Address Registers ROMBAH — ROM Array Base Address Register High 15 0 RESET: 1 1 1 1 1 1 1 1 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 ADDR 23 6 ADDR 22 5 ADDR 21 4 ADDR 20 3 ADDR 19 2 ADDR 18 $YFF824 1 ADDR 17 0 ADDR 16 The reset value of the shaded bits is user specified, but the bits can be written after reset to change the base address. If the values of ROMBAH bits ADDR[23:20] do not match that of ADDR19, the CPU16 cannot access the ROM array. ROMBAL — ROM Array Base Address Register Low $YFF826 5 ADDR 5 4 ADDR 4 3 ADDR 3 2 ADDR 2 1 ADDR 1 0 ADDR 0 Freescale Semiconductor, Inc... 15 ADDR 15 14 ADDR 14 13 ADDR 13 12 ADDR 12 11 ADDR 11 10 ADDR 10 9 ADDR 9 8 ADDR 8 7 ADDR 7 6 ADDR 6 RESET: 0 0 0 ROMBAH and ROMBAL specify the ROM array base address. The reset state of these registers is specified at mask time. They can only be written when STOP = 1 and LOCK = 0. This prevents accidental remapping of the array. Because the 8-Kbyte ROM array in the MC68HC16Z2 and the MC68HC16Z3 must be mapped to an 8Kbyte boundary, ROMBAL bits [12:0] always contain $0000. ROMBAH ADDR[15:8] read zero. D.4.3 ROM Signature Registers High RSIGHI — ROM Signature Register High 15 14 13 12 11 10 9 NOT USED RESET: 0 0 0 8 7 6 5 4 3 2 RSP18 $YFF828 1 RSP17 0 RSP16 RSIGLO — ROM Signature Register Low 15 RSP15 14 RSP14 13 RSP13 12 RSP12 11 RSP11 10 RSP10 9 RSP9 8 RSP8 7 RSP7 6 RSP6 5 RSP5 4 RSP4 3 RSP3 2 RSP2 $YFF82A 1 RSP1 0 RSP0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Signature registers RSIGHI and RSIGLO contain a user-specified mask-programmed signature pattern. A user-specified signature algorithm provides the capability to verify ROM array contents. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-27 Freescale Semiconductor, Inc. D.4.4 ROM Bootstrap Words ROMBS0 — ROM Bootstrap Word 0 15 14 13 12 11 10 ZK[3:0] 9 8 7 6 SK[3:0] 5 4 3 2 PK[3:0] NOT USED $YFF830 1 0 ROMBS1 — ROM Bootstrap Word 1 15 14 13 12 11 10 9 8 PC[15:0] 7 6 5 4 3 2 $YFF832 1 0 ROMBS2 — ROM Bootstrap Word 2 15 14 13 12 11 10 9 8 SP[15:0] 7 6 5 4 3 2 $YFF834 1 0 Freescale Semiconductor, Inc... ROMBS3 — ROM Bootstrap Word 3 15 14 13 12 11 10 9 8 IZ[15:0] 7 6 5 4 3 2 $YFF836 1 0 Typically, CPU16 reset vectors reside in non-volatile memory and are fetched when the CPU16 comes out of reset. These four words can be used as reset vectors with the contents specified at mask time. The content of these words cannot be changed. On generic (blank ROM) MC68HC16Z2 and MC68HC16Z3 devices, ROMBS[0:3] are masked to $0000. When the ROM on the MC68HC16Z2 and MC68HC16Z3 is masked with customer specific code, ROMBS[0:3] respond to system addresses $00000 to $00006 during the reset vector fetch if BOOT = 0. REGISTER SUMMARY D-28 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.5 Analog-to-Digital Converter Module Table D-24 ADC Module Address Map Address 1 15 87 ADC Module Configuration Register (ADCMCR) ADC Test Register (ADCTEST) Not Used Not Used 0 $YFF700 $YFF702 $YFF704 $YFF706 $YFF708 $YFF70A $YFF70C $YFF70E $YFF710 Port ADA Data Register (PORTADA) Not Used Control Register 0 (ADCTL0) Control Register 1 (ADCTL1) Status Register (ADCSTAT) Right-Justified Unsigned Result Register 0 (RJURR0) Right-Justified Unsigned Result Register 1 (RJURR1) Right-Justified Unsigned Result Register 2 (RJURR2) Right-Justified Unsigned Result Register 3 (RJURR3) Right-Justified Unsigned Result Register 4 (RJURR4) Right-Justified Unsigned Result Register 5 (RJURR5) Right-Justified Unsigned Result Register 6 (RJURR6) Right-Justified Unsigned Result Register 7 (RJURR7) Left-Justified Signed Result Register 0 (LJSRR0) Left-Justified Signed Result Register 1 (LJSRR1) Left-Justified Signed Result Register 2 (LJSRR2) Left-Justified Signed Result Register 3 (LJSRR3) Left-Justified Signed Result Register 4 (LJSRR4) Left-Justified Signed Result Register 5 (LJSRR5) Left-Justified Signed Result Register 6 (LJSRR6) Left-Justified Signed Result Register 7 (LJSRR7) Left-Justified Unsigned Result Register 0 (LJURR0) Left-Justified Unsigned Result Register 1 (LJURR1) Left-Justified Unsigned Result Register 2 (LJURR2) Left-Justified Unsigned Result Register 3 (LJURR3) Left-Justified Unsigned Result Register 4 (LJURR4) Left-Justified Unsigned Result Register 5 (LJURR5) Left-Justified Unsigned Result Register 6 (LJURR6) Left-Justified Unsigned Result Register 7 (LJURR7) Freescale Semiconductor, Inc... $YFF712 $YFF714 $YFF716 $YFF718 $YFF71A $YFF71C $YFF71E $YFF720 $YFF722 $YFF724 $YFF726 $YFF728 $YFF72A $YFF72C $YFF72E $YFF730 $YFF732 $YFF734 $YFF736 $YFF738 $YFF73A $YFF73C $YFF73E NOTES: 1. Y = M111, where M is the logic state of the MM bit in the SIMCR M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-29 Freescale Semiconductor, Inc. D.5.1 ADC Module Configuration Register ADCMCR — ADC Module Configuration Register 15 STOP RESET: 1 0 0 1 14 FRZ 13 12 NOT USED 8 7 SUPV 6 NOT USED $YFF700 0 ADCMCR controls ADC operation during low-power stop mode, background debug mode, and freeze mode. STOP — Low-Power Stop Mode Enable 0 = Normal operation 1 = Low-power operation STOP places the ADC in low-power state. Setting STOP aborts any conversion in progress. STOP is set to logic level one during reset, and may be cleared to logic level zero by the CPU16. Clearing STOP enables normal ADC operation. However, because analog circuitry bias current has been turned off, there is a period of recovery before output stabilization. FRZ[1:0] — Freeze Assertion Response The FRZ field determines ADC response to assertion of the FREEZE signal when the device is placed in background debug mode. Refer to Table D-25. Table D-25 Freeze Encoding FRZ[1:0] 00 01 10 11 Reserved Finish conversion in process, then freeze Freeze immediately Response Ignore FREEZE, continue conversions Freescale Semiconductor, Inc... SUPV — Supervisor/Unrestricted This bit has no effect because the CPU16 always operates in supervisor mode. D.5.2 ADC Test Register ADCTEST — ADC Test Register Used for factory test only. D.5.3 Port ADA Data Register PORTADA — Port ADA Data Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 NOT USED RESET: REFLECTS STATE OF THE INPUT PINS $YFF702 $YFF706 1 0 PADA7 PADA6 PADA5 PADA4 PADA3 PADA2 PADA1 PADA0 Port ADA is an input port that shares pins with the A/D converter inputs. REGISTER SUMMARY D-30 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. PADA[7:0] — Port ADA Data Pins A read of PADA[7:0] returns the logic level of the port ADA pins. If an input is not at an appropriate logic level (that is, outside the defined levels), the read is indeterminate. Use of a port ADA pin for digital input does not preclude its simultaneous use as an analog input. D.5.4 ADC Control Register 0 ADCTL0 — ADC Control Register 0 15 14 13 12 11 10 9 8 7 RES10 6 STS[1:0] 5 4 3 2 PRS[4:0] NOT USED RESET: 0 0 0 0 0 0 1 1 $YFF70A 1 0 Freescale Semiconductor, Inc... ADCTL0 is used to select 8- or 10-bit conversions, sample time, and ADC clock frequency. Writes to it have immediate effect. RES10 — 10-Bit Resolution 0 = 8-bit conversion 1 = 10-bit conversion Conversion results are appropriately aligned in result registers to reflect the number of bits. STS[1:0] — Sample Time Selection Total conversion time is the sum of initial sample time, transfer time, final sample time, and resolution time. Initial sample time is fixed at two ADC clocks. Transfer time is fixed at two ADC clocks. Resolution time is fixed at ten ADC clocks for an 8-bit conversion and twelve ADC clocks for a 10-bit conversion. Final sample time is determined by the STS[1:0] field. Refer to Table D-26. Table D-26 Sample Time Selection STS[1:0] 00 01 10 11 Sample Time 2 ADC Clock Periods 4 ADC Clock Periods 8 ADC Clock Periods 16 ADC Clock Periods PRS[4:0] — Prescaler Rate Selection The ADC clock is derived from the system clock by a programmable prescaler. ADC clock period is determined by the value of the PRS field in ADCTL0. The prescaler has two stages. The first stage is a 5-bit modulus counter. It divides the system clock by any value from two to 32 (PRS[4:0] = %00000 to %11111). The second stage is a divide-by-two circuit. Refer to Table D-27. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-31 Freescale Semiconductor, Inc. Table D-27 Prescaler Output PRS[4:0] %00000 %00001 %00010 %00011 … %11101 %11110 %11111 ADC Clock Reserved System Clock/4 System Clock/6 System Clock/8 … System Clock/60 System Clock/62 System Clock/64 Minimum System Clock — 2.0 MHz 3.0 MHz 4.0 MHz … 30.0 MHz 31.0 MHz 32.0 MHz Maximum System Clock — 8.4 MHz 12.6 MHz 16.8 MHz … — — — Freescale Semiconductor, Inc... D.5.5 ADC Control Register 1 ADCTL1 — ADC Control Register 1 15 NOT USED RESET: 0 0 0 0 0 0 0 7 6 SCAN 5 MULT 4 S8CM 3 CD 2 CC $YFF70C 1 CB 0 CA ADCTL1 is used to initiate an A/D conversion and to select conversion modes and a conversion channel or channels. It can be read or written at any time. A write to ADCTL1 initiates a conversion sequence. If a conversion sequence is already in progress, a write to ADCTL1 aborts it and resets the SCF and CCF flags in the ADC status register. SCAN — Scan Mode Selection 0 = Single conversion 1 = Continuous conversions Length of conversion sequence(s) is determined by S8CM. MULT — Multichannel Conversion 0 = Conversion sequence(s) run on a single channel selected by [CD:CA]. 1 = Sequential conversions of four or eight channels selected by [CD:CA]. Length of conversion sequence(s) is determined by S8CM. S8CM — Select Eight-Conversion Sequence Mode 0 = Four-conversion sequence 1 = Eight-conversion sequence This bit determines the number of conversions in a conversion sequence. Table D-28 displays the different ADC conversion modes. REGISTER SUMMARY D-32 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table D-28 ADC Conversion Mode SCAN 0 0 0 0 1 1 1 1 MULT 0 0 1 1 0 0 1 1 S8CM 0 1 0 1 0 1 0 1 MODE Single 4-Conversion Single-Channel Sequence Single 8-Conversion Single-Channel Sequence Single 4-Conversion Multichannel Sequence Single 8-Conversion Multichannel Sequence Multiple 4-Conversion Single-Channel Sequences Multiple 8-Conversion Single-Channel Sequences Multiple 4-Conversion Multichannel Sequences Multiple 8-Conversion Multichannel Sequences Freescale Semiconductor, Inc... CD:CA — Channel Selection Bits in this field select input channel or channels for A/D conversion. Conversion mode determines which channel or channels are selected for conversion and which result registers are used to store conversion results. Tables D-29 and D-30 contain a summary of the effects of ADCTL1 bits and fields. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-33 Freescale Semiconductor, Inc. Table D-29 Single-Channel Conversions (MULT = 0) S8CM 0 0 0 0 0 0 0 0 0 0 CD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH VRL (VRH – VRL) / 2 Test/Reserved AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH VRL (VRH – VRL) / 2 Test/Reserved Result Register1 RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:3] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] RSLT[0:7] Freescale Semiconductor, Inc... 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES: 1. Result register (RSLT) is either RJURRX, LJSRRX, or LJURRX, depending on the address read. REGISTER SUMMARY D-34 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table D-30 Multiple-Channel Conversions (MULT = 1) S8CM 0 CD 0 CC 0 CB X CA X Input AN0 AN1 AN2 AN3 0 0 1 X X AN4 AN5 AN6 AN7 0 1 0 X X Reserved Reserved Reserved Reserved 0 1 1 X X VRH VRL (VRH – VRL) / 2 Test/Reserved 1 0 X X X AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 1 1 X X X Reserved Reserved Reserved Reserved VRH VRL (VRH – VRL) / 2 Test/Reserved Result Register1 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT4 RSLT5 RSLT6 RSLT7 RSLT0 RSLT1 RSLT2 RSLT3 RSLT4 RSLT5 RSLT6 RSLT7 Freescale Semiconductor, Inc... NOTES: 1. Result register (RSLT) is either RJURRX, LJSRRX, or LJURRX, depending on the address read. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-35 Freescale Semiconductor, Inc. D.5.6 ADC Status Register ADCSTAT — ADC Status Register 15 SCF RESET: 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 CCTR[2:0] 8 7 6 5 4 3 2 NOT USED CCF[7:0] $YFF70E 1 0 ADCSTAT contains information related to the status of a conversion sequence. SCF — Sequence Complete Flag 0 = Sequence not complete 1 = Sequence complete SCF is set at the end of the conversion sequence when SCAN is cleared, and at the end of the first conversion sequence when SCAN is set. SCF is cleared when ADCTL1 is written and a new conversion sequence begins. CCTR[2:0] — Conversion Counter This field reflects the contents of the conversion counter pointer in either four or eight count conversion sequence. The value corresponds to the number of the next result register to be written, and thus indicates which channel is being converted. CCF[7:0] — Conversion Complete Flags Each bit in this field corresponds to an A/D result register (for example, CCF7 to RSLT7). A bit is set when conversion for the corresponding channel is complete, and remains set until the associated result register is read. D.5.7 Right Justified, Unsigned Result Register RJURR — Right-Justified, Unsigned Result Register 15 NOT USED 10 9 10 8 10 7 8/10 6 8/10 5 8/10 4 8/10 Freescale Semiconductor, Inc... $YFF710–$YFF71F 3 8/10 2 8/10 1 8/10 0 8/10 Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution. For 8-bit conversions, bits [7:0] contain data and bits [9:8] are zero. Bits [15:10] always return zero when read. D.5.8 Left Justified, Signed Result Register LJSRR — Left Justified, Signed Result Register 15 8/10 14 8/10 13 8/10 12 8/10 11 8/10 10 8/10 9 8/10 8 8/10 7 10 6 10 5 NOT USED $YFF720–$YFF72F 0 Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution. For 8-bit conversions, bits [15:8] contain data and bits [7:6] are zero. Although the ADC is unipolar, it is assumed that the zero point is halfway between low and high reference when this format is used (VRH – VRL/2). For positive input, bit 15 = 0. For negative input, bit 15 = 1. Bits [5:0] always return zero when read. REGISTER SUMMARY D-36 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.5.9 Left Justified, Unsigned Result Register LJURR — Left Justified, Unsigned Result Register 15 8/10 14 8/10 13 8/10 12 8/10 11 8/10 10 8/10 9 8/10 8 8/10 7 10 6 10 5 NOT USED $YFF730–$YFF73F 0 Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolution. For 8-bit conversions, bits [15:8] contain data and bits [7:6] are zero. Bits [5:0] always return zero when read. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-37 Freescale Semiconductor, Inc. D.6 Queued Serial Module Table D-31 QSM Address Map Address1 $YFFC00 $YFFC02 $YFFC04 $YFFC06 $YFFC08 $YFFC0A $YFFC0C $YFFC0E $YFFC10 $YFFC12 $YFFC14 $YFFC16 $YFFC18 $YFFC1A $YFFC1C $YFFC1E $YFFC20 – $YFFCFF $YFFD00 – $YFFD1F $YFFD20 – $YFFD3F $YFFD40 – $YFFD4F Not Used Port QS Pin Assignment Register (PQSPAR) 15 87 QSM Module Configuration Register (QSMCR) QSM Test Register (QTEST) QSM Interrupt Level Register (QILR) QSM Interrupt Vector Register (QIVR) Not Used SCI Control 0 Register (SCCR0) SCI Control 1 Register (SCCR1) SCI Status Register (SCSR) SCI Data Register (SCDR) Not Used Not Used Port QS Data Register (PORTQS) Port QS Data Direction Register (DDRQS) 0 Freescale Semiconductor, Inc... SPI Control Register 0 (SPCR0) SPI Control Register 1 (SPCR1) SPI Control Register 2 (SPCR2) SPI Control Register 3 (SPCR3) Not Used Receive RAM (RR[0:F]) Transmit RAM (TR[0:F]) Command RAM (CR[0:F]) SPI Status Register (SPSR) NOTES: 1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR. D.6.1 QSM Configuration Register QSMCR — QSM Configuration Register 15 STOP RESET: 0 0 0 1 0 0 0 0 14 FRZ1 13 FRZ0 12 11 10 NOT USED 9 8 7 SUPV 6 5 NOT USED 4 3 2 $YFFC00 1 0 IARB[3:0] QSMCR bits enable stop and freeze modes, and determine the arbitration priority of QSM interrupt requests. REGISTER SUMMARY D-38 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. STOP — Low-Power Stop Mode Enable 0 = QSM clock operates normally. 1 = QSM clock is stopped. When STOP is set, the QSM enters low-power stop mode. The system clock input to the module is disabled. While STOP is set, only QSMCR reads and writes are guaranteed to be valid, but only writes to the QSPI RAM and other QSM registers are guaranteed valid. The SCI receiver and transmitter and the QSPI should be disabled before STOP is set. To stop the QSPI, set the HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP. To stop the SCI, clear the TS and RE bits in SCCR1. FRZ1 — FREEZE Assertion Response FRZ1 determines what action is taken by the QSPI when the IMB FREEZE signal is asserted. 0 = Ignore the IMB FREEZE signal. 1 = Halt the QSPI on a transfer boundary. FRZ0 — Not Implemented Bits [12:8] — Not Implemented SUPV — Supervisor/Unrestricted This bit has no effect because the CPU16 in the MCU operates only in supervisor mode. Bits [6:4] — Not Implemented IARB[3:0] — Interrupt Arbitration ID The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each module that can generate interrupt requests must be assigned a unique, non-zero IARB field value in order to request an interrupt. D.6.2 QSM Test Register QTEST — QSM Test Register Used for factory test only. D.6.3 QSM Interrupt Level Register/Interrupt Vector Register QILR — QSM Interrupt Levels Register QIVR — QSM Interrupt Vector Register 15 14 13 12 ILQSPI[2:0] 11 10 9 ILSCI[2:0] 8 7 6 5 4 3 2 NOT USED RESET: 0 0 0 0 0 0 0 0 0 0 1 1 1 1 INTV[7:0] Freescale Semiconductor, Inc... $YFFC02 $YFFC04 $YFFC05 1 0 The values of ILQSPI[2:0] and ILSCI[2:0] in QILR determine the priority of QSPI and SCI interrupt requests. QIVR determines the value of the interrupt vector number the QSM supplies when it responds to an interrupt acknowledge cycle. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-39 Freescale Semiconductor, Inc. ILQSPI[2:0] — Interrupt Level for QSPI When an interrupt request is made, the ILQSPI value determines the priority level of all QSPI interrupts. When a request is acknowledged, the QSM compares this value to a mask value supplied by the CPU16 to determine whether to respond. ILQSPI must have a value in the range $0 (interrupts disabled) to $7 (highest priority). ILSCI[2:0] — Interrupt Level for SCI When an interrupt request is made, the ILSCI value determines the priority level of all SCI interrupts. When a request is acknowledged, the QSM compares this value to a mask value supplied by the CPU16 to determine whether to respond. The field must have a value in the range $0 (interrupts disabled) to $7 (highest priority). If ILQSPI[2:0] and ILSCI[2:0] have the same non-zero value, and both submodules simultaneously request interrupt service, the QSPI takes priority over the SCI. Freescale Semiconductor, Inc... INTV[7:0] — Interrupt Vector Number The value of INTV[7:1] is used for both QSPI and SCI interrupt requests; the value of INTV0 used during an interrupt acknowledge cycle is supplied by the QSM. INTV0 is at logic level zero during an SCI interrupt and at logic level one during a QSPI interrupt. A write to INTV0 has no effect. Reads of INTV0 return a value of one. At reset, QIVR is initialized to $0F, the uninitialized interrupt vector number. To use interrupt-driven serial communication, a user-defined vector number must be written to QIVR. D.6.4 SCI Control Register SCCR0 — SCI Control Register 0 15 14 NOT USED RESET: 0 0 0 0 0 0 0 0 0 0 1 0 0 13 12 11 10 9 8 7 6 SCBR[12:0] 5 4 3 2 $YFFC08 1 0 SCCR0 contains the SCI baud rate selection field. Baud rate must be set before the SCI is enabled. The CPU16 can read and write SCCR0 at any time. Changing the value of SCCR0 bits during a transfer operation disrupts operation. Bits [15:13] — Not Implemented SCBR[12:0] — SCI Baud Rate SCI baud rate is programmed by writing a 13-bit value to this field. Writing a value of zero to SCBR disables the baud rate generator. The baud clock rate is calculated as follows: f sys SCI Baud Rate = ------------------------------------------32 × SCBR[12:0] or f sys SCBR[12:0] = -------------------------------------------------------------------------32 × SCI Baud Rate Desired where SCBR[12:0] is in the range of 1 to 8191. REGISTER SUMMARY D-40 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Writing a value of zero to SCBR disables the baud rate generator. There are 8191 different bauds available. The baud value depends on the value for SCBR and the system clock, as used in the equation above. Table D-32 shows possible baud rates for a 16.78 MHz system clock. The maximum baud rate with this system clock speed is 524 kbaud. Table D-32 Examples of SCI Baud Rates Nominal Baud Rate 500,00.00 38,400.00 32,768.00 19,200.00 Actual Baud Rate 524,288.00 37,449.14 32,768.00 19,418.07 9,532.51 4,809.98 2,404.99 1,199.74 599.87 299.94 110.01 64.00 Percent Error 4.86 –2.48 0.00 1.14 –0.70 0.21 0.21 –0.02 –0.02 –0.02 0.01 0.01 Value of SCBR 1 14 16 27 55 109 218 437 874 1,748 4,766 8,191 Freescale Semiconductor, Inc... 9,600.00 4,800.00 2,400.00 1,200.00 600.00 300.00 110.00 64.00 More accurate baud rates can be obtained by varying the system clock frequency with the VCO synthesizer. Each VCO speed increment adjusts the baud rate up or down by 1/64 or 1.56%. D.6.5 SCI Control Register 1 SCCR1 — SCI Control Register 1 15 NOT USED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 LOOPS 13 WOMS 12 ILT 11 PT 10 PE 9 M 8 WAKE 7 TIE 6 TCIE 5 RIE 4 ILIE 3 TE $YFFC0A 2 RE 1 RWU 0 SBK SCCR1 contains SCI configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. SCCR0 can be read or written at any time. The SCI can modify the RWU bit under certain circumstances. Changing the value of SCCR1 bits during a transfer operation disrupts operation. Bit 15 — Not Implemented LOOPS — Loop Mode 0 = Normal SCI operation, no looping, feedback path disabled. 1 = Test SCI operation, looping, feedback path enabled. WOMS — Wired-OR Mode for SCI Pins 0 = If configured as an output, TXD is a normal CMOS output. 1 = If configured as an output, TXD is an open-drain output. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-41 Freescale Semiconductor, Inc. ILT — Idle-Line Detect Type 0 = Short idle-line detect (start count on first one). 1 = Long idle-line detect (start count on first one after stop bit(s)). PT — Parity Type 0 = Even parity 1 = Odd parity PE — Parity Enable 0 = SCI parity disabled. 1 = SCI parity enabled. M — Mode Select 0 = 10-bit SCI frame (1 start bit, 8 data bits, 1 stop bit) 1 = 11-bit SCI frame (1 start bit, 9 data bits, 1 stop bit) WAKE — Wake-Up by Address Mark 0 = SCI receiver awakened by idle-line detection. 1 = SCI receiver awakened by address mark (last data bit set). TIE — Transmit Interrupt Enable 0 = SCI TDRE interrupts disabled. 1 = SCI TDRE interrupts enabled. TCIE — Transmit Complete Interrupt Enable 0 = SCI TC interrupts disabled. 1 = SCI TC interrupts enabled. RIE — Receiver Interrupt Enable 0 = SCI RDRF and OR interrupts disabled. 1 = SCI RDRF and OR interrupts enabled. ILIE — Idle-Line Interrupt Enable 0 = SCI IDLE interrupts disabled. 1 = SCI IDLE interrupts enabled. TE — Transmitter Enable 0 = SCI transmitter disabled (TXD pin can be used as I/O). 1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter). RE — Receiver Enable 0 = SCI receiver disabled. 1 = SCI receiver enabled. RWU — Receiver Wake-Up 0 = Normal receiver operation (received data recognized). 1 = Wake-up mode enabled (received data ignored until receiver is awakened). SBK — Send Break 0 = Normal operation 1 = Break frame(s) transmitted after completion of the current frame. REGISTER SUMMARY D-42 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. D.6.6 SCI Status Register SCSR — SCI Status Register 15 NOT USED RESET: 1 1 0 0 0 0 0 0 0 9 8 TDRE 7 TC 6 RDRF 5 RAF 4 IDLE 3 OR 2 NF $YFFC0C 1 FE 0 PF SCSR contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware or by a read/write sequence. The sequence consists of reading SCSR, then reading or writing SCDR. If an internal SCI signal for setting a status bit comes after reading the asserted status bits, but before writing or reading SCDR, the newly set status bit is not cleared. SCSR must be read again with the bit set and SCDR must be read or written before the status bit is cleared. A long-word read can consecutively access both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the read, but does not clear TDRE or TC flags. Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit already set in either byte is cleared on a subsequent read or write of SCDR. Bits [15:9] — Not implemented TDRE — Transmit Data Register Empty 0 = Transmit data register still contains data to be sent to the transmit serial shifter. 1 = A new character can now be written to the transmit data register. TC — Transmit Complete 0 = SCI transmitter is busy. 1 = SCI transmitter is idle. RDRF — Receive Data Register Full 0 = Receive data register is empty or contains previously read data. 1 = Receive data register contains new data. RAF — Receiver Active 0 = SCI receiver is idle. 1 = SCI receiver is busy. IDLE — Idle-Line Detected 0 = SCI receiver did not detect an idle-line condition. 1 = SCI receiver detected an idle-line condition. OR — Overrun Error 0 = Receive data register is empty and can accept data from the receive serial shifter. 1 = Receive data register is full and cannot accept data from the receive serial shifter. Any data in the shifter is lost and RDRF remains set. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-43 Freescale Semiconductor, Inc. NF — Noise Error 0 = No noise detected in the received data. 1 = Noise detected in the received data. FE — Framing Error 0 = No framing error detected in the received data. 1 = Framing error or break detected in the received data. PF — Parity Error 0 = No parity error detected in the received data. 1 = Parity error detected in the received data. D.6.7 SCI Data Register Freescale Semiconductor, Inc... SCDR — SCI Data Register 15 NOT USED RESET: U U U U U U U 9 8 R8/T8 7 R7/T7 6 R6/T6 5 R5/T5 4 R4/T4 3 R3/T3 2 R2/T2 $YFFC0E 1 R1/T1 0 R0/T0 U U SCDR consists of two data registers located at the same address. The receive data register (RDR) is a read-only register that contains data received by the SCI serial interface. Data comes into the receive serial shifter and is transferred to RDR. The transmit data register (TDR) is a write-only register that contains data to be transmitted. Data is first written to TDR, then transferred to the transmit serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for nine-bit operation. When the SCI is configured for 8-bit operation, R8/T8 has no meaning or effect. D.6.8 Port QS Data Register PORTQS — Port QS Data Register 15 NOT USED 8 7 PQS7 RESET: 0 0 0 0 0 0 0 0 6 PQS6 5 PQS5 4 PQS4 3 PQS3 2 PQS2 $YFFC14 1 PQS1 0 PQS0 PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the pins. To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS. REGISTER SUMMARY D-44 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.6.9 Port QS Pin Assignment Register/Data Direction Register PQSPAR — PORT QS Pin Assignment Register DDRQS — PORT QS Data Direction Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 NOT USED PQSPA6 PQSPA5 PQSPA4 NOT PQSPA3 USED PQSPA1 $YFFC16 $YFFC17 1 0 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O. Setting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI. Table D-33 displays PQSPAR pin assignments. Freescale Semiconductor, Inc... Table D-33 PQSPAR Pin Assignments PQSPAR Field PQSPA0 PQSPA1 — PQSPA3 PQSPA4 PQSPA5 PQSPA6 — PQSPAR Bit 0 1 0 1 — — 0 1 0 1 0 1 0 1 — — Pin Function PQS0 MISO PQS1 MOSI PQS21 SCK PQS3 PCS0/SS PQS4 PCS1 PQS5 PCS2 PQS6 PCS3 PQS72 TXD NOTES: 1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which case it becomes the QSPI serial clock SCK. 2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE set in SCCR1), in which case it becomes the SCI serial output TXD. DDRQS determines whether pins configured for general-purpose I/O are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function.Table D-34 shows the effect of DDRQS on QSM pin function. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-45 Freescale Semiconductor, Inc. Table D-34 Effect of DDRQS on QSM Pin Function QSM Pin MISO Mode Master Slave MOSI Master Slave SCK1 PCS0/SS Master Slave Master Slave PCS[1:3] Master Slave TXD2 RXD — — DDQS7 None DDQS[4:6] DDQS2 DDQS3 DDQS1 DDRQS Bit DDQS0 Bit State 0 1 0 1 0 1 0 1 — — 0 1 0 1 0 1 0 1 X NA Pin Function Serial data input to QSPI Disables data input Disables data output Serial data output from QSPI Disables data output Serial data output from QSPI Serial data input to QSPI Disables data input Clock output from QSPI Clock input to QSPI Assertion causes mode fault Chip-select output QSPI slave select input Disables slave select Input Disables chip-select output Chip-select outputs enabled No effect No effect Serial data output from SCI Serial data input to SCI Freescale Semiconductor, Inc... NOTES: 1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which case it becomes the QSPI serial clock SCK. 2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE set in SCCR1), in which case it becomes the SCI serial data output TXD. DDQS7 determines the direction of PQS7 only when the SCI transmitter is disabled. When the SCI transmitter is enabled, PQS7 is the TXD output. D.6.10 QSPI Control Register 0 SPCR0 — QSPI Control Register 0 15 MSTR RESET: 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 WOMQ 13 12 11 10 9 CPOL 8 CPHA 7 6 5 4 3 2 BITS[3:0] SPBR[7:0] $YFFC18 1 0 SPCR0 contains parameters for configuring the QSPI and enabling various modes of operation. SPCR0 must be initialized before QSPI operation begins. Writing a new value to SPCR0 while the QSPI is enabled disrupts operation. MSTR — Master/Slave Mode Select 0 = QSPI is a slave device. 1 = QSPI is the system master. REGISTER SUMMARY D-46 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. WOMQ — Wired-OR Mode for QSPI Pins 0 = Pins designated for output by DDRQS operate in normal mode. 1 = Pins designated for output by DDRQS operate in open-drain mode. BITS[3:0] — Bits Per Transfer In master mode, when BITSE is set in a command RAM byte, BITS[3:0] determines the number of data bits transferred. When BITSE is cleared, eight bits are transferred. Reserved values default to eight bits. In slave mode, the command RAM is not used and the setting of BITSE has no effect on QSPI transfers. Instead, the BITS[3:0] field determines the number of bits the QSPI will receive during each transfer before storing the received data. Table D-35 shows the number of bits per transfer. Freescale Semiconductor, Inc... Table D-35 Bits Per Transfer BITS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 8 9 10 11 12 13 14 15 CPOL — Clock Polarity 0 = The inactive state of SCK is logic zero. 1 = The inactive state of SCK is logic one. CPOL is used to determine the inactive state of the serial clock (SCK). It is used with CPHA to produce a desired clock/data relationship between master and slave devices. CPHA — Clock Phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK CPHA determines which edge of SCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-47 Freescale Semiconductor, Inc. SPBR[7:0] — Serial Clock Baud Rate The QSPI uses a modulus counter to derive the SCK baud rate from the MCU system clock. Baud rate is selected by writing a value from two to 255 into SPBR[7:0]. The following equation determines the SCK baud rate: f sys SCK Baud Rate = -----------------------------------2 × SPBR[7:0] or f sys SPBR[7:0] = ------------------------------------------------------------------------2 × SCK Baud Rate Desired Giving SPBR[7:0] a value of zero or one disables the baud rate generator. SCK is disabled and assumes its inactive state value. No serial transfers occur. At reset, the SCK baud rate is initialized to one-eighth of the system clock frequency. SPBR has 254 active values. Table D-36 lists several possible baud values and the corresponding SCK frequency based on a 16.78-MHz system clock. Table D-36 Examples of SCK Frequencies fsys 16.78 MHz Required Division Ratio 4 8 16 34 168 510 Value of SPBR 2 4 8 17 84 255 Actual SCK Frequency 4.19 MHz 2.10 MHz 1.05 MHz 493 kHz 100 kHz 33 kHz Freescale Semiconductor, Inc... D.6.11 QSPI Control Register 1 SPCR1 — QSPI Control Register 1 15 SPE RESET: 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 14 13 12 11 DSCKL[6:0] 10 9 8 7 6 5 4 3 2 DTL[7:0] $YFFC1A 1 0 SPCR1 enables the QSPI and specifies transfer delays. SPCR1 must be written last during initialization because it contains SPE. Writing a new value to SPCR1 while the QSPI is enabled disrupts operation. SPE — QSPI Enable 0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O. 1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI. REGISTER SUMMARY D-48 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. DSCKL[6:0] — Delay before SCK When the DSCK bit is set in a command RAM byte, this field determines the length of the delay from PCS valid to SCK transition. PCS can be any of the four peripheral chipselect pins. The following equation determines the actual delay before SCK: DSCKL[6:0] PCS to SCK Delay = -----------------------------f sys where DSCKL[6:0] is in the range of one to 127. When DSCK is zero in a command RAM byte, then DSCKL[6:0] is not used. Instead, the PCS valid to SCK transition is one-half the SCK period. Freescale Semiconductor, Inc... DTL[7:0] — Length of Delay after Transfer When the DT bit is set in a command RAM byte, this field determines the length of the delay after a serial transfer. The following equation is used to calculate the delay: 32 × DTL[7:0] Delay after Transfer = ----------------------------------f sys where DTL is in the range of one to 255. A zero value for DTL[7:0] causes a delay-after-transfer value of 8192 ÷ fsys. If DT is zero in a command RAM byte, a standard delay is inserted: 17 Standard Delay after Transfer = ------f sys Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. This is controlled by the DT bit in a command RAM byte. D.6.12 QSPI Control Register 2 SPCR2 — QSPI Control Register 2 15 SPIFIE RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 WREN 13 WRTO 12 0 11 10 9 8 7 0 6 0 5 0 4 0 3 2 ENDQP[3:0] $YFFC1C 1 0 NEWQP[3:0] M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-49 Freescale Semiconductor, Inc. SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt enable bit. SPCR2 is buffered. New SPCR2 values become effective only after completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location. Reads of SPCR2 return the value of the register, not the buffer. SPIFIE — SPI Finished Interrupt Enable 0 = QSPI interrupts disabled. 1 = QSPI interrupts enabled. WREN — Wrap Enable 0 = Wraparound mode disabled. 1 = Wraparound mode enabled. Freescale Semiconductor, Inc... WRTO — Wrap To 0 = Wrap to pointer address $0. 1 = Wrap to address in NEWQP. Bit 12 — Not Implemented ENDQP[3:0] — Ending Queue Pointer This field contains the last QSPI queue address. Bits [7:4] — Not Implemented NEWQP[3:0] — New Queue Pointer Value This field contains the first QSPI queue address. D.6.13 QSPI Control Register 3 SPCR3 — QSPI Control Register SPSR — QSPI Status Register 15 14 13 NOT USED RESET: 0 0 0 0 0 0 0 0 0 0 12 11 10 LOOPQ 9 HMIE 8 HALT 7 SPIF 6 MODF 5 HALTA 4 NOT USED 3 2 $YFFC1E $YFFC1F 1 0 CPTQP[3:0] SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and the halt control bit. SPCR3 must be initialized before QSPI operation begins. Writing a new value to SPCR3 while the QSPI is enabled disrupts operation. SPSR contains information concerning the current serial transmission. Bits [15:11] — Not Implemented LOOPQ — QSPI Loop Mode 0 = Feedback path disabled. 1 = Feedback path enabled. LOOPQ controls feedback on the data serializer for testing. REGISTER SUMMARY D-50 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. HMIE — HALTA and MODF Interrupt Enable 0 = HALTA and MODF interrupts disabled. 1 = HALTA and MODF interrupts enabled. HMIE enables interrupt requests generated by the HALTA status flag or the MODF status flag in SPSR. HALT — Halt QSPI 0 = QSPI operates normally. 1 = QSPI is halted for subsequent restart. When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state from which it can later be restarted. SPIF — QSPI Finished Flag 0 = QSPI is not finished. 1 = QSPI is finished. SPIF is set after execution of the command at the address in ENDQP[3:0]. MODF — Mode Fault Flag 0 = Normal operation. 1 = Another SPI node requested to become the network SPI master while the QSPI was enabled in master mode. The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the SS input pin is negated by an external driver. HALTA — Halt Acknowledge Flag 0 = QSPI is not halted. 1 = QSPI is halted. HALTA is set when the QSPI halts in response to setting the SPCR3 HALT bit. Bit 4 — Not Implemented CPTQP[3:0] — Completed Queue Pointer CPTQP[3:0] points to the last command executed. It is updated when the current command is complete. When the first command in a queue is executing, CPTQP[3:0] contains either the reset value $0 or a pointer to the last command completed in the previous queue. D.6.14 Receive Data RAM RR[0:F] — Receive Data RAM $YFFD00 – $YFFD1F Data received by the QSPI is stored in this segment. The CPU16 reads this segment to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry. Receive RAM data can be accessed using byte, word, or longword addressing. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-51 Freescale Semiconductor, Inc. D.6.15 Transmit Data RAM TR[0:F] — Transmit Data RAM $YFFD20 – $YFFD3F Data that is to be transmitted by the QSPI is stored in this segment. The CPU16 normally writes one word of data into this segment for each queue command to be executed. Information to be transmitted must be written to the transmit data RAM in a right-justified format. The QSPI cannot modify information in the transmit data RAM. The QSPI copies the information to its data serializer for transmission. Information remains in the transmit RAM until overwritten. D.6.16 Command RAM Freescale Semiconductor, Inc... CR[0:F] — Command RAM 7 CONT — CONT 6 BITSE 5 DT 4 DSCK 3 PCS3 2 PCS2 1 $YFFD40 – $YFFD4F 0 PCS01 PCS1 — BITSE — DT — DSCK — PCS3 — PCS2 — PCS1 — PCS01 COMMAND CONTROL PERIPHERAL CHIP SELECT NOTES: 1. The PCS0 bit represents the dual-function PCS0/SS. Command RAM is used by the QSPI when in master mode. The CPU16 writes one byte of control information to this segment for each QSPI command to be executed. The QSPI cannot modify information in command RAM. Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer. The command control field provides transfer options. A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in NEWQP through the address in ENDQP (both of these fields are in SPCR2). CONT — Continue 0 = Control of chip selects returned to PORTQS after transfer is complete. 1 = Peripheral chip selects remain asserted after transfer is complete. This allows for transfers greater than 16 bits to peripherals without negation of their chipselects. BITSE — Bits per Transfer Enable 0 = Eight bits 1 = Number of bits set in BITS field of SPCR0. REGISTER SUMMARY D-52 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. DT — Delay after Transfer 0 = Delay after transfer is 17 ÷ fsys. 1 = SPCR1 DTL[7:0] specifies delay after transfer. DSCK — PCS to SCK Delay 0 = PCS valid to SCK delay is one-half SCK. 1 = SPCR1 DSCKL[6:0] specifies delay from PCS valid to SCK. PCS[3:0] — Peripheral Chip Select Use peripheral chip-select bits to select one or more external devices for serial data transfers. More than one peripheral chip select may be activated at a time, and more than one peripheral chip can be connected to each PCS pin, provided proper fanout is observed. PCS0 shares a pin with the slave select (SS) signal, which initiates slave mode serial transfers. If SS is taken low when the QSPI is in master mode, a mode fault occurs. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-53 Freescale Semiconductor, Inc. D.7 Multichannel Communication Interface Module The MCCI is used only in the MC68HC16Z4 and the MC68CK16Z4. Table D-37 shows the MCCI address map. Table D-37 MCCI Address Map Address1 $YFFC00 $YFFC02 $YFFC04 $YFFC06 $YFFC08 $YFFC0A 15 87 MCCI Module Configuration Register (MMCR) MCCI Test Register (MTEST) SCI Interrupt Level Register (ILSCI) SPI Interrupt Level Register (ILSPI) Not Used Not Used Not Used Not Used MCCI Interrupt Vector Register (MIVR) Not Used MCCI Pin Assignment Register (MPAR) MCCI Data Direction Register (MDDR) MCCI Port Data Register (PORTMC) MCCI Port Pin State Register (PORTMCP) Not Used SCIA Control Register 0 (SCCR0A) SCIA Control Register 1 (SCCR1A) SCIA Status Register (SCSRA) SCIA Data Register (SCDRA) Not Used SCIB Control Register 0 (SCCR0B) SCIB Control Register 1 (SCCR1B) SCIB Status Register (SCSRB) SCIB Data Register (SCDRB) Not Used SPI Control Register (SPCR) Not Used SPI Status Register (SPSR) SPI Data Register (SPDR) 0 Freescale Semiconductor, Inc... $YFFC0C $YFFC0E $YFFC10 – $YFFC16 $YFFC18 $YFFC1A $YFFC1C $YFFC1E $YFFC20 – $YFFC26 $YFFC28 $YFFC2A $YFFC2C $YFFC2E $YFFC30 – $YFFC36 $YFFC38 $YFFC3A $YFFC3C $YFFC3E NOTES: 1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR. D.7.1 MCCI Module Configuration Register MMCR — MCCI Module Configuration Register 15 STOP RESET: 0 1 0 0 0 0 14 13 12 11 NOT USED 10 9 8 7 SUPV 6 5 NOT USED 4 3 2 $YFFC00 1 0 IARB[3:0] MMCR bits enable stop mode, establish the privilege level required to access certain MCCI registers, and determine the arbitration priority of MCCI interrupt requests. REGISTER SUMMARY D-54 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. STOP — Low-Power Stop Mode Enable 0 = MCCI clock operates normally. 1 = MCCI clock is stopped. When STOP is set, the MCCI enters low-power stop mode. The system clock input to the module is disabled. While STOP is set, only MMCR reads and writes are guaranteed to be valid. Only writes to other MCCI registers are guaranteed valid. The SCI receiver and transmitter must be disabled before STOP is set. To stop the SPI, set the HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP. Bits [14:8] — Not Implemented SUPV — Supervisor/Unrestricted This bit has no effect because the CPU16 in the MCU operates only in supervisor mode. Freescale Semiconductor, Inc... Bits [6:4] — Not Implemented IARB[3:0] — Interrupt Arbitration ID The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each module that can generate interrupt requests must be assigned a unique, non-zero IARB field value. D.7.2 MCCI Test Register MTEST — MCCI Test Register Used for factory test only. D.7.3 SCI Interrupt Level Register/MCCI Interrupt Vector Register ILSCI — SCI Interrupt Level Register 15 14 13 12 ILSCIB[2:0] 11 10 9 ILSCIA[2:0] 8 7 6 5 4 MIVR 3 2 NOT USED RESET: 0 0 0 0 0 0 0 0 0 0 1 1 1 1 $YFFC02 $YFFC04 1 0 Bits [15:14] — Not Implemented ILSCIA[2:0], ILSCIB[2:0] — Interrupt Level for SCIA, SCIB The values of ILSCIA[2:0] and ILSCIB[2:0] in ILSCI determine the interrupt request levels of SCIA and SCIB interrupts, respectively. Program this field to a value from $0 (interrupts disabled) through $7 (highest priority). M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-55 Freescale Semiconductor, Inc. D.7.4 MCCI Interrupt Vector Register MIVR — MCCI Interrupt Vector Register 15 14 13 12 ILSCI RESET: 0 0 0 0 1 1 1 1 11 10 9 8 7 6 5 4 3 2 INTV[7:2] $YFFC05 1 0 INTV[1:0] The MIVR determines which three vectors in the exception vector table are to be used for MCCI interrupts. The SPI and both SCI interfaces have separate interrupt vectors adjacent to one another. When initializing the MCCI, program INTV[7:2] so that INTV[7:0] correspond to three of the user-defined vectors ($40–$FF). INTV[1:0] are determined by the serial interface causing the interrupt, and are set by the MCCI. Freescale Semiconductor, Inc... At reset, MIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the exception table. INTV[7:2] — Interrupt Vector INTV[7:2] are the six high-order bits of the three MCCI interrupt vectors for the MCCI, as programmed by the user. INTV[1:0] — Interrupt Vector Source INTV[1:0] are the two low-order bits of the three interrupt vectors for the MCCI. They are automatically set by the MCCI to indicate the source of the interrupt. Refer to Table D-38. Table D-38 Interrupt Vector Sources INTV[1:0] 00 01 10 Source of Interrupt SCIA SCIB SPI Writes to INTV0 and INTV1 have no meaning or effect. Reads of INTV0 and INTV1 return a value of one. D.7.5 SPI Interrupt Level Register ILSPI — SPI Interrupt Level Register 15 14 13 12 ILSPI[2:0] 11 10 9 NOT USED 8 7 6 5 4 3 2 NOT USED RESET: 0 0 0 NOT USED $YFFC06 1 0 The ILSPI determines the priority level of interrupts requested by the SPI. Bits [15:14] — Not Implemented REGISTER SUMMARY D-56 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. ILSPI[2:0] — Interrupt Level for SPI ILSPI[2:0] determine the interrupt request levels of SPI interrupts. Program this field to a value from $0 (interrupts disabled) through $7 (highest priority). If the interruptrequest level programmed in this field matches the interrupt-request level programmed for one of the SCI interfaces and both request an interrupt simultaneously, the SPI is given priority. Bits [10:8] — Not Implemented D.7.6 MCCI Pin Assignment Register MPAR — MCCI Pin Assignment Register 15 14 13 12 11 10 9 8 7 6 5 4 3 MPA3 2 NOT USED $YFFC08 1 MPA1 0 MPA0 Freescale Semiconductor, Inc... NOT USED RESET: 0 0 0 0 0 0 0 0 0 0 0 The MPAR determines which of the SPI pins, with the exception of the SCK pin, are actually used by the SPI submodule, and which pins are available for general-purpose I/O. The state of SCK is determined by the SPI enable bit in SPCR1. Clearing a bit in MPAR assigns the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the SPI. Refer to Table D-39. Table D-39 MPAR Pin Assignments MPAR Field MPA0 MPA1 —1 MPA3 —1 —1 —1 —1 MPAR Bit 0 1 0 1 — 0 1 — — — — Pin Function PMC0 MISO PMC1 MOSI PMC2 SCK PMC3 SS PMC4 RXDB PMC5 TXDB PMC6 RXDA PMC7 TXDA NOTES: 1. MPA[7:4], MPA2 are not implemented. Bits [15:8], [7:4], 2 — Not Implemented SPI pins designated by the MPAR as general-purpose I/O are controlled only by MDDR and PORTMC. The SPI has no effect on these pins. The MPAR does not affect the operation of the SCI submodule. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-57 Freescale Semiconductor, Inc. D.7.7 MCCI Data Direction Register MDDR — MCCI Data Direction Register 15 NOT USED RESET: 0 0 0 0 0 0 0 0 8 7 DDR7 6 DDR6 5 DDR5 4 DDR4 3 DDR3 2 DDR2 $YFFC0A 1 DDR1 0 DDR0 MDDR determines whether pins configured for general-purpose I/O are inputs or outputs. MDDR affects both SPI function and I/O function. During reset, all MCCI pins are configured as inputs. Table D-40 shows the effect of MDDR on MCCI pin function. Table D-40 Effect of MDDR on MCCI Pin Function Freescale Semiconductor, Inc... MCCI Pin MISO Mode Master Slave MDDR Bit DDR0 MOSI Master Slave DDR1 SCK1 SS Master Slave Master Slave DDR2 DDR3 RXDB2 TXDB3 RXDA TXDA3 — — — — DDR4 DDR5 DDR6 DDR7 Bit State 0 1 0 1 0 1 0 1 — — 0 1 0 1 0 1 0 1 0 1 0 1 Pin Function Serial data input to SPI Disables data input Disables data output Serial data output from SPI Disables data output Serial data output from SPI Serial data input to SPI Disables data input Clock output from SPI Clock input to SPI Assertion causes mode fault General-purpose I/O SPI slave-select input Disables slave-select input General-purpose I/O Serial data input to SCIB General-purpose I/O Serial data output from SCIB General-purpose I/O Serial data input to SCIA General-purpose I/O Serial data output from SCIA NOTES: 1. SCK is automatically assigned to the SPI whenever the SPI is enabled (when the SPE bit in the SPCR1 is set). 2. PMC4 and PMC6 function as general-purpose I/O pins when the corresponding RE bit in the SCI control register (SCCR0A or SCCR0B) is cleared. 3. PMC5 and PMC7 function as general-purpose I/O pins when the corresponding TE bit in the SCI control register (SCCR0A or SCCR0B) is cleared. REGISTER SUMMARY D-58 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.7.8 MCCI Port Data Registers PORTMC — MCCI Port Data Register PORTMCP — MCCI Port Pin State Register 15 NOT USED RESET: U U U U U U U U U 9 8 PMC7 7 PMC6 6 PMC5 5 PMC5 4 PMC4 3 PMC3 2 PMC2 $YFFC0C $YFFC0E 1 PMC1 0 PMC0 Freescale Semiconductor, Inc... Two registers are associated with port MCCI, the MCCI general-purpose I/O port. Pins used for general-purpose I/O must be configured for that function. When using port MCCI as an output port, after configuring the pins as I/O, write the first byte to be output before writing to the MDDR. Afterwards, write to the MDDR to assign each I/O pin as either input or output. This outputs the value contained in register PORTMC for all pins defined as outputs. To output different data, write another byte to PORTMC. Writes to PORTMC are stored in the internal data latch. If any bit of PORTMC is configured as discrete output, the value latched for that bit is driven onto the pin. Reads of PORTMC return the value of the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value of the latch. Reads of PORTMCP always return the state of the pins regardless of whether the pins are configured for input or output. Writes to PORTMCP have no effect. D.7.9 SCI Control Register 0 SCCR0A — SCIA Control Register 0 SCCR0B — SCIB Control Register 0 15 NOT USED RESET: 0 0 0 0 0 0 0 0 0 0 1 0 0 13 12 11 10 9 8 7 6 SCBR[12:0] 5 4 3 2 $YFFC18 $YFFC28 1 0 SCCR0 contains the SCI baud rate selection field. Baud rate must be set before the SCI is enabled. The CPU16 can read and write SCCR0 at any time. Changing the value of SCCR0 bits during a transfer operation can disrupt the transfer. Bits [15:13] — Not Implemented SCBR[12:0] — SCI Baud Rate SCI baud rate is programmed by writing a 13-bit value to this field. Writing a value of zero to SCBR disables the baud rate generator. Baud clock rate is calculated as follows: M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-59 Freescale Semiconductor, Inc. f sys SCI Baud Rate = ------------------------------------------32 × SCBR[12:0] or f sys SCBR[12:0] = -------------------------------------------------------------------------32 × SCI Baud Rate Desired where SCBR[12:0] is in the range of one to 8191. Writing a value of zero to SCBR disables the baud rate generator. There are 8191 different baud rates available. The baud value depends on the value for SCBR and the system clock, as used in the equation above. Table D-41 shows possible baud rates for a 16.78-MHz system clock. The maximum baud rate with this system clock speed is 524 kbaud. Table D-41 Examples of SCI Baud Rates Nominal Baud Rate 500,00.00 38,400.00 32,768.00 19,200.00 9,600.00 4,800.00 2,400.00 1,200.00 600.00 300.00 110.00 64.00 Actual Baud Rate 524,288.00 37,449.14 32,768.00 19,418.07 9,532.51 4,809.98 2,404.99 1,199.74 599.87 299.94 110.01 64.00 Percent Error 4.86 –2.48 0.00 1.14 –0.70 0.21 0.21 –0.02 –0.02 –0.02 0.01 0.01 Value of SCBR 1 14 16 27 55 109 218 437 874 1,748 4,766 8,191 Freescale Semiconductor, Inc... D.7.10 SCI Control Register 1 SCCR1A — SCIA Control Register 1 SCCR1B — SCIB Control Register 1 15 NOT USED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 LOOPS 13 WOMS 12 ILT 11 PT 10 PE 9 M 8 WAKE 7 TIE 6 TCIE 5 RIE 4 ILIE 3 TE 2 RE $YFFC1A $YFFC2A 1 RWU 0 SBK SCCR1 contains SCI configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. SCCR0 can be read or written at any time. The SCI can modify the RWU bit under certain circumstances. Changing the value of SCCR1 bits during a transfer operation can disrupt the transfer. REGISTER SUMMARY D-60 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Bit 15 — Not Implemented LOOPS — Loop Mode 0 = Normal SCI operation, no looping, feedback path disabled. 1 = Test SCI operation, looping, feedback path enabled. The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter. When LOOPS is set, SCI transmitter output is fed back into the receive serial shifter. The TXD pin is asserted (idle line). Both transmitter and receiver must be enabled prior to entering loop mode. WOMS — Wired-OR Mode for SCI Pins 0 = If configured as an output, TXD is a normal CMOS output. 1 = If configured as an output, TXD is an open-drain output. Freescale Semiconductor, Inc... ILT — Idle-Line Detect Type 0 = Short idle-line detect (start count on first one). 1 = Long idle-line detect (start count on first one after stop bit(s)). PT — Parity Type 0 = Even parity 1 = Odd parity PE — Parity Enable 0 = SCI parity disabled. 1 = SCI parity enabled. M — Mode Select 0 = 10-bit SCI frame (1 start bit, 8 data bits, 1 stop bit) 1 = 11-bit SCI frame (1 start bit, 9 data bits, 1 stop bit) WAKE — Wake-Up by Address Mark 0 = SCI receiver awakened by idle-line detection. 1 = SCI receiver awakened by address mark (last data bit set). TIE — Transmit Interrupt Enable 0 = SCI TDRE interrupts disabled. 1 = SCI TDRE interrupts enabled. TCIE — Transmit Complete Interrupt Enable 0 = SCI TC interrupts disabled. 1 = SCI TC interrupts enabled. RIE — Receiver Interrupt Enable 0 = SCI RDRF and OR interrupts disabled. 1 = SCI RDRF and OR interrupts enabled. ILIE — Idle-Line Interrupt Enable 0 = SCI IDLE interrupts disabled. 1 = SCI IDLE interrupts enabled. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-61 Freescale Semiconductor, Inc. TE — Transmitter Enable 0 = SCI transmitter disabled (TXD pin can be used as I/O). 1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter). RE — Receiver Enable 0 = SCI receiver disabled. 1 = SCI receiver enabled. RWU — Receiver Wake-Up 0 = Normal receiver operation (received data recognized). 1 = Wake-up mode enabled (received data ignored until receiver is awakened). SBK — Send Break 0 = Normal operation 1 = Break frame(s) transmitted after completion of the current frame. D.7.11 SCI Status Register SCSRA — SCIA Status Register SCSRB — SCIB Status Register 15 NOT USED RESET: 1 1 0 0 0 0 0 0 0 9 8 TDRE 7 TC 6 RDRF 5 RAF 4 IDLE 3 OR 2 NF Freescale Semiconductor, Inc... $YFFC1C $YFFC2C 1 FE 0 PF SCSR contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware or by a read/write sequence. The sequence consists of reading SCSR, then reading or writing SCDR. If an internal SCI signal for setting a status bit comes after reading the asserted status bits, but before writing or reading SCDR, the newly set status bit is not cleared. SCSR must be read again with the bit set and SCDR must be read or written before the status bit is cleared. A long-word read can consecutively access both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the read, but does not clear TDRE or TC flags. Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit already set in either byte is cleared on a subsequent read or write of SCDR. Bits [15:9] — Not Implemented TDRE — Transmit Data Register Empty 0 = Transmit data register still contains data to be sent to the transmit serial shifter. 1 = A new character can now be written to the transmit data register. TC — Transmit Complete 0 = SCI transmitter is busy. 1 = SCI transmitter is idle. REGISTER SUMMARY D-62 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. RDRF — Receive Data Register Full 0 = Receive data register is empty or contains previously read data. 1 = Receive data register contains new data. RAF — Receiver Active 0 = SCI receiver is idle. 1 = SCI receiver is busy. IDLE — Idle-Line Detected 0 = SCI receiver did not detect an idle-line condition. 1 = SCI receiver detected an idle-line condition. OR — Overrun Error 0 = Receive data register is empty and can accept data from the receive serial shifter. 1 = Receive data register is full and cannot accept data from the receive serial shifter. Any data in the shifter is lost and RDRF remains set. NF — Noise Error 0 = No noise detected in the received data. 1 = Noise detected in the received data. FE — Framing Error 0 = No framing error detected in the received data. 1 = Framing error or break detected in the received data. PF — Parity Error 0 = No parity error detected in the received data. 1 = Parity error detected in the received data. D.7.12 SCI Data Register SCDRA — SCIA Data Register SCDRB — SCIB Data Register 15 NOT USED RESET: U U U U U U U U U 9 8 R8/T8 7 R7/T7 6 R6/T6 5 R5/T5 4 R4/T4 3 R3/T3 2 R2/T2 Freescale Semiconductor, Inc... $YFFC1E $YFFC2E 1 R1/T1 0 R0/T0 SCDR consists of two data registers located at the same address. The receive data register (RDR) is a read-only register that contains data received by the SCI serial interface. Data comes into the receive serial shifter and is transferred to RDR. The transmit data register (TDR) is a write-only register that contains data to be transmitted. Data is first written to TDR, then transferred to the transmit serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for nine-bit operation. When the SCI is configured for 8-bit operation, R8/T8 have no meaning or effect. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-63 Freescale Semiconductor, Inc. D.7.13 SPI Control Register SPCR — SPI Control Register 15 SPIE RESET: 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 SPE 13 WOMP 12 MSTR 11 CPOL 10 CPHA 9 LSBF 8 SIZE 7 6 5 4 3 2 SPBR[7:0] $YFFC38 1 0 The SPCR contains parameters for configuring the SPI. The register can be read or written at any time. SPIE — SPI Interrupt Enable 0 = SPI interrupts disabled. 1 = SPI interrupts enabled. Freescale Semiconductor, Inc... SPE — SPI Enable 0 = SPI is disabled. 1 = SPI is enabled. WOMP — Wired-OR Mode for SPI Pins 0 = Outputs have normal CMOS drivers. 1 = Pins designated for output by MDDR have open-drain drivers, regardless of whether the pins are used as SPI outputs or for general-purpose I/O, and regardless of whether the SPI is enabled. MSTR — Master/Slave Mode Select 0 = SPI is a slave device. 1 = SPI is system master. CPOL — Clock Polarity 0 = The inactive state value of SCK is logic level zero. 1 = The inactive state value of SCK is logic level one. CPOL is used to determine the inactive state of the serial clock (SCK). It is used with CPHA to produce a desired clock/data relationship between master and slave devices. CPHA — Clock Phase 0 = Data captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK. CPHA determines which edge of SCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices. LSBF — Least Significant Bit First 0 = Serial data transfer starts with LSB. 1 = Serial data transfer starts with MSB. REGISTER SUMMARY D-64 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. SIZE — Transfer Data Size 0 = 8-bit data transfer. 1 = 16-bit data transfer. SPBR[7:0] — Serial Clock Baud Rate The SPI uses a modulus counter to derive the SCK baud rate from the MCU system clock. Baud rate is selected by writing a value from 2 to 255 into SPBR[7:0]. The following expressions apply to SCK baud rate: f sys SCK Baud Rate = -----------------------------------2 × SPBR[7:0] Freescale Semiconductor, Inc... or f sys SPBR[7:0] = ------------------------------------------------------------------------2 × SCK Baud Rate Desired Giving SPBR[7:0] a value of zero or one disables SCK (disable state determined by CPOL). At reset, the SCK baud rate is initialized to one-eighth of the system clock frequency. D.7.14 SPI Status Register SPSR — SPI Status Register 15 SPIF 14 WCOL 13 0 12 MODF 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 $YFFC3C 1 0 0 0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPSR contains information concerning the current serial transmission. Only the SPI can set bits in SPSR. The CPU16 reads SPSR to obtain SPI status information and writes it to clear status flags. SPIF — SPI Finished Flag 0 = SPI is not finished. 1 = SPI is finished. WCOL — Write Collision 0 = No attempt to write to the SPDR happened during the serial transfer. 1 = Write collision occurred. Clearing WCOL is accomplished by reading the SPSR while WCOL is set and then either reading the SPDR prior to SPIF being set, or reading or writing the SPDR after SPIF is set. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-65 Freescale Semiconductor, Inc. MODF — Mode Fault Flag 0 = Normal operation. 1 = Another SPI node requested to become the network SPI master while the SPI was enabled in master mode (SS input taken low). The SPI asserts MODF when the SPI is in master mode (MSTR = 1) and the SS input pin is negated by an external driver. D.7.15 SPI Data Register SPDR — SPI Data Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 UPPB[7:0] RESET: LOWB[7:0] $YFFC3E 1 0 Freescale Semiconductor, Inc... U U U U U U U U U U U U U U U U UPPB — Upper Byte In 16-bit transfer mode, the upper byte contains the most significant eight bits of the transmitted or received data. Bit 15 of the SPDR is the MSB of the 16-bit data. LOWB — Lower Byte In 8-bit transfer mode, the lower byte contains the transmitted or received data. MSB in 8-bit transfer mode is bit 7 of the SPDR. In 16-bit transfer mode, the lower byte holds the least significant eight bits of the data. REGISTER SUMMARY D-66 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.8 General-Purpose Timer Table D-42 GPT Address Map Address1 $YFF900 $YFF902 $YFF904 $YFFE06 $YFF908 $YFF90A $YFF90C 15 87 GPT Module Configuration Register (GPTMCR) GPT Module Test Register (GPTMTR) GPT Interrupt Configuration Register (ICR) Port GP Data Direction Register (DDRGP) Output Compare 1 Action Mask Register (OC1M) Pulse Accumulator Control Register (PACTL) Port GP Data Register (PORTGP) Output Compare 1 Action Data Register (OC1D) Pulse Accumulator Counter Register (PACNT) 0 Timer Counter Register (TCNT) Freescale Semiconductor, Inc... $YFF90E $YFF910 $YFF912 $YFF914 $YFF916 $YFF918 $YFF91A $YFF91C $YFF91E $YFF920 $YFF922 $YFF924 $YFF926 $YFF928 $YFF92A $YFF92C $YFF92E – $YFF93F Timer Input Capture Register 1 (TIC1) Timer Input Capture Register 2 (TIC2) Timer Input Capture Register 3 (TIC3) Timer Output Compare Register 1 (TOC1) Timer Output Compare Register 2 (TOC2) Timer Output Compare Register 3 (TOC3) Timer Output Compare Register 4 (TOC4) Timer Input Capture 4/Output Compare Register 5 (TI4/O5) Timer Control Register 1 (TCTL1) Timer Mask Register 1 (TMSK1) Timer Flag Register 1 (TFLG1) Compare Force Register (CFORC) PWM Control Register A (PWMA) PWM Buffer Register A (PWMBUFA) Timer Control Register 2 (TCTL2) Timer Mask Register 2 (TMSK2) Timer Flag Register 2 (TFLG2) PWM Control Register C (PWMC) PWM Control Register B (PWMB) PWM Buffer Register B (PWMBUFB) PWM Count Register (PWMCNT) GPT Prescaler Register (PRESCL) Reserved NOTES: 1. Y = M111, where M is the logic state of the MM bit in the SIMCR. D.8.1 GPT Module Configuration Register GPTMCR — GPT Module Configuration Register 15 STOP RESET: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 14 FRZ1 13 FRZ0 12 STOPP 11 INCP 10 0 9 0 8 0 7 SUPV 6 0 5 0 4 0 3 2 IARB $YFF900 1 0 The GPTMCR contains parameters for configuring the GPT. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-67 Freescale Semiconductor, Inc. STOP — Stop Clocks 0 = GPT clock operates normally. 1 = GPT clock is stopped. FRZ1 — Not Implemented FRZ0 — FREEZE Assertion Response 0 = Ignore IMB FREEZE signal. 1 = FREEZE the current state of the GPT. STOPP — Stop Prescaler 0 = Normal operation. 1 = Stop prescaler and pulse accumulator from incrementing. Ignore changes to input pins. Freescale Semiconductor, Inc... INCP — Increment Prescaler 0 = Has no effect. 1 = If STOPP is asserted, increment prescaler once and clock input synchronizers once. SUPV — Supervisor/Unrestricted Data Space This bit has no effect because the CPU16 always operates in supervisor mode. IARB[3:0] — Interrupt Arbitration ID The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each module that can generate interrupt requests must be assigned a unique, non-zero IARB field value. D.8.2 GPT Test Register GPTMTR — GPT Module Test Register Used for factory test only. D.8.3 GPT Interrupt Configuration Register ICR — GPT Interrupt Configuration Register 15 14 13 12 11 0 10 9 IPL[2:0] 8 7 6 5 4 3 0 2 0 IPA[3:0] RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IVBA[3:0] $YFF902 $YFF904 1 0 0 0 ICR fields determine internal and external interrupt priority, and provide the upper nibble of the interrupt vector number supplied to the CPU when an interrupt is acknowledged. IPA[3:0] — Interrupt Priority Adjust This field specifies which GPT interrupt source is given highest internal priority. Refer to Table D-43. REGISTER SUMMARY D-68 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table D-43 GPT Interrupt Sources Name — IC1 IC2 IC3 OC1 OC2 OC3 OC4 IC4/OC5 TO Source Number 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Source Adjusted Channel Input Capture 1 Input Capture 2 Input Capture 3 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Input Capture 4/Output Compare 5 Timer Overflow Pulse Accumulator Overflow Pulse Accumulator Input Vector Number IVBA : 0000 IVBA : 0001 IVBA : 0010 IVBA : 0011 IVBA : 0100 IVBA : 0101 IVBA : 0110 IVBA : 0111 IVBA : 1000 IVBA : 1001 IVBA : 1010 IVBA : 1011 Freescale Semiconductor, Inc... PAOV PAI IPL[2:0] — Interrupt Priority Level This field specifies the priority level of interrupts generated by the GPT. IVBA[3:0] — Interrupt Vector Base Address Most significant nibble of interrupt vector numbers generated by the GPT. Refer to Table D-43. D.8.4 Port GP Data Direction Register/Data Register DDRGP/PORTGP — Port GP Data Direction Register/Data Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 DDGP[7:0] RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTGP $YFF906 1 0 When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and PORTGP holds the 8-bit data. DDGP[7:0] — Port GP Data Direction Register 0 = Input only 1 = Output D.8.5 OC1 Action Mask Register/Data Register OC1M/OC1D — OC1 Action Mask Register/OC1 Action Data Register 15 14 13 OC1M[5:1] RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 11 10 0 9 0 8 0 7 6 5 OC1D[5:1] 4 3 2 0 $YFF908 1 0 0 0 All OC outputs can be controlled by the action of OC1. OC1M contains a mask that determines which pins are affected. OC1D determines what the outputs are. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-69 Freescale Semiconductor, Inc. OC1M[5:1] — OC1 Mask Field OC1M[5:1] correspond to OC[5:1]. 0 = Corresponding output compare pin is not affected by OC1 compare. 1 = Corresponding output compare pin is affected by OC1 compare. OC1D[5:1] — OC1 Data Field OC1D[5:1] correspond to OC[5:1]. 0 = If OC1 mask bit is set, clear the corresponding output compare pin on OC1 match. 1 = If OC1 mask bit is set, the set corresponding output compare pin on OC1 match. D.8.6 Timer Counter Register Freescale Semiconductor, Inc... TCNT — Timer Counter Register $YFF90A TCNT is the 16-bit free-running counter associated with the input capture, output compare, and pulse accumulator functions of the GPT module. D.8.7 Pulse Accumulator Control Register/Counter PACTL/PACNT — Pulse Accumulator Control Register/Counter 15 PAIS 14 PAEN 13 12 11 10 I4/O5 9 8 7 6 5 4 3 2 PAMOD PEDGE PCLKS PACLK[1:0] PULSE ACCUMULATOR COUNTER $YFF90C 1 0 RESET: U 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PACTL enables the pulse accumulator and selects either event counting or gated mode. In event counting mode, PACNT is incremented each time an event occurs. In gated mode, it is incremented by an internal clock. PAIS — PAI Pin State (Read Only) PAEN — Pulse Accumulator Enable 0 = Pulse accumulator disabled. 1 = Pulse accumulator enabled. PAMOD — Pulse Accumulator Mode 0 = External event counting. 1 = Gated time accumulation. PEDGE — Pulse Accumulator Edge Control The effects of PAMOD and PEDGE are shown in Table D-44. REGISTER SUMMARY D-70 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. Table D-44 PAMOD and PEDGE Effects PAMOD 0 0 1 1 PEDGE 0 1 0 1 Effect PAI falling edge increments counter PAI rising edge increments counter Zero on PAI inhibits counting One on PAI inhibits counting PCLKS — PCLK Pin State (Read Only) I4/O5 — Input Capture 4/Output Compare 5 0 = Output compare 5 enabled 1 = Input capture 4 enabled Freescale Semiconductor, Inc... PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode) Table D-45 shows the PACLK[1:0] bit field effects. Table D-45 PACLK[1:0] Effects PACLK[1:0] 00 01 10 11 Pulse Accumulator Clock Selected System clock divided by 512 Same clock used to increment TCNT TOF flag from TCNT External clock, PCLK PACNT — Pulse Accumulator Counter Eight-bit read/write counter used for external event counting or gated time accumulation. D.8.8 Input Capture Registers 1–3 TIC[1:3] — Input Capture Registers 1–3 $YFF90E – $YFF912 The input capture registers are 16-bit read-only registers used to latch the value of TCNT when a specified transition is detected on the corresponding input capture pin. They are reset to $FFFF. D.8.9 Output Compare Registers 1–4 TOC[1:4] — Output Compare Registers 1–4 $YFF914 – $YFF91A The output compare registers are 16-bit read/write registers which can be used as output waveform controls or as elapsed time indicators. For output compare functions, they are written to a desired match value and compared against TCNT to control specified pin actions. They are reset to $FFFF. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-71 Freescale Semiconductor, Inc. D.8.10 Input Capture 4/Output Compare 5 Register TI4/O5 — Input Capture 4/Output Compare 5 Register $YFF91C This register serves either as input capture register 4 or output compare register 5, depending on the state of I4/O5 in PACTL. It is reset to $FFFF. D.8.11 Timer Control Registers 1 and 2 TCTL1/TCTL2 — Timer Control Registers 1–2 15 OM5 14 OL5 13 OM4 12 OL4 11 OM3 10 OL3 9 OM2 8 OL2 7 6 5 4 3 2 $YFF91E 1 0 EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... TCTL1 determines output compare mode and output logic level. TCTL2 determines the type of input capture to be performed. OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits Each pair of bits specifies an action to be taken when output comparison is successful. Refer to Table D-46. Table D-46 OM/OL[5:2] Effects OM/OL[5:2] 00 01 10 11 Action Taken Timer disconnected from output logic Toggle OCx output line Clear OCx output line to zero Set OCx output line to one EDGE[4:1] — Input Capture Edge Control Each pair of bits configures input sensing logic for the corresponding input capture. Refer to Table D-47. Table D-47 EDGE[4:1] Effects EDGE[4:1] 00 01 10 11 Configuration Capture disabled Capture on rising edge only Capture on falling edge only Capture on any (rising or falling) edge D.8.12 Timer Interrupt Mask Registers 1 and 2 TMSK1/TMSK2 — Timer Interrupt Mask Registers 1–2 15 I4/O5I RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 ICI[3:1] 8 7 TOI 6 0 5 PAOVI 4 PAII 3 CPROUT 2 OCI[4:1] $YFF920 1 CPR[2:0] 0 REGISTER SUMMARY D-72 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. TMSK1 enables OC and IC interrupts. TMSK2 controls pulse accumulator interrupts and TCNT functions. I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable 0 = IC4/OC5 interrupt disabled. 1 = IC4/OC5 interrupt requested when I4/O5F flag in TFLG1 is set. OCI[4:1] — Output Compare Interrupt Enable OCI[4:1] correspond to OC[4:1]. 0 = OC interrupt disabled. 1 = OC interrupt requested when OC flag set. ICI[3:1] — Input Capture Interrupt Enable ICI[3:1] correspond to IC[3:1]. 0 = IC interrupt disabled. 1 = IC interrupt requested when IC flag set. TOI — Timer Overflow Interrupt Enable 0 = Timer overflow interrupt disabled. 1 = Interrupt requested when TOF flag is set. PAOVI — Pulse Accumulator Overflow Interrupt Enable 0 = Pulse accumulator overflow interrupt disabled. 1 = Interrupt requested when PAOVF flag is set. PAII — Pulse Accumulator Input Interrupt Enable 0 = Pulse accumulator interrupt disabled. 1 = Interrupt requested when PAIF flag is set. CPROUT — Capture/Compare Unit Clock Output Enable 0 = Normal operation for OC1 pin. 1 = TCNT clock driven out OC1 pin. CPR[2:0] — Timer Prescaler/PCLK Select Field This field selects one of seven prescaler taps or PCLK to be TCNT input. Refer to Table D-48. Table D-48 CPR[2:0]/Prescaler Select Field CPR[2:0] 000 001 010 011 100 101 110 111 System Clock Divide-By Factor 4 8 16 32 64 128 256 PCLK Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-73 Freescale Semiconductor, Inc. D.8.13 Timer Interrupt Flag Registers 1 and 2 TFLG1/TFLG2 — Timer Interrupt Flag Registers 1–2 15 I4/O5F RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 ICF[3:1] 8 7 TOF 6 0 5 PAOVF 4 PAIF 3 0 2 0 OCF[4:1] $YFF922 1 0 0 0 These registers show condition flags that correspond to GPT events. If the corresponding interrupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs. I4/O5F — Input Capture 4/Output Compare 5 Flag When I4/O5 in PACTL is zero, this flag is set each time TCNT matches the TOC5 value in TI4/O5. When I4/O5 in PACTL is one, the flag is set each time a selected edge is detected at the I4/O5 pin. OCF[4:1] — Output Compare Flags An output compare flag is set each time TCNT matches the corresponding TOC register. OCF[4:1] correspond to OC[4:1]. ICF[3:1] — Input Capture Flags A flag is set each time a selected edge is detected at the corresponding input capture pin. ICF[3:1] correspond to IC[3:1]. TOF — Timer Overflow Flag This flag is set each time TCNT advances from a value of $FFFF to $0000. PAOVF — Pulse Accumulator Overflow Flag This flag is set each time the pulse accumulator counter advances from a value of $FF to $00. PAIF — Pulse Accumulator Flag In event counting mode, this flag is set when an active edge is detected on the PAI pin. In gated time accumulation mode, it is set at the end of the timed period. D.8.14 Compare Force Register/PWM Control Register C CFORC — Compare Force Register/PWM Control Register 15 FOC RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 10 0 9 FPWMA 8 FPWMB 7 PPROUT 6 PPR 4 3 SFA 2 SFB Freescale Semiconductor, Inc... $YFF924 1 F1A 0 F1B Setting a bit in CFORC causes a specific output on OC or PWM pins. PWMC sets PWM operating conditions. REGISTER SUMMARY D-74 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. FOC[5:1] — Force Output Compare FOC[5:1] correspond to OC[5:1]. 0 = Has no effect. 1 = Causes pin action programmed for corresponding OC pin, but the OC flag is not set. FOC[5:1] correspond to OC[5:1]. FPWMA/B — Force PWM Value 0 = PWM pin A/B is used for PWM functions; normal operation. 1 = PWM pin A/B is used for discrete output. The value of the F1A/B bit will be driven out on the PWMA/B pin. This is true for PWMA regardless of the state of the PPROUT bit. PPROUT — PWM Clock Output Enable 0 = Normal PWM operation on PWMA. 1 = Clock selected by PPR[2:0] is driven out PWMA pin. PPR[2:0] — PWM Prescaler/PCLK Select This field selects one of seven prescaler taps or PCLK to be PWMCNT input. Refer to Table D-49. Table D-49 PPR[2:0] Field PPR[2:0] 000 001 010 011 100 101 110 111 System Clock Divide-By Factor 2 4 8 16 32 64 128 PCLK Freescale Semiconductor, Inc... SFA — PWMA Slow/Fast Select 0 = PWMA period is 256 PWMCNT increments long. 1 = PWMA period is 32768 PWMCNT increments long. SFB — PWMB Slow/Fast Select 0 = PWMB period is 256 PWMCNT increments long. 1 = PWMB period is 32768 PWMCNT increments long. Table D-50 shows a range of PWM output frequencies using 16.78 MHz, 20.97 MHz, and 25.17 MHz system clocks. M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-75 Freescale Semiconductor, Inc. Table D-50 PWM Frequency Ranges PPR [2:0] Prescaler Tap 16.78 MHz Div 2 = 8.39 MHz Div 4 = 4.19 MHz Div 8 = 2.10 MHz 20.97 MHz Div 2 = 10.5 MHz Div 4 = 5.25 MHz Div 8 = 2.62 MHz 25.17 MHz Div 2 = 12.6 MHz Div 4 = 6.29 MHz Div 8 = 3.15 MHz 16.78 MHz 32.8 kHz 16.4 kHz 8.19 kHz 4.09 kHz 2.05 kHz 1.02 kHz 512 Hz SFA/B = 0 20.97 MHz 41 kHz 20.5 kHz 10.2 kHz 5.15 kHz 2.56 kHz 1.28 kHz 641 Hz 25.17 MHz 49.2 kHz 24.6 kHz 12.3 kHz 6.13 kHz 3.07 kHz 1.54 kHz 770 Hz 16.78 MHz 256 Hz 128 Hz 64.0 Hz 32.0 Hz 16.0 Hz 8.0 Hz 4.0 Hz PCLK/32768 SFA/B = 1 20.97 MHz 320 Hz 160 Hz 80.0 Hz 40.0 Hz 20.0 Hz 10.0 Hz 5.0 Hz PCLK/32768 25.17 MHz 384 Hz 192 Hz 96 Hz 48 Hz 24 Hz 12 Hz 6 Hz PCLK/32768 000 001 010 011 100 101 110 111 Div 16 = 1.05 MHz Div 16 = 1.31 MHz Div 16 = 1.57 MHz Div 32 = 524 kHz Div 64 = 262 kHz Div 128 = 131 kHz PCLK Div 32 = 655 kHz Div 64 = 328 kHz Div 128 = 164 kHz PCLK Div 32 = 787 kHz Div 64 = 393 kHz Div 128 = 197 kHz PCLK PCLK/256 PCLK/256 PCLK/256 Freescale Semiconductor, Inc... F1A/B — Force Logic Level One on PWMA/B 0 = Force logic level zero output on PWMA/B pin. 1 = Force logic level one output on PWMA/B pin. D.8.15 PWM Registers A/B PWMA — PWM Register A $YFF926 PWMB — PWM Register B $YFF927 The value in these registers determines pulse width of the corresponding PWM output. A value of $00 corresponds to continuously low output; a value of $80 to 50% duty cycle. Maximum value ($FF) selects an output that is high for 255/256 of the period. Writes to these registers are buffered by PWMBUFA and PWMBUFB. D.8.16 PWM Count Register PWMCNT — PWM Count Register $YFF928 PWMCNT is the 16-bit free-running counter used for GPT PWM functions. D.8.17 PWM Buffer Registers A/B PWMBUFA — PWM Buffer Register A $YFF92A PWMBUFB — PWM Buffer Register B $YFF92B To prevent glitches when PWM duty cycle is changed, the contents of PWMA and PWMB are transferred to these read-only registers at the end of each duty cycle. Reset state is $0000. REGISTER SUMMARY D-76 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. D.8.18 GPT Prescaler PRESCL — GPT Prescaler 15 14 13 12 UNUSED POWER ON RESET ONLY: 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 $YFF92C 1 0 The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always read as zeros. Reset state is $0000. Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL REGISTER SUMMARY For More Information On This Product, Go to: www.freescale.com D-77 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... REGISTER SUMMARY D-78 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. APPENDIX E INITIALIZATION AND PROGRAMMING EXAMPLES This section contains basic initialization programs and several programming exercises using different M68HC16 Z-series modules. The purpose of these exercises is to provide the designer and programmer with a means to shorten design time. All of the programs were written to run on the M68HC16Z1EVB evaluation board. Refer to the M68HC16Z1EVB Evaluation Board User’s Manual (M68HC16Z1EVB/D) for further information. Freescale Semiconductor, Inc... NOTE These programs will also work on the Modular Evaluation Board (MEVB) using a microcontroller personality board for the appropriate Z-series derivative. See APPENDIX C DEVELOPMENT SUPPORT for more information on the MEVB. E.1 Initialization Programs The following initialization routines accompany the programming examples used in this manual. For information on assembler commands and directives, refer to the M68HC16Z1EVB Evaluation Board User’s Manual (M68HC16Z1EVB/D). • EQUATES.ASM — This program lists of all the MC68HC16 registers equated to their memory address. This allows programmers to use the register name in their programs, and then the assembler selects the correct memory address for that register. • ORG00000.ASM — This program consists of five lines of code that set the reset vector information into the proper locations. • ORG00008.ASM — This program initializes the interrupt/exception vectors ($0008 – $01FE). If an interrupt occurs requiring the use of any of these vectors, program flow continues at the label “BDM”. The programmer must add code at the label location to put the program running on the EVB16 into background debug mode or some other appropriate routine. • INITSYS.ASM — This program consists of ten to twelve lines of code that initialize the system clock, set the extension registers, and chip-selects. It also turns off the COP (software watchdog) that is set to “on” after reset. • INITRAM.ASM — This program initializes the 1-Kbyte internal SRAM at $10000, and sets the stack inside it. • INITSCI.ASM — This program initializes the SCI to transmit and receive at 9600 baud. NOTE These programs and others can be obtained from the Freescale web site at http://www.freescale.com M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-1 Freescale Semiconductor, Inc. E.1.1 EQUATES.ASM *DESCRIPTION :THIS IS A TABLE OF EQUATES FOR ALL M68HC16 Z-SERIES * REGISTERS. ************************************************************************** ***** SIM MODULE REGISTERS ***** SIMMCR EQU $FA00 ;SIM MODULE CONFIGURATION REGISTER SIMTR EQU $FA02 ;SYSTEM INTEGRATION TEST REGISTER SYNCR EQU $FA04 ;CLOCK SYNTHESIZER CONTROL REGISTER RSR EQU $FA07 ;RESET STATUS REGISTER SIMTRE EQU $FA08 ;SYSTEM INTEGRATION TEST REGISTER (E CLOCK) PORTE0 EQU $FA11 ;PORTE DATA REGISTER (SAME DATA AS PORTE1) PORTE1 EQU $FA13 ;PORTE DATA REGISTER (SAME DATA AS PORTE0) DDRE EQU $FA15 ;PORTE DATA DIRECTION REGISTER PEPAR EQU $FA17 ;PORTE PIN ASSIGNMENT REGISTER PORTF0 EQU $FA19 ;PORT F DATA REGISTER (SAME DATA AS PORTF1) PORTF1 EQU $FA1B ;PORT F DATA REGISTER (SAME DATA AS PORTF0) DDRF EQU $FA1D ;PORT F DATA DIRECTION REGISTER PFPAR EQU $FA1F ;PORT F PIN ASSIGNMENT REGISTER SYPCR EQU $FA21 ;SYSTEM PROTECTION CONTROL REGISTER PICR EQU $FA22 ;PERIODIC INTERRUPT CONTROL REGISTER PITR EQU $FA24 ;PERIODIC INTERRUPT TIMING REGISTER SWSR EQU $FA27 ;SOFTWARE SERVICE REGISTER TSTMSRA EQU $FA30 ;MASTER SHIFT REGISTER A TSTMSRB EQU $FA32 ;MASTER SHIFT REGISTER B TSTSC EQU $FA34 ;TEST MODULE SHIFT COUNT TSTRC EQU $FA36 ;TEST MODULE REPETITION COUNT CREG EQU $FA38 ;TEST SUBMODULE CONTROL REGISTER DREG EQU $FA3A ;DISTRIBUTED REGISTER CSPDR EQU $FA41 ;PORT C DATA REGISTER CSPAR0 EQU $FA44 ;CHIP-SELECT PIN ASSIGNMENT REGISTER 0 CSPAR1 EQU $FA46 ;CHIP-SELECT PIN ASSIGNMENT REGISTER 1 CSBARBT EQU $FA48 ;CHIP-SELECT BOOT BASE ADDRESS REGISTER CSORBT EQU $FA4A ;CHIP-SELECT BOOT OPTION REGISTER CSBAR0 EQU $FA4C ;CHIP-SELECT 0 BASE ADDRESS REGISTER CSOR0 EQU $FA4E ;CHIP SELECT 0 OPTION REGISTER CSBAR1 EQU $FA50 ;CHIP-SELECT 1 BASE ADDRESS REGISTER CSOR1 EQU $FA52 ;CHIP-SELECT 1 OPTION REGISTER CSBAR2 EQU $FA54 ;CHIP-SELECT 2 BASE ADDRESS REGISTER CSOR2 EQU $FA56 ;CHIP-SELECT 2 OPTION REGISTER CSBAR3 EQU $FA58 ;CHIP-SELECT 3 BASE ADDRESS REGISTER CSOR3 EQU $FA5A ;CHIP-SELECT 3 OPTION REGISTER CSBAR4 EQU $FA5C ;CHIP-SELECT 4 BASE ADDRESS REGISTER CSOR4 EQU $FA5E ;CHIP-SELECT 4 OPTION REGISTER CSBAR5 EQU $FA60 ;CHIP-SELECT 5 BASE ADDRESS REGISTER CSOR5 EQU $FA62 ;CHIP-SELECT 5 OPTION REGISTER CSBAR6 EQU $FA64 ;CHIP-SELECT 6 BASE ADDRESS REGISTER CSOR6 EQU $FA66 ;CHIP-SELECT 6 OPTION REGISTER CSBAR7 EQU $FA68 ;CHIP-SELECT 7 BASE ADDRESS REGISTER CSOR7 EQU $FA6A ;CHIP-SELECT 7 OPTION REGISTER CSBAR8 EQU $FA6C ;CHIP-SELECT 8 BASE ADDRESS REGISTER CSOR8 EQU $FA6E ;CHIP-SELECT 8 OPTION REGISTER CSBAR9 EQU $FA70 ;CHIP-SELECT 9 BASE ADDRESS REGISTER CSOR9 EQU $FA72 ;CHIP-SELECT 9 OPTION REGISTER CSBAR10 EQU $FA74 ;CHIP-SELECT 10 BASE ADDRESS REGISTER CSOR10 EQU $FA76 ;CHIP-SELECT 10 OPTION REGISTER INITIALIZATION AND PROGRAMMING EXAMPLES E-2 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. ***** SRAM MODULE REGISTERS ***** RAMMCR EQU $FB00 ;RAM MODULE CONFIGURATION REGISTER RAMTST EQU $FB02 ;RAM TEST REGISTER RAMBAH EQU $FB04 ;RAM BASE ADDRESS HIGH REGISTER RAMBAL EQU $FB06 ;RAM BASE ADDRESS LOW REGISTER ***** MRM MODULE REGISTERS ***** MRMCR EQU $F820 ;MASKED ROM MODULE CONFIGURATION REGISTER ROMBAH EQU $F824 ;ROM ARRAY BASE ADDRESS REGISTER HIGH ROMBAL EQU $F826 ;ROM ARRAY BASE ADDRESS REGISTER LOW SIGHI EQU $F828 ;SIGNATURE REGISTER HIGH SIGLO EQU $F82A ;SIGNATURE REGISTER LOW ROMBS0 EQU $F830 ;ROM BOOTSTRAP WORD 0 ROMBS1 EQU $F832 ;ROM BOOTSTRAP WORD 1 ROMBS2 EQU $F834 ;ROM BOOTSTRAP WORD 2 ROMBS3 EQU $F836 ;ROM BOOTSTRAP WORD 3 ***** QSM MODULE REGISTERS ***** QMCR EQU $FC00 ;QSM MODULE CONFIGURATION REGISTER QTEST EQU $FC02 ;QSM TEST REGISTER QILR EQU $FC04 ;QSM INTERRUPT LEVELS REGISTER QIVR EQU $FC05 ;QSM INTERRUPT VECTOR REGISTER SCCR0 EQU $FC08 ;SCI CONTROL REGISTER 0 SCCR1 EQU $FC0A ;SCI CONTROL REGISTER 1 SCSR EQU $FC0C ;SCI STATUS REGISTER SCDR EQU $FC0E ;SCI DATA REGISTER (FULL WORD, NOT LAST 8 BITS) QPDR EQU $FC15 ;QSM PORT DATA REGISTER QPAR EQU $FC16 ;QSM PIN ASSIGNMENT REGISTER QDDR EQU $FC17 ;QSM DATA DIRECTION REGISTER SPCR0 EQU $FC18 ;QSPI CONTROL REGISTER 0 SPCR1 EQU $FC1A ;QSPI CONTROL REGISTER 1 SPCR2 EQU $FC1C ;QSPI CONTROL REGISTER 2 SPCR3 EQU $FC1E ;QSPI CONTROL REGISTER 3 SPSR EQU $FC1F ;QSPI STATUS REGISTER RR0 EQU $FD00 ;SPI REC.RAM 0 RR1 EQU $FD02 ;SPI REC.RAM 1 RR2 EQU $FD04 ;SPI REC.RAM 2 RR3 EQU $FD06 ;SPI REC.RAM 3 RR4 EQU $FD08 ;SPI REC.RAM 4 RR5 EQU $FD0A ;SPI REC.RAM 5 RR6 EQU $FD0C ;SPI REC.RAM 6 RR7 EQU $FD0E ;SPI REC.RAM 7 RR8 EQU $FD00 ;SPI REC.RAM 8 RR9 EQU $FD02 ;SPI REC.RAM 9 RRA EQU $FD04 ;SPI REC.RAM A RRB EQU $FD06 ;SPI REC.RAM B RRC EQU $FD08 ;SPI REC.RAM C RRD EQU $FD0A ;SPI REC.RAM D RRE EQU $FD0C ;SPI REC.RAM E RRF EQU $FD0E ;SPI REC.RAM F TR0 EQU $FD20 ;SPI TXD.RAM 0 TR1 EQU $FD22 ;SPI TXD.RAM 1 TR2 EQU $FD24 ;SPI TXD.RAM 2 TR3 EQU $FD26 ;SPI TXD.RAM 3 TR4 EQU $FD28 ;SPI TXD.RAM 4 TR5 EQU $FD2A ;SPI TXD.RAM 5 TR6 EQU $FD2C ;SPI TXD.RAM 6 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-3 Freescale Semiconductor, Inc. TR7 EQU $FD2E ;SPI TXD.RAM 7 TR8 EQU $FD30 ;SPI TXD.RAM 8 TR9 EQU $FD32 ;SPI TXD.RAM 9 TRA EQU $FD34 ;SPI TXD.RAM A TRB EQU $FD36 ;SPI TXD.RAM B TRC EQU $FD38 ;SPI TXD.RAM C TRD EQU $FD3A ;SPI TXD.RAM D TRE EQU $FD3C ;SPI TXD.RAM E TRF EQU $FD3E ;SPI TXD.RAM F CR0 EQU $FD40 ;SPI CMD.RAM 0 CR1 EQU $FD41 ;SPI CMD.RAM 1 CR2 EQU $FD42 ;SPI CMD.RAM 2 CR3 EQU $FD43 ;SPI CMD.RAM 3 CR4 EQU $FD44 ;SPI CMD.RAM 4 CR5 EQU $FD45 ;SPI CMD.RAM 5 CR6 EQU $FD46 ;SPI CMD.RAM 6 CR7 EQU $FD47 ;SPI CMD.RAM 7 CR8 EQU $FD48 ;SPI CMD.RAM 8 CR9 EQU $FD49 ;SPI CMD.RAM 9 CRA EQU $FD4A ;SPI CMD.RAM A CRB EQU $FD4B ;SPI CMD.RAM B CRC EQU $FD4C ;SPI CMD.RAM C CRD EQU $FD4D ;SPI CMD.RAM D CRE EQU $FD4E ;SPI CMD.RAM E CRF EQU $FD4F ;SPI CMD.RAM F ***** MCCI MODULE REGISTERS ***** MMCR EQU $FC00 ;MCCI MODULE CONFIGURATION REGISTER MTEST EQU $FC02 ;MCCI TEST REGISTER ILSCI EQU $FC04 ;SCI INTERRUPT LEVEL REGISTER MIVR EQU $FC05 ;MCCI INTERRUPT VECTOR REGISTER ILSPI EQU $FC06 ;SPI INTERRUPT LEVEL REGISTER MPAR EQU $FC09 ;MCCI PIN ASSIGNMENT REGISTER MDDR EQU $FC0B ;MCCI DATA DIRECTION REGISTER PORTMC EQU $FC0D ;MCCI PORT DATA REGISTER PORTMCP EQU $FC0F ;MCCI PORT PIN STATE REGISTER SCCR0A EQU $FC18 ;SCIA CONTROL REGISTER 0 SCCR1A EQU $FC1A ;SCIA CONTROL REGISTER 1 SCSRA EQU $FC1C ;SCIA STATUS REGISTER SCDRA EQU $FC1E ;SCIA DATA REGISTER SCCR0B EQU $FC28 ;SCIB CONTROL REGISTER 0 SCCR1B EQU $FC2A ;SCIB CONTROL REGISTER 1 SCSRB EQU $FC2C ;SCIB STATUS REGISTER SCDRB EQU $FC2E ;SCIB DATA REGISTER SPCR EQU $FC38 ;SPI CONTROL REGISTER SPSR EQU $FC3C ;SPI STATUS REGISTER SPDR EQU $FC3E ;SPI DATA REGISTER ***** GPT MODULE REGISTERS ***** GPTMCR EQU $F900 ;GPT MODULE CONFIGURATION REGISTER GPTMTR EQU $F902 ;GPT MODULE TEST REGISTER (RESERVED) ICR EQU $F904 ;GPT INTERRUPT CONFIGURATION REGISTER PDDR EQU $F906 ;PARALLEL DATA DIRECTION REGISTER GPTPDR EQU $F907 ;PARALLEL DATA REGISTER OC1M EQU $F908 ;OC1 ACTION MASK REGISTER OC1D EQU $F909 ;OC1 ACTION DATA REGISTER TCNT EQU $F90A ;TIMER COUNTER REGISTER Freescale Semiconductor, Inc... INITIALIZATION AND PROGRAMMING EXAMPLES E-4 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. PACTL EQU $F90C ;PULSE ACCUMULATOR CONTROL REGISTER PACNT EQU $F90D ;PULSE ACCUMULATOR COUNTER TIC1 EQU $F90E ;INPUT CAPTURE REGISTER 1 TIC2 EQU $F910 ;INPUT CAPTURE REGISTER 2 TIC3 EQU $F912 ;INPUT CAPTURE REGISTER 3 TOC1 EQU $F914 ;OUTPUT COMPARE REGISTER 1 TOC2 EQU $F916 ;OUTPUT COMPARE REGISTER 2 TOC3 EQU $F918 ;OUTPUT COMPARE REGISTER 3 TOC4 EQU $F91A ;OUTPUT COMPARE REGISTER 4 TI4O5 EQU $F91C ;INPUT CAPTURE 4 OR OUTPUT COMPARE 5 TCTL1 EQU $F91E ;TIMER CONTROL REGISTER 1 TCTL2 EQU $F91F ;TIMER CONTROL REGISTER 2 TMSK1 EQU $F920 ;TIMER INTERRUPT MASK REGISTER 1 TMSK2 EQU $F921 ;TIMER INTERRUPT MASK REGISTER 2 TFLG1 EQU $F922 ;TIMER INTERRUPT FLAG REGISTER 1 TFLG2 EQU $F923 ;TIMER INTERRUPT FLAG REGISTER 2 CFORC EQU $F924 ;COMPARE FORCE REGISTER PWMC EQU $F924 ;PWM CONTROL REGISTER PWMA EQU $F926 ;PWM REGISTER A PWMB EQU $F927 ;PWM REGISTER B PWMCNT EQU $F928 ;PWM COUNTER REGISTER PWMBUFA EQU $F92A ;PWM BUFFER REGISTER A PWMBUFB EQU $F92B ;PWM BUFFER REGISTER B PRESCL EQU $F92C ;GPT PRESCALER ***** ADC MODULE REGISTERS ***** ADCMCR EQU $F700 ;ADC MODULE CONFIGURATION REGISTER ADTEST EQU $F702 ;ADC TEST REGISTER ADCPDR EQU $F706 ;ADC PORT DATA REGISTER ADCTL0 EQU $F70A ;A/D CONTROL REGISTER 0 ADCTL1 EQU $F70C ;A/D CONTROL REGISTER 1 ADSTAT EQU $F70E ;ADC STATUS REGISTER RJURR0 EQU $F710 ;RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 0 RJURR1 EQU $F712 ;RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 1 RJURR2 EQU $F714 ;RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 2 RJURR3 EQU $F716 ;RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 3 RJURR4 EQU $F718 ;RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 4 RJURR5 EQU $F71A ;RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 5 RJURR6 EQU $F71C ;RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 6 RJURR7 EQU $F71E ;RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 7 LJSRR0 EQU $F720 ;LEFT JUSTIFIED SIGNED RESULT REGISTER 0 LJSRR1 EQU $F722 ;LEFT JUSTIFIED SIGNED RESULT REGISTER 1 LJSRR2 EQU $F724 ;LEFT JUSTIFIED SIGNED RESULT REGISTER 2 LJSRR3 EQU $F726 ;LEFT JUSTIFIED SIGNED RESULT REGISTER 3 LJSRR4 EQU $F728 ;LEFT JUSTIFIED SIGNED RESULT REGISTER 4 LJSRR5 EQU $F72A ;LEFT JUSTIFIED SIGNED RESULT REGISTER 5 LJSRR6 EQU $F72C ;LEFT JUSTIFIED SIGNED RESULT REGISTER 6 LJSRR7 EQU $F72E ;LEFT JUSTIFIED SIGNED RESULT REGISTER 7 LJURR0 EQU $F730 ;LEFT JUSTIFIED UNSIGNED RESULT REGISTER 0 LJURR1 EQU $F732 ;LEFT JUSTIFIED UNSIGNED RESULT REGISTER 1 LJURR2 EQU $F734 ;LEFT JUSTIFIED UNSIGNED RESULT REGISTER 2 LJURR3 EQU $F736 ;LEFT JUSTIFIED UNSIGNED RESULT REGISTER 3 LJURR4 EQU $F738 ;LEFT JUSTIFIED UNSIGNED RESULT REGISTER 4 LJURR5 EQU $F73A ;LEFT JUSTIFIED UNSIGNED RESULT REGISTER 5 LJURR6 EQU $F73C ;LEFT JUSTIFIED UNSIGNED RESULT REGISTER 6 LJURR7 EQU $F73E ;LEFT JUSTIFIED UNSIGNED RESULT REGISTER 7 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-5 Freescale Semiconductor, Inc. E.1.2 ORG00000.ASM * Title : ORG00000 * Description : This file is included to set up the reset * vector ($00000 - $00006). * **************************************************************************** ORG $0000 ;put the following reset vector ;information ;at address $00000 of the memory map ;zk=0, sk=1, pk=0 ;pc=200 -- initial program counter ;sp=03fe -- initial stack pointer ;iz=0 -- direct page pointer DC.W DC.W DC.W DC.W $0010 $0200 $03FE $0000 Freescale Semiconductor, Inc... E.1.3 ORG00008.ASM * Title : ORG00008 * Description : This file initializes the interrupt/ * exception vectors ($0008 - $01fe). * If an interrupt occurs requiring the use of * any of these vectors, program flow will * continue at the label “bdm” which must be * added by the programmer to his/her code to * put the program into background debug mode * or some other appropriate routine. * ********************************************************************* ORG $0008 ;put the following code in memory ;starting at address $0008 of the map ;(after the reset vector). ;there is a total of 252 of these ;”DC.W BDM” lines ;Vector Number (in base 10) ;and Vector Description DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM ;4 ;5 ;6 ;7 ;8 ;9 ;10 ;11 ;12 ;13 ;14 ;15 ;16 ;17 ;18 ;19 ;20 Breakpoint (BKPT) Bus Error (BERR) Software Interrupt (SWI) Illegal Instruction Divide by Zero (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) Uninitialized Interrupt (Unassigned Reserved) Level 1 Interrupt Autovector Level 2 Interrupt Autovector Level 3 Interrupt Autovector Level 4 Interrupt Autovector M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES E-6 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM ;21 ;22 ;23 ;24 ;25 ;26 ;27 ;28 ;29 ;30 ;31 ;32 ;33 ;34 ;35 ;36 ;37 ;38 ;39 ;40 ;41 ;42 ;43 ;44 ;45 ;46 ;47 ;48 ;49 ;50 ;51 ;52 ;53 ;54 ;55 ;56 ;57 ;58 ;59 ;60 ;61 ;62 ;63 ;64 ;65 ;66 ;67 ;68 ;69 ;70 ;71 ;72 ;73 ;74 ;75 Level 5 Interrupt Autovector Level 6 Interrupt Autovector Level 7 Interrupt Autovector Spurious Interrupt (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) (Unassigned Reserved) User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector User Defined Interrupt Vector Freescale Semiconductor, Inc... 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-7 Freescale Semiconductor, Inc. DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM ;76 ;77 ;78 ;79 ;80 ;81 ;82 ;83 ;84 ;85 ;86 ;87 ;88 ;89 ;90 ;91 ;92 ;93 ;94 ;95 ;96 ;97 ;98 ;99 ;100 ;101 ;102 ;103 ;104 ;105 ;106 ;107 ;108 ;109 ;100 ;111 ;112 ;113 ;114 ;115 ;116 ;117 ;118 ;119 ;120 ;121 ;122 ;123 ;124 ;125 ;126 ;127 ;128 ;129 ;130 User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Freescale Semiconductor, Inc... INITIALIZATION AND PROGRAMMING EXAMPLES E-8 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM ;131 ;132 ;133 ;134 ;135 ;136 ;137 ;138 ;139 ;140 ;141 ;142 ;143 ;144 ;145 ;146 ;147 ;148 ;149 ;150 ;151 ;152 ;153 ;154 ;155 ;156 ;157 ;158 ;159 ;160 ;161 ;162 ;163 ;164 ;165 ;166 ;167 ;168 ;169 ;170 ;171 ;172 ;173 ;174 ;175 ;176 ;177 ;178 ;179 ;180 ;181 ;182 ;183 ;184 ;185 User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Freescale Semiconductor, Inc... M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-9 Freescale Semiconductor, Inc. DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM ;186 ;187 ;188 ;189 ;190 ;191 ;192 ;193 ;194 ;195 ;196 ;197 ;198 ;199 ;200 ;201 ;202 ;203 ;204 ;205 ;206 ;207 ;208 ;209 ;210 ;211 ;212 ;213 ;214 ;215 ;216 ;217 ;218 ;219 ;220 ;221 ;222 ;223 ;224 ;225 ;226 ;227 ;228 ;229 ;230 ;231 ;232 ;233 ;234 ;235 ;236 ;237 ;238 ;239 ;240 User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User User Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 Freescale Semiconductor, Inc... INITIALIZATION AND PROGRAMMING EXAMPLES E-10 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM ;241 ;242 ;243 ;244 ;245 ;246 ;247 ;248 ;249 ;250 ;251 ;252 ;253 ;254 ;255 User User User User User User User User User User User User User User User Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector Vector 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Freescale Semiconductor, Inc... E.1.4 INITSYS.ASM * Title : INITSYS * Description : Initialize & configure system including * the Software Watchdog and System Clock. **************************************************************************** INITSYS: LDAB TBEK LDAB TBXK TBYK TBZK LDD STD LDD STD LDAA STAA CLR #$0F ; point EK to bank F for register access #$00 ; point XK to bank 0 ; point YK to bank 0 ; point ZK to bank 0 #$0003 ; at reset, the CSBOOT block size is 512k. CSBARBT ; this line sets the block size to 64k #$3830; async, both byte, R/W, AS, Zero WS, S/U SP, IPL all, ;AVEC off CSORBT ; #$7F ; w=0, x=1, y=111111 SYNCR ; set system clock to 16.78 Mhz SYPCR ; turn COP (software watchdog) off, ; since COP is on after reset ;give initial values for extension registers ;and initialize system clock and COP E.1.5 INITRAM.ASM * Title : INITRAM * Description : Initialize the HC16's 1K internal SRAM * (put SRAM in memory map at $10000, bank 1) * and set the stack inside it. ***************************************************************************** INITRAM: LDD STD LDD M68HC16 Z SERIES USER’S MANUAL #$0001 RAMBAH #$0000 ;initialize internal SRAM and stack ; store high ram array, bank 1 INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-11 Freescale Semiconductor, Inc. STD CLR LDAB TBSK LDS RAMBAL RAMMCR #$01 #$03FE ; set SK to bank 1 for system stack ; put SP at top of 1k internal SRAM ; store low ram array ; enable ram E.1.6 INITSCI.ASM * Title : INITSCI * Description : Initialize the SCI to transmit and receive * at 9600 baud. * ************************************************************************* Freescale Semiconductor, Inc... INITSCI: LDD STD LDD STD #$0037 SCCR0 #$000C SCCR1 ;initialize the SCI ;set the SCI baud rate to 9600 baud ;enable the SCI receiver and transmitter E.2 Programming Examples The following programming examples use different M68HC16 Z-series modules. All programs were written to run on the M68HC16Z1EVB evaluation board. Refer to the M68HC16Z1EVB Evaluation Board User’s Manual (M68HC16Z1EVB/D) for further information. NOTE These programs will also work on the modular evaluation board (MEVB) using a microcontroller personality board for the appropriate Z-series derivative. See APPENDIX C DEVELOPMENT SUPPORT for more information on the MEVB. Several of these programs send status messages using the SCI in the QSM on the MC68HC16Z1, MC68CK16Z1, MC68CM16Z1, MC68HC16Z2, and MC68HC16Z3. These programs can be made to function with SCIA in the MCCI on the MC68HC16Z4 and MC68CKZ4 as follows: • Replace SCCR0 with SCCR0A. • Replace SCCR1 with SCCR1A. • Replace SCSR with SCSRA. • Replace SCDR with SCDRA. INITIALIZATION AND PROGRAMMING EXAMPLES E-12 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. E.2.1 SIM Programming Examples The following programming examples involve using the system integration module (SIM). The programs include: • Using ports E and F. • Setting up U1 and U3 RAM slots with two 32K X 8 RAM chips using chip selects. • Demonstrating the ability of the M68HC16 to change clock frequencies on the fly. • Demonstrating the software watchdog, the periodic interrupt, and an autovector. Refer to SECTION 5 SYSTEM INTEGRATION MODULE for more information on the SIM. E.2.1.1 Example 1 - Using Ports E and F Freescale Semiconductor, Inc... * * * * * * * * * * ************************************************************************* INCLUDE INCLUDE INCLUDE ORG 'EQUATES.ASM' 'ORG00000.ASM' 'ORG00008.ASM' $00200 ;table of EQUates for common register ;addresses ;initialize reset vector ;initialize exception vectors ;start program right after exception ;vectors Description : This program demonstrates a simple I/O usage of Ports E and F with a loop that will load Port E with a number, pass that number over to Port F through a hardwire of the M68HC16Z1EVB, and then read that number from the Port F data register. Port E will be incremented each loop. The hardwire of the M68HC16Z1EVB is from DSACK0 to MODCLK, from DSACK1 to IRQ1, and from AVEC to IRQ2. The numbers start at #$00 and go to #$07. ***** Initialize INCLUDE INCLUDE ***** 'INITSYS.ASM' 'INITRAM.ASM' ;initially set EK=F, XK=0, YK=0, ZK=0 ;set sys clock at 16.78MHz, disable COP ;turn on internal SRAM at $10000 ;set stack in bank 1 (SK=1, SP=03FE) LDAB #$00 STAB PEPAR STAB PFPAR LDAB #$00 STAB PORTE0 STAB PORTF0 LDAB #$FF STAB DDRE LDAB #$FF ;define the Port E pins as I/O pins ;define the Port F pins as I/O pins ;clear the Port E data register ;clear the Port F data register ;initialize Port E pins as outputs ;note that Port E pin 3 does not exist! M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-13 Freescale Semiconductor, Inc. STAB DDRF LDAB #$01 LDAA #$00 ***** START: Main Loop ***** ;store counter into Port E data register ;load A register with Port F data register ;go back and start the counting again at zero ***** ;exception vectors point here ;and will put user into background mode ;Port F pins 0-7 as outputs (force 3-7 to 0) STAB PORTF0 STAA PORTF0 BRA START ***** Exceptions/Interrupts BDM: BGND Freescale Semiconductor, Inc... E.2.1.2 Example 2 - Using Chip-Selects * Description : Demo of how to set up the U1 and U3 RAM slots with * two 32Kx8 RAM chips using the Chip Selects. The new * memory will start at address $30000 and will be both * byte and word readable/writable. * This program assumes that the RAM to be installed * (such as MCM60L256AP85 or MCM6206P85) have * access times of 85 ns and require no wait states. * The DSACK field of the Chip Select Option Registers * may need to be adjusted for chips that have faster or * slower access times. **************************************************************************** INCLUDE addresses INCLUDE INCLUDE ORG ***** INIT: INCLUDE COP INCLUDE INCLUDE 'INITRAM.ASM' 'INITSCI.ASM' ;turn on 1k internal SRAM at $10000 ;set stack in bank 1 (SK=1, SP=03FE) ;set SCI baud rate at 9600 baud ;enable SCI transmitter and receiver 'EQUATES.ASM' 'ORG00000.ASM' 'ORG00008.ASM' $0200 ***** ;Initialization stuff..... 'INITSYS.ASM' ;initially set EK=F, XK=0, YK=0, ZK=0 ;set sys clock at 16.78 MHz, disable ;table of EQUates for common register ;initialize reset vector ;initialize exception vector table ;start program right after vector table Initialization CSINIT: LDD STD STD LDD STD #$0303 CSBAR0 CSBAR1 #$5030 CSOR0 ;Initialize the Chip Selects..... ;set U1 RAM base addr to $30000: bank 3, 64k ;set U3 RAM base addr to $30000: bank 3, 64k ;set Chip Select 0, upper byte, write only INITIALIZATION AND PROGRAMMING EXAMPLES E-14 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. LDD STD LDD STD LDD STD LDD STD ***** MAIN: LDAB TBXK LDX LDAB TBZK LDZ XLOOP: LDD STD AIX AIZ CMPA BEQ CMPB BNE PRINT: LDAB TBXK LDX JSR BRA ***** #$03 #$0000 SEND_STRING PRINT ***** ;subroutine to send out the entire ASCII ;string ;get next char in string as pointed to by IX ;if B=00, then message is done ;go send out a character ;increment IX to point to the next ASCII char ;loop back ;go back to whence we came ;subroutine to send out one character at a LDAA ANDA SCSR #01 ;read the SCI status reg to check TDRE bit ;check only the tdre flag bit ;set XK:IX index to point to bank 3 ;point to the beginning of the ASCII string ;go output the ASCII string ;loop back and print again #$00 #STRING #$03 #0000 0,X 0,Z #2 #2 #$00 PRINT #$00 XLOOP ;set XK to bank 0 for access to the STRING ;load the starting address of STRING into IX ;set ZK to bank 3 ;for access to U1 & U3 during write in XLOOP ;clear IZ so ZK:IZ = $30000 ;load two bytes from $10000 into accum. D ;store accum. D into U1 and U3 RAM: ;the chip select logic takes care of us! ;increment X index register to next word ;increment Z index register to next word ;end xloop if the end of the string $00 is ;detected in either accumulator A or B #$3030 CSOR1 #$0303 CSBAR2 #$7830 CSOR2 #$3FFF CSPAR0 ***** ;Move data from another place in memory ;into the U1 and U3 RAM slots..... ;set Chip Select 1, lower byte, write only ;set Chip Select 2 to fire at base addr $30000 ;set Chip Select 2, both bytes, read and write ;set Chip Selects 0,1,2 to 16-bit ports The Main Program Freescale Semiconductor, Inc... ;This loop reads its string from the U1 and U3 ;slots and prints it at the dummy terminal.... Subroutines SEND_STRING: LDAB BEQ JSR AIX BRA STRING_DONE: RTS SEND_CH: time 0,X STRING_DONE SEND_CH #1 SEND_STRING M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-15 Freescale Semiconductor, Inc. BEQ again CLRA STD TC_LOOP: LDAB ANDB BEQ RTS ***** BDM: Exceptions/Interrupts BGND SCSR+1 #$80 TC_LOOP ;test the TC bit (transfer complete) ;continue to wait until TC is set ;finish sending out one character ***** ;exception vectors point here ;and put the user in background mode ***** SCDR ;transmit one ASCII character to the screen SEND_CH ;if TDR is not empty, go back to check it Freescale Semiconductor, Inc... ***** The string ORG $0310 STRING DC 'I LIKE MY NEW MEMORY!!!',0A,0D,00 E.2.1.3 Example 3 - Changing Clock Frequencies * Description : This program demonstrates the ability of the * M68HC16 to change clock frequencies on the fly. * In this particular case, we alternate between * a frequency of 16.78MHz and 4.194MHz. Note * that because we are writing to the screen, * we also need to correct the BAUD rate (1200) * each time we change the frequency. Make sure * that your terminal has been set up to receive * at 1200 baud. An oscilloscope may be connected * to the CLKOUT pin on the EVB to observe the * frequency change. *************************************************************************** INCLUDE INCLUDE INCLUDE ORG 'EQUATES.ASM' 'ORG00000.ASM' 'ORG00008.ASM' $0200 ;table of EQUates for common registers ;initialize reset vectors ;initialize interrupt vectors ;start program after the exception ;vector table ***** INIT: Initialize ***** INCLUDE COP INCLUDE 'INITSYS.ASM' ;initially set EK=F, XK=0, YK=0, ZK=0 ;set sys clock at 16.78 MHz, disable ;turn on internal 1K SRAM at $10000 ;set stack in bank 1 (SK=1, SP=03FE) 'INITRAM.ASM' LDD #$000C INITIALIZATION AND PROGRAMMING EXAMPLES E-16 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. STD LDAB TBZK LDZ CNT DLY ***** MAIN: NOT_L: EQU EQU SCCR1 #$01 #$0000 $0000 $0002 ***** ;point ZK at bank 1 (the SRAM) ;for indexing the variables CNT and DLY ;loop counter ;delay counter ;enable SCI receiver and transmitter Main Program LDAB STAB BRCLR LDD STD JSR LDX JSR LDAB STAB LDX JSR DEC BNE LDAB STAB BRCLR LDD STD JSR LDX JSR LDAB STAB LDX JSR DEC BNE LBRA Freescale Semiconductor, Inc... LOOP1: #$7F ;set clock speed to 16.777MHz SYNCR ;w=0, x=1, y=111111 SYNCR+1,#8,NOT_L ;wait until synthesizer lock bit is set #$01B5 SCCR0 ;set baud rate to 1200 DELAY ;delay for modulus counter of SCI to flush #STRING ;load address of string into IX SEND_STRING ;subroutine to send string to dummy terminal #$05 ;set up loop counter CNT,Z #SEC_STR ;load address of string into IX SEND_STRING ;subroutine to send string to dummy terminal CNT,Z ;decrement loop counter LOOP1 ;loop 5 times #$4F ;change clock frequency to 4.194MHz SYNCR ;w=0, x=1, y=001111 SYNCR+1,#8,LOOP2 ;wait until synthesizer lock bit is set #$006D SCCR0 ;set BAUD rate back to 1200 DELAY ;delay for modulus counter of SCI to flush #STRING2 ;load address of string into IX SEND_STRING ;subroutine to send string to dummy terminal #$05 ;set up # of loops for loop counter to 5 CNT,Z #SEC_STR ;load address of string into IX SEND_STRING ;subroutine to send string to dummy terminal CNT,Z ;decrement loop counter LOOP3 ;loop 5 times MAIN ***** ;delay loop ;branch back to main LOOP2: LOOP3: ***** DELAY: LOOP4: Subroutines LDD STD DEC BNE RTS #$FFFF DLY,Z DLY,Z LOOP4 SEND_STRING: LDAB BEQ 0,X STRING_DONE ;subroutine to send out the entire ASCII ;string ;get next byte in string as pointed to by IX ;if B=00, then message is done M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-17 Freescale Semiconductor, Inc. JSR AIX BRA STRING_DONE: JSR RTS SEND_CH: LDAA ANDA BEQ LDAA STD LDAB ANDB BEQ RTS SCSR #$01 SEND_CH #$00 SCDR SCSR+1 #$80 LOOP5 SEND_CH #$01 SEND_STRING DELAY ;go send out the byte ;increment IX to point to the next byte ;loop back and do next byte in string ;wait for a moment ;go back to whence we came ;subroutine to send out one byte to SCI ;read SCI status reg to check/clear TDRE bit ;check only the TDRE flag bit ;if TDR is not empty, go back to check it ;again ;clear A to send a full word to SCDR ($FFC0E) ;transmit one ASCII character to the screen ;test the TC bit (transfer complete) ;continue to wait until TC is set ;return to send_string subroutine LOOP5: Freescale Semiconductor, Inc... ***** The STRINGs ***** STRING DC SEC_STR DC STRING2 DC 'The System Clock is now running at 16.777 MHz...',0a,0d,00 'check this out!',0a,0d,00,00 'The System Clock is now running at 4.194 MHz...',0a,0d,00 ***** BDM: Interrupts/Exceptions BGND ***** ;exception vectors point here ;and put the user into background debug mode E.2.1.4 Example 4 - Software Watchdog, Periodic Interrupt, and Autovector Demo * Description : This program demonstrates the software watchdog, * the periodic interrupt, and an autovector. * The periodic interrupt runs a clock which is updated * on the dummy terminal. Every eight seconds the COP * will force a reset unless IRQ6 is grounded. When IRQ6 * is pulled low, an autovectored interrupt routine will * “feed” the watchdog with $55 and $AA, and the * clock will run without being reset on the dummy terminal. * ********************************************************************* INCLUDE INCLUDE INCLUDE 'EQUATES.ASM' 'ORG00000.ASM' 'ORG00008.ASM' ;table of EQUates for common registers ;initialize reset vectors ;initialize interrupt vectors ORG DC.W ORG DC.W $002C AUTOV $0070 VECRT ;put address of autovector routine ;at the level 6 vector (IRQ6) ;put address of periodic interrupt routine ;at 1st user defined interrupt vector INITIALIZATION AND PROGRAMMING EXAMPLES E-18 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. ORG $0200 ;start program after interrupt table ***** INIT: TEMP SCCNT MNCNT HRCNT Initialize ***** ;initialization stuff EQU EQU EQU EQU $0006 $0004 $0002 $0000 ;variable space used in hex to asc routine ;stores the current number of seconds ;stores the current number of minutes ;stores the current number of hours ;The following section is normally part of ;INCLUDE 'INITSYS.ASM', but we want to ;leave the COP on. INITSYS: Freescale Semiconductor, Inc... LDAB TBEK LDAB TBXK TBYK TBZK LDD STD LDAA STAA LDAB STAB #$0F ;point EK to bank F for register access #$00 ;point XK to bank 0 ;point YK to bank 0 ;point ZK to bank 0 ;initialize the SIM MCR ;this is redundant; it happens at reset ;set system clock to 16.78 Mhz ;enable the watchdog (COP) ;and set time-out period to 8 seconds 'INITRAM.ASM' 'INITSCI.ASM' ;turn on internal SRAM at $10000 ;set stack in bank 1 (SK=1, SP=03FE) ;set SCI baud rate at 9600 baud ;enable SCI transmitter and receiver #$00CF SIMMCR #$7F SYNCR #$C0 SYPCR INCLUDE INCLUDE LDD STD LDD STD LDD STD LDD Autovector: STD LDAB STAB LDAB TBZK LDZ LDD STD STD STD STD LDAB #$0638 PICR #$0110 PITR #$FFF9 CSBAR3 #$7801 CSOR3 #$FF PFPAR #$01 #$0000 #$0000 SCCNT,Z MNCNT,Z HRCNT,Z TEMP,Z RSR ;set the periodic interrupt at request level 6 ;& assign vector #56 (address $00070) to it ;initialize ;initialize ;on an IACK ;initialize PITR to interrupt every 1 sec Chip Sel Base Reg for Autovector cycle: A24-A11=$FFF8, blK_sz = 8K Chip Sel Option Reg for ;asynchronous, any Interrupt Priority Level ;set port F pins to be IRQ pins ;this is redundant: it happens at reset ;set zk nibble to bank 1 for variable access ;index those variables from $10000 ;clear sccnt register ;clear mncnt register ;clear hrcnt register ;clear “save” variable space ;find out who caused the last reset M68HC16 Z SERIES USER’S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product, Go to: www.freescale.com E-19 Freescale Semiconductor, Inc. CMPB BNE LDX BRA NO_DOG: LDX PRINT: JSR ANDP #$20 NO_DOG #DOG_STRING PRINT #NO_DOG_STR SEND_STRING #$FF1F ;choose which string start address to load ;COP caused the reset ;COP did not cause the reset ;print the string to the screen ;set interrupt priority mask level to 0 ***** MAIN: The Main Program NOP BRA ***** MAIN ***** Freescale Semiconductor, Inc... ;keep on looping until watchdog causes a reset ;or we get some other interrupt ***** Subroutines SEND_STRING: string LDAB BEQ JSR AIX BRA STRING_DONE: RTS SEND_CH: LDAA ANDA BEQ again LDAA STD TC_LOOP: LDAB ANDB BEQ RTS ***** ;subroutine to send out the entire ASCII 0,X STRING_DONE SEND_CH #$01 SEND_STRING ;get next byte in string as pointed to by IX ;if B=00, then we're done ;go send out the byte ;increment IX to point to the next byte ;loop back and do next byte in string ;go back to whence we came ;subroutine to send out one byte to SCI ;read SCI status reg to check/clear TDRE bit ;check only the TDRE flag bit ;if TDR is not empty, go back to check it ;clear A to send a full word to SCDR ($FFC0E) ;transmit one ASCII character to the screen SCSR #$01 SEND_CH #$00 SCDR SCSR+1 #$80 TC_LOOP ;test the TC bit (transfer complete) ;continue to wait until TC is set ;finish sending out byte The STRINGs ***** DOG_STRING DC 'The Software Watchdog just caused a reset!',0a,0d,00 NO_DOG_STR DC 'The last reset was not caused by the COP.',0a,0d,00 AUTOV_STRING DC 'Feeding the dog...',0a,0d,00 ***** VECRT: Periodic Interrupt Vector Routine ***** SECONDS: ;When the processor is interrupted by the ;periodic timer, it will run this routine. ;This routine simply increments a clock ;every time it is interrupted, and prints ;the clock out on the dummy terminal. ;advance the counter for seconds INITIALIZATION AND PROGRAMMING EXAMPLES E-20 For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL Freescale Semiconductor, Inc. LDAA ADDA DAA CMPA BEQ STD JSR RTI MINUTES: CLR LDAA ADDA DAA CMPA BEQ STD JSR RTI HOURS: CLR LDAA ADDA DAA STD CMPA BNE CLR RETURN: JSR RTI ***** MNCNT,Z HRCNT,Z #$01 HRCNT,Z #$24 RETURN HRCNT,Z DISPLAY SCCNT,Z MNCNT,Z #$01 #$60 HOURS MNCNT,Z DISPLAY SCCNT,Z #$01 #$60 MINUTES SCCNT,Z DISPLAY ;increment # of seconds ;decimal adjust A ;compare # of seconds to 60 ;if # of sec=60, then branch to minute routine ;if # of sec