FT313HQ-T

FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 Future Technology Devices International Ltd. FT313H (USB2.0 Host Controller) The FT313H is a Hi-Speed Universal Serial Bus (USB) Host Controller compatible with Universal Serial Bus Specification Rev 2.0 and supports data transfer speeds of up to 480M bit/s. The FT313H has the following advanced features:  Single chip USB2.0 Hi-Speed compatible.  Compatible to Enhanced Host Interface Specification Rev 1.0.  The USB1.1 host is integrated into the USB2.0 EHCI compatible host controller.  Single USB host port.  Supports data transfer at high-speed (480M bit/s), full-speed (12M bit/s), and low-speed (1.5M bit/s).  Supports the Isochronous, Interrupt, Control, and Bulk transfers.  Supports the split transaction for high-speed Hub and the preamble transaction for fullspeed Hub.  Supports multiple processor interfaces with 8bit or 16-bit bus: SRAM, NOR Flash, and General multiplex.  Single configurable interrupt (INT) line for host controller.  Integrated 24kB high speed RAM memory.  Supports DMA operation.  Integrated Phase-Locked Loop (PLL) supports external 12MHz, 19.2MHz, and 24MHz crystal, and direct external clock source input. Controller  Low power application. consumption for  Supports bus interface I/O voltage from 1.62V to 3.63V.  Supports hybrid power mode; VCC(3V3) is not present, VCC(I/O) is powered.  Internal voltage regulator supplies 1.2v to the digital core.  Supports Battery Charging Specification Rev 1.2.  The downstream port can be configured as SDP, CDP or DCP.  Supports VBUS power current control.  -40°C to 85°C extended operating temperature range.  Available in compact Pb-free 64 Pin QFN, LQFP and TQFP packages (all RoHS compliant). switching portable and over Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or fa ilure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640 Copyright © Future Technology Devices International Limited 1 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 1 Typical Applications    TV/TV box Printer Instrumentation    Media player Tablet Set-top box 1.1 Part Numbers Part Number FT313HQ-x FT313HL-x FT313HP-x Package 64 Pin QFN 64 Pin LQFP 64 Pin TQFP Table 1-1 FT313H Numbers Note: Packaging codes for x is: -R: Taped and Reel, (QFN is 3000pcs, LQFP is 1000 pcs, TQFP is 2500pcs per reel) -T: Tray packing, (QFN is 2600pcs, LQFP is 1600 pcs, TQFP is 2500pcs per tray) For example: FT313HQ-R is 3000 QFN pcs in taped and reel packaging 1.1 USB Compliant The FT313H is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID) 120000254. Copyright © Future Technology Devices International Limited 2 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 2 FT313H Block Diagram DMA Controller AD[15:0] VCC(I/O) RAM 24KB A[7:0] X1/CLKIN ALE/ADV_N X2 MEMORY ARBITER CLE CS_N/CE_N RD_N/RE_N/ OE_N FT313H Interface Control Logic PLL FREQSEL2 AGND EHCI Compatible Host Controller WR_N/WE_N POR RESET_N INT GND DREQ ATX DACK REGULATOR VBUS CPE0 CPE1 FREQSEL1 VCC(1V2) VOUT(1V2) TESTEN BCD VCC(3V3) OC_N RREF DP DM AGND PSW_N Figure 2-1 FT313H Block Diagram For a description of each function please refer to Section 4 Function Description. Copyright © Future Technology Devices International Limited 3 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 Table of Contents 1 Typical Applications....................................................... 2 1.1 Part Numbers ............................................................................. 2 1.1 USB Compliant ........................................................................... 2 2 FT313H Block Diagram .................................................. 3 3 Device Pin Out and Signal Description ........................... 7 3.1 Pin Out – 64pin QFN................................................................... 7 3.2 Pin Out – 64pin LQFP ................................................................. 8 3.3 Pin Out – 64pin TQFP ................................................................. 9 3.4 Pin Description ........................................................................ 10 4 Function Description ................................................... 13 4.1 Microcontroller Bus Interface .................................................. 13 4.2 SRAM bus interface mode ........................................................ 14 4.3 NOR bus interface mode .......................................................... 15 4.4 General multiplex bus interface mode...................................... 15 4.5 Interface mode lock ................................................................. 15 4.6 DMA controller ......................................................................... 15 4.7 EHCI host controller ................................................................. 16 4.8 System clock ............................................................................ 16 4.8.1 4.9 Phase Locked Loop (PLL) clock multiplier ...................................................... 16 Power management ................................................................. 16 4.9.1 Power up and reset sequence ..................................................................... 16 4.9.2 Power supply ............................................................................................ 17 4.9.3 ATX reference voltage ................................................................................ 17 4.9.4 Power modes ............................................................................................ 17 4.10 5 BCD mode .............................................................................. 17 Host controller specific registers ................................. 19 5.1 Overview of registers ............................................................... 19 5.2 EHCI operational registers ....................................................... 19 5.2.1 HCCAPLENGTH register (address = 00h) ...................................................... 19 5.2.2 HCSPARAMS register (address = 04h) ......................................................... 20 5.2.3 HCCPARAMS register (address = 08h) ......................................................... 20 5.2.4 USBCMD register (address = 10h) ............................................................... 20 5.2.5 USBSTS register (address = 14h)................................................................ 22 5.2.6 USBINTR register (address = 18h) .............................................................. 23 Copyright © Future Technology Devices International Limited 4 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 5.2.7 FRINDEX register (address = 1Ch) .............................................................. 24 5.2.8 PERIODICLISTADDR register (address = 24h) .............................................. 24 5.2.9 ASYNCLISTADDR register (address = 28h) ................................................... 24 5.2.10 POSTSC register (address = 30h) ................................................................ 24 5.3 Configuration registers ............................................................ 26 5.3.1 5.4 EOTTIME register (address = 34h) .............................................................. 26 CHIPID register (address = 80h) ............................................. 28 5.4.1 HWMODE register (address = 84h) .............................................................. 28 5.4.2 EDGEINTC register (address = 88h) ............................................................ 29 5.4.3 SWRESET register (address = 8Ch) ............................................................. 29 5.4.4 MEMADDR register (address = 90h) ............................................................ 30 5.4.5 DATAPORT register (address = 92h) ............................................................ 30 5.4.6 DATASESSION register (address = 94h) ...................................................... 30 5.4.7 CONFIG register (address = 96h) ................................................................ 30 5.4.8 AUX_MEMADDR register (address = 98h) ..................................................... 31 5.4.9 AUX_DATAPORT register (address = 9Ah) .................................................... 31 5.4.10 SLEEPTIMER register (address = 9Ch) ......................................................... 31 5.5 Interrupt registers ................................................................... 32 5.5.1 HCINTSTS register (address = A0h) ............................................................ 32 5.5.2 HCINTEN register (address = A4h) .............................................................. 32 5.6 USB testing registers ............................................................... 33 5.6.1 TESTMODE register (address = 50h) ........................................................... 34 5.6.2 TESTPMSET1 register (address = 70h) ......................................................... 34 5.6.3 TESTPMSET2 register (address = 74h) ......................................................... 34 6 Devices Characteristics and Ratings ............................ 35 6.1 Absolute Maximum Ratings ...................................................... 35 6.2 DC Characteristics .................................................................... 35 6.3 AC Characteristics .................................................................... 38 6.4 Timing...................................................................................... 39 6.4.1 PIO timing ................................................................................................ 39 6.4.2 DMA timing .............................................................................................. 44 7 Application Examples .................................................. 45 7.1 Examples of Bus Interface connection ..................................... 46 7.1.1 16-Bit SRAM asynchronous bus interface ...................................................... 46 7.1.2 8-Bit SRAM asynchronous bus interface ....................................................... 47 7.1.3 16-Bit NOR asynchronous bus interface ....................................................... 47 7.1.4 8-Bit NOR asynchronous bus interface ......................................................... 47 7.1.5 16-Bit General Multiplex asynchronous bus interface ..................................... 48 Copyright © Future Technology Devices International Limited 5 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 7.1.6 8 Clearance No.: FTDI# 318 8-Bit General Multiplex asynchronous bus interface ....................................... 48 Package Parameters .................................................... 49 8.1 FT313H Package Markings ....................................................... 49 8.1.1 QFN-64 .................................................................................................... 49 8.1.2 LQFP-64 ................................................................................................... 49 8.1.3 TQFP-64 .................................................................................................. 50 8.2 QFN-64 Package Dimensions ................................................... 51 8.3 LQFP-64 Package Dimensions .................................................. 52 8.4 TQFP-64 Package Dimensions .................................................. 53 8.5 Solder Reflow Profile ............................................................... 54 9 Contact Information .................................................... 55 Appendix A – References ................................................... 56 Document References ...................................................................... 56 Acronyms and Abbreviations............................................................ 56 Appendix B - List of Figures and Tables ............................. 57 List of Figures .................................................................................. 57 List of Tables.................................................................................... 57 Appendix C - Revision History ............................................ 59 Copyright © Future Technology Devices International Limited 6 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 3 Device Pin Out and Signal Description NC VCC(3V3) NC AGND DP NC DM NC RREF OC_N 59 58 57 56 55 54 53 52 51 50 49 VBUS 61 NC CPE0 62 AGND TESTEN 63 60 CPE1 64 3.1 Pin Out – 64pin QFN AGND 1 48 PSW_N AD0 2 47 AGND AD1 3 46 VOUT(1V2) 45 X2 AD2 4 AD3 5 VCC(I/O) 6 AD4 7 AD5 8 AD6 9 AD7 10 AD8 11 AD9 12 AD10 13 FTDI XXXXXXXXXX FT313HQ YYWW-B 44 X1/CLKIN 43 AGND 42 FREQSEL2 41 FREQSEL1 40 RESET_N 39 CLE 38 ALE/ADV_N 37 DACK 36 DREQ VCC(I/O) 20 21 22 23 24 25 26 27 28 29 30 31 32 VCC(1V2) CS_N/CE_N RD_N/RE_N/OE_N WR_N/WE_N INT VCC(I/O) A0 A1 A2 A3 A4 A5 VCC(1V2) 33 19 A7 A6 AD15 34 16 18 15 AD12 AD14 35 17 14 AD13 AD11 VCC(I/O) Figure 3-1 Pin Configuration QFN64 (top-down view) Copyright © Future Technology Devices International Limited 7 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 NC RREF OC_N 51 50 49 NC DM 53 52 AGND DP 54 NC 56 55 NC VCC(3V3) 57 AGND 59 58 VBUS NC 61 60 TESTEN CPE0 62 CPE1 64 63 3.2 Pin Out – 64pin LQFP AGND 1 48 PSW_N AD0 2 47 AGND AD1 3 46 VOUT(1V2) 45 X2 44 X1/CLKIN 43 AGND 42 FREQSEL2 41 FREQSEL1 40 RESET_N 39 CLE 38 ALE/ADV_N 37 DACK 36 DREQ 35 VCC(I/O) 34 A7 33 A6 30 31 32 A4 VCC(1V2) 29 A5 28 16 A2 AD12 A3 15 27 VCC(I/O) A1 14 25 AD11 26 13 A0 AD10 VCC(I/O) 12 24 AD9 INT 11 22 AD8 23 10 WR_N/WE_N AD7 XXXXXXXXXX FT313HL YYWW-B RD_N/RE_N/OE_N 9 20 AD6 21 8 VCC(1V2) AD5 CS_N/CE_N 7 19 AD4 FTDI AD15 6 17 VCC(I/O) 18 5 AD13 4 AD3 AD14 AD2 Figure 3-2 Pin Configuration LQFP64 (top-down view) Copyright © Future Technology Devices International Limited 8 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 NC RREF OC_N 51 50 49 NC DM 53 52 AGND DP 54 NC 56 55 NC VCC(3V3) 57 AGND 59 58 VBUS NC 61 60 TESTEN CPE0 62 CPE1 64 63 3.3 Pin Out – 64pin TQFP AGND 1 48 PSW_N AD0 2 47 AGND AD1 3 46 VOUT(1V2) 45 X2 44 X1/CLKIN 43 AGND 42 FREQSEL2 41 FREQSEL1 40 RESET_N 39 CLE 38 ALE/ADV_N 37 DACK 36 DREQ 35 VCC(I/O) 34 A7 33 A6 30 31 32 A4 VCC(1V2) 29 A5 28 16 A2 AD12 A3 15 27 VCC(I/O) A1 14 25 AD11 26 13 A0 AD10 VCC(I/O) 12 24 AD9 INT 11 22 AD8 23 10 WR_N/WE_N AD7 XXXXXXXXXX FT313HP YYWW-B RD_N/RE_N/OE_N 9 20 AD6 21 8 VCC(1V2) AD5 CS_N/CE_N 7 19 AD4 FTDI AD15 6 17 VCC(I/O) 18 5 AD13 4 AD3 AD14 AD2 Figure 3-3 Pin Configuration TQFP64 (top-down view) Copyright © Future Technology Devices International Limited 9 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 3.4 Pin Description Pin No. Name Type 1 AGND P 2 AD0 I/O 3 AD1 I/O 4 AD2 I/O 5 AD3 I/O 6 VCC(I/O) P 7 AD4 I/O 8 AD5 I/O 9 AD6 I/O 10 AD7 I/O 11 AD8 I/O 12 AD9 I/O 13 AD10 I/O 14 AD11 I/O 15 VCC(I/O) P 16 AD12 I/O 17 AD13 I/O 18 AD14 I/O 19 AD15 I/O 20 VCC(1V2) P 21 CS_N/CE_N I Description Analog Ground Bit 0 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 1 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 2 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 3 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant I/O supply voltage; connect a 0.1uF decoupling capacitor 1.8V, 2.5V or 3.3V Bit 4 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 5 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 6 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 7 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 8 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 9 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 10 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 11 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant I/O supply voltage; connect a 0.1uF decoupling capacitor 1.8V, 2.5V or 3.3V Bit 12 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 13 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 14 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Bit 15 of the address and data bus Bidirectional pad; push-pull, three-state output. 3.3V tolerant Core power 1.2V input; for normal operation, this pin must be connected to pin 46. Connect a 0.1uF decoupling capacitor Chip select; Copyright © Future Technology Devices International Limited 10 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Pin No. Name Type Clearance No.: FTDI# 318 Description Input ; 3.3V tolerant 22 RD_N /RE_N/OE_N I 23 WR_N /WE_N I 24 INT O 25 VCC(I/O) P 26 A0 I 27 A1 I 28 A2 I 29 A3 I 30 A4 I 31 A5 I 32 VCC (1V2) P 33 A6 I 34 A7 I 35 VCC(I/O) P 36 DREQ O 37 DACK I 38 ALE/ADV_N I 39 CLE I 40 RESET_N I 41 FREQSEL1 I 42 FREQSEL2 I 43 AGND P 44 X1/CLKIN AI 45 X2 AO 46 VOUT(1V2) AO Read enable, or read latch; when not in use, connect to VCC(I/O) Input; 3.3V tolerant Write enable; when not in use, connect to VCC(I/O) Input; 3.3V tolerant Interrupt output Push-pull output; 3.3V tolerant I/O supply voltage; connect a 0.1uF decoupling capacitor 1.8V, 2.5V or 3.3V Bit 0 of the address bus; when not in use, connect to GND Input; 3.3V tolerant Bit 1 of the address bus; when not in use, connect to GND Input; 3.3V tolerant Bit 2 of the address bus; when not in use, connect to GND Input; 3.3V tolerant Bit 3 of the address bus; when not in use, connect to GND Input; 3.3V tolerant Bit 4 of the address bus; when not in use, connect to GND Input; 3.3V tolerant Bit 5 of the address bus; when not in use, connect to GND Input; 3.3V tolerant Core power 1.2V input; for normal operation, this pin must be connected to pin 46. Connect a 0.1uF decoupling capacitor. Bit 6 of the address bus; when not in use, connect to GND Input; 3.3V tolerant Bit 7 of the address bus; when not in use, connect to GND Input; 3.3V tolerant I/O supply voltage; connect a 0.1uF decoupling capacitor 1.8V, 2.5V or 3.3V DMA request; Push-pull output; 3.3V tolerant DMA acknowledge; Internal pull-down. Input; 3.3V tolerant Address latch enable Input; 3.3V tolerant Command latch enable Input; 3.3V tolerant Chip reset; Internal pull-up. Input; 3.3V tolerant Input clock frequency selection pin1 Input; 3.3V tolerant Input clock frequency selection pin2 Input; 3.3V tolerant Analog Ground Crystal oscillator or clock input; 3.3V peak input allowed Crystal oscillator output; leave open if an external clock is applied on pin X1/CLKIN Internal 1.2V regulator output; connect 4.7uF and Copyright © Future Technology Devices International Limited 11 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Pin No. Name Type Clearance No.: FTDI# 318 Description 0.1uF decoupling capacitors to this pin. 47 AGND P 48 PSW_N OD 49 OC_N I 50 RREF AI 51 NC 52 DM 53 NC Analog Ground Port power switch; when not in use, connect to VCC(3V3) through a 10kΩ resistor Open drain output; 5V tolerant Over current input; when not in use, connect to VCC(3V3) through a 10KΩ resistor Input; 5V tolerant Port reference resistor connection Connect 12 kΩ±1% resistor between RREF and GND No connect AI/O Port DM; connect to the D- pin of the USB connector No connect 54 DP AI/O 55 AGND P Port DP; connect to the D+ pin of the USB connector Analog Ground 56 NC 57 VCC(3V3) P 58 NC No connect Supply 3.3V voltage; Connect 10uF and 0.1uF decoupling capacitors No connect 59 AGND P Analog Ground 60 NC 61 VBUS OD 62 CPE0 I Bit 0 to select charging port emulation type 63 TESTEN I Enable test mode. Internal pull-down. For normal operation leave floating. 64 CPE1 I Bit 1 to select charging port emulation type No connect VBUS discharge. 5V tolerant Table 3-1 FT313H pin description Notes: P I O OD : : : : Power or ground Input Output Open drain output I/O AI AO AI/O Copyright © Future Technology Devices International Limited : : : : Bi-direction Input and Output Analog Input Analog Output Analog Input / Output 12 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 4 Function Description The FT313H is a USB2.0 compatible EHCI single port host controller which is mainly composed of the following:          Microcontroller bus interfaceSRAM bus interface mode NOR bus interface mode General multiplex bus interface mode Interface mode lock DMA controller EHCI host controller System clock Power management BCD mode The functions for each block are briefly described in the following subsections. 4.1 Microcontroller Bus Interface The FT313H has a fast advance general purpose interface to communicate with most types of microcontrollers and microprocessors. This microcontroller interface is configured using pins ALE/ADV_N and CLE to accommodate most types of interfaces. The bus interface supports 8-bit and 16-bit, which can be configured using bit DATA_BUS_WIDTH. Three bus interface types are selected using inputs ALE/ADV_N and CLE during power up, the RD_N /RE_N/OE_N and CS_N/CE_N pins, or the RESET_N pin. Table 4-1 provides detail of bus configuration for each mode. Table 4-2 shows pinout information of each bus interface. Bus Mode SRAM 8-bit SRAM 16-bit ALE/ADV_N CLE HIGH HIGH HIGH HIGH DATA_BUS _WIDTH 1 Signal Description         0     NOR 8-bit HIGH LOW 1 NOR 16-bit HIGH LOW 0   General Multiplex 8-bit LOW HIGH 1   General Multiplex 16-bit LOW HIGH     0   A[7:0]: 8-bit address bus AD[7:0]: 8-bit data bus Write (WR_N), read (RD_N), chip select (CS_N): control signals for normal SRAM mode DACK: DMA acknowledge input DREQ: DMA request output A[7:0]: 8-bit address bus AD[15:0]: 16-bit data bus Write (WR_N), read (RD_N), chip select (CS_N): control signals for normal SRAM mode DACK: DMA acknowledge input DREQ: DMA request output AD[7:0]: 8-bit data bus ADV_N, write enable, output enable, chip select: control signals AD[15:0]: 16-bit data bus ADV_N, write enable, output enable, chip select: control signals AD[7:0]: 8-bit data bus ALE, write(WR_N), read(RD_N), chip select: control signals DACK: DMA acknowledge input DREQ: DMA request output AD[15:0]: 16-bit data bus ALE, write(WR_N), read(RD_N), chip select: control signals DACK: DMA acknowledge input DREQ: DMA request output Table 4-1 Bus Configuration modes SRAM mode NOR mode General Type Copyright © Future Technology Devices International Limited Description 13 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 AD[15:0] A[7:0] CS_N RD_N/RE_N AD[15:0] ADV_N CS_N OE_N Multiplex mode AD[15:0] ALE CS_N RD_N/RE_N I/O I I I I Data or address bus Address bus Address or command valid Chip select Read control WR_N/WE_N INT DREQ DACK WE_N INT - WR_N/WE_N INT DREQ DACK I O O I Write control Interrupt request DMA request DMA acknowledge Table 4-2 Pin information of the bus interface 4.2 SRAM bus interface mode The bus interface will be in SRAM 16-bit mode if pins ALE/ADV_N and CLE are HIGH, when: The CS_N/CE_N pin goes LOW, and the RD_N /RE_N/OE_N pin goes LOW. Then, if the DATA_BUS_WIDTH bit is set, the bus interface will be in SRAM 8-bit mode. In SRAM mode, A[7:0] is the 8-bit address bus and AD[15:0] is the separate 16-bit data bus. The FT313H pins RD_N /RE_N/OE_N and WR_N/WE_N are the read and write strobes. The SRAM bus interface supports both 8-bit and 16-bit bus width that can be configured by setting or clearing bit DATA_BUS_WIDTH. The DMA transfer is also applicable to this interface. Copyright © Future Technology Devices International Limited 14 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 4.3 NOR bus interface mode The bus interface will be in NOR 16-bit mode, if pin ALE/ADV_N is HIGH and pin CLE is LOW, when: • The CS_N/CE_N pin goes LOW, and the RD_N /RE_N/OE_N pin goes LOW. Then, if the DATA_BUS_WIDTH bit is set, the bus interface will be in NOR 8-bit mode. The NOR Flash interface access consists of two phases: address and data. The address is valid when CS_N/CE_N and ADV_N are LOW, and the address is latched at the rising edge of ADV_N. For a read operation, WE_N must be HIGH. OE_N is the data output control. When active, the addressed register or the buffer data is driven to the I/O bus. The read operation is completed when CS_N/CE_N is de-asserted. For a write operation, OE_N must be HIGH. The WE_N assertion can start when ADV_N is de-asserted. WE_N is the data input strobe signal. When de-asserted, data will be written to the addressed register or the buffer. The write operation is completed when CS_N/CE_N is deasserted. 4.4 General multiplex bus interface mode The bus interface will be in general multiplex 16-bit mode, if pin ALE/ADV_N is LOW and pin CLE is HIGH, when: • The CS_N/CE_N pin goes LOW, and the RD_N /RE_N/OE_N pin goes LOW. Then, if the DATA_BUS_WIDTH bit is set, the bus interface will be in general multiplex 8-bit mode. The general multiplex bus interface supports most advance application processors. The general multiplex interface access consists of two phases: address and data. The address is valid when ALE/ADV_N goes HIGH, and the address is latched at the falling edge of ALE/ADV_N. For a read operation, WR_N/WE_N must be HIGH. RD_N /RE_N/OE_N is the data output control. When active, the addressed register or the buffer data is driven to the I/O bus. The read operation is completed when CS_N/CE_N is de-asserted. For a write operation, RD_N /RE_N/OE_N must be HIGH. The WR_N/WE_N assertion can start when ALE/ADV_N is de-asserted. WR_N/WE_N is the data input strobe signal. When de-asserted, data will be written to the addressed register or the buffer. The write operation is completed when CS_N/CE_N is de-asserted. The DMA transfer is also applicable to this interface. 4.5 Interface mode lock The bus interface can be locked in any of the modes, SRAM, NOR, or general multiplex, using bit 3 of the HW Mode Control register. To lock the interface in a particular mode: 1. Read bits 7 and 6 of the SW Reset register. 2. Set bit 3 of the HW Mode Control register to logic 1. 3. Read bits 7 and 6 of the SW Reset register to ensure that the interface is locked in the desired mode. Note: the default is 16-bit SRAM mode. 4.6 DMA controller The DMA controller of the FT313H is used to transfer data between the system memory and local buffers. It shares data bus AD[15:0] and control signals WR_N/WE_N, RD_N /RE_N/OE_N, and CS_N/CE_N. The logic is dependent on the bus interface mode setting. DREQ signal is from the FT313H to indicate the start of DMA transfer. DACK signal is used to differentiate if data transferred is for the DMA or PIO access. When DACK is asserted, it indicates that it is still in DMA mode. When DACK is de-asserted, it indicates that PIO is to be accessed. ALE/ADV_N and CLE are ignored in a DMA access cycle. Correct data will be captured only on the rising edge of WR_N/WE_N and RD_N /RE_N/OE_N. Copyright © Future Technology Devices International Limited 15 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 The DMA controller of the FT313H has only one DMA channel. Therefore, only one DMA read or DMA write may take place at a time. Assign the DMA transfer length in the Data Session Length register for each DMA transfer. If the transfer length is larger than the burst counter, the DREQ signal will de-assert at the end of each burst transfer. DREQ will re-assert at the beginning of the each burst. When DMA is transferring data from/to local buffer, if it wants to access local buffer content by PIO mode, can use auxiliary memory access registers AUX_MEMADDR and AUX_DATAPORT to read/write data from/to local buffer with single cycle. For a 16-bit DMA transfer, the minimum burst length is 2 bytes. This means that the burst length is only one DMA cycle. Therefore, DREQ and DACK will assert and de-assert at each DMA cycle. The FT313H will be asserted DMA EOT interrupt to indicate that the DMA transfer has either successfully completed or terminated. 4.7 EHCI host controller The FT313H is a one-port EHCI-compatible host controller which supports all the USB 2.0 compliant Lowspeed, Full-speed, and High-speed devices and split/preamble transactions for the HS/FS hub. The EHCI host controller supports two categories of the transfer types, the periodic and asynchronous transfer types. The periodic transfer type includes the isochronous and interrupt transfers, while the asynchronous transfer type includes the control and bulk transfers. The EHCI host controller has schedule interface that provides to the separate schedules for each category of the transfer type. The periodic schedule is based on a time-oriented frame list that represents a slide window of time of the host controller work items. All the ISO and INT transfers are serviced via the periodic schedule. The asynchronous schedule is a simple circular list of the schedule work items that provides a round robin service opportunity for all the asynchronous transfers. The EHCI host controller contains the Isochronous Transfer Descriptor (iTD), Queue Head (qH) and Queue Element Transfer Descriptor (qTD), and Split Transaction Isochronous Transfer Descriptor (siTD) data structure interface to support the isochronous/interrupt/control/bulk transfers and split transaction. The EHCI host controller internal buffer memory is 24KB. START_ADDR_MEM register is allocated from 0x0000 to 0x5FFF. 4.8 System clock 4.8.1 Phase Locked Loop (PLL) clock multiplier The internal PLL supports 12MHz, 19.2MHz, or 24MHz input, which can be crystal or a clock already existing in system. The frequency selection can be done using the FREQSEL1 and FREQSEL2 pins. Table 4-3 provides clock frequency selection. FREQSEL1 FREQSEL2 Clock Frequency 0 0 12MHz 1 0 19.2MHz 0 1 24MHz Table 4-3 Clock frequency select 4.9 Power management 4.9.1 Power up and reset sequence When VCC(I/O) and VCC(3V3) are on, an internal regulator will power on with VCC(3V3) on. An internal POR pulse will be generated during the regulator power on, so that internal circuits are in reset state until the regulator power is stable. Copyright © Future Technology Devices International Limited 16 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 4.9.2 Clearance No.: FTDI# 318 Power supply Power supplies are defined in Table 4-4. Symbol VCC(I/O) VCC(3V3) Typical 1.8V, or 2.5V, or 3.3V 3.3V Description Supply for digital I/O pad Supply for chip Table 4-4 Power supply 4.9.3 ATX reference voltage The ATX circuit provides a stable internal voltage reference (+1.2V) to bias the analog circuitry. This circuit requires an accurate external reference resistor. Connect 12kΩ±1% resistor between pins RREF and GND. 4.9.4 Power modes Power management configuration defined in Table 4-5. For each bit description, see CONFIG register. OSC_EN 1 0 PLL_EN 1 0 HC_CLK_EN 1 0 Description Operation mode Suspend mode Table 4-5 power management configuration 4.9.4.1 Operation mode All power supplies are present. Host controller is active. 4.9.4.2 Suspend mode All power supplies are present. Host controller goes to USB suspend. The steps for the host suspend are as follows: 1. 2. 3. 4. Clear the RS bit of the USBCMD register to stop the host controller from executing schedule. Set the PO_SUSP bit of the PORTSC register to force the host controller to go into suspend. Disable OSC_EN, PLL_EN and HC_CLK_EN bits of the CONFIG register to save power. Clear the U_SUSP_U bit of the EOTTIME register to put the chip into suspend mode. 4.9.4.3 Wake up The regulator will be in normal operating mode and the clock/oscillator/PLL will be enabled when either of these conditions is triggered: 1. 2. 3. 4. Dummy read access with a LOW pulse on pins CS_N/CE_N and RD_N /RE_N/OE_N. USB device connects or disconnects. Remote wake up from external USB device. Over current condition is triggered on OC_N if enabled by register. After wake up automatically set corresponding bit of the CONFIG register, must set the U_SUSP_U bit of the EOTTIME register to wake up the chip. 4.10 BCD mode The FT313H is an EHCI-compatible host controller with BCD block function, which follows the Battery Charging Specification Revision 1.2(BC1.2) by USB-IF. The block function that emulates USB host port as either Charging Downstream Port (CDP) or Dedicated Charging Port (DCP) which provides higher current source than Standard Downstream Port (SDP). The BCD logic block will decode the mode of operation and choose by following setting: Copyright © Future Technology Devices International Limited 17 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 1. BCD function is default enable by CONFIG register bit[5] setting. 2. BCD mode selection is default controlled by external pins configuration. Set CONFIG register bit[15] to take over BCD mode setting by software. 3. Same configuration by CONFIG register bit[14:13] to set BCD mode if software takes over control. CPE1 0 CPE0 0 Mode SDP BCD_EN 1 0 1 DCP 1 1 1 CDP 1 X X X 0 Description Standard downstream port, VBUS current limit ≤ 500mA Dedicated charging port, USB host no functional on this port, VBUS current limit ≤ 1.5A Charging downstream port alternative configuration, VBUS current limit ≤ 1.5A BCD function disable Table 4-6 BCD mode configuration Copyright © Future Technology Devices International Limited 18 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 5 Host controller specific registers 5.1 Overview of registers Table 5-1 shows the definitions of the FT313H host controller specific registers. Address Register EHCI operational register 00h HCCAPLENGTH 04h HCSPARAMS 08h HCCPARAMS 10h USBCMD 14h USBSTS 18h USBINTR 1Ch FRINDEX 24h PERIODICLISTADDR 28h ASYNCLISTADDR 30h POSTSC Configuration register 34h EOFTIME Reset value Description 0100 0000 0000 0008 0000 0000 0000 0000 0000 0000 Capability register Structural parameter register Capability parameter register USB command register USB status register USB interrupt enable register Frame index register Periodic frame list base address register Current asynchronous list address register Port status and control register 0010h 0001h 0006h 0B00h 1000h 0000h 0000h 0000h 0000h 0000h 0000 0041h EOF time and asynchronous schedule sleep timer register Chip ID register HW mode control register Edge interrupt control register SW reset register Memory address register Data port register Data session length register Configuration register Auxiliary memory address register Auxiliary data port register Sleep timer register 80h CHIPID 0313 0001h 84h HWMODE 0000 0000h 88h EDGEINTC 0000 001Fh 8Ch SWRESET 0000 0000h 90h MEMADDR 0000h 92h DATAPORT 0000h 94h DATASESSION 0000h 96h CONFIG 1FA0h 98h AUX_MEMADDR 0000h 9Ah AUX_DATAPORT 0000h 9Ch SLEEPTIMER 0400h Interrupt register A0h HCINTSTS 0000h Host controller interrupt status register A4h HCINTEN 0000h Host controller interrupt enable register USB testing register 50h TESTMODE 0000 0000h Test mode register 70h TESTPMSET1 0000 0000h Test parameter setting 1 register 74h TESTPMSET2 0000 0000h Test parameter setting 2 register Table 5-1 Overview of host controller specific registers 5.2 EHCI operational registers 5.2.1 HCCAPLENGTH register (address = 00h) This register is used as an offset to add to register base to find the beginning of the operational register space. The high two bytes contain a BCD encoding of the EHCI revision number supported by this host controller. The most signification byte of this register represents a major revision and the least signification byte is the minor revision. Bit [31:16] Name HCIVERSION Type RO [15:8] [7:0] Reserved CAPLENGTH RO RO Default value 16’h0100 Description Host Controller Interface Version Number This register is a 2-byte register containing a BCD encoding of the EHCI revision number supported by the host controller. 8’h0 8’h10 Capability Register Length This register is used as an offset added to register base to find out the beginning of the Operational Register Space. Table 5-2 Capability register Copyright © Future Technology Devices International Limited 19 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 5.2.2 Clearance No.: FTDI# 318 HCSPARAMS register (address = 04h) This is a set of fields that are structural parameter: number of downstream ports, etc. Bit [31:4] [3:0] Name Reserved N_PORTS Type RO RO Default value 28’h0 4’h1 Description Number of Ports This field specifies the number of the physical downstream ports implemented on the host controller. Table 5-3 Structural parameter register 5.2.3 HCCPARAMS register (address = 08h) This is multiple mode control (time base bit functionality) and addressing capability. Bit [31:3] 2 1 Name Reserved ASPC PFLF Type RO RO RO Default value 29’h0 1’b1 Description Asynchronous Schedule Park Capability 1’b1 The host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. This feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. Programmable Frame List Flag When this bit is set to 1b, the system software can specify and use a smaller frame list and configure the host controller via Frame List Size field of the USBCMD register. This requirement ensures that the frame list is always physically contiguous. RO 1’b0 Table 5-4 Capability parameter register 0 Reserved 5.2.4 USBCMD register (address = 10h) The command register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. Bit [31:24] [23:16] Name Reserved INT_THRC Type RO R/W Default value 8’h0 8’h08 Description Interrupt Threshold Control This field is used by the system software to select the maximum rate at which the host controller will issue the interrupts. The only valid values are described as below: Value Max Interrupt Interval for the high-speed 00h Reserved 01h No limited interval 02h 2 micro-frames 04h 4 micro-frames Copyright © Future Technology Devices International Limited 20 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Bit Name Type Default value Description 08h 8 micro-frames (Default, equals to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h [15:12] 11 10 [9:8] 7 6 5 Reserved ASYN_PK_EN Reserved ASYN_PK_CNT Reserved INT_OAAD ASCH_EN RO R/W RO R/W RO R/W R/W Clearance No.: FTDI# 318 64 micro-frames (8 ms) 4’b0 1’b1 Note1: This is further gated by MIN_WIDTH bits of EDGEINTC register if edge trigger interrupt is used. Note2: In the full-speed mode, these registers are reserved. Asynchronous Schedule Park Mode Enable 1’b0 2’b11 Software uses this register to enable or disable the Park mode. When this register is set to ‘1’, the Park mode is enabled. Asynchronous Schedule Park Mode Count 1’b0 1’b0 1’b0 This field contains a count for the number of successive transactions that the host controller is allowed to execute from a high-speed queue head on the asynchronous schedule. Interrupt on Asynchronous Advance Doorbell This bit is used as a doorbell by software to ring the host controller to issue an interrupt at the next advance of the asynchronous schedule. Asynchronous Schedule Enable This bit controls whether the host controller skips the processing of asynchronous schedule. 0: Do not process the asynchronous schedule 4 PSCH_EN R/W 1’b0 1: Use the ASYNCLISTADDR register to access the asynchronous schedule Periodic Schedule Enable This bit controls whether the host controller skips the processing of the periodic schedule. 0: Do not process the periodic schedule [3:2] FRL_SIZE R/W 2’b00 1: Use the PERIODICKISTBASE register to access the periodic schedule Frame List Size This field specifies the size of the frame list. 1 HC_RESET R/W 1’b0 00: 1024 elements (4096 bytes; default value) 01: 512 elements (2048 bytes) 10: 256 elements (1024 bytes) 11: Reserved Host Controller Reset Copyright © Future Technology Devices International Limited 21 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Bit 0 Name RS Type R/W Clearance No.: FTDI# 318 Default value Description 1’b0 This control bit is used by the software to reset the host controller. Run/Stop When this bit is set to 1b, the host controller proceeds with the execution of schedule. 0: Stop 1: Run Table 5-5 USB command register 5.2.5 USBSTS register (address = 14h) This register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by writing a 1 to it. Bit [31:16] 15 Name Reserved ASCH_STS Type RO RO Default value 16’h0 1’b0 Description Asynchronous Schedule Status 14 PSCH_STS RO 1’b0 13 Reclamation RO 1’b0 This bit reports the actual status of the asynchronous schedule. Periodic Schedule Status This bit reports the actual status of the periodic schedule. Reclamation 1’b1 This is a read-only status bit, and used to detect an empty of the asynchronous schedule. Host Controller Halted 6’b0 1’b0 This bit is a zero whenever the Run/Stop bit is set to ‘1.’ The host controller sets this bit to ‘1’ after it has stopped the executing as a result of the Run/Stop bit being set to 0b. Interrupt on Asynchronous Advance 1’b0 This status bit indicates the assertion of interrupt on Async Advance Doorbell. Host System Error 1’b0 The Host Controller sets this bit to ‘1’ when a serious error occurred during a host system access involving the host controller module. Frame List Rollover 1’b0 The host controller sets this bit to ’1’ when the Frame List Index rolls over from its maximum value to zero. Port Change Detect 1’b0 The host controller sets this bit to ’1’ when any port has a change bit transition from ‘0’ to ‘1.’ In addition, this bit is loaded with the OR of all of the PORTSC change bits. USB Error Interrupt 12 [11:6] 5 4 3 2 1 HCHalted Reserved INT_OAA H_SYSERR FRL_ROL PO_CHG_DET USBERR_INT RO RO R/WC R/WC R/WC R/WC R/WC The host controller sets this bit to ‘1’ when the Copyright © Future Technology Devices International Limited 22 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Bit Name Type Default value 0 USB_INT R/WC 1’b0 Clearance No.: FTDI# 318 Description completion of a USB transaction results in an error condition. USB Interrupt The host controller sets this bit to ‘1’ upon the completion of a USB transaction. Table 5-6 USB status register 5.2.6 USBINTR register (address = 18h) This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the USBSTS to allow the software to poll for events. Bit [31:6] 5 4 3 2 1 0 Name Reserved INT_OAA_EN H_SYSERR_EN FRL_ROL_EN PO_CHG_DET_EN USBERR_INT_EN USB_INT_EN Type RO R/W R/W R/W R/W R/W R/W Default value 26’h0 1’b0 Description Interrupt on Async Advance Enable 1’b0 When this bit is set to ‘1,’ and the Interrupt on Async Advance bit in the USBSTS register is set to ‘1’ also, the host controller will issue an interrupt at the next interrupt threshold. Host System Error Enable 1’b0 When this bit is set to ‘1,’ and the Host System Error Status bit in the USBSTS register is set to ‘1’ also, the host controller will issue an interrupt. Frame List Rollover Enable 1’b0 When this bit is set to ‘1,’ and the Frame List Rollover bit in the USBSTS register is set to ‘1’ also, the host controller will issue an interrupt. Port Change Interrupt Enable 1’b0 When this bit is set to ‘1,’ and the Port Change Detect bit in the USBSTS register is set to ‘1’ also, the host controller will issue an interrupt. USB Error Interrupt Enable 1’b0 When this bit is set to ‘1,’ and the USBERRINT bit in the USBSTS register is set to ‘1’ also, the host controller will issue an interrupt at the next interrupt threshold. USB Interrupt Enable When this bit is set to ‘1,’ and the USBINT bit in the USBSTS register is a set to ‘1’ also, the host controller will issue an interrupt at the next interrupt threshold. If set interrupt threshold to 01h, means that when interrupt event occurred, the INT signal will be toggled at once. Table 5-7 USB interrupt enable register Copyright © Future Technology Devices International Limited 23 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 5.2.7 Clearance No.: FTDI# 318 FRINDEX register (address = 1Ch) This register is used by the host controller to index into the periodic frame. The register updates very 125 microseconds (one each micro-frame). Bit [31:14] [13:0] Name Reserved FRINDEX Type RO R/W Default value 28’h0 14’b0 Description Frame Index This register is used by the host controller to index the frame into the Periodic Frame List. It updates every 125 microseconds. This register cannot be written unless the host controller is at the halted state. Bits[N:3] are used for Frame List current index. This means that each location of the frame list is accessed 8 times before moving to the next index. USBCMD[Frame List Size] Number Elements N 00b (1024) 12 01b (512) 11 10b (256) 10 11b Reserved Table 5-8 Frame index register 5.2.8 PERIODICLISTADDR register (address = 24h) This 32-bit register contains the beginning address of the periodic frame list in the system memory. Bit [31:12] Name PERI_BASEADR Type R/W Default value 20’h0 Description Periodic Frame List Base Address This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. These bits correspond to the memory address signals[31:12]. RO 12’b0 Table 5-9 Periodic frame list base address register [11:0] Reserved 5.2.9 ASYNCLISTADDR register (address = 28h) This 32-bit register contains the address of the next asynchronous queue head to be executed. Bit [31:5] Name ASYNC_LADR [4:0] Reserved Type R/W RO Default value 27’h0 Description Current Asynchronous List Address 5’b0 This 32-bit register contains the address of the next asynchronous queue head to be executed. These bits correspond to the memory address signals [31:5]. - Table 5-10 Current asynchronous list address register 5.2.10 POSTSC register (address = 30h) The port status and control register is in the power well. It is only reset by hardware when the power is initially applied or in response to a host controller reset. The initial conditions of a port are:   No peripheral connected Port disable Copyright © Future Technology Devices International Limited 24 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 The software must not attempt to change the state of the port until the power is stable on the port. The host is required to have power stable to the port within 20 milliseconds of the zero to one transition. When a peripheral device is attached, the port state transitions to the connected state and system software will process this as with any status change notification. Bit [31:17] 16 [15:12] [11:10] 9 8 Name Reserved TST_FORCEEN Reserved LINE_STS Reserved PO_RESET Type RO R/W RO RO RO R/W Default value 15’h0 1’b0 Description Test Force Enable 4’b0 2’b00 When this signal is written as ‘1,’ the downstream facing port will be enabled in the high-speed mode. Then the Run/Stop bit must be transitioned to one in order to enable the transmission of the SOFs out of the port under test. This enables testing of the disconnect detection. Line Status 1’b0 1’b0 These bits reflect the current logical levels of the D+ and D- signal lines. Bits[11:10] USB state 00b SE0 10b J-state 01b K-state 11b Undefined Port Reset 1 = Port is in the reset state. 0 = Port is not in the reset state. 7 PO_SUSP R/W 1’b0 When the software writes a ‘1’ to this bit, the bus reset sequence as defined in the USB specification will start. Software writes a ‘0’ to this bit to terminate the bus reset sequence. Software must keep this bit at a ‘1’ long enough to ensure the reset sequence. Note: Reset signal which shall be followed by the USB2.0 chapter 7.1.7.5 Reset Signal requirement. If detected HS device, the software shall wait more than 200us for port reset clearing. Before setting this bit, RUN/STOP bit should be set to ‘0.’ Port Suspend 1 = Port is in the suspend state 0 = Port is not in the suspend state. The Port Enable Bit and Suspend Bit of this register define the port state as follows: Bits[Port Enable, Suspend] 0X 10 11 Port State Disable Enable Suspend At the suspend state, the downstream propagation of the data is blocked on this port, except for the port reset. While at the suspend state, the port is sensitive to resume detection. Writing a ‘0’ to this bit is ignored by the host controller. The host controller will Copyright © Future Technology Devices International Limited 25 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Bit Name Type Default value 6 F_PO_RESM R/W 1’b0 Clearance No.: FTDI# 318 Description unconditionally set this bit to a ‘0’ when: The software sets Force Port Resume bit to a ‘0’ (From a one) The software sets Port Reset bit to a ‘1’ (From a ‘0’) Note: Before setting this bit, RUN/STOP bit should be set to 0. Force Port Resume 1 = Resume detected/driven on port. 0 = No resume detected/driven on port. [5:4] 3 2 Reserved PO_EN_CHG PO_EN RO R/WC R/W 2’b00 1’b0 Software sets this bit to a ‘1’ to resume signal. The host controller sets this bit to a ‘1’ if a J-to-K transition is detected while the port is in the suspend state. When this bit transits to a ‘1’ for the detection of a J-to-K transition, the Port Change Detect bit in USBSTS register is also set to a ‘1’. Port Enable/Disable Change 1’b0 1 = Port enable/disable status has changed. 0 = No change Port Enable/Disable 1 = Enable 0 = Disable 1 CONN_CHG R/WC 1’b0 Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Connect Status Change 1 = Change current connect status 0 = No change. 0 CONN_STS RO 1’b0 This bit indicates a change has occurred in the current connect status of the port. Current Connect Status 1 = Device is presented on the port. 0 = No device is presented. This value reflects the current state of the port, and may not correspond directly to cause the Connect Status Change bit to be set. Table 5-11 Port status and control register 5.3 Configuration registers 5.3.1 EOTTIME register (address = 34h) Bit Name Type [31:7] 6 Reserved U_SUSP_N RO R/W Default value 25’h0 1’b1 Description Transceiver Suspend Mode Active low Places the transceiver in the suspend mode that draws the minimal power from the power supplies. This is Copyright © Future Technology Devices International Limited 26 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Bit Name Type Default value [5:4] EOF2_TIME R/W 2’b00 Clearance No.: FTDI# 318 Description part of the power management. EOF 2 Timing Points Control EOF2 timing point before next SOF. High-Speed EOF2 Time 00b 2 clocks (30 MHz) = 66 ns 01b 4 clocks (30 MHz) = 133 ns 10b 8 clocks (30 MHz) = 266 ns 11b 16 clocks (30 MHz) = 533 ns Full-Speed EOF2 Time 00b 20 clocks (30 MHz)=8 clocks (12 MHz) = 666 ns 01b 40 clocks (30 MHz)=16 clocks (12 MHz) = 1.333 µs 10b 80 clocks (30 MHz) = 32 clocks (12 MHz) = 2.66 µs 11b 160 clocks (30 MHz) = 64 clocks (12 MHz) = 5.3 µs [3:2] EOF1_TIME R/W 2’b00 Low-Speed EOF2 Time 00b 40 clocks (30 MHz) = 16 clocks (12 MHz) = 1.33 µs 01b 80 clocks (30 MHz) = 32 clocks (12 MHz) = 2.66 µs 10b 160 clocks (30 MHz) = 64 clocks (12 MHz) = 5.33 µs 11b 320 clocks (30 MHz) = 128 clocks (12 MHz) = 10.66 µs EOF 1 Timing Points Controls the EOF1 timing point before next SOF. This value should be adjusted according to the maximum packet size. High-Speed EOF1 Time 00b 540 clocks (30 MHz) 01b 360 clocks (30 MHz) 10b 180 clocks (30 MHz) 11b 720 clocks (30 MHz) = = = = 18 µs 12 µs 6 µs 24 µs Full-Speed EOF1 Time 00b 1600 clocks (30 MHz) = 640 clocks (12 MHz) = 53.3 µs 01b 1400 clocks (30 MHz) = 560 clocks (12 MHz) = 46.6 µs 10b 1200 clocks (30 MHz) = 480 clocks (12 MHz) = 40 µs 11b 21000 clocks (30 MHz) = 8400 clocks (12 MHz)=700 µs [1:0] ASYN_SCH_SLPT R/W 2’b01 Low-Speed EOF1 Time 00b 3750 clocks (30 MHz) = 1500 clocks 125 µs 01b 3500 clocks (30 MHz) = 1400 clocks 116 µs 10b 3250 clocks (30 MHz) = 1300 clocks 108 µs 11b 4000 clocks (30 MHz) = 1600 clocks 133 µs Asynchronous Schedule Sleep Timer (12 MHz) = (12 MHz) = (12 MHz) = (12 MHz) = Controls the Asynchronous Schedule sleep timer. Copyright © Future Technology Devices International Limited 27 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Bit Name Type Default value Clearance No.: FTDI# 318 Description 00b 5 µs 01b 10 µs 10b 15 µs 11b 20 µs Table 5-12 EOF time and asynchronous schedule sleep timer register 5.4 CHIPID register (address = 80h) This chip ID register contains the chip identification and hardware version numbers. Bit [31:0] Name CHIP_ID 5.4.1 HWMODE register (address = 84h) Bit [15: 8] Name Reserved [7: 6] HOST_SPD_TYP 5 DACK_POL 4 DREQ_POL 3 INTF_LOCK 2 INTR_POL 1 INTR_LEVEL 0 GLOBAL_INTR_EN Type RO Default value Description 32’h03130001 Chip ID Table 5-13 Chip ID Register Type RO Default value 8’b0 Description Host Speed Type Indicate the speed type of attached device RO 2’b00 2’b10: HS 2’b00: FS 2’b01: LS 2’b11: Reserved R/W 1’b0 DACK Polarity 0: active LOW 1: active HIGH R/W 1’b0 DREQ Polarity 0: active LOW 1: active HIGH R/W 1’b0 Interface Lock 0: Unlock the bus interface 1: Lock the bus interface R/W 1’b0 Interrupt Polarity 0: active LOW 1: active HIGH R/W 1’b0 Interrupt Level 0: level trigger 1: Edge trigged. The pulse width depends on the NO_OF_CLK bits in the EDGEINTC register. R/W 1’b0 Globe interrupt enable 0: INT assertion disabled. INT will never be asserted, regardless of other settings or INT events. 1: INT assertion enabled. INT will be asserted according to the HCINTEN register, and event setting and occurrence. Table 5-14 HW mode register Copyright © Future Technology Devices International Limited 28 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 5.4.2 EDGEINTC register (address = 88h) Bit [31:24] Name MIN_WIDTH [23:16] [15: 0] Reserved NO_OF_CLK 5.4.3 SWRESET register (address = 8Ch) Type R/W Clearance No.: FTDI# 318 Default value 8’b0 Description Minimum Interval Indicates the minimum interval between two edge interrupts in uSOFs (1 uSOF = 125us). This is not valid for level interrupts. A count of zero means that an interrupt occurs as when an event occurs. RO 8’b0 R/W 16’b1F Number of clocks Number of clocks that an Edge Interrupt must be kept asserted on the interface. The default INT pulse width is approximately 500ns. (N+1)*60MHz system clock. Table 5-15 Edge interrupt control register Bit [15: 8] [7: 6] Name Reserved INTF_MODE Type RO RO Default value 8’b0 2’b00 5 4 Reserved DATA_BUS_WIDTH RO R/W 1’b0 1’b0 3 2 Reserved RESET_ATX RO R/W 1’b0 1’b0 1 RESET_HC R/W 1’b0 0 RESET_ALL R/W 1’b0 Copyright © Future Technology Devices International Limited Description Interface mode 00b: Reserved 01b: Generic Multiplex mode 10b: NOR mode 11b: SRAM mode Write to these bits have no effect. Data bus width 0: Defines a 16bit data bus width. 1: Sets an 8-bit data bus width. Reset USB transceiver 0: No reset 1: Enable reset When the software writes a ‘1’ to this bit, the USB PHY reset sequence will start. Automatic clear zero. Reset host controller 0: No reset 1: Enable reset When the software writes a ‘1’ to this bit, the Host Controller reset sequence will start. Automatic clear zero. Reset all system 0: No reset 1: Enable reset When the software writes a ‘1’ to this bit, the whole 29 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Bit Name Document No.: FT_000589 Clearance No.: FTDI# 318 Default value Description system reset sequence will start. Automatic clear zero. Type Table 5-16 SW reset register 5.4.4 MEMADDR register (address = 90h) Bit [15: 0] Name START_ADDR_MEM 5.4.5 DATAPORT register (address = 92h) Bit [15: 0] Name DATA_PORT 5.4.6 DATASESSION register (address = 94h) Bit 15 Name MEM_RW [14: 0] DATA_LEN 5.4.7 CONFIG register (address = 96h) Bit 15 Name BCD_MODE_CTRL Type R/W Default value 1’b0 [14:13] BCD_MODE[1:0] R/W 2’b00 12 11 Reserved OSC_EN R/W 1’b1 1’b1 10 PLL_EN R/W 1’b1 Type R/W Description Start address for memory read / write Internal 24K RAM memory address from 0x0000 to 0x5FFF. Used by PIO and DMA. Table 5-17 Memory address register Type R/W Default value 16’b0 Description Data port Read / write data from / to memory must go through this port. Used by PIO and DMA. Table 5-18 Data port register Type R/W Default value 16’b0 Default value 1’b0 Description Memory read or write 0: Write data into memory 1: Read data from memory Used by PIO and DMA R/W 15’b0 Data length for memory read or write Preset the data length for memory read/write. The max data length is 24K. Used by PIO and DMA Table 5-19 Data session length register Description BCD Mode override control 0: External CPE0 and CPE1 pins configuration take effect. 1: BCD_MODE [1:0] register bits take effect BCD Mode setting 00: SDP Standard downstream port, VBUS current limit ≥ 500mA. 01: DCP Dedicated charging port. USB host not functional on this port, VBUS current limit ≤ 1.5A. 10: Reserved 11: CDP Charging downstream port, VBUS current limit ≤ 1.5A. Oscillator enable 0: Oscillator is not active 1: Oscillator is active Internal PLL enable Copyright © Future Technology Devices International Limited 30 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Bit Name Type Default value 9 8 Reserved HC_CLK_EN R/W 1’b1 1’b1 7 VBUS_OFF R/W 1’b1 6 PORT_OC_EN R/W 1’b0 5 BCD_EN R/W 1’b1 4 [3: 2] Reserved BURST_LEN RO R/W 1’b0 2’b00 1 ENABLE_DMA R/W 1’b0 0 DMA_ABORT R/W 1'b0 Clearance No.: FTDI# 318 Description 0: PLL is disable 1: PLL is enable Host controller clock enable 0: clocks are disabled 1: clocks are enabled VBUS power switch This bit controls the voltage on the VBUS on/off (default is “1”) by switch external power switcher. 0: VBUS on, PSW_N signal is active LOW. 1: VBUS off, PSW_N signal is not active. Port overcurrent enable 0: disable over current detection 1: enable over current detection BCD module enable 0: disable BCD module 1: enable BCD module DMA burst length 00: Single DMA burst 01: 4-cycle DMA burst 10: 8-cycle DMA burst 11: 16-cycle DMA burst Enable DMA 0: terminate DMA 1: enable DMA DMA abort 0: DMA continuous running 1: DMA abort implement Table 5-20 DMA configuration register 5.4.8 AUX_MEMADDR register (address = 98h) Bit Name Type [15: 0] AUX_START_ADDR_MEM R/W Default value 16’b0 Description Auxiliary start address of memory read / write When memory is occurred by DMA, use auxiliary start address for PIO memory access. Table 5-21 AUX Memory address register 5.4.9 AUX_DATAPORT register (address = 9Ah) Bit [15: 0] Name AUX_DATA_PORT 5.4.10 SLEEPTIMER register (address = 9Ch) Bit [15: 0] Name SLEEP_TIMER Type R/W Description Auxiliary data port When memory is occurred by DMA, use auxiliary data port for PIO memory access. Table 5-22 AUX data port register Type R/W Default value 16’b0 Default value 16’b0400 Description Sleep timer When host controller detected USB bus has no activity, the sleep timer will be started. When timer reduce to zero, the BUSINACTIVE interrupt will be generated, if the respective enable bit in the HCINTEN register is set. Default sleep timer is approximately 10ms. Table 5-23 Sleep timer register Copyright © Future Technology Devices International Limited 31 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 5.5 Interrupt registers 5.5.1 HCINTSTS register (address = A0h) Bit [15: 8] 7 Name Reserved WAKEUPINT 6 OCINT 5 CLKREADY 4 BUSINACTIVE 3 REMOTEWKINT 2 DMAEOTINT 1 SOFINT 0 MSOFINT 5.5.2 HCINTEN register (address = A4h) Bit Name Type RO R/WC Description Wake up interrupt on device connect or disconnect Indicates that wake up event is triggered. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No wake up event has occurred on the port when device connects or disconnects. 1: Wake up event has occurred on the port when device connects or disconnects. R/WC 1’b0 Overcurrent interrupt Indicates that overcurrent event is triggered. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No overcurrent event has occurred. 1: Overcurrent event has occurred. R/WC 1’b0 Clock ready Indicates that internal clock signals are running stable. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No clock ready event has occurred. 1: Clock ready event has occurred. R/WC 1’b0 USB Bus inactive interrupt Indicates that USB bus is inactive. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: USB bus is active. 1: USB bus is inactive. R/WC 1’b0 Remote Wake up interrupt Indicates INT was generated when the host controller remote wakeup. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No remote wake up. 1: Remote wake up event occurred. R/WC 1’b0 DMA EOT interrupt Indicates the DMA transfer completion. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No DMA transfer is completed. 1: DMA transfer is completed. R/WC 1’b0 SOF interrupt The INT line will be asserted if the respective bit enable is set. 0: No SOF event has occurred. 1: SOF event has occurred. R/WC 1’b0 uSOF interrupt The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No uSOF event has occurred. 1: uSOF event has occurred. Table 5-24 HC interrupt status register Type Default value 10’b0 1’b0 Default value Description Copyright © Future Technology Devices International Limited 32 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Bit [15: 8] 7 Name Reserved WAKEUPINT_EN Type RO R/W 6 OCINT_EN R/W 5 CLKREADY_EN R/W 4 R/W BUSINACTIVE_EN 3 R/W REMOTEWKINT _EN 2 DMAEOTINT_EN R/W 1 SOFINT_EN R/W 0 MSOFINT_EN R/W Table Clearance No.: FTDI# 318 Default value 10’b0 1’b0 Description Wake up interrupt enable on device connect or disconnect Control the INT generation when the device connects or disconnects as wake up events. 0: No INT will be generated when device connects or disconnects as wake up events. 1: INT will be asserted when device connects or disconnects as wake up events. 1’b0 Overcurrent interrupt enable Control the INT generation when the overcurrent event triggers 0: No INT will be generated after overcurrent event is triggered. 1: INT will be asserted after overcurrent event is triggered. 1’b0 Clock ready enable Control the INT generation when the internal clock signals are running stable 0: No INT will be generated after clock runs stable. 1: INT will be asserted after clock runs stable. 1’b0 USB Bus inactive enable Control the INT generation when the USB bus is inactive 0: No INT will be generated when the USB bus is inactive. 1: INT will be asserted when the USB bus is inactive. 1’b0 Remote wake up interrupt enable Control the INT generation when the host controller supports remote wake up 0: No INT will be generated when remote wake up occurred. 1: INT will be asserted when remote wake up occurred. 1’b0 DMA EOT interrupt enable Control assertion of INT on the DMA transfer completion 0: No INT will be generated when a DMA transfer is completed. 1: INT will be asserted when a DMA transfer is completed. 1’b0 SOF interrupt enable Control the INT generation at every SOF occurrence 0: No INT will be generated on SOF. 1: INT will be asserted at every SOF. 1’b0 uSOF interrupt enable Control the INT generation at every uSOF occurrence 0: No INT will be generated on uSOF. 1: INT will be asserted at every uSOF. 5-25 HC interrupt status register 5.6 USB testing registers Copyright © Future Technology Devices International Limited 33 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 5.6.1 Clearance No.: FTDI# 318 TESTMODE register (address = 50h) This register allows the firmware to set the DP and DM pins to predetermined states for testing purposes. Once force one test mode on host, must use test device on port connection. Note: Only one bit can be set to logic 1 at a time. After writing to this register, need add 150ns delay before writing this register again. The registers 70h and 74h both have same operation. Bit [31:5] 4 Name Reserved TST_LOOPBK Type RO R/W Default value 27’b0 1’b0 3 2 Reserved TST_PKT RO R/W 1’b0 1’b0 1 TST_KSTA R/W 1’b0 Description Turn on the loop back mode. When this bit is set to ‘1’, the host controller will enter the loop back mode. TEST_PACKET After entering the high speed and writing 1’b1 to this bit, users should command the DMA by the test parameter setting registers (0x70h and 0x74h) to move the packet data defined in the USB2.0 specification from the memory to FIFO. Then, send the packet to the transceiver. TEST_K 1’b0 Upon writing a ‘1,’ the D+/D- are set to the high-speed K state. TEST_J 0 TST_JSTA R/W Upon writing a ‘1,’ the D+/D- are set to the high-speed J state. Table 5-26 Test mode register 5.6.2 TESTPMSET1 register (address = 70h) This parameter setting register is only used by test packet Bit Name Type Default value [31:25] Reserved RO 7’b0 [24: 8] DMA_LEN R/W 11’h000 [7: 2] 1 0 Reserved DMA_TYPE DMA_START RO R/W R/W 6’b0 1’b0 mode. Description DMA Length The total bytes of the DMA controller will move. The maximum length is 1024 – 1 Bytes. DMA Type 1’b0 The transfer type of data moving 0: FIFO to Memory 1: Memory to FIFO DMA Start This bit informs the DMA controller to initiate the DMA transfer. Table 5-27 Test mode parameter setting 1 register 5.6.3 TESTPMSET2 register (address = 74h) This parameter setting register is only used by test packet mode. Bit Name Type Default value Description [31:0] DMA_MADDR R/W 32’b0 DMA Memory Address The starting address of memory to request the DMA transfer. Table 5-28 Test parameter setting 2 register Copyright © Future Technology Devices International Limited 34 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 6 Devices Characteristics and Ratings 6.1 Absolute Maximum Ratings The absolute maximum ratings for the FT313H device are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device. Parameter Storage Temperature Value -65°C to 150°C 168 Hours Floor Life (Out of Bag) At Factory Ambient (IPC/JEDEC J-STD-033A MSL Level 3 (30°C / 60% Relative Humidity) Compliant)* Ambient Temperature (Power Applied) -40°C to 85°C VCC Supply Voltage 0 to +5 VCC(I/O) Supply Voltage 0 to +5 DC Input Voltage – USBDP and USBDM -0.5 to +5 DC Input Voltage – OC_N (5V tolerant) -0.5 to +5.5 DC Input Voltage – All Other Inputs -0.5 to +5 Table 6-1 Absolute Maximum Ratings Unit Degrees C Hours Degrees C V V V V V * If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours. 6.2 DC Characteristics DC Characteristics (Ambient Temperature = -40°C to +85°C) Parameter Description Minimum Typical 1.62 1.8 VCCIO operating VCC(I/O) 2.25 2.5 supply voltage 2.97 3.3 VCC operating VCC(3V3) 2.97 3.3 supply voltage Icc1 Idle current 20 3.63 V Normal Operation - mA - mA uA Idle Normal Operation High speed data transfer USB suspend V Normal Operation V Normal Operation Operating current Icc3 USB suspend 200 Core supply 1.08 1.2 1.32 voltage Internal 1.2V 1.2 regulator voltage Table 6-2 Operating Voltage and Current VOUT(1V2) Parameter Voh Vol Vih Vil Vth Ipu Rpu Ipd Description Output Voltage High Output Voltage Low Input High Voltage Input Low Voltage Schmitt Hysteresis Voltage Input pull-up current Input pull-up resistance equivalent Input pull-down current 35 Units V V V Icc2 VCC(1V2) - Maximum 1.98 2.75 3.63 Conditions Normal Operation Minimum Typical Maximum Units Conditions 2.4 3.3 - V Ioh=8mA - - 0.4 V Iol=8mA 2.0 - - 0.8 V V - 0.3 0.45 0.5 V - 25 42 60 uA Vin = 0V 120K 78K 60K ohm Vin = 0V 25 42 60 uA Vin = VCC(I/O) Copyright © Future Technology Devices International Limited 35 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Input pull-down resistance 120K 78K equivalent Input leakage Iin -10 ±1 current Tri-state output Ioz -10 ±1 leakage current Table 6-3 Digital I/O Pin Characteristics (VCC(I/O) = Rpd Parameter Description Voh Output Voltage High Vol Output Voltage Low Vih Input High Voltage Vil Input Low Voltage Voh Output Voltage High Vol Output Voltage Low Vih Input High Voltage Vil Input Low Voltage ohm Vin = VCC(I/O) 10 uA Vin = VCC(I/O) or 0 10 uA - +3.3V, Standard Drive Level) Typical Maximum Units Conditions 2.5 - V Ioh=6mA - 0.4 V Iol=6mA - - V - - - 0.3VCC(I/O ) V - 0.5 V - 35 uA Vin = 0 78K ohm Vin = 0 35 uA Vin = VCC(I/O) 78K ohm Vin = VCC(I/O) 10 uA Vin = VCC(I/O) or 0 10 uA - Schmitt Hysteresis 0.28 0.39 Voltage Ipu Input pull-up current 14 23 Input pull-up Rpu resistance 160K 108K equivalent Input pull-down Ipd 14 23 current Input pull-down Rpd resistance 160K 108K equivalent Input leakage Iin -10 ±1 current Tri-state output Ioz -10 ±1 leakage current Table 6-4 Digital I/O Pin Characteristics (VCC(I/O) = Description 60K Minimum VCC(I/O)0.4 0.7VCC(I/O ) Vth Parameter Clearance No.: FTDI# 318 +2.5V, Standard Drive Level) Minimum VCC(I/O)0.4 0.7VCC(I/O ) Typical Maximum Units Conditions 1.8 - V Ioh=3.6mA - 0.4 V Iol=3.6mA - - V - - - 0.3VCC(I/O ) V - 0.5 V - 15 uA Vin = 0 130K ohm Vin = 0 15 uA Vin = VCC(I/O) 130K ohm Vin = VCC(I/O) 10 uA Vin = VCC(I/O) or 0 10 uA - Schmitt Hysteresis 0.25 0.35 Voltage Ipu Input pull-up current 6 10 Input pull-up Rpu resistance 270K 180K equivalent Input pull-down Ipd 6 10 current Input pull-down Rpd resistance 270K 180K equivalent Input leakage Iin -10 ±1 current Tri-state output Ioz -10 ±1 leakage current Table 6-5 Digital I/O Pin Characteristics (VCC(I/O) = Vth Copyright © Future Technology Devices International Limited +1.8V, Standard Drive Level) 36 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Parameter Description Vhscm Voltage of high speed data signal in the common mode Vhssq High speed squelch detection threshold Vhsdsc Vhsoi Vhsol Vhsoh Vchirpj Vchirpk Vdi Vcm Vse Vol Voh Rdrv High speed disconnection detection threshold Minimum Typical Maximum Input level for high speed Driver output impedance Units Conditions - -50 - 500 mV - - 100 mV 150 - - mV 625 - - mV - - 525 mV Output level for high speed High speed idle output voltage -10 10 (Differential) High speed low level output voltage -10 10 (Differential) High speed high level output voltage -360 400 (Differential) Chirp-J output 700 1100 voltage (Differential) Chirp-K output -900 -500 voltage (Differential) Input level for full speed and low speed Differential input 0.2 voltage sensitivity Differential common 0.8 2.5 mode voltage Single ended 0.8 2.0 receiver threshold Output level for full speed and low speed Low level output 0 0.3 voltage High level output 2.8 3.6 voltage Resistance 40.5 45 49.5 Clearance No.: FTDI# 318 Squelch is detected Squelch is not detected Disconnection is detected Disconnection is not detected mV - mV - mV - mV - mV - V |Vdp-Vdm| V - V - V - V - ohm Equivalent resistance used as an internal chip Table 6-6 USB I/O Pin (USBDP, USBDM) Characteristics Parameter Voh Vol Vih Vil Vopu* Iin Cin Description Output Voltage High Output Voltage Low Input High Voltage Input Low Voltage Output pull up voltage for 5V tolerant I/Os Minimum 2.4 2.0 - Typical - Maximum 0.4 0.8 Units V V V V Conditions Ioh=2mA~16mA Iol=2mA~16mA LVTTL LVTTL VCC(3V3)0.9 - - V Ipu = 1uA Input leakage current - ±1 - uA - ±1 - uA Input capacitor - 2.3 - pF Vin = VCC(3V3) or 0 Vin = 5V or 0 VCC(3V3) with 5V tolerant I/O Table 6-7 5V Tolerant Pin (PSW_N, OC_N, VBUS) Characteristics Copyright © Future Technology Devices International Limited 37 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 Note*: This parameter is to indicate that the pull up resistor for the 5V tolerant I/Os cannot reach VCC(3V3) DC level even without DC loading current. 6.3 AC Characteristics AC Characteristics (Ambient Temperature = -40°C to +85°C) System clock dynamic characteristics: Parameter Minimum Crystal oscillator Clock frequency External clock input external clock jitter clock duty cycle 45 Input voltage on pin X1/CLKIN Value Typical Maximum Unit 12.00 19.20 24.00 - MHz - 500 ps 50 55 % 3.3 - V Recommended accuracy of the clock frequency is 50ppm for the crystal. Table 6-8 System clock characteristics Analog I/O pins (DP/DM) dynamic characteristics: Parameter Thsr Thsf Description Minimum Typical Maximum Driver characteristic for high speed High speed 500 differential rise time High speed 500 differential fall time Driver characteristic for full speed Units Conditions ps - ps - Tfr Rise time of DP/DM 4 - 20 ns Tff Fall time of DP/DM 4 - 20 ns Tfrma Differential rise/fall time matching 90 - 110 % Cl=50pF 10%~90% of |Voh–Vol| Cl=50pF 10%~90% of |Voh–Vol| The first transition exclude from the idle mode Driver characteristic for low speed Tlr Rise time of DP/DM 75 - 300 ns Tlf Fall time of DP/DM 75 - 300 ns Tlrma Differential rise/fall time matching 80 - 125 % Cl=200pF~600pF 10%~90% of |Voh–Vol| Cl=200pF~600pF 10%~90% of |Voh–Vol| The first transition exclude from the idle mode Table 6-9 Analog I/O pins characteristics Copyright © Future Technology Devices International Limited 38 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 6.4 Timing 6.4.1 PIO timing SRAM PIO timing characteristics (Ambient Temperature = -40°C to +85°C) Parameter Tcs Tch Tcp Tasrw Tahrw Tap Twc Twp Tdh Tdadvh Toe Trp Trc VCC(I/O)=1.8 V Min Max Description CS_N setup time before WR_N / RD_N low CS_N hold time after WR_N / RD_N high CS_N pulse width for read CS_N pulse width for write address setup time before WR_N / RD_N low Address Hold Time after WR_N/RD_N LOW Address Latch Pulse Width Write Cycle Time WR_N Pulse Width RD_N High to Output Hi-Z WR_N High to Input Hi-Z DATA Setup Time before DATA Latch RD_N Low to DATA Output Enable RD_N Pulse Width Read Cycle Time VCC(I/O)=2.5 V Min Max VCC(I/O)=3.3 V Min Max 0 - 0 - 0 - 0 - 0 - 0 - 40 - 40 - 40 - 40 - 40 - 40 - 0 - 0 - 0 - 0 - 0 - 0 - Unit ns ns ns ns ns ns ns 80 40 - 79 40 - 78.5 40 - 4 9 4 7 4 6 0 - 0 - 0 - 6 - 6 - 6 - 8 - 7 - 6 - 40 80 - 40 79.5 - 40 79 - ns ns ns ns ns ns ns ns Table 6-10 SRAM PIO timing Copyright © Future Technology Devices International Limited 39 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Toe Tdadvh AD[15:0] Clearance No.: FTDI# 318 Tdh Data Tasrw Tahrw A[7:0] Address ALE/ADV_N CLE Trp RD_N/RE_N/ OE_N Tch Tcs CS_N/CE_N Tcp WR_N/WE_N Trc Figure 6-1 Read in SRAM mode Tdadvh AD[15:0] Tdh Data Tasrw Tahrw A[7:0] Address ALE/ADV_N CLE Twp WR_N/WE_N Tch Tcs CS_N/CE_N Tcp RD_N/RE_N/ OE_N Twc Figure 6-2 Write in SRAM mode Copyright © Future Technology Devices International Limited 40 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 NOR PIO timing characteristics (Ambient Temperature = -40°C to +85°C) Paramete r Tch Tcsadval Tah Tas Tap Twc Twp Tdh Tdadvh Toe Tbds Trp Trc VCC(I/O)=1.8 V Min Max Description CS_N hold time after WR_N / RD_N high CS_N setup time before Address Latch Address Hold Time after Address Latch Address Setup Time before Address Latch Address Latch Pulse Width Write Cycle Time WR_N Pulse Width RD_N High to Output Hi-Z WR_N High to Input Hi-Z DATA Setup Time before DATA Latch RD_N Low to DATA Output Enable Ready to WR_N/RD_N Low RD_N Pulse Width Read Cycle Time AD[15:0] VCC(I/O)=3.3 V Min Max 0 - 0 - 0 - 6.5 - 6.5 - 6 - 0 - 0 - 0 - 6 - 6 - 5 - 10 - 10 - 10 - 80 40 - 78.5 40 - 78.5 40 - 4 8 4 7 4 7 0 - 0 - 0 - 6 - 5 - 5 - 8 - 6 - 5 - 5 - 5 - 5 - - 40 79 - 40 40 80 79 Table 6-11 NOR PIO timing Tah Tas VCC(I/O)=2.5 V Min Max Toe Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Tdh Address Data Tbds Tap ALE/ADV_N CLE RD_N/RE_N/ OE_N Trp Tcsadval Tch CS_N/CE_N Trc WR_N/WE_N Figure 6-3 Read in NOR mode Copyright © Future Technology Devices International Limited 41 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Tah Tas AD[15:0] Tdh Tdadvh Address Clearance No.: FTDI# 318 Data Tbds Tap ALE/ADV_N CLE RD_N/DS_N/ RE_N/OE_N Tcsadval Tch CS_N/CE_N Twc WR_N/RW_N/ WE_N Twp Figure 6-4 Write in NOR mode General Multiplex PIO timing characteristics (Ambient Temperature = -40°C to +85°C) Parameter Tch Tcsadval Tah Tas Tap Twc Twp Tdh Tdadvh Toe Tbds Trp Trc Description VCC(I/O)=1.8 V Min Max CS_N hold time after WR_N / RD_N 0 high CS_N setup time before Address 7.5 Latch Address Hold Time 0 after Address Latch Address Setup Time before 7 Address Latch Address Latch 10 Pulse Width Write Cycle Time 80 WR_N Pulse Width 40 RD_N High to 4 Output Hi-Z WR_N High to 0 Input Hi-Z DATA Setup Time 6.5 before DATA Latch RD_N Low to DATA 8 Output Enable Ready to 5 WR_N/RD_N Low RD_N Pulse Width 40 Read Cycle Time 80 Table 6-12 General VCC(I/O)=2.5 V Min Max VCC(I/O)=3.3 V Min Max Unit ns - 0 - 0 - - 6.5 - 6.5 - - 0 - 0 - - 6 - 6 - - 10 - 10 - - 78.5 40 - 78.5 40 - 9 4 6.5 3.5 6 - 0 - 0 - - 5 - 5 - - 6 - 5 - - 5 - 5 - 40 79 - ns ns ns 40 79 Multiplex PIO timing Copyright © Future Technology Devices International Limited ns ns ns ns ns ns ns ns ns ns 42 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Tas AD[15:0] Tah Toe Clearance No.: FTDI# 318 Tdh Address Data Tbds Tap ALE/ADV_N CLE RD_N/RE_N/ OE_N Trp Tcsadval Tch CS_N/CE_N Trc WR_N/WE_N Figure 6-5 Read in General Multiplex mode Tas AD[15:0] Tah Tdadvh Address Tdh Data Tbds Tap ALE/ADV_N CLE RD_N/RE_N/ OE_N Tcsadval Tch CS_N/CE_N WR_N/WE_N Twp Twc Figure 6-6 Write in General Multiplex mode Copyright © Future Technology Devices International Limited 43 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 6.4.2 Clearance No.: FTDI# 318 DMA timing DMA timing characteristics (Ambient Temperature = -40°C to +85°C) Parameter Description DREQ Set-up Time before DACK Assertion DACK De-assertion to Next DREQ Assertion Time DREQ Hold Time after Last Strobe Assertion RD_N/WR_N Pulse Width Data Valid Time after RD_N Assertion Read Data Hold Time after RD_N Deasserts Write Data Hold Time after WR_N Deassertion Write Data Set-up Time before WR_N De-assertion DACK Set-up Time before RD_N/WR_N Assertion DACK De-assertion after RD_N/WR_N De-assertion DMA Read/Write Cycle Time Table 6-13 DMA timing Tsudreqdack Tddackdreq Thdreqdack Trwp Toe Trdh Twdh Tdadvh Tsudackrw Trwdack Tcyc Min Max - Unit 18 - ns - 35 ns 40 8 4 9 ns ns ns 0 - ns 6 - ns 0 - ns 0 - ns 80 - ns 0 ns DREQ Tsudreqdack DACK Thdreqdack Trwp Tcyc Tsudackrw Tddackdreq RD_N/ WR_N Toe Trwdack Trdh DATA[15:0] (read) Tdadvh DATA[15:0] (write) Twdh DATA1 DATA2 DATAn Figure 6-7 DMA read and write Copyright © Future Technology Devices International Limited 44 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 7 Application Examples FT313H can be configured to communicate with a microcontroller uses 16-bit/8-bit SRAM asynchronous bus interface, NOR interface, and General Multiplex interface. An example schematic is show in Figure 7-1. See Note on following page regarding RD_N signal (See Note) Copyright © Future Technology Devices International Limited 45 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 Figure 7-1 FT313H Chip Schematic Important Note: The configuration shown in Figure 7-1 above is for cases where the FT313H is the only device present on the processor bus. The FT313H drives the bus lines when CS_N is high and RD_N is low, and therefore bus contention will result if other devices also share the bus. When other devices share the processor bus, the OR gate shown in Figure 7-2 must be added to gate the RD_N signal with CS_N. This avoids the FT313H driving the bus lines and causing contention with other slaves present. Figure 7-2 OR Gate required when multiple devices present on the parallel bus 7.1 Examples of Bus Interface connection 7.1.1 16-Bit SRAM asynchronous bus interface FT313H CS_E/CS_N Microcontroller CS_N OE_N/RE_N/RD_N RD_N WE_N/WR_N WR_N AD A INT AD A INT DACK DACK DREQ DREQ If DMA transfers are not used the DACK and DREQ signals may be left floating or the DACK signal may be terminated with external 10k ohm pull-down resistor. If the microcontroller has no AD pin for 16-bit wide devices, the unused AD signal with must be terminated with an external 10k ohm pull-down resistor. Copyright © Future Technology Devices International Limited 46 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 7.1.2 Clearance No.: FTDI# 318 8-Bit SRAM asynchronous bus interface FT313H Microcontroller CS_E/CS_N CS_N OE_N/RE_N/RD_N RD_N WE_N/WR_N WR_N AD A INT AD A INT DACK DACK DREQ DREQ 8-Bit SRAM bus interface doesn’t use high AD data bus, must terminate AD signals with external 10k ohm pull-down resistors. If DMA transfers are not used the DACK and DREQ signals may be left floating or the DACK signal may be terminated with external 10k ohm pull-down resistor. 7.1.3 16-Bit NOR asynchronous bus interface FT313H Microcontroller CS_E/CS_N CS_N OE_N/RE_N/RD_N OE_N WE_N/WR_N AD WE_N AD A INT ADV_N/ALE INT ADV_N 16-Bit NOR uses AD signals as address and data bus. Unused A address must be terminated with external 10k ohm pull-down resistor. If the microcontroller has no AD pin for 16-bit wide devices, the unused AD signal with must be terminated with an external 10k ohm pull-down resistor. 7.1.4 8-Bit NOR asynchronous bus interface FT313H Microcontroller CS_E/CS_N CS_N OE_N/RE_N/RD_N OE_N WE_N/WR_N WE_N AD AD A INT ADV_N/ALE INT ADV_N 8-Bit NOR uses AD signals as address and data bus. The unused high data bus AD and A address bus must be terminated with external 10k ohm pull-down resistors. Copyright © Future Technology Devices International Limited 47 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 7.1.5 Clearance No.: FTDI# 318 16-Bit General Multiplex asynchronous bus interface FT313H Microcontroller CS_E/CS_N CS_N OE_N/RE_N/RD_N RE_N WE_N/WR_N AD WE_N AD A INT ADV_N/ALE INT DACK ALE DACK DREQ DREQ 16-Bit General Multiplex uses AD signals as address and data bus. Unused A address must be terminated with external 10k ohm pull-down resistor. If the microcontroller has no AD pin for 16-bit wide devices, the unused AD signal with must be terminated with an external 10k ohm pull-down resistor. If DMA transfers are not used the DACK and DREQ signals may be left floating or the DACK signal may be terminated with external 10k ohm pull-down resistor. 7.1.6 8-Bit General Multiplex asynchronous bus interface FT313H Microcontroller CS_E/CS_N CS_N OE_N/RE_N/RD_N RE_N WE_N/WR_N WE_N AD AD A INT ADV_N/ALE INT DACK ALE DACK DREQ DREQ 8-Bit General Multiplex uses AD signals as address and data bus. The unused high data bus AD and A address bus must be terminated with external 10k ohm pull-down resistors. If DMA transfers are not used the DACK and DREQ signals may be left floating or the DACK signal may be terminated with external 10k ohm pull-down resistor. Copyright © Future Technology Devices International Limited 48 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 8 Package Parameters The FT313H is available in three different packages. The FT313HQ is the QFN-64 package, the FT313HL is the LQFP-64 package and the FT313HP is the TQFP-64 package. The solder reflow profile for all packages is described in following sections. 8.1 FT313H Package Markings 8.1.1 QFN-64 An example of the markings on the QFN package are shown in Figure 8-1. The FTDI part number is too long for the 64 QFN package so in this case the last two digits are wrapped down onto the date code line. 64 1 FTDI XXXXXXXXXX FT313HQ YYWW-B Line 1 – FTDI Logo Line 2 – Wafer Lot Number Line 3 – FTDI Part Number Line 4 – Date Code, Revision Figure 8-1 QFN Package Markings Notes: 1. YYWW = Date Code, where YY is year and WW is week number 2. Marking alignment should be centre justified 3. Laser Marking should be used 8.1.2 LQFP-64 An example of the markings on the LQFP package are shown in Figure 8-2. 64 1 FTDI XXXXXXXXXX FT313HL YYWW-B Line 1 – FTDI Logo Line 2 – Wafer Lot Number Line 3 – FTDI Part Number Line 4 – Date Code, Revision Figure 8-2 LQFP Package Markings Copyright © Future Technology Devices International Limited 49 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 Notes: 1. YYWW = Date Code, where YY is year and WW is week number 2. Marking alignment should be centre justified 3. Laser Marking should be used 8.1.3 TQFP-64 An example of the markings on the TQFP package are shown in Figure 8-3. 64 1 FTDI XXXXXXXXXX FT313HP YYWW-B Line 1 – FTDI Logo Line 2 – Wafer Lot Number Line 3 – FTDI Part Number Line 4 – Date Code, Revision Figure 8-3 TQFP Package Markings Notes: 1. YYWW = Date Code, where YY is year and WW is week number 2. Marking alignment should be centre justified 3. Laser Marking should be used Copyright © Future Technology Devices International Limited 50 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 8.2 QFN-64 Package Dimensions Figure 8-4 QFN-64 Package Markings Copyright © Future Technology Devices International Limited 51 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 8.3 LQFP-64 Package Dimensions Figure 8-5 LQFP-64 Package Markings Copyright © Future Technology Devices International Limited 52 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 8.4 TQFP-64 Package Dimensions Figure 8-6 TQFP-64 Package Markings Copyright © Future Technology Devices International Limited 53 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 8.5 Solder Reflow Profile The FT313H is supplied in Pb free QFN-64, LQFP-64 and TQFP-64 packages. The recommended solder reflow profile for all package options is shown in Figure 8-7. . Temperature, T (Degrees C) tp Tp Critical Zone: when T is in the range TL to Tp Ramp Up TL tL TS Max Ramp Down TS Min tS Preheat 25 T = 25º C to TP Time, t (seconds) Figure 8-7 FT313H Solder Reflow Profile The recommended values for the solder reflow profile are detailed in Table 8-1. Values are shown for both a completely Pb free solder process (i.e. the FT313H is used with Pb free solder), and for a non-Pb free solder process (i.e. the FT313H is used with non-Pb free solder). Profile Feature Pb Free Solder Process Non-Pb Free Solder Process Average Ramp Up Rate (Ts to Tp) 3°C / second Max. 3°C / Second Max. Preheat - Temperature Min (Ts Min.) - Temperature Max (Ts Max.) - Time (ts Min to ts Max) 150°C 200°C 60 to 120 seconds 100°C 150°C 60 to 120 seconds Time Maintained Above Critical Temperature TL: 217°C - Temperature (TL) 60 to 150 seconds - Time (tL) Peak Temperature (Tp) 260°C Time within 5°C of actual Peak 20 to 40 seconds Temperature (tp) Ramp Down Rate 6°C / second Max. Time for T= 25°C to Peak Temperature, 8 minutes Max. Tp Table 8-1 Reflow Profile Parameter Values Copyright © Future Technology Devices International Limited 183°C 60 to 150 seconds 240°C 20 to 40 seconds 6°C / second Max. 6 minutes Max. 54 FT313H USB2.0 HS Host Controller Datasheet Version 1.3 Document No.: FT_000589 Clearance No.: FTDI# 318 9 Contact Information Head Office – Glasgow, UK Unit 1, 2 Seaward Place, Centurion Business Park Glasgow G41 1HH United Kingdom Tel: +44 (0) 141 429 2777 Fax: +44 (0) 141 429 2758 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) sales1@ftdichip.com support1@ftdichip.com admin1@ftdichip.com Branch Office – Tigard, Oregon, USA 7130 SW Fir Loop Tigard, OR 97223 USA Tel: +1 (503) 547 0988 Fax: +1 (503) 547 0987 E-Mail (Sales) E-Mail (Support) E-Mail (General Enquiries) us.sales@ftdichip.com us.support@ftdichip.com us.admin@ftdichip.com Branch Office – Shanghai, China Branch Office – Taipei, Taiwan 2F, No. 516, Sec. 1, NeiHu Road Taipei 114 Taiwan, R.O.C. Tel: +886 (0) 2 8797 1330 Fax: +886 (0) 2 8751 9737 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) tw.sales1@ftdichip.com tw.support1@ftdichip.com tw.admin1@ftdichip.com Room 1103, No. 666 West Huaihai Road, Changning District Shanghai, 200052 China Tel: +86 21 62351596 Fax: +86 21 62351595 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) cn.sales@ftdichip.com cn.support@ftdichip.com cn.admin@ftdichip.com Web Site http://ftdichip.com System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level performance requirements. All application-related information in this document (including application descriptions, suggested FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640 Copyright © Future Technology Devices International Limited 55