VNC2-48L1B-TRAY

Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Future Technology Devices International Ltd Vinculum-II Embedded Dual USB Host Controller IC Vinculum-II is FTDI’s 2nd generation of USB Host device. The CPU has been upgraded from the previous VNC1L device, dramatically increasing the processing power. The IC architecture has been designed to take care of most of the general USB data transfers, thus freeing up processing power for user applications. Flash and RAM memory have been increased providing larger user areas of memory for the designer to incorporate his own code. The designers also have the ability to create their own firmware using the new suite of software development tools. VNC2 has the following advanced features:  Embedded processor core  16 bit Harvard architecture  Two full-speed or low-speed USB 2.0 interfaces capable of host or slave functions  256kbytes on-chip E-Flash Memory (128k x 16-bits)  16kbytes on-chip Data RAM (4k x 32bits  Programmable UART up to 6Mbaud  Two SPI (Serial Peripheral) slave interfaces and one SPI master interface  Eight bit wide FIFO Interface  Firmware upgrades via UART, SPI, and FIFO interface  12MHz oscillator using external crystal  General-purpose timers  +3.3V single supply operation with 5V safe inputs  Software development suite of tools to create customised firmware. Compiler Linker – Debugger – IDE  Available in six RoHS compliant packages - 32 LQFP, 32 QFN, 48 LQFP, 48 QFN, 64 LQFP and 64 QFN  VNC2-48L1 package option compatible with VNC1L-1A  44 configurable I/O pins on the 64 pin device, 28 I/O pins on the 48 pin device and 12 I/O on the 32 pin device using the I/O multiplexer  -40°C to +85°C extended operating temperature range  Simultaneous multiple file access on BOMS devices  Eight Pulse Width Modulation outputs to allow connectivity with motor control applications  Reduced power modes capability  Variable instruction length  Debugger interface module  Native support for 8, 16 and 32 bit data types  System Suspend Modes Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use. Copyright © Future Technology Devices International Limited 1 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 1 Typical Applications  Add USB host capability to embedded products  Interface USB Flash drive to MCU/PLD/FPGA – data storage and firmware updates  Mobile phone to USB Flash drive*  GPS to mobile phone interface  Instrumentation USB Flash drive*  Data-logger USB Flash drive*  USB Flash drive data storage or firmware updates  Set Top Box - USB device interface  USB Flash drive to USB Flash drive file transfer interface  GPS tracker with USB Flash disk storage  USB webcam  Digital camera to USB Flash drive*  Flash drive to SD Card data transfer  PDA to USB Flash drive*  Vending machine connectivity  MP3 Player to USB Flash drive or other USB slave device interface  TLM Serial converter  Geotagging of photos – GPS location linked to image  OSI Wireless Interface  USB wireless process controller  Motorcycle system telemetry logging  Telecom system calls logging to replace printer log  Medical systems  PWM applications for motor control applications e.g. Toys  FPGA Interfacing  Data logging * Or similar USB slave device interface e.g. USB external drive. 1.1 Part Numbers Part Number VNC2-64L VNC2-64Q VNC2-48L VNC2-48Q VNC2-32L VNC2-32Q Package 64 Pin LQFP 64 Pin QFN 48 Pin LQFP 48 Pin QFN 32 Pin LQFP 32 Pin QFN Table 1.1 Part Numbers Please refer to Section 11 for all package mechanical parameters. 1.2 USB Compliant At time of writing this data sheet, VNC2 has not completed USB compliancy testing. Copyright © Future Technology Devices International Limited 2 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 2 VNC2 Block Diagram For a description of each function please refer to Section 4. XTOUT UART XTIN Oscillator/ PLL Internal Clocks and Timers PWMs FIFO Interface Program Memory Bus Flash Programmer 256K Bytes E-FLASH (64K x 32) Debugger SPI Master Peripheral Bus Input / Output Multiplexer SPI Slave 1 Embedded CPU SPI Slave 0 DMA 0 GPIOS DMA 1 DMA 2 DMA 3 Debugger I/F USB1DP USB1DM USB2DP USB2DM USB Host/ Device Transceiver 0 USB Host/ Device Transceiver 1 USB Host/ Device Controller Data Memory Bus General Purpose Timers 16K Bytes Data Ram (4K x 32) 8 bit bus 32 bit bus USB Host/ Device Controller Figure 2.1 Simplified VNC2 Block Diagram Copyright © Future Technology Devices International Limited 3 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Table of Contents 1 Typical Applications....................................................... 2 1.1 Part Numbers ............................................................................. 2 1.2 USB Compliant ........................................................................... 2 2 VNC2 Block Diagram ...................................................... 3 3 Device Pin Out and Signal Description Summary ........... 7 3.1 Pin Out - 32 pin LQFP ................................................................. 7 3.2 Pin Out - 32 pin QFN .................................................................. 8 3.3 Pin Out - 48 pin LQFP ................................................................. 9 3.4 Pin Out - 48 pin QFN ................................................................ 10 3.5 Pin Out - 64 pin LQFP ............................................................... 11 3.6 Pin Out - 64 pin QFN ................................................................ 12 3.7 VNC2 Schematic Symbol 32 Pin ............................................... 13 3.8 VNC2 Schematic symbol 48 Pin ................................................ 14 3.9 VNC2 Schematic symbol 64 Pin ................................................ 15 3.10 Pin Configuration USB and Power .......................................... 16 3.11 Miscellaneous Signals ............................................................ 16 3.12 Pin Configuration Input / Output .......................................... 17 4 Function Description ................................................... 19 4.1 Key Features ............................................................................ 19 4.2 Functional Block Descriptions .................................................. 19 4.2.1 Embedded CPU ......................................................................................... 19 4.2.2 Flash Module ............................................................................................ 19 4.2.3 Flash Programming Module......................................................................... 19 4.2.4 Input / Output Multiplexer Module ............................................................... 19 4.2.5 Peripheral DMA Modules 0, 1, 2 & 3 ............................................................. 20 4.2.6 RAM Module ............................................................................................. 20 4.2.7 Peripheral Interface Modules ...................................................................... 20 4.2.8 USB Transceivers 0 and 1 .......................................................................... 20 4.2.9 USB Host / Device Controllers ..................................................................... 20 4.2.10 12MHz Oscillator ....................................................................................... 20 4.2.11 Power Saving Modes and Standby mode ...................................................... 21 5 5.1 I/O Multiplexer ........................................................... 22 I/O Peripherals Signal Names ................................................. 26 Copyright © Future Technology Devices International Limited 4 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 5.2 I/O Multiplexer Configuration .................................................. 27 5.3 I/O Mux Group 0 ...................................................................... 28 5.4 I/O Mux Group 1 ...................................................................... 28 5.5 I/O Mux Group 2 ...................................................................... 29 5.6 I/O Mux Group 3 ...................................................................... 29 5.7 I/O Mux Interface Configuration Example ............................... 30 6 Peripheral Interfaces .................................................. 31 6.1 UART Interface ........................................................................ 31 6.1.1 6.2 UART Mode Signal Descriptions ................................................................... 32 Serial Peripheral Interface – SPI Modes .................................. 33 6.2.1 6.3 SPI Clock Phase Modes .............................................................................. 34 Serial Peripheral Interface – Slave .......................................... 35 6.3.1 SPI Slave Signal Descriptions ..................................................................... 36 6.3.2 Full Duplex ............................................................................................... 36 6.3.3 Half Duplex, 4 pin ..................................................................................... 38 6.3.4 Half Duplex, 3 pin ..................................................................................... 39 6.3.5 Unmanaged Mode ..................................................................................... 40 6.3.6 VNC1L Legacy Interface ............................................................................. 41 6.4 Serial Peripheral Interface – SPI Master .................................. 45 6.4.1 6.5 SPI Master Signal Descriptions .................................................................... 46 Debugger Interface .................................................................. 47 6.5.1 6.6 Debugger Interface Signal description ......................................................... 47 Parallel FIFO – Asynchronous Mode ......................................... 48 6.6.1 FIFO Signal Descriptions ............................................................................ 48 6.6.2 Read / Write Transaction Asynchronous FIFO Mode ....................................... 49 6.7 Parallel FIFO – Synchronous Mode ........................................... 50 6.7.1 Read / Write Transaction Synchronous FIFO Mode ......................................... 51 6.8 General Purpose Timers ........................................................... 52 6.9 Pulse Width Modulation ........................................................... 52 6.10 General Purpose Input Output............................................... 53 7 USB Interfaces ............................................................ 54 8 Firmware ..................................................................... 55 8.1 RTOS ........................................................................................ 55 8.2 Device drivers .......................................................................... 55 8.3 Firmware – Software Development Toolchain .......................... 55 Copyright © Future Technology Devices International Limited 5 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 8.4 9 Clearance No.: FTDI# 143 Precompiled Firmware ............................................................. 56 Device Characteristics and Ratings .............................. 57 9.1 Absolute Maximum Ratings ...................................................... 57 9.2 DC Characteristics .................................................................... 57 9.3 ESD and Latch-up Specifications .............................................. 58 10 Application Examples .................................................. 59 10.1 Example VNC2 Schematic (MCU – UART Interface) ............... 59 11 Package Parameters .................................................... 60 11.1 VNC2 Package Markings ....................................................... 60 11.2 VNC2, LQFP-32 Package Dimensions ..................................... 61 11.3 VNC2, QFN-32 Package Dimensions ...................................... 61 11.4 VNC2, LQFP-48 Package Dimensions ..................................... 62 11.5 VNC2, QFN-48 Package Dimensions ...................................... 63 11.6 VNC2, LQFP-64 Package Dimensions ..................................... 64 11.7 VNC2, QFN-64 Package Dimensions ...................................... 65 11.8 Solder Reflow Profile ............................................................. 66 12 Contact Information .................................................... 68 Appendix A – References ................................................... 69 Document References ...................................................................... 69 Acronyms and Abbreviations............................................................ 70 Appendix B – List of Figures and Tables ............................. 71 List of Tables.................................................................................... 71 List of Figures .................................................................................. 72 Appendix C – Revision History ........................................... 74 Copyright © Future Technology Devices International Limited 6 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 3 Device Pin Out and Signal Description Summary VNC2 is available in six packages: 32 pin LQFP, 32 pin QFN, 48 pin LQFP (pin compatible with VNC1L), 48 pin QFN, 64 pin LQFP and 64 pin QFN. Figure 3.3 shows how the VNC2 pins map to the VNC1L pins (VNC2 pins labelled in bold text): IO BUS6 25 IO BUS7 26 GND Core 27 VCCIO 3.3V 28 IO BUS8 29 IO BUS9 30 IO BUS10 IO BUS11 IO BUS5 IO BUS4 VCCIO 3.3V USB2DM USB2DP GND Core USB1DM USB1DP 24 23 22 21 20 19 18 17 3.1 Pin Out - 32 pin LQFP 16 GND IO 15 IO BUS3 14 IO BUS2 13 VCCIO 3.3V 12 IO BUS1 11 IO BUS0 31 10 RESET# 32 9 PROG# FTDI 1 2 3 4 5 6 7 8 GND Core 3.3V VREG IN 1.8V VCC PLL IN XTIN XTOUT GND PLL 1.8V VREG OUT NC XXXXXXXXXX VNC2-32L1A YYWW Figure 3.1 32 Pin LQFP – Top Down View Copyright © Future Technology Devices International Limited 7 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 IO BUS5 IO BUS4 VCCIO 3.3V USB2DM USB2DP GND Core USB1DM USB1DP 24 23 22 21 20 19 18 17 3.2 Pin Out - 32 pin QFN IO BUS6 25 16 GND IO IO BUS7 26 15 IO BUS3 GND Core 27 14 IO BUS2 VCCIO 3.3V 28 13 VCCIO 3.3V IO BUS8 29 12 IO BUS1 IO BUS9 30 11 IO BUS0 IO BUS10 31 10 RESET# IO BUS11 32 9 PROG# FTDI 4 5 6 7 8 XTIN XTOUT GND PLL 1.8V VREG OUT NC 3 1.8V VCC PLL IN 2 3.3V VREG IN GND Core 1 XXXXXXXXXX VNC2-32Q 1A YYWW Figure 3.2 32 Pin QFN – Top Down View Copyright © Future Technology Devices International Limited 8 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 IO BUS18 ADBUS6 37 IO BUS19 ADBUS7 38 GND Core GND 39 VCCIO 3.3V VCCIO 40 IO BUS20 ACBUS0 41 IO BUS21 ACBUS1 42 IO BUS22 ACBUS2 43 IO BUS23 ACBUS3 44 IO BUS24 ACBUS4 45 IO BUS25 ACBUS5 46 IO BUS26 ACBUS6 47 IO BUS27 ACBUS7 48 IO BUS17 IO BUS16 IO BUS15 IO BUS14 IO BUS13 IO BUS12 VCCIO 3.3V USB2DM USB2DP GND Core USB1DM USB1DP ADBUS5 ADBUS4 ADBUS3 ADBUS2 ADBUS1 ADBUS0 VCCIO USB2DM USB2DP GND USB1DM USB1DP 36 35 34 33 32 31 30 29 28 27 26 25 3.3 Pin Out - 48 pin LQFP FTDI XXXXXXXXXX VNC2-48L1A YYWW 24 GND GND IO 23 BCBUS3 IO BUS11 22 BCBUS2 IO BUS10 21 BCBUS1 IO BUS9 20 BCBUS0 IO BUS8 19 BDBUS7 IO BUS7 18 BDBUS6 IO BUS6 17 VCCIO VCCIO 3.3V 16 BDBUS5 IO BUS5 15 BDBUS4 IO BUS4 14 BDBUS3 IO BUS3 13 BDBUS2 IO BUS2 1 2 3 4 5 6 7 8 9 10 11 12 GND VCC AVCC XTIN XTOUT AGND PLLFLTR TEST RESET# PROG# BDBUS0 BDBUS1 GND Core 1.8V VCC PLL IN XTIN XTOUT GND PLL 1.8V VREG OUT NC RESET# PROG# IO BUS0 IO BUS1 BOLD TEXT = VNC2 3.3V VREG IN ITALIC TEXT = VNC1 Figure 3.3 48 Pin LQFP – Top Down View Copyright © Future Technology Devices International Limited 9 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 IOBUS17 IOBUS16 IOBUS15 IOBUS14 IOBUS13 IOBUS12 VCCIO 3.3V USB2DM USB2DP GND CORE USB1DM USB1DP 36 35 34 33 32 31 30 29 28 27 26 25 3.4 Pin Out - 48 pin QFN IOBUS18 37 24 GND IO IOBUS19 38 23 IOBUS11 GND 39 22 IOBUS10 21 IOBUS9 20 IOBUS8 19 IOBUS7 18 IOBUS6 17 VCCIO 3.3 V 16 IOBUS5 FTDI VCCIO 3.3V 40 IOBUS20 41 IOBUS21 42 IOBUS22 43 IOBUS23 44 IOBUS24 45 IOBUS25 46 15 IOBUS4 IOBUS26 47 14 IOBUS3 IOBUS27 48 13 IOBUS2 1 2 3 4 5 6 7 8 9 10 11 12 Gnd Core 3.3 VREG IN 1.8 VCC PLL IN XTIN XTOUT Gnd PLL 1.8 VREG OUT NC RESET# PROG# IOBUS0 IOBUS1 XXXXXXXXXX VNC2-48Q1A YYWW Figure 3.4 48 Pin QFN – Top Down View Copyright © Future Technology Devices International Limited 10 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 IO BUS29 IO BUS28 IO BUS27 IO BUS26 IO BUS25 IO BUS24 IO BUS23 IO BUS22 IO BUS21 IO BUS20 VCCIO 3.3V USB2DM USB2DP GND Core USB1DM USB1DP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 3.5 Pin Out - 64 pin LQFP IO BUS30 49 32 IO BUS19 IO BUS31 50 31 IO BUS18 IO BUS32 51 IO BUS33 52 GND Core 53 VCCIO 3.3V 54 IO BUS34 55 IO BUS35 56 IO BUS36 57 IO BUS37 58 IO BUS38 59 IO BUS39 60 IO BUS40 61 IO BUS41 FTDI XXXXXXXXXX VNC2-64L1A YYWW 30 GND IO 29 IO BUS17 28 IO BUS16 27 IO BUS15 26 IO BUS14 25 IO BUS13 24 IO BUS12 8 9 10 11 12 13 14 15 16 NC RESET# PROG# IO BUS0 IO BUS1 IO BUS2 IO BUS3 IO BUS4 IO BUS5 IO BUS6 1.8V VREG OUT 17 7 64 6 IO BUS43 5 IO BUS7 XTOUT IO BUS42 GND PLL IO BUS8 18 4 19 63 3 62 XTIN IO BUS9 1.8V VCC PLL IN VCCIO 3.3V 20 2 21 1 IO BUS10 GND Core IO BUS11 22 3.3V VREG IN 23 Figure 3.5 64 Pin LQFP – Top Down View Copyright © Future Technology Devices International Limited 11 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 IOBUS23 IOBUS22 IOBUS21 IOBUS20 VCCIO 3.3V USB2DM USB2DP GND CORE USB1DM USB1DP 43 42 41 40 39 38 37 36 35 34 33 IOBUS26 45 IOBUS25 IOBUS27 46 IOBUS24 IOBUS28 47 44 IOBUS29 48 3.6 Pin Out - 64 pin QFN IOBUS30 49 32 IOBUS19 IOBUS31 50 31 IOBUS18 IOBUS32 51 30 GND IO IOBUS33 52 29 IOBUS17 GND CORE 53 28 IOBUS16 VCCIO 3.3V 54 27 IOBUS15 IOBUS34 55 26 IOBUS14 IOBUS35 56 25 IOBUS13 IOBUS36 57 24 IOBUS12 IOBUS37 58 23 IOBUS11 IOBUS38 59 22 IOBUS10 IOBUS39 60 21 VCCIO 3.3V IOBUS40 61 20 IOBUS9 IOBUS41 62 19 IOBUS8 IOBUS42 63 18 IOBUS7 IOBUS43 64 17 IOBUS6 FTDI 16 14 IOBUS3 IOBUS5 13 IOBUS2 15 12 IOBUS1 IOBUS4 11 IOBUS0 8 NC 10 7 PROG# 6 1.8 VREG OUT 9 5 Gnd PLL RESET# 4 3 XTIN 2 1.8 VCC PLL IN XTOUT 1 Gnd Core 3.3 VREG IN XXXXXXXXXX VNC2-64Q1A YYWW Figure 3.6 64 Pin QFN – Top Down View Copyright © Future Technology Devices International Limited 12 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 3.7 VNC2 Schematic Symbol 32 Pin 2 28 22 13 V V C C C C I I O O 17 18 20 21 4 5 10 V R E G I N V C C I O USB1DP USB1DM 3 V C C P L L I N IOBUS1 USB2DP IOBUS2 USB2DM IOBUS3 IOBUS4 XTIN XTOUT PROG# 7 8 VREG OUT NC G N D G P N L D L 1 6 G N D G N D 11 12 14 15 23 24 IOBUS5 25 IOBUS6 26 IOBUS7 29 IOBUS8 30 IOBUS9 31 IOBUS10 32 IOBUS11 VNC2 32 Pin RESET# 9 IOBUS0 G N D 16 19 27 Figure 3.7 Schematic Symbol 32 Pin Copyright © Future Technology Devices International Limited 13 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 3.8 VNC2 Schematic symbol 48 Pin 40 30 17 V V C C C C I I O O 25 26 28 29 4 5 9 V C C I O 2 V R E G I N USB1DP USB1DM USB2DP USB2DM XTIN XTOUT VNC2 48 Pin RESET# 10 PROG# 7 8 VREG OUT NC G N D G P N L D L 1 6 3 V C C P L L I N IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 G N D G N D 12 13 14 15 16 IOBUS5 18 IOBUS6 19 IOBUS7 20 IOBUS8 21 IOBUS9 22 IOBUS10 23 IOBUS11 31 IOBUS12 32 IOBUS13 33 IOBUS14 34 IOBUS15 35 IOBUS16 36 IOBUS17 37 IOBUS18 38 IOBUS19 41 IOBUS20 42 IOBUS21 43 IOBUS22 44 IOBUS23 IOBUS24 G N D 11 IOBUS25 IOBUS26 IOBUS27 45 46 47 48 24 27 39 Figure 3.8 Schematic Symbol 48 Pin Copyright © Future Technology Devices International Limited 14 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 3.9 VNC2 Schematic symbol 64 Pin 54 38 21 V V C C C C I I O O 33 34 36 37 4 5 9 V C C I O 2 V R E G I N USB1DP USB1DM 3 V C C P L L I N USB2DP USB2DM XTIN XTOUT RESET# 10 PROG# VNC2 64 Pin 7 8 VREG OUT NC IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS25 IOBUS26 IOBUS27 IOBUS43 IOBUS28 63 12 13 14 15 16 IOBUS5 17 IOBUS6 18 IOBUS7 19 IOBUS8 20 IOBUS9 22 IOBUS10 23 IOBUS11 24 IOBUS12 25 IOBUS13 26 IOBUS14 27 IOBUS15 28 IOBUS16 29 IOBUS17 31 IOBUS18 32 IOBUS19 39 IOBUS20 40 IOBUS21 41 IOBUS22 42 IOBUS23 IOBUS24 64 11 43 44 45 46 47 48 IOBUS29 49 IOBUS30 50 IOBUS31 IOBUS42 62 IOBUS41 61 IOBUS40 60 IOBUS39 59 IOBUS38 58 IOBUS37 57 IOBUS36 G N D G P N L D L 1 6 IOBUS32 51 52 IOBUS33 55 IOBUS34 56 IOBUS35 G N D G N D G N D 30 35 53 Figure 3.9 Schematic Symbol 64 Pin Copyright © Future Technology Devices International Limited 15 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 3.10 Pin Configuration USB and Power Pin No Name Type 17 USB1DP I/O 26 18 USB1D M I/O 36 28 20 USB2DP I/O 37 29 21 64 pin 48 pin 32 pin 33 25 34 Pin No USB2D I/O M Table 3.1 Description USB host/slave port 1 - USB Data Signal integrated pull-up/pull-down resistor. USB host/slave port 1 - USB Data Signal integrated pull-up/pull-down resistor. USB host/slave port 2 - USB Data Signal integrated pull-up/pull-down resistor. USB host/slave port 2 - USB Data Signal integrated pull-up/pull-down resistor. USB Interface Group Name Type 1, 16, 19, 27 GND PWR Device ground supply pins. 2 3.3V VREGIN PWR +3.3V supply to the regulator. 64 pin 48 pin 32 pin 1, 30, 35, 53 1, 24, 27, 39 2 2 Plus with Minus with Plus with Minus with Description +1.8V supply to the internal clock multiplier. This pin requires a 100nF decoupling capacitor. 3 3* 3 1.8V VCC PLL IN PWR 6 6 6 GND PLL PWR 7 7* 7 VREG OUT Outpu t 21, 38, 54 17, 30, 40 13, 22, 28 * 48 pin LQFP package only – This power input is internally connected to VREG_OUT. All other packages need this pin connected to a 1.8V power source. Most common applications will connect this to VREG_OUT. Device analogue ground supply for internal clock multiplier. 1.8V output from regulator to device core * N/C on 48 pin LQFP package only. All other packages will typically need to connect pins 7 and 3. +3.3V supply to the input / output. Interface pins VCCIO PWR (IOBUS). Leaving the VCCIO unconnected will lead to unpredictable operation on the interface pins. Table 3.2 Power and Ground 3.11 Miscellaneous Signals Pin No Name Type 4 XTIN Input 5 5 XTOUT Outpu t 8 8 8 9 9 10 NC RESET # 64 pin 48 pin 32 pin 4 4 5 NC Input Description Input to 12MHz Oscillator Cell. Connect 12MHz crystal across pins 4 and 5. If driven by an external source, reference to 1.8V VCC PLL IN. Output from 12MHz Oscillator Cell. Connect 12MHz crystal across pins 4 and 5. No connect if XTIN is driven by an external source. No Connect (rev C) – (was TEST Rev A, B) Can be used by an external device to reset VNC2. Asserting PROG# on its own enables programming mode. Table 3.3 Miscellaneous Signal Group Note 1: # is used to indicate an active low signal. Note 2: Pin 9 and 10 are 5V safe inputs 10 10 9 PROG# Input Copyright © Future Technology Devices International Limited 16 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 3.12 Pin Configuration Input / Output VNC2 has multiple interfaces available for connecting to external devices. These are UART, FIFO, SPI slave, SPI master, GPIO and PWM. The Interface I/O Multiplexer is used to share the available I/O Pins between each peripheral. VNC2 is configured with default settings for the I/O pins however they can be easily changed to suit the needs of a designer. This is explained in Section 5 – I/O Multiplexer. Default configuration for each package type is shown in Table 3.4- Default I/O Configuration. The signal names are also indicated for the VNC1L device as it is pin-compatible with the 48 pin LQFP VNC2 device. Note: The default values of the pins listed in the following table are only available when the I/O Mux is enabled. A blank VNC2 chip defaults to all I/O pins as inputs. Pin No 64 Pin 48 Pin 32 Pin 11 11 11 12 12 12 13 13 14 14 14 15 15 15 23 16 16 24 17 18 25 18 19 26 19 20 29 20 21 30 22 22 31 23 23 32 24 31 - 25 32 - 26 33 - 27 34 - 28 35 - 29 36 - 31 37 - 32 38 - Name (VINC1L) 64 Pin Default 48 Pin Default 32 PIN Default Typ e Description IOBUS0 (BDBUS0) debug_if debug_if debug_if I/O GPIO Input pwm[1] gpio[A1] I/O GPIO Input pwm[2] gpio[A2] I/O GPIO Input pwm[3] gpio[A3] I/O GPIO fifo_data[0] spi_s0_clk uart_txd I/O GPIO fifo_data[1] spi_s0_mosi uart_rxd I/O GPIO fifo_data[2] spi_s0_miso uart_rts# I/O GPIO fifo_data[3] spi_s0_ss# uart_cts# I/O GPIO fifo_data[4] spi_m_clk spi_s0_clk I/O GPIO fifo_data[5] spi_m_mosi spi_s0_mosi I/O GPIO fifo_data[6] spi_m_miso spi_s0_miso I/O GPIO fifo_data[7] spi_m_ss_0# spi_s0_ss# I/O GPIO fifo_rxf# uart_txd I/O GPIO fifo_txe# uart_rxd I/O GPIO fifo_rd# uart_rts# I/O GPIO fifo_wr# uart_cts# I/O GPIO fifo_oe# uart_dtr# I/O GPIO Input uart_dsr# I/O GPIO Input uart_dcd# I/O GPIO Input uart_ri# I/O GPIO IOBUS1 (BDBUS1) IOBUS2 (BDBUS2) IOBUS3 (BDBUS3) IOBUS4 (BDBUS4) IOBUS5 (BDBUS5) IOBUS6 (BDBUS6) IOBUS7 (BDBUS7) IOBUS8 (BCBUS0) IOBUS9 (BCBUS1) IOBUS10 (BCBUS2) IOBUS11 (BCBUS3) IOBUS12 (ADBUS0) IOBUS13 (ADBUS1) IOBUS14 (ADBUS2) IOBUS15 (ADBUS3) IOBUS16 (ADBUS4) IOBUS17 (ADBUS5) IOBUS18 (ADBUS6) IOBUS19 (ADBUS7) Copyright © Future Technology Devices International Limited 17 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Pin No 64 Pin 48 Pin 32 Pin 39 41 - 40 42 - 41 43 - 42 44 - 43 45 - 44 46 - 45 47 - 46 48 - 47 - - 48 49 50 51 52 55 56 57 58 59 60 61 62 63 - - 64 - - Note: All GPIO are Name (VINC1L) IOBUS20 (ACBUS0) IOBUS21 (ACBUS1) IOBUS22 (ACBUS2) IOBUS23 (ACBUS3) IOBUS24 (ACBUS4) IOBUS25 (ACBUS5) IOBUS26 (ACBUS6) IOBUS27 (ACBUS7) 64 Pin Default 48 Pin Default uart_txd 32 PIN Default Clearance No.: FTDI# 143 Typ e Description uart_tx_active I/O GPIO uart_rxd gpio[A5] I/O GPIO uart_rts# gpio[A6] I/O GPIO uart_cts# gpio[A7] I/O GPIO uart_dtr# gpio[A0] I/O GPIO uart_dsr# gpio[A1] I/O GPIO uart_dcd# gpio[A2] I/O GPIO uart_ri# gpio[A3] I/O GPIO I/O GPIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO I/O GPIO uart_tx_acti ve IOBUS29 Input IOBUS30 Input IOBUS31 Input IOBUS32 spi_s0_clk IOBUS33 spi_s0_mosi IOBUS34 spi_s0_miso IOBUS35 spi_s0_ss# IOBUS36 spi_s1_clk IOBUS37 spi_s1_mosi IOBUS38 spi_s1_miso IOBUS39 spi_s1_ss# IOBUS40 spi_m_clk IOBUS41 spi_m_mosi IOBUS42 spi_m_miso spi_m_ss_0 IOBUS43 # Table 3.4 Default I/O Configuration 5V safe inputs IOBUS28 Copyright © Future Technology Devices International Limited 18 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 4 Function Description VNC2 is the second of FTDIs Vinculum family of Embedded USB host controller integrated circuit devices. VNC2 can encapsulate certain USB device classes by handling the USB Host Interface and data transfer functions using the in-built EMCU and embedded Flash memory. When interfacing to mass storage devices, such as USB Flash drives, VNC2 transparently handles the FAT file structure using a simple to implement command set. VNC2 provides a cost effective solution for introducing USB host capability into products that previously did not have the hardware resources to do so. VNC2 has an associated software development tool suite to allow users to create customised firmware. 4.1 Key Features VNC2 is a programmable SoC device with a powerful embedded microprocessor core and dual USB interfaces, large RAM and Flash capacity and the ability to develop and customise firmware using the VNC2 Toolchain. VNC2 has an enhanced feature list over and above VNC1L; however the 48 pin LQFP package is backward compatible with the VNC1L. 4.2 Functional Block Descriptions The following paragraphs describe each function within VNC2. Please refer to the block diagram shown in Figure 2.1 4.2.1 Embedded CPU The processor core is based on FTDIs proprietary 16-bit embedded MCU architecture. The EMCU has a Harvard architecture with separate code and data space. 4.2.2 Flash Module VNC2 has 256k bytes (128k x 16-bits) of embedded Flash (E-FLASH) memory. No special programming voltages are necessary for programming the on-board E-FLASH as these are provided internally on-chip. 4.2.3 Flash Programming Module The purpose of the flash programmer module is to perform all necessary operations for programming the flash, from general usage to first power on sequencing. This block is responsible for handling device firmware upgrades which can be accessed by the debugger interface, a USB cable or Flash drive interface. 4.2.4 Input / Output Multiplexer Module VNC2 peripheral interfaces are UART, SPI slave0, SPI slave1, SPI master, FIFO-Asynchronous, FIFOSynchronous, GPIO, debug interface and PWM. The I/O multiplexer allows the designer to select which peripherals are connected to the device I/O pins. The selectable peripheral interfaces are only limited by the number of I/O pins available. All peripherals are available across the package range except synchronous FIFO mode which cannot be selected on 32 pin packages. The available configurable I/O pins per package are as follows:    32 pin package – 12 I/O pins 48 pin package – 28 I/O pins 64 pin package – 44 I/O pins Table 4.1 lists the peripherals which can be multiplexed to I/O and the maximum number of pins required for each one. The designer can choose any mix of peripheral configurations as long as they are within the specific package I/O pin count. Depending on the design not all 9 UART pins need to be configured. Similarly the GIPO peripheral does not need all pins configured. Copyright © Future Technology Devices International Limited 19 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 E.g. The 48 pin package has 28 I/O pins which could be configured as UART – 9 pins, SPI Master – 5 pins, FIFO Asynchronous – 12 pins and GPIO – 2 pins. This makes a total of 28 pins. Please refer to Section 5 for a detailed description of the I/O multiplexer. Peripherals Maximum pins required UART 9 SPI Slave 0 4 SPI Slave 1 4 SPI Master 5 FIFO Asynchronous 12 FIFO Synchronous 14 GPIO 40 Debug 1 PWM 8 Table 4.1 - Peripheral Pin Requirements 4.2.5 Peripheral DMA Modules 0, 1, 2 & 3 The peripheral DMA has the capability to transfer data to and from an I/O device. The CPU can offload the transfer of data between the processor and the peripheral freeing the CPU to execute other instructions. The DMA module collects or transmits data from memory to an I/O address space; it is also capable of copying data in memory and transferring it to another location. The DMA is not accessible by the user as it automatically controlled by the CPU. 4.2.6 RAM Module The RAM module consists of 16k bytes on-chip (4k x 32-bits) data memory. The RAM is byte addressable. 4.2.7 Peripheral Interface Modules VNC2 has nine peripheral interface modules. Full descriptions of each module are described in Section 6.     Debugger Interface UART PWM FIFO     SPI Master SPI Slave 0 & 1 GPIO - General purpose I/O pins General purpose timers 4.2.8 USB Transceivers 0 and 1 Two USB transceiver cells provide the physical USB device interface supporting USB 1.1 and USB 2.0 standards. Low-speed and full-speed USB data rates are supported. Each output driver provides +3.3V level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB DATA IN, SE0 and USB Reset condition detection. These cells also include integrated internal USB pull-up or pull-down resistors as required for host or slave mode. 4.2.9 USB Host / Device Controllers These blocks handle the parallel-to-serial and serial-to-parallel conversion of the USB physical layer. This includes bit stuffing, CRC generation, USB frame generation and protocol error checking. The Host / Device controller is autonomous and therefore requires limited load from the CPU. 4.2.10 12MHz Oscillator The 12MHz Oscillator cell generates a 12MHz reference clock input to the Clock Multiplier PLL from an external 12MHz crystal. The external crystal is connected across Pin 4 – XTIN and Pin 5 – XTOUT in the configuration shown in Figure 10.1. Copyright © Future Technology Devices International Limited 20 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 4.2.11 Power Saving Modes and Standby mode VNC2 can be set to operate in three frequencies allowing the user to select a slower speed to reduce power consumption. Three operating frequencies available are 12MHz, 24MHz and normal operation of 48MHz. These operating modes can be configured using the RTOS. Full details are available in the RTOS manual available from the FTDI website. When a particular peripheral is not used, it is powered down internally thus saving power. Standby mode is available under firmware control, this mode puts the VNC2 in a state with no clocks running or system blocks powered. The device will wake up out of this mode by toggling any of the following signals: USB0/1 DP or DM, SPI slave 0 select (spi_s0_ss#), SPI slave 1select (spi_s1_ss#) or UART ring indicator (uart_ri#). Copyright © Future Technology Devices International Limited 21 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 5 I/O Multiplexer FTDI devices typically have multiple interfaces available to communicate with external devices. VNC2 has UART, SPI slave0, SPI slave1, SPI master, FIFO, GPIO, and PWM peripherals. The available packages for VNC2 provide any of these interfaces to be active on the available pins through the use of an I/O Multiplexer. Table 5.1 lists the signals available for each peripheral. Table 5.2 to Table 5.5 explains the use of the I/O multiplexer. Multiplexers are used to connect the VNC2 peripherals to the external IOBUS pins. This enables the designer to select which IOBUS pins he wishes to map a particular peripheral to. Peripheral signals are allocated to one of four groups, which connect to the I/O multiplexer. Each I/O peripheral signal can connect to one out of every four external IOBUS pins. The IOBUS pin that a peripheral signal can connect to is dictated by the peripheral signal’s group. For example, if a peripheral signal is allocated to group 0 then it can connect to IOBUS0, IOBUS4, IOBUS8, and IOBUS12 and so on. If a peripheral signal is allocated to group 1 then it can connect to IOBUS1, IOBUS5, IOBUS9, and IOBUS13 and so on. Figure 5.1 details the I/O multiplexer concept, where, for example, a white peripheral signal can connect to any white IOBUS pin; a green peripheral signal can connect to a green IOBUS pin. Figure 5.2, Figure 5.3 and Figure 5.4 give examples of connecting peripheral signals to differing IOBUS pins. The IO Multiplexer also provides the following features:   Ability to configure an I/O pad as an input, output or bidirectional pad. At power on reset, all pins are set as inputs by default. Whenever the I/O Mux is enabled the pins are configured as their default values listed Table 6 within section 3.12. Note: It is recommended not to reassign the debug interface signal (debug_if) from its default setting of IOBUS0 (Pin 11 on all packages). This assumes that the debug pin is required in the application design, if not; pin 11 can be assigned to any other group 0 signal. An application (IOMUX) within the RTOS is available to aid with pin configuration, Section 5.2 has more details. Further details of the IO Multiplexer are available within Application Note AN_139 Vinculum-II IO Mux Explained. Peripheral Pin IOBUS Pin uart_txd uart_rxd uart_rts# uart_cts# uart_dtr# uart_dsr# uart_dcd# uart_ri# uart_tx_active IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 IOBUS9 IOBUS10 IOBUS11 IOBUS12 IOBUS13 IOBUS14 IOBUS15 IOBUS16 IOBUS17 IOBUS18 IOBUS19 IOBUS20 IOBUS21 Key: Group 0 allocated pin Group 1 allocated pin Group 2 allocated pin Group 3 allocated pin IOBUS43 Figure 5.1 IOBUS to Group Relationship-64 Pin Copyright © Future Technology Devices International Limited 22 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Figure 5.2 details the UART, SPI slave0 and SPI master connecting to IOBUS pins: Peripheral Pin IOBUS Pin uart_txd uart_rxd uart_rts# uart_cts# uart_dtr# uart_dsr# uart_dcd# uart_ri# uart_tx_active IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 IOBUS9 IOBUS10 IOBUS11 IOBUS12 IOBUS13 IOBUS14 IOBUS15 IOBUS16 IOBUS17 IOBUS18 IOBUS19 IOBUS20 IOBUS21 IOBUS22 IOBUS23 IOBUS24 IOBUS25 IOBUS26 IOBUS27 IOBUS28 IOBUS29 IOBUS30 IOBUS31 spi_s0_clk spi_s0_mosi spi_s0_miso spi_s0_ss# spi_s1_clk spi_s1_mosi spi_s1_miso spi_s1_ss# spi_m_clk spi_m_mosi spi_m_miso spi_m_ss_0# spi_m_ss_1# gpio[A0] gpio[A1] gpio[A2] gpio[A3] gpio[A4] gpio[A5] gpio[A6] gpio[A7] IOBUS43 gpio[E7] Figure 5.2 IOBUS to UART, SPI slave0 and SPI master example Copyright © Future Technology Devices International Limited 23 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Figure 5.3 expands upon Figure 5.2 by moving the UART, SPI slave0 and SPI master signals to different IOBUS positions. The purpose of this diagram to highlight peripherals connected to differing IOBUS positions. Peripheral Pin IOBUS Pin uart_txd uart_rxd uart_rts# uart_cts# uart_dtr# uart_dsr# uart_dcd# uart_ri# uart_tx_active IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 IOBUS9 IOBUS10 IOBUS11 IOBUS12 IOBUS13 IOBUS14 IOBUS15 IOBUS16 IOBUS17 IOBUS18 IOBUS19 IOBUS20 IOBUS21 IOBUS22 IOBUS23 IOBUS24 IOBUS25 IOBUS26 IOBUS27 IOBUS28 IOBUS29 IOBUS30 IOBUS31 spi_s0_clk spi_s0_mosi spi_s0_miso spi_s0_ss# spi_s1_clk spi_s1_mosi spi_s1_miso spi_s1_ss# spi_m_clk spi_m_mosi spi_m_miso spi_m_ss_0# spi_m_ss_1# gpio[A0] gpio[A1] gpio[A2] gpio[A3] gpio[A4] gpio[A5] gpio[A6] gpio[A7] IOBUS43 gpio[E7] Figure 5.3 IOBUS to UART, SPI slave0 and SPI master second example Copyright © Future Technology Devices International Limited 24 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 With reference to Figure 5.3, it can be seen that IOBUS9-11 and IOBUS16-19 were unused. Figure 5.4 expands upon the previous two figures to detail a fully occupied IOBUS, up to and including IOBUS19. The gaps at IOBUS9-11 have been filed with 3 GPIO pins, the gaps at IOBUS16-19 have been filled with the second SPI slave and a further 3 IOBUS pins (17-19) have been allocated to 3 GPIO pins. Note that GPIO pins A0 and A4 are unused as a sufficient gap wasn't available. Peripheral Pin IOBUS Pin uart_txd uart_rxd uart_rts# uart_cts# uart_dtr# uart_dsr# uart_dcd# uart_ri# uart_tx_active IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 IOBUS9 IOBUS10 IOBUS11 IOBUS12 IOBUS13 IOBUS14 IOBUS15 IOBUS16 IOBUS17 IOBUS18 IOBUS19 IOBUS20 IOBUS21 IOBUS22 IOBUS23 IOBUS24 IOBUS25 IOBUS26 IOBUS27 IOBUS28 IOBUS29 IOBUS30 IOBUS31 spi_s0_clk spi_s0_mosi spi_s0_miso spi_s0_ss# spi_s1_clk spi_s1_mosi spi_s1_miso spi_s1_ss# spi_m_clk spi_m_mosi spi_m_miso spi_m_ss_0# spi_m_ss_1# gpio[A0] gpio[A1] gpio[A2] gpio[A3] gpio[A4] gpio[A5] gpio[A6] gpio[A7] IOBUS43 gpio[E7] Figure 5.4 IOBUS to UART, SPI slave0 and SPI master third example Copyright © Future Technology Devices International Limited 25 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 5.1 I/O Peripherals Signal Names Peripheral Signal Name Outputs Inputs Debugger debug_if 1 1 debugger interface UART FIFO GPIO SPI Slave 0 SPI Slave 1 SPI Master PWM Description uart_txd 1 0 Transmit asynchronous data output uart_rts# 1 0 uart_dtr# 1 0 uart_tx_active 1 0 Request to send control output Data acknowledge (data terminal ready control) output Enable transmit data for RS485 designs uart_rxd 0 1 Receive asynchronous data input uart_cts# 0 1 Clear to send control input uart_dsr# 0 1 Data request (data set ready control) input uart_ri# 0 1 Ring indicator control input uart_dcd# 0 1 Data carrier detect control input fifo_data 8 8 fifo_txe# 1 0 fifo_rxf# 1 0 fifo_wr# 0 1 fifo_rd# 0 1 fifo_oe# 0 1 FIFO data bus When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing WR high, then low. When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by strobing RD# low, then high. Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR goes from high to low. Enables the current FIFO data byte on D0...D7 when low. Fetches the next FIFO data byte (if available) from the receive FIFO buffer when RD# goes from high to low FIFO output enable – synchronous FIFO only fifo_clkout 0 1 FIFO clock out – synchronous FIFO only gpio 40 40 spi_s0_clk 0 1 General purpose I/O SPI clock input – slave 0 spi_s0_ss# 0 1 SPI chip select input – slave 0 spi_s0_mosi 1 1 SPI master out serial in – slave 0 spi_s0_miso 1 0 SPI master in slave out – slave 0 spi_s1_clk 0 1 SPI clock input – slave 1 spi_s1_ss# 0 1 SPI chip select input – slave 1 spi_s1_mosi 1 1 Master out slave in – slave 1 spi_s1_miso 1 0 Master in slave out – slave 1 spi_m_clk 1 0 SPI clock input – master spi_m_mosi 1 1 Master out slave in - master spi_m_miso 0 1 Master in slave out - master spi_m_ss_0# 1 0 Active low slave select 0 from master to slave 0 spi_m_ss_1# 1 0 Active low slave select 1 from master to slave 1 pwm 8 0 Pulse width modulation Table 5.1 I/O Peripherals Signal Names Note: # is used to indicate an active low signal. Copyright © Future Technology Devices International Limited 26 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 5.2 Clearance No.: FTDI# 143 I/O Multiplexer Configuration The VNC2 I/O Multiplexer allows signals to be routed to different pins on the device. To simplify the routing of signals, the VNC2 RTOS provides a utility (IOMux) to configure the I/O Multiplexer as the designer requires. The IOMux is fully integrated into the VNC2 IDE (Integrated development Environment) which is available to download: Vinculum-II Toolchain. A screenshot of the IOMux utility is shown in figure 5.5 below. The IOMux utility user guide is available to download: VINCULUM-II IO_Mux Configuration Utility User Guide The following tables provide a lookup guide to determine what signals are available and the list of pins that can be used:     Table Table Table Table 5.2 5.3 5.4 5.5 Group Group Group Group 0 1 2 3 Each VNC2 has a default state of IOBUS signals following a hard reset. The number of I/O pins available is determined by the package size:    Package 32pin (LQFP & QFN)- Twelve I/O pins – IOBUS0 to IOBUS11 Package 48pin (LQFP & QFN)- Twenty eight I/O pins – IOBUS0 to IOBUS27 Package 64pin (LQFP & QFN)- Forty-four I/O pins – IOBUS0 to IOBUS43 Section 3.12 shows the default signal settings for all three package sizes. Figure 5.5 VNC2 Toolchain App Wizard showing IOMux Configuration Copyright © Future Technology Devices International Limited 27 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 5.3 Clearance No.: FTDI# 143 I/O Mux Group 0 Available Input signals Available output signals debug_if fifo_data[0] fifo_data[4] fifo_oe# spi_s0_clk spi_s1_clk gpio[A0] gpio[A4] gpio[B0] gpio[B4] gpio[C0] gpio[C4] gpio[D0] gpio[D4] gpio[E0] gpio[E4] debug_if uart_txd uart_dtr# uart_tx_active fifo_data[0] fifo_data[4] fifo_rxf# pwm[0] pwm[4] spi_m_clk spi_m_ss_1# gpio[A0] gpio[A4] gpio[B0] gpio[B4] gpio[C0] gpio[C4] gpio[D0] gpio[D4] gpio[E0] gpio[E4] 64 Pin Package Available pins 48 Pin Package Available pins 32 Pin Package Available pins 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 Table 5.2 Group 0 Table 5.2 - Input and output signals that are available for all the IOBUS pins that are in group 0. For example if using the 48 pin package device this would allow pins 11, 15, 20, 31, 35, 41 and 45 to be configured as either an input signal (listed in the first column) or a output signal (listed in the second column). 5.4 I/O Mux Group 1 Available Input signals uart_rxd uart_dsr# fifo_data[1] fifo_data[5] spi_s0_mosi spi_s1_mosi gpio[A1] gpio[A5] gpio[B1] gpio[B5] gpio[C1] gpio[C5] gpio[D1] gpio[D5] gpio[E1] gpio[E5] Available output signals 64 Pin Package Available pins fifo_data[1] fifo_data[5] fifo_txe# pwm[1] pwm[5] spi_s0_mosi spi_s1_mosi 12, 16, spi_m_mosi 20, 25, fifo_clkout 29, 40, gpio[A1] 44, 48, gpio[A5] 52, 58, gpio[B1] 62 gpio[B5] gpio[C1] gpio[C5] gpio[D1] gpio[D5] gpio[E1] gpio[E5] Table 5.3 Group 1 Copyright © Future Technology Devices International Limited 48 Pin Package Available pins 32 Pin Package Available pins 12,16, 21, 32, 36, 42, 46 12, 24, 30 28 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Table 5.3 - Input and output signals that are available for all the IOBUS pins that are in group 1. For example if using the 64 pin package device this would allow pins 12, 16, 20, 25, 29, 40, 44, 48, 52, 58 and 62 to be configured as either an input signal (listed in the first column) or a output signal (listed in the second column). 5.5 I/O Mux Group 2 Available Input signals Available output signals 64 Pin Package Available pins 48 Pin Package Available pins 32 Pin Package Available pins uart_rts# fifo_data[2] fifo_data[6] pwm[2] pwm[6] spi_s0_miso 13, 17, spi_s1_miso 22, 26, 13, 18, gpio[A2] 14, 25, 31, 41, 22, 33, gpio[A6] 31 45, 49, 37, 43, gpio[B2] 55, 59, 47 gpio[B6] 63 gpio[C2] gpio[C6] gpio[D2] gpio[D6] gpio[E2] gpio[E6] Table 5.4 Group 2 Table 5.4 - Input and output signals that are available for all the IOBUS pins that are in group 2. For example if using the 32 pin package device this would allow pins 14, 25 and 31 to be configured as either an input signal (listed in the first column) or a output signal (listed in the second column). uart_dcd# fifo_data[2] fifo_data[6] fifo_rd# spi_m_miso gpio[A2] gpio[A6] gpio[B2] gpio[B6] gpio[C2] gpio[C6] gpio[D2] gpio[D6] gpio[E2] gpio[E6] 5.6 I/O Mux Group 3 Available Input signals uart_cts# uart_ri# fifo_data[3] fifo_data[7] fifo_wr# spi_s0_ss# spi_s1_ss# gpio[A3] gpio[A7] gpio[B3] gpio[B7] gpio[C3] gpio[C7] gpio[D3] gpio[D7] gpio[E3] gpio[E7] Available output signals fifo_data[3] fifo_data[7] pwm[3] pwm[7] spi_m_ss_0# gpio[A3] gpio[A7] gpio[B3] gpio[B7] gpio[C3] gpio[C7] gpio[D3] gpio[D7] gpio[E3] gpio[E7] 64 Pin Package Available pins 48 Pin Package Available pins 32 Pin Package Available pins 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 15, 26, 32 Table 5.5 Group 3 Table 5.5 - Input and output signals that are available for all the IOBUS pins that are in group 3. For example if you using the 48 pin package device this would allow pins 14, 19, 23, 34, 38, 44 and 48 to be configured as either an input signal (listed in the first column) or a output signal (listed in the second column). Copyright © Future Technology Devices International Limited 29 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 5.7 Clearance No.: FTDI# 143 I/O Mux Interface Configuration Example This example shows how to set a UART interface on the VNC2 64 pin package. The UART is made up of two output signals (uart_txd and uart_rts#) and two input signals (uart_rxd and uart_cts#). For PCB design it is best to have the four pins of the UART interface adjacent to each other. This can be achieved easily since the four signals are members of each different groups. Figure 5.1 clearly shows that the four groups are adjacent to each other. So the four adjacent pins can be used for the UART interface as long as they are selected one from each of the four groups. Tables 9, 10, 11 & 12 can now be used to select where the UART interface can be placed. Figure 5.6 shows the four UART signal selected on pins 11, 12, 13 & 14 however they could have been selected on any of the other four pins highlighted in blue dashed lines. 54 38 21 V V C C C C I I O O 33 34 36 37 4 5 9 V C C I O 2 V C C USB1DP USB1DM USB2DP USB2DM XTIN XTOUT VNC2 64 Pin 8 IOBUS0 IOBUS1 IOBUS2 IOBUS3 VREG OUT NC IOBUS24 IOBUS25 IOBUS26 64 11 uart_txd – group0 12 uart_rxd – group1 13 uart_rts# – group2 14 uart_cts# – group3 15 16 IOBUS5 17 IOBUS6 18 IOBUS7 19 IOBUS8 20 IOBUS9 22 IOBUS10 23 IOBUS11 24 IOBUS12 25 IOBUS13 26 IOBUS14 27 IOBUS15 28 IOBUS16 29 IOBUS17 31 IOBUS18 32 IOBUS19 39 IOBUS20 40 IOBUS21 41 IOBUS22 42 IOBUS23 PROG# 7 V C C P L L IOBUS4 RESET# 10 3 IOBUS27 IOBUS43 IOBUS28 63 43 44 45 46 47 48 IOBUS29 49 IOBUS30 50 IOBUS31 IOBUS42 62 IOBUS41 61 IOBUS40 60 IOBUS39 59 IOBUS38 58 IOBUS37 57 IOBUS36 G N D G P N L D L 1 6 IOBUS32 51 52 IOBUS33 55 IOBUS34 56 IOBUS35 G N D G N D G N D 30 35 53 Figure 5.6 UART Example 64 pin Copyright © Future Technology Devices International Limited 30 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6 Peripheral Interfaces In addition to the two USB Host and Slave blocks, VNC2 contains the following peripheral interfaces:         Universal Asynchronous Receiver Transmitter (UART) Two Serial Peripheral Interface (SPI) slaves SPI Master Debugger Interface Parallel FIFO Interface (245 mode and synchronous FIFO mode) General Purpose Timers Eight Pulse Width Modulation blocks (PWM) General Purpose Input Output (GPIO) The following sections describe each peripheral in detail. 6.1 UART Interface When the data and control bus are configured in UART mode, the interface implements a standard asynchronous serial UART port with flow control, for example RS232/422/485. The UART can support baud rates from 183 baud to 6 Mbaud. The maximum UART speed is determined by the CPU speed/8.The CPU can be run at three frequencies, therefore the following maximum rates apply: CPU Frequency Maximum UART Speed 48 MHz 6 Mbaud 24 MHz 3 Mbaud 12 MHz 1.5 Mbaud Data transfer uses NRZ (Non-Return to Zero) data format consisting of 1 start bit, 7 or 8 data bits, an optional parity bit, and one or two stop bits. When transmitting the data bits, the least significant bit is transmitted first. Transmit and receive waveforms are illustrated in Figure 6.1 and Figure 6.2: Figure 6.1 UART Receive Waveform Figure 6.2 UART Transmit Waveform Baud rate (default =9600 baud), flow control settings (default = RTS/CTS), number of data bits (default=8), parity (default is no parity) and number of stop bits (default=1) are all configurable using the firmware command interface. Please refer to http://www.ftdichip.com. uart_tx_active is transmit enable, this output may be used in RS485 designs to control the transmit of the line driver. Copyright © Future Technology Devices International Limited 31 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6.1.1 UART Mode Signal Descriptions 64 Pin Package Available pins 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 48 Pin Package Available pins 32 Pin Package Available pins Name Type 11, 15, 20, 31, 35, 41, 45 11, 23 29 uart_tx d Output 12,16, 21, 32, 36, 42, 46 12, 24, 30 uart_rx d Input uart_rt s# Output 13, 18, 22, 33, 37, 43, 47 14, 25, 31 Description Transmit asynchronous data output Receive asynchronous data input Request to send control output 14, 19, 23, 34, 38, 44, 48 15, 26, 32 uart_ct s# Input 11, 15, 20, 31, 35, 41, 45 11, 23 29 uart_dt r# Output Data acknowledge (data terminal ready control) output uart_d cd# Input Data carrier detect control input uart_ri # Input Ring indicator is used to wake VNC2 depending on firmware 13, 18, 22, 33, 37, 43, 47 14, 19, 23, 34, 38, 44, 48 14, 25, 31 15, 26, 32 Clear to send control input Enable transmit data for RS485 designs. This signal may be used to 11, 15, signal that a transmit operation is in 20, 31, 11, 23 uart_tx progress. The uart_tx_active signal Output 35, 41, 29 _active will be set high one bit-time before 45 data is transmitted and return low one bit time after the last bit of a data frame has been transmitted. Table 6.1 Data and Control Bus Signal Mode Options – UART Interface The UART signals can be programmed to a choice of I/O pins depending on the package size. Table 6.1 details the available pins for each of the UART signals. Further details on the configuration of input and output signals are available in Section 5 - I/O Multiplexer. Copyright © Future Technology Devices International Limited 32 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6.2 Serial Peripheral Interface – SPI Modes The Serial Peripheral Interface Bus is an industry standard communications interface. Devices communicate in Master / Slave mode, with the Master initiating the data transfer. VNC2 has one master module and two slave modules. Each SPI slave module has four signals – clock, slave select, MOSI (master out – slave in) and MISO (master in – slave out). The SPI Master has the same four signals as the slave modules but with one additional signal because it requires a slave select for the second slave module. Table 6.2 lists how the signals are named in each module. The SPI Master clock can operate up to one half of the CPU system clock depending on what power mode the device is set to:    Normal power mode 48Mhz would set the SPI maximum clock to 24Mhz Low power mode 24Mhz would set the SPI maximum clock to 12Mhz Lowest power mode 12Mhz would set the SPI maximum clock to 6hMz Module Signal Name Type Description spi_s0_clk Input Clock input – slave 0 SPI Slave 0 spi_s0_ss# Input Active low chip select input – slave 0 spi_s0_mosi Input Master out serial in – slave 0 spi_s0_miso Output Master in slave out – slave 0 spi_s1_clk Input Clock input – slave 1 spi_s1_ss# Input Active low chip select input – slave 1 spi_s1_mosi Input Master out slave in – slave 1 spi_s1_miso Output Master in slave out – slave 1 spi_m_clk Output Clock output – master spi_m_mosi Output Master out slave in - master Master in slave out - master SPI Slave 1 SPI Master spi_m_miso Input spi_m_ss_0# Output spi_m_ss_1# Output Active low slave select 1 from master to slave 1 Table 6.2 SPI Signal Names Active low slave select 0 from master to slave 0 The SPI slave protocol by default does not support any form of handshaking. FTDI have added extra modes to support handshaking, faster throughput of data and reduced pin count. There are 5 modes (Table 15) of operation in the VNC2 SPI Slave.      Full Duplex – Section 0 Half Duplex, 4 pin - Section 6.3.3 Half Duplex, 3 pin - Section 6.3.4 Unmanaged - Section 6.3.5 VNC1L legacy mode – Section 6.3.6 Copyright © Future Technology Devices International Limited 33 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Mode Pins Word Size Handshaking Speed VNC1L 4 12 Yes Full Duplex 4 8 Yes Half Duplex 4 pin 4 8 Yes Read 100% Write 100% Half Duplex 3 pin 3 8 Yes Read 50% Write 50% Unmanaged 4 8 No Read 100% Write 100% Read 66% Write 66% Read 50% Write 100% Clearance No.: FTDI# 143 Comments Legacy mode MOSI becomes bidirectional MOSI becomes bidirectional Table 6.3 - SPI Slave Speeds VNC2 SPI Master is described in Section 6.4.1 SPI Master Signal Descriptions Table 6.5 shows the SPI master signals and the available pins that they can be mapped to depending on the package size. Further details on the configuration of input and output signals are available in Section 5 - I/O Multiplexer. 6.2.1 SPI Clock Phase Modes SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known as Mode 0, Mode 1, Mode 2 and Mode 3. Table 6.4 summarizes these modes and available interface and Figure 6.3 is the function timing diagram. For CPOL = 0, the base (inactive) level of SCLK is 0. In this mode:  When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on the falling edge of SCLK.  When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on the rising edge of SCLK For CPOL =1, the base (inactive) level of SCLK is 1. In this mode:  When CPHA = 0, data v in on the falling edge of SCLK, and data is clocked out on the rising edge of SCLK  When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on the falling edge of SCLK. N Half Duplex 4 pin N Half Duplex 3 pin N Y Y Y N N N Mode CPOL CPHA Full Duplex 0 0 0 1 0 1 2 1 0 3 1 Unmanaged VNC1L Legacy Y N Y N Y N Y N 1 Y Y Y Table 6.4 - Clock Phase/Polarity Modes Copyright © Future Technology Devices International Limited 34 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Figure 6.3 - SPI CPOL CPHA Function 6.3 Serial Peripheral Interface – Slave CLK SS# External - SPI Master MOSI VNC2 - SPI Slave MISO Figure 6.4 SPI Slave block diagram VNC2 has two SPI Slave modules both of which use four wire interfaces: MOSI, MISO, CLK and SS#. Their main purpose is to send data from main memory to the attached SPI master, and / or receive data and send it to main memory. The SPI Slave is controlled by the internal CPU using internal memory mapped I/O registers. It operates from the main system clock, although sampling of input data and transmission of output data is controlled by the SPI clock (CLK). An SPI transfer can only be initiated by the SPI Master and begins with the slave select signal being asserted. This is followed by a data byte being clocked out with the master supplying CLK. The master always supplies the first byte, which is called a command byte. After this the desired number of data bytes are transferred before the transaction is terminated by the master de-asserting slave select. An SPI Master is able to abort a transfer at any time by de-asserting its SS# output. This will cause the Slave to end its current transfer and return to idle state. Copyright © Future Technology Devices International Limited 35 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6.3.1 SPI Slave Signal Descriptions 64 Pin Package Available pins 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 48 Pin Package Available pins 32 Pin Package Available pins 11, 15, 20, 31, 35, 41, 45 11, 23 29 12,16, 21, 32, 36, 42, 46 12, 24, 30 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 14, 25, 31 15, 26, 32 Name spi_s0_clk spi_s1_clk Type Description Input Slave clock input spi_s0_mosi spi_s1_mosi Input Mater Out Slave In Synchronous data from master to slave spi_s0_miso spi_s1_miso Output spi_s0_ss# spi_s1_ss# Input Master In Slave Out Synchronous data from slave to master Slave chip select Table 6.5 Data and Control Bus Signal Mode Options - SPI Slave Interface 6.3.2 Full Duplex In full duplex mode, the SPI slave sends data on MISO line at the same time as it receives data on MOSI. During the command phase this data is always the slave status byte. For a write command, write data can be streamed out of MOSI and status can be sent during each write phase from slave to master. As long as the slave status indicates that it can receive more data, the master can continue to stream further write bytes. Figure 6.5 is an example of this. SS# MOSI 8 bit CMD W0 W1 W2 MISO STATUS STATUS STATUS STATUS Figure 6.5 Full Duplex Data Master Write Copyright © Future Technology Devices International Limited 36 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 When the master is performing a data read, the data and status both need to share the same pin (MISO). In this case the master and slave will exchange command and status bytes, followed by the slave sending its data. If the Master keeps SS# active the Slave will send a further status byte after the data followed by another data byte. This continues until the Master indicates the end of the communications by raising SS#. Figure 6.6 is an example of this. SS# MOSI 8 bit CMD MISO STATUS R0 STATUS R1 Figure 6.6 Full Duplex Data Master Read The command and status formats for this mode can be seen in Figure 6.7 below with a description of each field in Table 6.6: Command: Status: A2 A1 A0 R/W# Z Z Z Z Z Z Z Z TXE RXF ACK Z Figure 6.7 SPI Command and Status Structure Field A2:A0 R/W# Z TXE RXF ACK Description Address of slave being used in a multi-slave environment. This would typically be used in the scenario where a shared data bus is used. Set to ‘1’ for a read and ‘0’ for a write. Tri-stated. Transmit Empty. When ‘1’ the Slave transmit buffer has no new data to transmit. When ‘0’ the Slave transmit buffer does have new data. Receive Full. When ‘1’ the Slave receive buffer has new data which has not been read yet. When ‘0’ the Slave receive buffer is empty and can be safely written to. Set to ‘1’ when a Slave has correctly decoded its address. Table 6.6 SPI Command and Status Fields Copyright © Future Technology Devices International Limited 37 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6.3.3 Half Duplex, 4 pin In half duplex mode, the MOSI signal is shared for both Master to Slave and Slave to Master communications. When using 4 pins, the MISO signal carries the status bits. The Master initiates data write transfer, this by asserting SS# and then sending out a command byte. This has the same format as that shown in Figure 6.7. The Slave sends status during this command phase and if this indicates that the Slave can accept data the Master will follow this up with a byte of write data. If the status continues to indicate that more data can be written, a whole stream of data can be written following one single command. The operation completes when the Master raises SS# again. Figure 6.8 is an example of this. SS# MOSI 8 bit CMD W0 W1 W2 MISO STATUS STATUS STATUS STATUS Figure 6.8 Half Duplex Data Master Write Data reads are similar, apart from the MOSI pin changing from Slave input to Slave output after the command phase. Figure 6.9 is an example. In this diagram, the Master drives the command while the Slave returns with status. Then the MOSI buffers are turned round and a stream of read data is sent from the Slave to the Master on the MOSI signal. Master to Slave Slave to Master SS# MOSI 8 bit CMD R0 R1 R2 MISO STATUS STATUS STATUS STATUS Figure 6.9 Half Duplex Data Master Read Copyright © Future Technology Devices International Limited 38 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6.3.4 Half Duplex, 3 pin The 3 pin half duplex mode eliminates the MISO pin from the protocol. This means that status bytes need to be sent on the MOSI pin. Again the Master initiates a transfer by asserting SS# and sending out a command byte. The Slave sends status back to the Master. If a write has been requested and the status indicates that the Slave can accept data, MOSI should be changed to an output again and data will be sent from Master to Slave. Following this data, the Slave will send a further status byte if SS# remains active. If the status indicates that more data can be written, the next data byte can be sent to the Slave and this process continues until SS# is de-asserted. Figure 6.10 is an example of this: Master to Slave Slave to Master Master to Slave Slave to Master Master to Slave 8 bit CMD STATUS W0 STATUS W1 SS# MOSI Figure 6.10 Half Duplex 3-pin Data Master Write Data reads are similar expect that after the command byte all data transfer is from Slave to Master. Figure 6.11 is an example of this: Master to Slave Slave to Master SS# MOSI 8 bit CMD STATUS R0 STATUS R1 Figure 6.11 Half Duplex 3-pin Data Master Read Copyright © Future Technology Devices International Limited 39 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6.3.5 Unmanaged Mode The VNC2 SPI Slave also supports an unmanaged SPI mode. This is a simple data exchange between Master and Slave. It operates in the standard 4 pin mode (SS#, CLK, MOSI and MISO) with all transfers controlled by the SPI Master. When the CPU wants to send data out of the SPI Slave it writes this into the spi_slave_data_tx register. This will then be moved into the transfer shift register to wait for the SPI Master to request it. The SPI Master will at some point assert SS# and start clocking data on MOSI with SCK. As this is shifted into the transfer shift register, the SPI Slave will also be shifting data in the opposite direction on MISO. At the end of the transfer the SPI Slave copies the received data from the shift register to spi_slave_data_rx as seen in Figure 6.12. SPI Master SPI Slave SPI Clk Div ss# clk 0 1 2 3 4 5 6 7 mosi 0 1 Shift Register 0 1 2 3 4 Shift Register 2 3 4 5 6 7 6 7 Rx Shift Register 5 6 0 7 1 miso 2 3 4 5 Tx Shift Register Figure 6.12 Unmanaged Mode Transfer Diagram Copyright © Future Technology Devices International Limited 40 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6.3.6 VNC1L Legacy Interface VNC2 SPI is compatible with the SPI slave of VNC1L. This is a custom protocol using 4 wires and will be explained here. The Master asserts the slave select, but in this case it is an active high signal. Following this, a 3 bit command is sent on the MOSI pin (see Figure 6.15 for command structure). This has instructions on whether a read or write is requested and if data or status is to be sent. For a data write, 8 bits of data are sent on MOSI followed by a status bit being returned on MISO. If this bit is ‘0’ it means the data write was successful. If it is ‘1’ it means that internal buffer was full and the write should be repeated. Finally, the slave select is de-asserted. See Figure 6.13 for an example of this. Figure 6.13 VNC1L Mode Data Write Data reads are similar, with the data from Slave to Master coming on the MISO pin. If the status bit is ‘0’ it means the data byte sent is new data that has not been read before. If it is ‘1’ it means that it is old data. See Figure 6.14 for an example. Figure 6.14 VNC1L Mode Data Read The command and status formats for this mode can be seen in Figure 6.15 below with a description of each field in Table 6.7. Command: Start R/W Addr Data: D7 D6 D5 Status: Status D4 D3 D2 D1 D0 Figure 6.15 VNC1L Compatible SPI Command and Status Structure Copyright © Future Technology Devices International Limited 41 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Field Description Start Driven to ‘1’. If set to ‘1’, the SPI Master wishes to read from the slave. If set to ‘0’, the SPI Master wishes to write to the slave. If set to ‘1’, a read operation will return the status byte in the data phase. A write will have no effect. If set to ‘0’, a read or a write will operate on the data register. Data. When ‘0’ this means a read or write was successful. When ‘1’ it means a read contains old data, or a write did not work and needs retried. Table 6.7 SPI Command and Status Fields R/W Addr D7:D0 Status 6.3.6.1 SPI Setup Bit Encoding The VNC1L compatible SPI interface differs from most other implementations in that it uses a 12 clock sequence to transfer a single byte of data. In addition to a ‘Start’ state, the SPI master must send two setup bits which indicate data direction and target address. The encoding of the setup bits is shown in Table 6.8. A single data byte is transmitted in each SPI transaction, with the most significant bit transmitted first. After each transaction VNC2 returns a single status bit. This indicates if a Data Write was successful or a Data Read was valid. Direction (R/W) Target Address Operation Meaning 1 0 Data Read Retrieve byte from Transmit Buffer 1 1 Status Read Read SPI Interface Status 0 0 Data Write Add byte to Receive Buffer 0 1 N/A N/A Table 6.8 SPI Setup Bit Encoding The VNC2 SPI interface uses 4 signal lines: SCLK, SS, MOSI and MISO. The signals MOSI, MISO and SS are always clocked on the rising edge of the SCLK signal. SS signal must be raised high for the duration of the entire transaction. For data transactions, the SS must be released for at least one clock cycle after a transaction has completed. It is not necessary to release SS between Status Read operations. The ‘Start’ state of MOSI and SS high on the rising edge of SCLK initiates the transfer. The transfer finishes after 13 clock cycles, and the next transfer starts when MOSI is high during the rising edge of CLK. The following Figure 6.16 and Table 6.9 give details of the bus timing requirements. Copyright © Future Technology Devices International Limited 42 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Figure 6.16 SPI Slave Mode Timing Time T1 T2 T3 T4 T5 T6 Description Minimu m 79.37 39.68 39.68 Typical Maximum Unit SCLK period 83.33 SCLK high period 41.67 39.68 SCLK low period 41.67 39.68 SCLK driving edge to 0.5 14 MISO/MOSI MISO/SS setup time to 3 sample SCLK edge MISO/SS hold time from 3 sample SCLK edge Table 6.9 SPI Slave Data Timing ns ns ns ns ns ns 6.3.6.2 SPI Master Data Read Transaction in VNC1L legacy mode The SPI master must periodically poll for new data in VNC2 Transmit Buffer. It is recommended that this is done first before sending any command. The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6.17. The VNC2 clocks out data from its Transmit Buffer on subsequent rising edge clock cycles provided by the SPI master. This is followed by a status bit generated by VNC2. The Data Read status bit is defined in Table 6.10. If the status bit indicates New Data then the byte received is valid. If it indicates Old Data then the Transmit Buffer in VNC2 is empty and the byte of data received in the current transaction should be disregarded. Status Bit Meaning 0 New Data 1 Old Data Data in current transaction is valid data. Byte removed from Transmit Buffer. This same data has been read in a previous read cycle. Repeat the read cycle until New Data is received. Table 6.10 SPI Master Data Read Status Bit Copyright © Future Technology Devices International Limited 43 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Figure 6.17 SPI Master Data Read (VNC2 Slave Mode) The status bit is only valid until the next rising edge of SCLK after the last data bit. During the Data Read operation the SS signal must not be de-asserted. The transfer completes after 12 clock cycles and the next transfer can begin when MOSI and SS are high during the rising edge of SCLK. 6.3.6.3 SPI Master Data Write Transaction in VNC1L legacy mode During an SPI master Data Write operation the Start and Setup sequence is sent by the SPI master to VNC2, see Figure 6.18. This is followed by the SPI master transmitting each bit of the data to be written to VNC2. The VNC2 then responds with a status bit on MISO on the rising edge of the next clock cycle. The SPI master must read the status bit at the end of each write transaction to determine if the data was written successfully to VNC2 Receive Buffer. The Data Write status bit is defined in Table 6.11.The status bit is only valid until the next rising edge of SCLK after the last data bit. If the status bit indicates Accept then the byte transmitted has been added to VNC2 Receive Buffer. If it shows Reject then the Receive Buffer is full and the byte of data transmitted in the current transaction should be re-transmitted by the SPI master to VNC2. Any application should poll VNC2 Receive Buffer by retrying the Data Write operation until the data is accepted. Status Bit Meaning 0 Accept 1 Reject Data from the current transaction was accepted and added to the Receive Buffer Write data was not accepted. Retry the same write cycle. Table 6.11 SPI Master Data Write Status Bit Figure 6.18 SPI Slave Mode Data Write Copyright © Future Technology Devices International Limited 44 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6.3.6.4 SPI Master Status Read Transaction in VNC1L legacy mode The VNC2 has a status byte which determines the state of the Receive and Transmit Buffers. The SPI master must poll VNC2 and read the status byte. The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6.19. The VNC2 clocks out its status byte on subsequent rising edge clock cycles from the SPI master. This is followed by a status bit generated by VNC2 (also on the MISO) which will always be zero (indicating new data). The meaning of the bits within the status byte sent by VNC2 during a Status Read operation is described in Table 6.12. The result of the Status Read transaction is only valid during the transaction itself. Data read and data write transactions must still check the status bit during a Data Read or Data Write cycle regardless of the result of a Status Read operation. Bit 0 1 2 3 4 Description RXF# TXE# RXF IRQEn Description Receive Buffer Full Transmit Buffer Empty Not used Not used Receive Buffer Full Interrupt Enable Transmit Buffer Empty Interrupt 5 TXE IRQEn Enable 6 Not used 7 Not used Table 6.12 SPI Status Read Byte – bit descriptions Figure 6.19 SPI Slave Mode Status Read 6.4 Serial Peripheral Interface – SPI Master CLK SS# VNC2 - SPI Master MOSI External - SPI Slave MISO Figure 6.20 SPI Master block diagram The SPI Master interface is used to interface to applications such as SD Cards. The SPI Master provides the following features:      Synchronous serial data link. Full and half duplex data transmission. Serial clock with programmable frequency, polarity and phase. One slave select output. Programmable delay between negative edge of slave select and start of transfer. Copyright © Future Technology Devices International Limited 45 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138   Clearance No.: FTDI# 143 SD Card interface. An interface that’s compatible with the VLSI VS1033 SCI mode used for VMUSIC capability The SPI Master only clocks in and out data that the VNC2 CPU sets up in its register space. The VNC2 CPU interprets the data words that are to be sent and received. 6.4.1 SPI Master Signal Descriptions Table 6.13 shows the SPI master signals and the available pins that they can be mapped to depending on the package size. Further details on the configuration of input and output signals are available in Section 5 - I/O Multiplexer. 64 Pin Package Available pins 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 48 Pin Package Available pins 32 Pin Package Available pins Name Type 11, 15, 20, 31, 35, 41, 45 11, 23 29 spi_m_clk Output 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 12,16, 21, 32, 36, 42, 46 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 Description SPI master clock input Master Out Slave In 12, 24, 30 spi_m_mosi Output Synchronous data from master to slave Master In Slave Out 14, 25, 31 spi_m_miso Input Synchronous data from slave to master Active low slave select 0 from 15, 26, 32 spi_m_ss_0# Output master to slave 0 Active low slave select 1 from 11, 23 29 spi_m_ss_1# Output master to slave 1 Table 6.13 SPI Master Signal Names The main purpose of the SPI Master block is to transfer data between an external SPI interface and the VNC2. It does this under the control of the CPU and DMA engine via the on chip I/O bus. An SPI master interface transfer can only be initiated by the SPI Master and begins with the slave select signal being asserted. This is followed by a data byte being clocked out with the master supplying SCLK. The master always supplies the first byte, which is called a command byte. After this the desired number of data bytes are transferred before the transaction is terminated by the master de-asserting slave select. The SPI Master will transmit on MOSI as well as receive on MISO during every data stage. At the end of each byte spi_tx_done and spi_rx_full_int are set. Figure 6.21 Typical SPI Master Timing and Table 6.14 SPI Master Timing show an example of this. Copyright © Future Technology Devices International Limited 46 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Figure 6.21 Typical SPI Master Timing Time t1 t2 t3 t4 t5 t6 Description Minimum Typical Maximum SCLK period 39.68 41.67 SCLK high period 19.84 20.84 21.93 SCLK low period 19.84 20.84 21.93 SCLK driving edge to -1.5 3 MOSI/SS MISO setup time to sample 6.5 SCLK edge MISO hold time from 0 sample SCLK edge Table 6.14 SPI Master Timing Unit ns ns ns ns ns ns 6.5 Debugger Interface The purpose of the debugger interface is to provide the Integrated Development Environment (IDE) with the following capabilities:    Flash Erase, Write and Program. Application debug - application code can have breakpoints, be single stepped and can be halted. Detailed internal debug - memory read/write access. The single wire interface has the following features:       Half Duplex Operation 1Mbps speed 1 start bit 1 stop bit 8 data bits Pull up Further information of the Debugger Interface is available in an Application Note AN_138 Vinculum-II Debug Interface Description. 6.5.1 Debugger Interface Signal description 64 Pin Package Available pins 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 48 Pin Package Available pins 32 Pin Package Available pins Name Type 11, 15, 20, 31, 35, 41, 45 11, 23 29 debug_if Input/ Output Description Debugger Interface Table 6.15 Debugger Signal Name Copyright © Future Technology Devices International Limited 47 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 6.6 Parallel FIFO – Asynchronous Mode Parallel FIFO Asynchronous mode known as ‘245’, is functionally the same as the one that is present in VNC1L has an eight bit data bus, individual read and write strobes and two hardware flow control signals. 6.6.1 FIFO Signal Descriptions The Parallel FIFO interface signals are described in Table 6.16 They can be programmed to a choice of I/O pins depending on the package size. Further details on the configuration of input and output signals are available in Section 5 - I/O Multiplexer. 64 Pin Package Available pins 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 13, 17, 22, 26, 31, 41, 48 Pin Package Available pins 32 Pin Package Available pins Name Type 11, 15, 20, 31, 35, 41, 45 11, 23 29 fifo_data[0] I/O FIFO Data Bus Bit 0 12,16, 21, 32, 36, 42, 46 12, 24, 30 fifo_data[1] I/O FIFO Data Bus Bit 1 fifo_data[2] I/O FIFO Data Bus Bit 2 13, 18, 22, 33, 37, 43, 47 14, 25, 31 Description 14, 19, 23, 34, 38, 44, 48 15, 26, 32 fifo_data[3] I/O FIFO Data Bus Bit 3 11, 15, 20, 31, 35, 41, 45 11, 23 29 fifo_data[4] I/O FIFO Data Bus Bit 4 12,16, 21, 32, 36, 42, 46 12, 24, 30 fifo_data[5] I/O FIFO Data Bus Bit 5 fifo_data[6] I/O FIFO Data Bus Bit 6 13, 18, 22, 33, 37, 43, 14, 25, 31 Copyright © Future Technology Devices International Limited 48 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 64 Pin Package Available pins 45, 49, 55, 59, 63 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 48 Pin Package Available pins 47 14, 19, 23, 34, 38, 44, 48 11, 15, 20, 31, 35, 41, 45 12,16, 21, 32, 36, 42, 46 32 Pin Package Available pins Name Type 15, 26, 32 fifo_data[7] I/O 11, 23 29 12, 24, 30 fifo_rxf# fifo_txe# Clearance No.: FTDI# 143 Description FIFO Data Bus Bit 7 Output When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by strobing fifo_rd# low, then high. Output When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing fifo_wr# high, then low. 13, 17, Enables the current FIFO data byte on 22, 26, 13, 18, 14, 25, D0...D7 when low. Fetches the next 31, 41, 22, 33, 31 fifo_rd# Input FIFO data byte (if available) from the 45, 49, 37, 43, receive FIFO buffer when fifo_rd# 55, 59, 47 goes from high to low 63 14, 18, 23, 27, 14, 19, Writes the data byte on the D0...D7 32, 42, 23, 34, 15, 26, fifo_wr# Input pins into the transmit FIFO buffer 46, 50, 38, 44, 32 when fifo_wr# goes from high to low. 56, 60, 48 64 Table 6.16 Data and Control Bus Signal Mode Options - Parallel FIFO Interface 6.6.2 Read / Write Transaction Asynchronous FIFO Mode When in Asynchronous FIFO interface mode, the timing of read and write operations on the FIFO interface are shown in Figure 6.22 and Table 6.17. In asynchronous mode an external device can control data transfer driving FIFO_WR# and FIFO_RD# inputs. In contrast to synchronous mode, in asynchronous mode the 245 FIFO module generates the output enable EN# signal. EN# signal is effectively the read signal RD#. Current byte is available to be read when FIFO_RD# goes low. When FIFO_RD# goes high, FIFO_RXF# output will also go high. It will only become low again when there is another byte to read. When FIFO_WR# goes low FIFO_TXE# flag will always go high. FIFO_TXE# goes low again only when there is still space for data to be written in to the module. Copyright © Future Technology Devices International Limited 49 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Figure 6.22 Asynchronous FIFO mode Read / Write Cycle Time Description Minimum Maximum Unit t1 RD# inactive to RXF# 1 14 ns t2 RXF# inactive after RD# cycle 100 t3 RD# to DATA 1 t4 RD# active pulse width 30 ns t5 RD# active after RXF# 0 ns t6 WR# active to TXE# inactive 1 t7 TXE# inactive after WR# cycle 100 ns t8 5 ns t9 DATA to TXE# active setup time DATA hold time after WR# inactive t10 WR# active pulse width 30 t11 5 ns 14 14 ns ns ns ns ns WR# active after TXE# 0 Table 6.17 Asynchronous FIFO mode Read / Write Timing 6.7 Parallel FIFO – Synchronous Mode The Parallel FIFO Synchronous mode has an eight bit data bus, individual read and write strobes, two hardware flow control signals, an output enable and a clock out. The synchronous FIFO mode uses the parallel FIFO interface signals detailed in Table 6.16 and an additional two signals detailed in Table 6.18. This mode is not available on the 32 pin packages. Copyright © Future Technology Devices International Limited 50 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 64 Pin Package Available pins 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 Clearance No.: FTDI# 143 48 Pin Package Available pins 32 Pin Package Available pins Name Type 11, 15, 20, 31, 35, 41, 45 11, 23 29 fifo_oe# I/O FIFO Output enable 12,16, 21, 32, 36, 42, 46 12, 24, 30 fifo_clkout I/O FIFO Clock out Description Table 6.18 Synchronous FIFO control signals 6.7.1 Read / Write Transaction Synchronous FIFO Mode When in Synchronous FIFO interface mode, the timing of read and write operations on the FIFO interface are shown in Figure 6.23 and Table 6.19. In synchronous mode data can be transmitted to and from the FIFO module on each clock edge. An external device synchronises to the CLKOUT output and it also has access to the output enable OE# input to control data flow. An external device should drive output enable OE# low before pulling RD# line down. When bursts of data are to be read from the module RD# should be kept low. RXF# remains low when there is still data to be read. Similarly when bursts of data are to be written to the module WR# should be kept low. TXE# remains low when there is still space available for the data to be written. Figure 6.23 Synchronous FIFO mode Read / Write Cycle Copyright © Future Technology Devices International Limited 51 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Time t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Description Minimum Typical Maximum CLKOUT period 20.83 CLKOUT high period 9.38 10.42 11.46 CLKOUT low period 9.38 10.42 11.46 CLKOUT to RXF# 1 7.83 CLKOUT to 1 7.83 read DATA valid OE# to read DATA 1 7.83 valid CLKOUT to OE# 1 7.83 RD# setup time 12 RD# hold time 0 CLKOUT TO TXE# 1 7.83 Write DATA setup time 12 Write DATA hold time 0 WR# setup time 12 WR# hold time 0 Table 6.19 Synchronous FIFO mode Read / Write Timing Clearance No.: FTDI# 143 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6.8 General Purpose Timers In VNC2 there are 4 General Purpose Timers available. Three are available to the designer and one is reserved for the RTOS. The timers have the following features:      16 bit Count down One shot and auto-reload enable Interrupt on zero 6.9 Pulse Width Modulation VNC2 provides 8 Pulse Width Modulation (PWM) outputs. These can be used to generate PWM signals which can be used to control motors, DC/DC converters, AC/DC supplies, etc. Further information is available in an Application Note AN_140 - Vinculum-II PWM Example. The features of the PWM module are as follows:       8 PWM outputs A trigger input 8-bit prescaler 16-bit counter Generation of up to 4-pulse signal with controlled output enable and configurable initial state Interrupt A single PWM cycle can have up to 4 pulses (8 edges). The PWM block uses a 16-bit counter to determine the period of a single PWM cycle. This counter counts system clocks which can also be divided by an optional 8-bit prescaler. The PWM drivers allow the user to select when PWM output toggles. These values correspond to the values of 16-bit counter. For example, on the timing diagram below - Figure 6.24, the 16-bit counter counts to 23 and pwm_out[0] output toggles when the counter’s current value is equal to 7, 8, 12, 14, 15, 16, 19 and 22. Copyright © Future Technology Devices International Limited 52 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Figure 6.24 PWM – Timing Diagram The user can also select the initial state of each of the PWM outputs (HI or LOW). PWM outputs can also be enabled continuously or a cycle can be repeated 1..255 times. The PWM cycle can be started by the PWM driver or externally using a trigger input. 6.10 General Purpose Input Output VNC2 provides up to 40 configurable Input/output pins depending on the package. The Input/output pins are connected to Ports A through E. These ports are controlled by the VNC2 CPU. All ports are configurable to be either inputs or outputs and allow level or edge driven interrupts to be generated. To simplify the use of the 40 available GPIO signals, they have been grouped into 5 "ports", identified as A, B, C, D and E. Each port is 1 byte wide and the RTOS drivers will allow each port to be individually accessed. Each GPIO signal is mapped on to a bit of the port value. For example, gpio[A0] is the least significant bit of the value read from or written to GPIO port A. Similarly, gpio[A7] is the most significant bit of the value read from or written to GPIO port A (see Figure 6.25 GPIO Port Groups). Each pin can be individually configured as input or output. GPIO port A supports an interrupt that can be used to detect a state change of any of its 8 pins. Port B features a more sophisticated set of 4 configurable interrupts that can be associated with individual pins and supports several conditions such as positive edge, negative edge, high or low. gpio[A0] gpio[C0] gpio[E0] gpio[A1] gpio[C1] gpio[E1] gpio[A2] gpio[C2] gpio[E2] gpio[A3] gpio[C3] gpio[A4] PORT A gpio[C4] PORT C gpio[E3] gpio[E4] gpio[A5] gpio[C5] gpio[E5] gpio[A6] gpio[C6] gpio[E6] gpio[A7] gpio[C7] gpio[E7] gpio[B0] gpio[D0] gpio[B1] gpio[D1] gpio[B2] gpio[D2] gpio[B3] gpio[B4] PORT B gpio[D3] gpio[D4] gpio[B5] gpio[D5] gpio[B6] gpio[D6] gpio[B7] gpio[D7] PORT E PORT D Figure 6.25 GPIO Port Groups Copyright © Future Technology Devices International Limited 53 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 7 USB Interfaces VNC2 has two USB 1.1 and USB 2.0 compliant interfaces available either as a USB host or slave device capable of supporting 1.5Mb/s (Low Speed) and 12Mb/s (full Speed) transactions. The USB specification defines 4 transfer types that are all supported by VNC2:     Interrupt transfer: Used for legacy devices where the device is periodically polled to see if the device has data to transfer e.g. Mouse, Keyboard. VNC2 interrupt transfers are valid for low- and full-speed transactions. Bulk transfer: Used for transferring large blocks of data that have no periodic or transfer rate requirement e.g. USB to RS232 (FT232R device), memory sticks. VNC2 bulk transfers are only valid for full-speed transactions. Isochronous transfer: Used for transferring data that requires a constant delivery rate e.g. web cam, wireless modem. VNC2 isochronous transfers are only valid for full-speed transactions. Control transfer: Used to transfer specific requests to all types USB devices (most commonly used during device configuration). VNC2 control transfers are valid for low- and full-speed transfers. USB 2.0 - 480Mb/s (High Speed) transactions are not supported as the power requirements are deemed excessive for VNC2 target applications. VNC2 configured to Full speed is supported. VNC2 has two main USB modes of operation: host mode or client (or Slave) mode. As a client, VNC2 is able to connect to a PC and act as a USB peripheral. At the same time as being a client the second USB interface is also able to act as a host and connect to a second USB device using two separate ports (i.e. Port 0 – Host Port 1- Client). Each USB interface can be either a host or a client. It is not possible to change from host to client or client to host “on-the-fly”. The following diagrams in figure 7.1 give examples of possible modes of operation: Port 0 USB Device Port 0 USB Host VNC2 VNC2 Port 1 Port 1 BOMS Flash Disk Port 0 in Slave mode Port 0 and 1 in Host mode Port 0 Port 0 USB Host USB Host VNC2 VNC2 Port 1 Port 1 BOMS Flash Disk Port 0 in Slave mode and Port 1 in Host mode USB Host Port 0 and 1 in Slave mode (Null Modem type application) Figure 7.1 USB Modes Copyright © Future Technology Devices International Limited 54 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 8 Firmware VNC2 firmware model has evolved considerably since VINC1L. For reasons of code maintainability, performance, stability and ease of use from the point of view of the customer, VNC2 has a modular firmware model. VNC2 firmware can be separated into 4 categories:     VNC2 real-time operating system (RTOS). VNC2 device drivers. User applications – Toolchain. Precompiled Firmware. 8.1 RTOS The VNC2 RTOS (VOS) is a pre-emptive priority-based multi-tasking operating system. VOS has been developed by FTDI and is available to customers for use in their own VNC2 based systems free of charge. VOS is supplied as linkable object files. A full explanation and how to use VOS is available in a separate application note which can be downloaded from the FTDI website. 8.2 Device drivers To facilitate communication between user applications and the VNC2 hardware peripherals FTDI provides device drivers which operate with VOS. In addition to the hardware device drivers, FTDI provides function drivers (available from the FTDI website) which build upon the basic hardware device driver functionality for a specific purpose. For example, drivers for standard USB device classes may be created which build upon the USB host hardware driver to implement a BOMS class, CDC, printer class or even a specific vendor class device driver. 8.3 Firmware – Software Development Toolchain The VNC2 provides customers with the opportunity to customise the firmware and perform useful tasks without an external MCU. A Firmware application note is available to download from the FTDI website, this give further details and operating instructions. The VNC2 Software Development Toolchain consists of the following components:  Compiler The compiler will take high-level source code and compile it into object code or direct to programmable code.  Linker The linker will take object code and libraries and link the code to produce either libraries or programmable code. It is designed to be as hardware independent as possible to allow reuse in future hardware devices.  Debugger The debugger allows a programmer to test code on the hardware platform using a special communication channel to the CPU. It is also used to debug code – run, stop, single step, breakpoints etc.  IDE All compiler, simulator and debugger functions are integrated into a single application for programmers. It provides a specialised text editor which is used generally used to develop application code, debugging and simulation. Copyright © Future Technology Devices International Limited 55 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 8.4 Precompiled Firmware VNC2 can be programmed with various pre-compiled firmware profiles to allow a designer to easily change the functionality of the chip. The following pre-compiled ROM files are currently available:  V2DAP firmware: USB Host for single Flash Disk and general purpose USB peripherals. Selectable UART, FIFO or SPI interface command monitor. Offers a migration path from VNC1L designs with VDAP firmware.  V2DPS firmware: USB Host for single Flash Disk and general purpose USB peripherals and USB peripheral emulating a FT232 on a Host computer. Offers a migration path for VNC1L designs with VDPS.  V2F2F firmware: USB Host for two Flash Disks with file copy functions. Offers a migration path for VNC1L designs with VF2F firmware.  CDC Modem Sample Application: Demonstrates connection of a CDC device to USB Port 1 by establishing a link between the CDC device and the UART of the VNC2.  USBHost FT232 UART Echo Sample Application: Demonstrates emulation of a FTDI FT232 device on USB Port 1. Data is looped back. Designers are advised to refer to the FTDI website for the most current details on available Firmware. Copyright © Future Technology Devices International Limited 56 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 9 Device Characteristics and Ratings 9.1 Absolute Maximum Ratings The absolute maximum ratings for VNC2 are shown in Table 9.1. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device. Parameter Storage Temperature Floor Life (Out of Bag) At Factory Ambient ( 30°C / 60% Relative Humidity) Value -65 to +150 168 (IPC/JEDEC J-STD-033A MSL Level 3 Compliant)* -40 to +85 0 to +3.63 0 to +3.63 0 to + 1.98 -0.5 to +(Vcc +0.5) -0.5 to +((1.8V VCC PLL IN) +0.5) Ambient Temperature (Power Applied) Vcc Supply Voltage VCC_IO VCC_PLL_IN DC Input Voltage - USBDP and USBDM DC Input Voltage - XTIN DC Input Voltage - High Impedance -0.5 to +5.00 Bidirectional DC Input Voltage - All other Inputs -0.5 to +(Vcc +0.5) DC Output Current - Outputs Default 4 ** DC Output Current - Low Impedance Default 4 ** Bidirectional Table 9.1 Absolute Maximum Ratings * Unit °C Hours °C V V V V V V V mA mA If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of 125°C and baked for up to 17 hours. ** The drive strength of the output stage may be configured for either 4mA, 8mA, 12mA or 16mA depending on the register setting controlled within the firmware. The default is 4mA. 9.2 DC Characteristics DC Characteristics (Ambient Temperature -40˚C to +125˚C) Parameter Vcc1 Vcc2 VCC_PLL Icc1 Icc2 Icc3 Icc4 Description Minimum Typical Maximum VCC Operating Supply 1.62 1.8 1.98 Voltage VCCIO Operating 2.97 3.3 3.63 Supply Voltage VCC_PLL Operating 1.62 1.8 1.98 Supply Voltage Operating Supply Current 25 48MHz Operating Supply Current 16 24MHz Operating Supply Current 8 12MHz Operating Supply 128 Current Table 9.2 Operating Voltage and Current Copyright © Future Technology Devices International Limited Units Conditions V V V mA Normal Operation mA Low Power Mode mA Lowest Power Mode µA USB Suspend 57 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Parameter Description Minimum Voh Output Voltage High 2.4 Vol Output Voltage Low Vin Parameter UVoh UVol UVse UCom UVdif UDrvZ Parameter VCCK VCC18IO TJ Iin Ioz Typical Maximum Clearance No.: FTDI# 143 Units V 0.4 V Input Switching 1.5 Threshold Table 9.3 I/O Pin Characteristics Conditions I source = 8mA I sink = 8mA V Description Minimum Typical Maximum Units I/O Pins Static Output 2.8 V ( High) I/O Pins Static Output 0.3 V ( Low ) Single Ended Rx 0.8 2.0 V Threshold Differential Common 0.8 2.5 V Mode Differential Input 0.2 V Sensitivity Driver Output 3 6 9 Ohms Impedance Table 9.4 USB I/O Pin (USBDP, USBDM) Characteristics Conditions Description Power supply of internal core cells and I/O to core interface Power supply of 1.8V OSC pad Operating junction temperature Input leackage current Minimum Typical Maximum Units Conditions 1.62 1.8 1.98 V 1.8V power supply 1.62 1.8 1.98 V 1.8V power supply -40 25 125 °C -10 ±1 10 µA Iin = VCC18IO or 0V Tri-state output -10 ±1 10 µA leakage current Table 9.5 Crystal Oscillator 1.8 Volts DC Characteristics 9.3 ESD and Latch-up Specifications Description Specification Human Body Mode (HBM) TBD Machine mode (MM) TBD Charged Device Mode (CDM) TBD Latch-up > ± 200mA Table 9.6 ESD and Latch-up Specifications Copyright © Future Technology Devices International Limited 58 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 10 Application Examples 10.1 Example VNC2 Schematic (MCU – UART Interface) VNC2 can be configured to communicate with a microcontroller using a UART interface. An example of this is shown in Figure 10.1. Figure 10.1 VNC2 Schematic (MCU – UART Interface) Note: This sample circuit is not intended to be a complete design. It shows the minimum connections for a basic VNC2 circuit. The value of the capacitors connected to the crystal will depend on the requirements of the crystal. The 5V0_SW power signal assumes proper switching and over-current detection conform to the USB-IF specifications for a USB host port. The 120uF capacitor should be a lowESR type. The value of the ferrite beads may need adjusted for EMI compatibility. Input and output capacitors for the 3.3V regulator should be chosen according to the datasheet of the selected part. The VNC2 outputs connect to the MCU inputs and MCU outputs to VNC2 inputs (TXD to RXD and RTS# to CTS# in each direction). Note for VNC2-48L1B only: With the 48-pin LQFP package, pin 7 is not connected (VREGOUT). The regulator output has an internal connection to VCCPLLIN to accommodate a migration path from VNC1L designs. In this case, pin 3 (VCCPLLIN) requires only one 100nF capacitor to ground. All other packages require the external circuitry shown to connect VREGOUT to VCCPLLIN. Copyright © Future Technology Devices International Limited 59 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 11 Package Parameters VNC2 is available in six RoHS Compliant packages, three QFN packages (64QFN, 48QFN & 32QFN) and three LQFP packages (64LQFP, 48LQFP & 32LQFP). All packages are lead (Pb) free and use a ‘green’ compound. The packages are fully compliant with European Union directive 2002/95/EC. The mechanical drawings of all six packages are shown in sections 11.2 to 11.7– all dimensions are in millimetres. The solder reflow profile for all packages can be viewed in Section 11.8. 11.1 VNC2 Package Markings An example of the markings on each package is shown in Figure 11.1. The FTDI part number is too long for the 32 QFN package so in this case the last two digits are wrapped down onto the date code line as shown in Figure 11.2. FTDl XXXXXXXXXX VNC2-64Q1A Line 1 – FTDI Logo Line 2 – Wafer Lot Number Line 3 – FTDI Part Number including revision. In this case it shows Rev A. Please check for most recent revision. YYWW Line 4 - Date Code YY - year year WW - work week Figure 11.1 Package Markings FTDl XXXXXXXXXX VNC2-32Q 1A YYWW Figure 11.2 Markings – 32 QFN The last letter of the FTDI part number is the silicon revision number. This may change from A to B to C, etc. Please check the part number for the most recent revision. Copyright © Future Technology Devices International Limited 60 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 11.2 VNC2, LQFP-32 Package Dimensions Figure 11.3 LQFP-32 Package Dimensions 11.3 VNC2, QFN-32 Package Dimensions Figure 11.4 QFN-32 Package Dimensions Copyright © Future Technology Devices International Limited 61 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 11.4 VNC2, LQFP-48 Package Dimensions Figure 11.5 LQFP-48 Package Dimensions Copyright © Future Technology Devices International Limited 62 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 11.5 VNC2, QFN-48 Package Dimensions Figure 11. 6 QFN-48 Package Dimensions Copyright © Future Technology Devices International Limited 63 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 11.6 VNC2, LQFP-64 Package Dimensions 12 10 FTDl 10 XXXXXXXX VNC2-64L1A YYWW 12 Pin # 64 Pin # 1 0.5 1.0 0. 22+/- 0.05 1.4 +/- 0.05 1.60 MAX 12o +/- 1o Mi 0.05Ma 0.15 n x 0.25 0.2 Mi n 0. 09 Min 0. 16 Max 0. 09 Min 0. 2 Max 0.6 +/-0.15 0.2+/- 0.03 Figure 11.7 64 pin LQFP Package Details Copyright © Future Technology Devices International Limited 64 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 11.7 VNC2, QFN-64 Package Dimensions FTDl XXXXXXXXXX VNC2-64Q1A YYWW Figure 11.8 64 pin QFN Package Details Copyright © Future Technology Devices International Limited 65 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 11.8 Solder Reflow Profile Figure 11.9 All packages Reflow Solder Profile Copyright © Future Technology Devices International Limited 66 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Profile Feature Pb Free Solder Process (green material) SnPb Eutectic and Pb free (non green material) Solder Process Average Ramp Up Rate (Ts to Tp) 3°C / second Max. 3°C / Second Max. Preheat: - Temperature Min (Ts Min.) - Temperature Max (Ts Max.) - Time (ts Min to ts Max) 150°C 200°C 60 to 120 seconds 100°C 150°C 60 to 120 seconds Time Maintained Above Critical Temperature TL: - Temperature (TL) 217°C 183°C - Time (tL) 60 to 150 seconds 60 to 150 seconds Peak Temperature (Tp) 260°C see Table 11.2 Time within 5°C of actual Peak 30 to 40 seconds 20 to 40 seconds Temperature (tp) Ramp Down Rate 6°C / second Max. 6°C / second Max. Time for T= 25°C to Peak 8 minutes Max. 6 minutes Max. Temperature, Tp Table 11.1 Reflow Profile Parameter Values SnPb Eutectic and Pb free (non green material) Package Thickness Volume mm3 < 350 Volume mm3 >=350 < 2.5 mm 235 +5/-0 °C 220 +5/-0 °C ≥ 2.5 mm 220 +5/-0 °C 220 +5/-0 °C Pb Free (green material) = 260 +5/-0 °C Table 11.2 Package Reflow Peak Temperature Copyright © Future Technology Devices International Limited 67 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 12 Contact Information Head Office – Glasgow, UK Branch Office – Tigard, Oregon, USA Future Technology Devices International Limited Unit 1, 2 Seaward Place, Centurion Business Park Glasgow G41 1HH United Kingdom Tel: +44 (0) 141 429 2777 Fax: +44 (0) 141 429 2758 Future Technology Devices International Limited (USA) 7130 SW Fir Loop Tigard, OR 97223-8160 USA Tel: +1 (503) 547 0988 Fax: +1 (503) 547 0987 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) E-Mail (Sales) E-Mail (Support) E-Mail (General Enquiries) sales1@ftdichip.com support1@ftdichip.com admin1@ftdichip.com us.sales@ftdichip.com us.support@ftdichip.com us.admin@ftdichip.com Branch Office – Taipei, Taiwan Branch Office – Shanghai, China Future Technology Devices International Limited (Taiwan) 2F, No. 516, Sec. 1, NeiHu Road Taipei 114 Taiwan, R.O.C. Tel: +886 (0) 2 8797 1330 Fax: +886 (0) 2 8751 9737 Future Technology Devices International Limited (China) Room 1103, No. 666 West Huaihai Road, Shanghai, 200052 China Tel: +86 21 62351596 Fax: +86 21 62351595 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) tw.sales1@ftdichip.com tw.support1@ftdichip.com tw.admin1@ftdichip.com E-mail (Sales) E-mail (Support) E-mail (General Enquiries) cn.sales@ftdichip.com cn.support@ftdichip.com cn.admin@ftdichip.com Web Site http://ftdichip.com Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country. Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640 Copyright © Future Technology Devices International Limited 68 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Appendix A – References Document References The following VNC2 documents and the full Vinculum-II Toolchain software suite can be downloaded by clicking on the appropriate links below: Technical note TN_108 Vinculum Chipset Feature Comparison Technical note TN_118 Vinculum-II Errata Technical Note Application note AN_118 Migrating Vinculum Designs From VNC1L to VNC2-48L1A Application note AN_137 Vinculum-II IO Cell Description Application note AN_138 Vinculum-II Debug Interface Description Application note AN_139 Vinculum-II IO Mux Explained Application note AN_140 Vinculum-II PWM Example Application note AN_142 Vinculum-II Toolchain Getting Started Guide Application note AN_144 Vinculum-II IO_Mux Configuration Utility User Guide Application note AN_145 Vinculum-II Toolchain Installation Guide Application note AN_151 Vinculum-II User Guide VNC2 FTDI Web Page Vinculum-II Web Page The following application notes provide pre-compiled example rom files and complete source code to allow users to get started:            Application Application Application Application Application Application Application Application Application Application Application note note note note note note note note note note note AN_182 AN_183 AN_185 AN_186 AN_187 AN_192 AN_193 AN_194 AN_195 AN_199 AN_203 : : : : : : : : : : : VNC2 UART to FT232 HostBridge VNC2 UART to CDC Modem Bridge VNC2 UART to USB HID Class HostBridge an SPI Slave to USB Memory bridge VNC2 UART to USB Memory Bridge an SPI Master to a USB HID class host bridge an SPI Master to a USB HID class host bridge VNC2 UART to HID Class device bridge an SPI Master to UART bridge VNC2 SPI Slave to HID Class device bridge Loading VNC2 ROM files Using V2PROG Utility For the most up to date pre-compiled rom files, please refer to the following FTDI webpage http://www.ftdichip.com/Firmware/Precompiled.htm Copyright © Future Technology Devices International Limited 69 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Acronyms and Abbreviations Terms USB FIFO SPI PWM GPIO I/O VNC1L VNC2 DMA IDE BOMS UART SIE CPU SoC FAT RTOS VOS OSI MOSI MISO SE0 EMCU FPGA Description Universal Serial Bus First In First Out Serial Peripheral Interface Pulse Width Modulation General Purpose Input Output Input / Output Vinculum-I Vinculum-II Direct Memory Access Integrated Development Environment Bulk Only Mass Storage Universal Asynchronous Receiver/Transmitter Serial Interface Engine Central Processing Unit System-on-a-chip File Allocation Table Real Time Operating System Vinculum Operating System Open System Interconnection Master Out Slave In Master In Slave Out Single Ended Zero Embedded Micro Central Processing Unit Field Programmable Gate Array Copyright © Future Technology Devices International Limited 70 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Appendix B – List of Figures and Tables List of Tables Table 1.1 Part Numbers ................................................................................................................. 2 Table 3.1 USB Interface Group ..................................................................................................... 16 Table 3.2 Power and Ground ........................................................................................................ 16 Table 3.3 Miscellaneous Signal Group ............................................................................................ 16 Table 3.4 Default I/O Configuration ............................................................................................... 18 Table 4.1 - Peripheral Pin Requirements ........................................................................................ 20 Table 5.1 I/O Peripherals Signal Names ........................................................................................ 26 Table 5.2 Group 0 ....................................................................................................................... 28 Table 5.3 Group 1 ....................................................................................................................... 28 Table 5.4 Group 2 ....................................................................................................................... 29 Table 5.5 Group 3 ....................................................................................................................... 29 Table 6.1 Data and Control Bus Signal Mode Options – UART Interface .............................................. 32 Table 6.2 SPI Signal Names ......................................................................................................... 33 Table 6.3 - SPI Slave Speeds ....................................................................................................... 34 Table 6.4 - Clock Phase/Polarity Modes.......................................................................................... 34 Table 6.5 Data and Control Bus Signal Mode Options - SPI Slave Interface ........................................ 36 Table 6.6 SPI Command and Status Fields ..................................................................................... 37 Table 6.7 SPI Command and Status Fields ..................................................................................... 42 Table 6.8 SPI Setup Bit Encoding .................................................................................................. 42 Table 6.9 SPI Slave Data Timing ................................................................................................... 43 Table 6.10 SPI Master Data Read Status Bit ................................................................................... 43 Table 6.11 SPI Master Data Write Status Bit .................................................................................. 44 Table 6.12 SPI Status Read Byte – bit descriptions ......................................................................... 45 Table 6.13 SPI Master Signal Names ............................................................................................. 46 Table 6.14 SPI Master Timing ....................................................................................................... 47 Table 6.15 Debugger Signal Name ............................................................................................... 47 Table 6.16 Data and Control Bus Signal Mode Options - Parallel FIFO Interface .................................. 49 Table 6.17 Asynchronous FIFO mode Read / Write Timing ............................................................... 50 Table 6.18 Synchronous FIFO control signals.................................................................................. 51 Table 6.19 Synchronous FIFO mode Read / Write Timing ................................................................. 52 Table 9.1 Absolute Maximum Ratings ............................................................................................ 57 Table 9.2 Operating Voltage and Current ....................................................................................... 57 Table 9.3 I/O Pin Characteristics ................................................................................................... 58 Table 9.4 USB I/O Pin (USBDP, USBDM) Characteristics .................................................................. 58 Table 9.5 Crystal Oscillator 1.8 Volts DC Characteristics .................................................................. 58 Table 9.6 ESD and Latch-up Specifications ..................................................................................... 58 Table 11.1 Reflow Profile Parameter Values .................................................................................... 67 Table 11.2 Package Reflow Peak Temperature ................................................................................ 67 Copyright © Future Technology Devices International Limited 71 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 List of Figures Figure 2.1 Simplified VNC2 Block Diagram ....................................................................................... 3 Figure 3.1 32 Pin LQFP – Top Down View ........................................................................................ 7 Figure 3.2 32 Pin QFN – Top Down View ......................................................................................... 8 Figure 3.3 48 Pin LQFP – Top Down View ........................................................................................ 9 Figure 3.4 48 Pin QFN – Top Down View ........................................................................................ 10 Figure 3.5 64 Pin LQFP – Top Down View ...................................................................................... 11 Figure 3.6 64 Pin QFN – Top Down View ........................................................................................ 12 Figure 3.7 Schematic Symbol 32 Pin ............................................................................................. 13 Figure 3.8 Schematic Symbol 48 Pin ............................................................................................. 14 Figure 3.9 Schematic Symbol 64 Pin ............................................................................................. 15 Figure 5.1 IOBUS to Group Relationship-64 Pin .............................................................................. 22 Figure 5.2 IOBUS to UART, SPI slave0 and SPI master example ....................................................... 23 Figure 5.3 IOBUS to UART, SPI slave0 and SPI master second example ............................................. 24 Figure 5.4 IOBUS to UART, SPI slave0 and SPI master third example ................................................ 25 Figure 5.5 VNC2 Toolchain App Wizard showing IOMux Configuration ................................................ 27 Figure 5.6 UART Example 64 pin ................................................................................................... 30 Figure 6.1 UART Receive Waveform .............................................................................................. 31 Figure 6.2 UART Transmit Waveform ............................................................................................. 31 Figure 6.3 - SPI CPOL CPHA Function ............................................................................................ 35 Figure 6.4 SPI Slave block diagram ............................................................................................... 35 Figure 6.5 Full Duplex Data Master Write ....................................................................................... 36 Figure 6.6 Full Duplex Data Master Read ....................................................................................... 37 Figure 6.7 SPI Command and Status Structure ............................................................................... 37 Figure 6.8 Half Duplex Data Master Write ...................................................................................... 38 Figure 6.9 Half Duplex Data Master Read ....................................................................................... 38 Figure 6.10 Half Duplex 3-pin Data Master Write ............................................................................ 39 Figure 6.11 Half Duplex 3-pin Data Master Read ............................................................................. 39 Figure 6.12 Unmanaged Mode Transfer Diagram ............................................................................. 40 Figure 6.13 VNC1L Mode Data Write ............................................................................................. 41 Figure 6.14 VNC1L Mode Data Read .............................................................................................. 41 Figure 6.15 VNC1L Compatible SPI Command and Status Structure .................................................. 41 Figure 6.16 SPI Slave Mode Timing ............................................................................................... 43 Figure 6.17 SPI Master Data Read (VNC2 Slave Mode) .................................................................... 44 Figure 6.18 SPI Slave Mode Data Write ......................................................................................... 44 Figure 6.19 SPI Slave Mode Status Read ....................................................................................... 45 Figure 6.20 SPI Master block diagram ........................................................................................... 45 Figure 6.21 Typical SPI Master Timing ........................................................................................... 47 Figure 6.22 Asynchronous FIFO mode Read / Write Cycle ................................................................ 50 Figure 6.23 Synchronous FIFO mode Read / Write Cycle .................................................................. 51 Figure 6.24 PWM – Timing Diagram .............................................................................................. 53 Figure 6.25 GPIO Port Groups ...................................................................................................... 53 Figure 7.1 USB Modes ................................................................................................................. 54 Figure 10.1 VNC2 Schematic (MCU – UART Interface) ..................................................................... 59 Copyright © Future Technology Devices International Limited 72 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Figure 11.1 Package Markings ...................................................................................................... 60 Figure 11.2 Markings – 32 QFN .................................................................................................... 60 Figure 11.3 LQFP-32 Package Dimensions ...................................................................................... 61 Figure 11.4 QFN-32 Package Dimensions ....................................................................................... 61 Figure 11.5 LQFP-48 Package Dimensions ...................................................................................... 62 Figure 11. 6 QFN-48 Package Dimensions ...................................................................................... 63 Figure 11.7 64 pin LQFP Package Details ....................................................................................... 64 Figure 11.8 64 pin QFN Package Details......................................................................................... 65 Figure 11.9 All packages Reflow Solder Profile ................................................................................ 66 Copyright © Future Technology Devices International Limited 73 Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.8 Document No.: FT_000138 Clearance No.: FTDI# 143 Appendix C – Revision History Document Title: Vinculum-II Embedded Dual USB Host Controller IC Datasheet Document Reference No.: FT_000138 Clearance No.: FTDI# 143 Product Page: Vinculum-II Document Feedback: Send Feedback Revision Changes Date 1.0 Initial Release 2010-02-26 1.1 Changed gpio signal names, fixed minor typographical errors, added crystal characteristic information, added ESD table 2010-09-09 1.2 Revised part numbers to “Rev B” in section 1.2, added notes to sections 3.12 and 5 – default pin assignments 2010-10-07 1.3 Added USB transfer/transaction combinations 2011-04-19 1.31 Table 37 (now 9.6) modified 2011-05-16 1.32 Table 33 (now 9.2) modified 2011-05-17 Renumbered and reformatted figures and tables, Added life/safety notice, Added comments regarding 48LQFP package in table 3.2, Replaced Figure 5.5 with new screen shot, Updated list of precompiled firmware in section 8.4, Replaced schematic and added notes in Section 10, Updated header, Updated revision history and contact information pages 2011-10-17 1.4 Added notes (5V safe inputs) in section 3.11, 3.12 and first page. 1.5 1.6 Added links to pre-compiled rom files. XTIN is referenced to 1.8V VCC PLL IN - Tables 3.3 and 9.1 2012-03-14 2016-07-07 Pin 8 updated from TEST to NC for rev C 1.7 Removed revision code in table1.1 2016-07-21 1.8 Updated Figure 11.3, Figure11.4, Figure11.5, Figure11.6 package dimensions 2019-05-27 Copyright © Future Technology Devices International Limited 74