MB90483CPMC

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13722-11E 16-bit Microcontroller CMOS F2MC-16LX MB90480B/485B Series MB90F481B/F482B/487B/488B/483C MB90F488B/F489B/V480B/V485B ■ DESCRIPTION The MB90480B/485B series is a 16-bit general-purpose FUJITSU SEMICONDUCTOR microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing. The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing. The MB90480B/485B series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I2C interface, DTP/ external interrupt, chip select, and 16-bit reload timer. *1 : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • Clock Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied × 4 (25 MHz internal operating frequency/3.3 V ± 0.3 V) 62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating frequency/3.0 V ± 0.3 V) PLL clock multiplier • Maximum memory space: 16 Mbytes (Continued) The information for microcontroller supports is shown in the following homepage. Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2002-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.7 MB90480B/485B Series (Continued) • Instruction set optimized for controller applications Supported data types (bit, byte, word, or long word) Typical addressing modes (23 types) 32-bit accumulator for enhanced high-precision calculation Enhanced signed multiplication/division instruction and RETI instruction functions • Instruction set designed for high-level programming language (C) and multi-task operations System stack pointer adopted Instruction set symmetry and barrel shift instructions • Non-multiplex bus/multiplex bus compatible • Enhanced execution speed 4-byte instruction queue • Enhanced interrupt functions 8 levels setting with programmable priority, 8 external interrupts • Data transfer function (μDMAC) Up to 16 channels • Embedded ROM Flash versions : 192 Kbytes, 256 Kbytes, 384 Kbytes, MASK versions : 192 Kbytes, 256 Kbytes • Embedded RAM Flash versions : 4 Kbytes, 6 Kbytes, 10 Kbytes, 24 Kbytes, MASK versions : 10 Kbytes, 16 Kbytes • General purpose ports Up to 84 ports (Includes 16 ports with input pull-up resistance settings, 16 ports with output open-drain settings) • A/D converter 8-channel RC sequential comparison type (10-bit resolution, 3.68 μs conversion time (at 25 MHz) ) • I2C interface (MB90485B series only) : 1channel, P76/P77 N-ch open drain pin (without P-ch) Do not apply high voltage in excess of recommended operating ranges to the N-ch open drain pin (with P-ch) in MB90V485B. • μPG (MB90485B series only) : 1 channel • UART : 1 channel • Extended I/O serial interface (SIO) : 2 channels • 8/16-bit PPG : 3 channels (with 8-bit × 6 channel/16-bit × 3 channel mode switching function) • 8/16-bit up/down counter/timer: 1 channel (with 8-bit × 2 channels/16-bit × 1-channel mode switching function) • PWC (MB90485B series only) : 3 channels (Capable of compare the inputs to two of the three) • 3 V/5 V I/F pin (MB90485B series only) P20 to P27, P30 to P37, P40 to P47, P70 to P77 • 16-bit reload timer : 1 channel • 16-bit I/O timer : 2 channels input capture, 6 channels output compare, 1 channel free-run timer • On chip dual clock generator system • Low-power consumption mode With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode • Packages : QFP 100/LQFP 100 • Process : CMOS technology • Power supply voltage : 3 V, single power supply (some ports can be operated by 5 V power supply at MB90485B series) 2 DS07-13722-11E MB90480B/485B Series ■ PRODUCT LINEUP • MB90480B series Part number Item Classification ROM size RAM size MB90F481B MB90F482B MB90V480B CPU function Ports UART 8/16-bit PPG 8/16-bit up/down counter/timer 16-bit free-run timer 16-bit Output compare I/O timers (OCU) Input capture (ICU) DTP/external interrupt circuit Extended I/O serial interface Timebase timer A/D converter Watchdog timer Low-power consumption (standby) modes Process Type Emulator power supply*2 Flash memory product Evaluation product 192 Kbytes 256 Kbytes ⎯ 4 Kbytes 6 Kbytes 16 Kbytes Number of instructions : 351 Instruction bit length : 8-bit, 16-bit Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bit, 16-bit Minimum instruction execution time : 40 ns (25 MHz machine clock) General-purpose I/O ports: up to 84 General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain output) 1 channel, start-stop synchronized 8-bit × 6 channels/16-bit × 3 channels Event input pins : 6, 8-bit up/down counters : 2 8-bit reload/compare registers : 2 Number of channels : 1 Overflow interrupt Number of channels : 6 Pin input factor : A match signal of compare register Number of channels : 2 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of external interrupt pin channels : 8 (edge or level detection) Embedded 2 channels 18-bit counter Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 MHz base oscillator) Stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode CMOS User pin*1, Not included security function 3 V/5 V versions ⎯ Included *1 : User pin : P20 to P27, P30 to P37, P40 to P47, P70 to P77 *2 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply switching) about details. Note : Ensure that you must write to Flash at VCC = 3.13 V to 3.60 V (3.3 V + 10%, −5%) . DS07-13722-11E 3 MB90480B/485B Series • MB90485B series Part number Item Classification ROM size RAM size MB90487B MB90488B MB90F488B MB90V485B MB90F489B Flash memory product 256 Kbytes 10 Kbytes Evaluation product ⎯ 16 Kbytes Flash memory product 384 Kbytes 24 Kbytes MB90483C MASK ROM product 256 Kbytes 16 Kbytes MASK ROM product 192 Kbytes 10 Kbytes 256 Kbytes 10 Kbytes CPU function Number of instructions : 351 Instruction bit length : 8-bit, 16-bit Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bit, 16-bit Minimum instruction execution time : 40 ns (25 MHz machine clock) General-purpose I/O ports : up to 84 General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain output) 1 channel, start-stop synchronized 8-bit × 6 channels/16-bit × 3 channels Event input pins : 6, 8-bit up/down counters : 2 8-bit reload/compare registers : 2 Number of channels : 1 Overflow interrupt Number of channels : 6 Pin input factor: A match signal of compare register Number of channels : 2 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of external interrupt pin channels: 8 (edge or level detection) Embedded 2 channels 1 channel 1 channel 3 channels 18-bit counter Interrupt cycles : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) (Continued) Ports UART 8/16-bit PPG 8/16-bit up/down counter/timer 16-bit free-run timer 16-bit I/O timers Output compare (OCU) Input capture (ICU) DTP/external interrupt circuit Extended I/O serial interface I2C interface*2 μPG PWC Timebase timer A/D converter 4 DS07-13722-11E MB90480B/485B Series (Continued) Part number Item Watchdog timer Low-power consumption (standby) modes Process MB90487B MB90488B MB90F488B MB90V485B MB90F489B MB90483C Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 MHz base oscillator) Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase timer mode CMOS 3 V/5 V power supply*1 ⎯ 3 V/5 V power supply*1 ⎯ 3 V/5 V power supply*1 Included security function ⎯ 3 V/5 V power supply*1 3 V/5 V power supply*1 Included security function ⎯ 3 V/5 V power supply*1 ⎯ Type Emulator power supply*3 Included *1 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and P70 to P77. *2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I2C. However, MB90V485B uses the N-ch open drain pin (with P-ch) . *3 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. Notes : • As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/μPG/I2C become CMOS input. • Ensure that you must write to Flash at VCC = 3.13 V to 3.60 V (3.3 V + 10%, − 5%) . DS07-13722-11E 5 MB90480B/485B Series ■ PIN ASSIGNMENT (TOP VIEW) P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 * : These are the pins for MB90485B series. The pins for MB90480B series are P36/A06, P37/A07, P43/A11, P44/A12, P45/A13, P75 to P77. Note : MB90485B series only • I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses the N-ch open drain pin (with P-ch) . • P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin. • As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/μPG/I2C become CMOS input. 6 DS07-13722-11E P74/TOT0 P75/PWC2* P76/SCL* P77/SDA* AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 Vss P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1* P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01* VCC5 P45/A13/EXTC* P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 P71/SOT0 P72/SCK0 P73/TIN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2 (FPT-100P-M06) MB90480B/485B Series (TOP VIEW) P21/A17 P20/A16 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS X0A X1A P57/CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1* P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01* VCC5 P45/A13/EXTC* P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 * : These are the pins for MB90485B series. The pins for MB90480B series are P36/A06, P37/A07, P43/A11, P44/A12, P45/A13, P75 to P77. Note : MB90485B series only • I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses the N-ch open drain pin (with P-ch) . • P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin. • As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ μPG/I2C become CMOS input. DS07-13722-11E P71/SOT0 P72/SCK0 P73/TIN0 P74/TOT0 P75/PWC2* P76/SCL* P77/SDA* AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 P82/IRQ2 (FPT-100P-M20) 7 MB90480B/485B Series ■ PIN DESCRIPTIONS Pin No. QFP*1 82 83 80 79 77 LQFP*2 80 81 78 77 75 Pin name X0 X1 X0A X1A RST P00 to P07 85 to 92 83 to 90 AD00 to AD07 D00 to D07 P10 to P17 93 to 100 91 to 98 AD08 to AD15 D08 to D15 P20 to P23 99, 100, 1, 2 E C (CMOS) C (CMOS) I/O circuit type*3 A A A A B Clock (oscillator) input pin Clock (oscillator) output pin Clock (32 kHz oscillator) input pin Clock (32 kHz oscillator) output pin Reset input pin This is a general purpose I/O port. A setting in the port 0 input resistance register (RDR0) can be used to apply pull-up resistance (RD00-RD07 = “1”) . (Disabled when pin is set for output.) In multiplex mode, these pins function as the external address/data bus low I/O pins. In non-multiplex mode, these pins function as the external data bus low output pins. This is a general purpose I/O port. A setting in the port 1 input resistance register (RDR1) can be used to apply pull-up resistance (RD10-RD17 = “1”) . (Disabled when pin is set for output.) In multiplex mode, these pins function as the external address/data bus high I/O pins. In non-multiplex mode, these pins function as the external data bus high output pins. This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. Function 1 to 4 When the bits of external address output control register (HACR) are (CMOS/H) set to "0" in multiplex mode, these pins function as address high output pins (A16 to A19). A16 to A19 When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins (A16 to A19). P24 to P27 This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. 5 to 8 3 to 6 When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high E output pins (A20 to A23). A20 to A23 (CMOS/H) When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins (A20 to A23). PPG0 to PPG3 Output pins for PPG. This is a general purpose I/O port. E (CMOS/H) In non-multiplex mode, this pin functions as an external address pin. P30 9 7 A00 AIN0 8/16-bit up/down timer input pin (ch.0) . 8 DS07-13722-11E MB90480B/485B Series (Continued) Pin No. QFP*1 LQFP*2 Pin name P31 10 8 A01 BIN0 P32 12 10 A02 ZIN0 P33 13 11 A03 AIN1 P34 14 12 A04 BIN1 P35 15 13 A05 ZIN1 P36, P37 A06, A07 16, 17 14, 15 P36, P37 A06, A07 PWC0, PWC1*4 P40 18 16 A08 SIN2 P41 19 17 A09 SOT2 P42 20 18 A10 SCK2 G (CMOS/H) G (CMOS/H) E D (CMOS) E (CMOS/H) E (CMOS/H) E (CMOS/H) E (CMOS/H) E (CMOS/H) I/O circuit type*3 Function This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.0) . This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.0) This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.1) . This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.1) . This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.1) This is a general purpose I/O port. MB90480B In non-multiplex mode, these pins function as external series address pins. This is a general purpose I/O port. In non-multiplex mode, these pins function as external PWC input pins This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. Extended I/O serial interface input pin. This is a general purpose I/O port. MB90485B address pins. series (CMOS/H) F (CMOS) In non-multiplex mode, this pin functions as an external address pin. Extended I/O serial interface output pin. This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. Extended I/O serial interface clock input/output pin. (Continued) DS07-13722-11E 9 MB90480B/485B Series Pin No. QFP*1 LQFP*2 Pin name P43, P44 I/O circuit type*3 Function This is a general purpose I/O port. F (CMOS) MB90480B In non-multiplex mode, these pins function as external series A11, A12 address pins. 21, 22 19, 20 P43, P44 A11, A12 MT00, MT01 P45 A13 24 22 P45 A13 EXTC*4 P46, P47 25, 26 23, 24 A14, A15 OUT4, OUT5 P50 70 68 ALE P51 71 69 RD P52 72 70 WRL This is a general purpose I/O port. In non-multiplex mode, these pins function as external F (CMOS) MB90485B address pins. series μPG output pins This is a general purpose I/O port. F MB90480B In non-multiplex mode, this pin functions as an external series (CMOS) address pin. This is a general purpose I/O port. G MB90485B In non-multiplex mode, this pin functions as an external series address pin. (CMOS/H) μPG input pin. This is a general purpose I/O port. F In non-multiplex mode, these pins function as external address pins. (CMOS) Output compare event output pins. This is a general purpose I/O port. In external bus mode, this pin functions as the ALE pin. D (CMOS) In external bus mode, this pin functions as the address load enable (ALE) signal pin. D (CMOS) In external bus mode, this pin functions as the read strobe output (RD) signal pin. This is a general purpose I/O port. In external bus mode, when the WRE bit in the EPCR register is set to “1”, this pin functions as the WRL pin. This is a general purpose I/O port. In external bus mode, this pin functions as the RD pin. D (CMOS) In external bus mode, this pin functions as the lower data write strobe output (WRL) pin. When the WRE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode with 16-bit bus width, when the WRE bit in the EPCR register is set to “1”, this pin functions as the WRH pin. P53 73 71 WRH D (CMOS) In external bus mode with 16-bit bus width, this pin functions as the upper data write strobe output (WRH) pin. When the WRE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. (Continued) 10 DS07-13722-11E MB90480B/485B Series Pin No. QFP*1 LQFP*2 Pin name I/O circuit type*3 Function This is a general purpose I/O port. In external bus mode, when the HDE bit in the EPCR register is set to “1”, this pin functions as the HRQ pin. In external bus mode, this pin functions as the hold request input (HRQ) pin. When the HDE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the HDE bit in the EPCR register is set to “1”, this pin functions as the HAK pin. In external bus mode, this pin functions as the hold acknowledge output (HAK) pin. When the HDE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the RYE bit in the EPCR register is set to “1”, this pin functions as the RDY pin. In external bus mode, this pin functions as the external ready (RDY) input pin. When the RYE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the CKE bit in the EPCR register is set to “1”, this pin functions as the CLK pin. In external bus mode, this pin functions as the machine cycle clock (CLK) output pin. When the CKE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. P54 74 72 HRQ D (CMOS) P55 75 73 HAK D (CMOS) P56 76 74 RDY D (CMOS) P57 78 76 CLK P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P70 SIN0 P71 SOT0 P72 SCK0 P73 TIN0 P74 TOT0 D (CMOS) 38 to 41 36 to 39 43 to 46 41 to 44 27 28 29 30 31 25 26 27 28 29 These are general purpose I/O ports. H (CMOS) These are the analog input pins for A/D converter. These are general purpose I/O ports. H (CMOS) These are the analog input pins for A/D converter. This is a general purpose I/O port. G (CMOS/H) This is the UART serial data input pin. F (CMOS) This is a general purpose I/O port. This is the UART serial data output pin. This is a general purpose I/O port. G (CMOS/H) This is the UART serial communication clock I/O pin. G F (CMOS) This is a general purpose I/O port. This is a general purpose I/O port. This is the 16-bit reload timer output pin. (Continued) (CMOS/H) This is the 16-bit reload timer event input pin. DS07-13722-11E 11 MB90480B/485B Series Pin No. QFP*1 LQFP*2 Pin name P75 32 30 P75 PWC2* P76 33 31 P76 SCL*4 P77 34 32 P77 SDA* 4 4 I/O circuit type*3 F (CMOS) Function MB90480B This is a general purpose I/O port. series G MB90485B This is a general purpose I/O port. series (CMOS/H) This is a PWC input pin. F (CMOS) MB90480B This is a general purpose I/O port. series This is a general purpose I/O port. I MB90485B Serves as the I2C interface data I/O pin. During oper(NMOS/H) series ation of the I2C interface, leave the port output in a high impedance state. F (CMOS) MB90480B This is a general purpose I/O port. series This is a general purpose I/O port. I MB90485B Serves as the I2C interface data I/O pin. During oper(NMOS/H) series ation of the I2C interface, leave the port output in a high impedance state. 47, 48 45, 46 P80, P81 IRQ0, IRQ1 P82 to P87 P90 58 56 SIN1 CS0 P91 59 57 SOT1 CS1 P92 60 58 SCK1 CS2 P93 FRCK 61 59 ADTG CS3 62 60 P94 PPG4 E (CMOS/H) E (CMOS/H) These are general purpose I/O ports. E (CMOS/H) External interrupt input pins. E These are general purpose I/O ports. This is a general purpose I/O port. Extended I/O serial interface data input pin. Chip select 0. This is a general purpose I/O port. D Extended I/O serial interface data output pin. (CMOS) Chip select 1. This is a general purpose I/O port. Extended I/O serial interface clock input/output pin. Chip select 2. This is a general purpose I/O port. E (CMOS/H) When the A/D converter is in use, this pin functions as the external trigger input pin. Chip select 3. This is a general purpose I/O port. D (CMOS) PPG timer output pin. (Continued) When the free-run timer is in use, this pin functions as the external clock input pin. 52 to 57 50 to 55 IRQ2 to IRQ7 (CMOS/H) External interrupt input pins. 12 DS07-13722-11E MB90480B/485B Series (Continued) Pin No. QFP*1 63 64 65 LQFP*2 61 62 63 Pin name P95 PPG5 P96 IN0 P97 IN1 PA0 to PA3 OUT0 to OUT3 I/O circuit type*3 D (CMOS) PPG timer output pin. Function This is a general purpose I/O port. This is a general purpose I/O port. E (CMOS/H) Input capture ch.0 trigger input pin. E D (CMOS) ⎯ ⎯ ⎯ This is a general purpose I/O port. These are general purpose I/O ports. Output compare event output pins. A/D converter analog power supply input pin. A/D converter reference voltage input pin. A/D converter GND pin. (CMOS/H) Input capture ch.1 trigger input pin. 66 to 69 64 to 67 35 36 37 33 34 35 AVCC AVRH AVSS MD0 to MD2 VCC3 49 to 51 47 to 49 84 82 J Operating mode selection input pins. (CMOS/H) ⎯ 3.3 V ± 0.3 V power supply pins (VCC3) . MB90480B 3.3 V ± 0.3 V power supply pin. series Usually, use VCC = VCC3 = VCC5 as a 3 V power supply. 23 21 VCC5 ⎯ 3 V/5 V power supply pin. 5 V power supply pin when P20 to P27, P30 to P37, MB90485B P40 to P47, P70 to P77 are used as 5 V I/F pins. series Usually, use VCC = VCC3 = VCC5 as a 3 V power supply (when the 3 V power supply is used alone) . GND pins. 11, 42, 81 9, 40, 79 VSS ⎯ *1 : QFP : FPT-100P-M06 *2 : LQFP : FPT-100P-M20 *3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”. *4 : As for MB90V485B, input pins become CMOS input. DS07-13722-11E 13 MB90480B/485B Series ■ I/O CIRCUIT TYPES Type X1, X1A Circuit Remarks • Feedback resistance X1, X0 : approx. 1 MΩ X1A, X0A : approx. 10 MΩ • With standby control X0, X0A A Standby control signal Hysteresis input with pull-up resistance B Hysteresis input • With input pull-up resistance control • CMOS level input/output CTL P-ch P-ch Pout N-ch Nout C CMOS P-ch Pout N-ch Nout CMOS level input/output D CMOS P-ch Pout N-ch • Hysteresis input • CMOS level output E Nout CMOS (Continued) 14 DS07-13722-11E MB90480B/485B Series (Continued) Type Circuit P-ch N-ch Remarks • CMOS level input/output • With open drain control Open drain control signal F CMOS P-ch N-ch Open drain control signal • CMOS level output • Hysteresis input • With open drain control G Hysteresis input • CMOS level input/output • Analog input Pout N-ch P-ch H Nout CMOS Analog input N-ch Digital output I Hysteresis input • Hysteresis input • N-ch open drain output (Flash memory product) (Flash memory product) • CMOS level input • With high voltage control for flash testing Control signal J Mode input Diffusion resistance (MASK ROM product) Hysteresis input (MASK ROM product) Hysteresis input DS07-13722-11E 15 MB90480B/485B Series ■ HANDLING DEVICES 1. Be careful never to exceed maximum rated voltages (preventing latch-up) In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and VSS pins exceeds the rated voltage level. When latch-up occurs, the power supply current increases rapidly causing the possibility of thermal damage to circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (AVCC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) . 2. Treatment of unused pins Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. 3. Treatment of Power Supply Pins (VCC/VSS) When multiple VCC/VSS pins are present, device design considerations for prevention of latch-up and unwanted electromagnetic interference, abnormal strobe signal operation due to ground level rise, and conformity with total output current ratings require that all power supply pins must be externally connected to power supply or ground. Consideration should be given to connecting power supply sources to the VCC/VSS pins of this device with as low impedance as possible. It is also recommended that a bypass capacitor of approximately 0.1 μF be placed between the VCC and VSS lines as close to this device as possible. 4. Crystal Oscillator Circuits Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable operation it is strongly recommended that printed circuit board artwork places ground bypass capacitors as close as possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits. 5. Precautions when turning the power supply on In order to prevent abnormal operation in the chip’s internal step-down circuits, a voltage rise time during poweron of 50 μs (0.2 V to 2.7 V) or greater should be assured. 6. Supply Voltage Stabilization Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation. As a standard for power supply voltage stability, it is recommended that the peak-to-peak VCC ripple voltage at commercial supply frequency (50/60 Hz) be 10 % or less of VCC, and that the transient voltage fluctuation be no more than 0.1 V/ms or less when the power supply is turned on or off. 7. Proper power-on/off sequence The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AVCC. 16 DS07-13722-11E MB90480B/485B Series 8. Treatment of power supply pins on models with A/D converters Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS. 9. Notes on Using Power Supply Only the MB90485B series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V power supply, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 can be interfaced as 5 V power supplies separately from the main 3 V power supply. Note that the analog power supplies (such as AVCC and AVSS) for the A/D converter can be used only as 3 V power supplies. 10. Notes on Using External Clock Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals. X0 OPEN X1 11. Treatment of NC pins NC (internally connected) pins should always be left open. 12. Notes on during operation of PLL clock mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operation if such failure occurs. 13. When the MB90480B/485B series microcontroller is used as a single system When the MB90480B/485B series microcontroller is used as a single system, use connections so the X0A = VSS, and X1A = Open. 14. Writing to Flash memory For writing to Flash memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V. DS07-13722-11E 17 MB90480B/485B Series ■ BLOCK DIAGRAM X0, X1, RST X0A, X1A MD2, MD1, MD0 8 Clock control Circuit RAM CPU F2MC16LX series core Interrupt controller ROM 8/16-bit PPG PPG0 to PPG5 μDMAC Communication prescaler 2 8/16-bit up/down counter/timer AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 F2MC-16LX Bus SIN0 SOT0 SCK0 SIN1, SIN2 SOT1, SOT2 SCK1, SCK2 UART μPG EXTC MT00 MT01 Extended I/O serial interface × 2 channels Chip select Input/output timer 16-bit input capture × 2 channels CS0 to CS3 AVCC AVRH AVSS ADTG AN0 to AN7 IN0, IN1 OUT0 to OUT5 A/D converter ( 8/10-bit ) 16-bit output compare × 6 channels 16-bit free-run timer 16-bit reload timer TIN0 TOT0 SCL SDA 8 PWC0 PWC1 PWC2 PWC × 3 channels I2C interface External interrupt IRQ0 to IRQ7 I/O port 8 P00 8 P10 8 P20 8 P30 8 P40 8 P50 8 P60 8 P70 8 P80 8 P90 4 PA0 to P07 to P17 to P27 to P37 to P47 to P57 to P67 to P77 to P87 to P97 to PA3 : Only MB90485B series P00 to P07 (8 pins) P10 to P17 (8 pins) P40 to P47 (8 pins) P70 to P77 (8 pins) : with an input pull-up resistance setting register. : with an input pull-up resistance setting register. : with an open drain setting register. : with an open drain setting register. MB90485B series only • I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses the N-ch open drain pin (with P-ch) . • P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin. • As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ μPG/I2C become CMOS input. Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a set of pins is used with an internal module, it cannot also be used as an I/O port. 18 DS07-13722-11E MB90480B/485B Series ■ MEMORY MAP • MB90F481B/F482B/487B/488B/483C/F488B/V480B/V485B/F489B Internal ROM Single chip external bus FFFFFFH External ROM external bus ROM area ROM area Address #1 010000H ROM area FF bank image ROM area FF bank image Address #2 * Address #3 RAM 000100H 0000D0H Register RAM Register RAM Register Peripheral 000000H Peripheral : External Peripheral : Access inhibited : Internal * : In models where address #3 overlaps with address #2, this external area does not exist. Model MB90F481B MB90F482B MB90487B MB90488B MB90F488B MB90V480B MB90V485B MB90483C MB90F489B Address #1 FC0000H *1 FC0000H FD0000H FC0000H FC0000H (FC0000H) (FC0000H) FB0000H*4 F90000H *2 Address #2 Address #3 001100H 001900H 002900H 002900H 002900H 004000H 004000H 004000H 006100H*3 004000H or 008000H, selected by the MS bit in the ROMM register 0080000H fixed *1 : No memory cells from FC0000H to FC7FFFH and FE0000H to FE7FFFH. The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00 bank are the same, enabling reference to tables in ROM without using the for specification in the pointer declaration. For example, in accessing address 00C000H it is actually the contents of ROM at FFC000H that are accessed. If the MS bit in the ROMM register is set to “0”, the ROM area in the FF bank will exceed 48 Kbytes and it is not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH is reflected in the 00 bank and the area from FF0000H to FF3FFFH can be seen in the FF bank only. (Continued) DS07-13722-11E 19 MB90480B/485B Series (Continued) *2 : In MB90F489B, there is no access to F8 bank and FC bank on the single-chip mode or the internal-ROM external-bus mode. *3 : Because installed-RAM area is larger than MB90V485B, MB90F489B should execute emulation in an area that is larger than 004000H by the emulation memory area setting on the tool side. *4 : In MB90483C, there is no access to F8 bank to FA bank and FC bank on the single-chip mode or the internalROM external-bus mode. 20 DS07-13722-11E MB90480B/485B Series • MB90F489B Single chip FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFFH ROM (FD bank) FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H F7FFFFH ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (FD bank) ROM (FE bank) ROM (FF bank) Internal ROM external bus External ROM external bus 010000H 00FFFFH 008000H 007FFFH 006100H 0060FFH ROM area FF bank image ROM area FF bank image RAM 000100H 0000FFH 0000D0H 0000CFH Register RAM Register RAM Register Peripheral 000000H Peripheral Peripheral : Internal : External : Access inhibited DS07-13722-11E 21 MB90480B/485B Series • MB90483C Internal ROM external bus External ROM external bus Single chip FFFFFFH ROM (FF bank) ROM (FF bank) ROM (FE bank) ROM (FD bank) FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H F7FFFFH ROM (FB bank) ROM (FB bank) ROM (FD bank) 010000H 00FFFFH 004000H or 008000H 004000H 003FFFH ROM area FF bank image ROM area FF bank image RAM 000100H 0000FFH 0000D0H 0000CFH Register RAM Register RAM Register Peripheral Peripheral Peripheral 000000H : Internal : External : Access inhibited 22 DS07-13722-11E MB90480B/485B Series ■ F2MC-16L CPU PROGRAMMING MODEL • Dedicated registers AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8-bit 16-bit 32-bit Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register • General purpose registers MSB 000180H + RP × 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R3 R5 R7 R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 16-bit LSB • Processor status 15 PS ILM 13 12 RP 87 CCR 0 DS07-13722-11E 23 MB90480B/485B Series ■ I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Up/down timer input enable register Interrupt/DTP enable register Interrupt/DTP source register Request level setting register Request level setting register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 4 output pin register Port 0 input resistance register Port 1 input resistance register Abbreviated Read/ register name Write Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Up/down timer input control DTP/external interrupts Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 4 (Open-drain control) Port 0 (resistance control) Port 1 (resistance control) Port 7 (Open-drain control) Port 6, A/D Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (MB90480B series) 11XXXXXXB (MB90485B series) XXXXXXXXB XXXXXXXXB ----XXXXB XX000000B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (MB90480B series) XX000000B (MB90485B series) 00000000B 00000000B ----0000B 00000000B 00000000B 00000000B 00000000B (MB90480B series) XX000000B (MB90485B series) 11111111B (Continued) PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA UDRE ENIR EIRR ELVR DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 RDR0 RDR1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1EH 1FH Port 7 output pin register Analog input enable register ODR7 ADER R/W R/W 24 DS07-13722-11E MB90480B/485B Series Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H Register name Serial mode register Serial control register Serial input/output register Serial status register Communication prescaler control register Serial mode control status register 0 Serial data register 0 Communication prescaler control register 0 Serial mode control status register 1 Serial data register 1 Communication prescaler control register 1 Reload register L (ch.0) Reload register H (ch.0) Reload register L (ch.1) Reload resister H (ch.1) Reload register L (ch.2) Reload register H (ch.2) Reload register L (ch.3) Reload register H (ch.3) Reload register L (ch.4) Reload register H (ch.4) Reload register L (ch.5) Reload register H (ch.5) PPG0 operating mode control register PPG1 operating mode control register PPG2 operating mode control register PPG3 operating mode control register PPG4 operating mode control register PPG5 operating mode control register PPG0, PPG1 output control register PPG2, PPG3 output control register Abbreviated register name Read/ Write SMR R/W SCR W, R/W SIDR/SODR R/W SSR R, R/W (Reserved area) CDCR SMCS0 SDR0 SDCR0 SMCS1 SDR1 SDCR1 R/W R, R/W R/W R/W R, R/W R/W R/W Resource name Initial value 00000X00B 00000100B XXXXXXXXB 00001000B UART Communication prescaler (UART) SIO1 (ch.0) Communication prescaler SIO1 (ch.0) SIO2 (ch.1) Communication prescaler SIO2 (ch.1) 00--0000B ----0000B 00000010B XXXXXXXXB 0---0000B ----0000B 00000010B XXXXXXXXB 0---0000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0X000XX1B 0X000001B 0X000XX1B 0X000001B 0X000XX1B 0X000001B 00000000B 00000000B PRLL0 R/W PRLH0 R/W PRLL1 R/W PRLH1 R/W PRLL2 R/W PRLH2 R/W PRLL3 R/W PRLH3 R/W PRLL4 R/W PRLH4 R/W PRLL5 R/W PRLH5 R/W PPGC0 R/W PPGC1 R/W PPGC2 R/W PPGC3 R/W PPGC4 R/W PPGC5 R/W PPG01 R/W (Reserved area) PPG23 R/W (Reserved area) 8/16-bit PPG (ch.0 to ch.5) 8/16-bit PPG 8/16-bit PPG (Continued) DS07-13722-11E 25 MB90480B/485B Series Abbreviated register name Address 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H Register name PPG4, PPG5 output control register Read/ Write Resource name 8/16-bit PPG Initial value 00000000B 00000000B PPG45 R/W (Reserved area) ADCS1 ADCS2 ADCR1 ADCR2 OCCP0 OCCP1 OCCP2 OCCP3 OCCP4 OCCP5 OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 R/W W, R/W R W, R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R IPCP0 R R IPCP1 R ICS01 R/W Control status register Data register Output compare register (ch.0) lower digits Output compare register (ch.0) upper digits Output compare register (ch.1) lower digits Output compare register (ch.1) upper digits Output compare register (ch.2) lower digits Output compare register (ch.2) upper digits Output compare register (ch.3) lower digits Output compare register (ch.3) upper digits Output compare register (ch.4) lower digits Output compare register (ch.4) upper digits Output compare register (ch.5) lower digits Output compare register (ch.5) upper digits Output compare control register (ch.0) Output compare control register (ch.1) Output compare control register (ch.2) Output compare control register (ch.3) Output compare control register (ch.4) Output compare control register (ch.5) Input capture data register (ch.0) lower digits Input capture data register (ch.0) upper digits Input capture data register (ch.1) lower digits Input capture data register (ch.1) upper digits Input capture control status register A/D converter 00000000B XXXXXXXXB 00000XXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 16-bit input/output timer output compare (ch.0 to ch.5) 00000000B 00000000B 00000000B 00000000B 00000000B 0000--00B ---00000B 0000--00B ---00000B 0000--00B ---00000B XXXXXXXXB 16-bit input/output timer input capture (ch.0, ch.1) XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B (Continued) (Reserved area) 26 DS07-13722-11E MB90480B/485B Series Abbreviated register name Address 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H* 77H* 78H* 79H* 7AH* 7BH* 7CH* 7DH* 7EH* 7FH* 80H* 81H* 82H* 83H 84H* 85H 86H* 87H Register name Timer counter data register lower digits Timer counter data register upper digits Timer counter control status register Timer counter control status register Compare clear register lower digits Compare clear register upper digits Up/down count register (ch.0) Up/down count register (ch.1) Reload/compare register (ch.0) Reload/compare register (ch.1) Counter control register (ch.0) lower digits Counter control register (ch.0) upper digits ROM mirror function select register Counter control register (ch.1) lower digits Counter control register (ch.1) upper digits Counter status register (ch.0) Counter status register (ch.1) Read/ Write R/W R/W R/W R/W R/W R R W W W, R/W R/W Resource name Initial value 00000000B 00000000B 00000000B 0--00000B XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 0X00X000B 00000000B TCDT TCDT TCCS TCCS CPCLR UDCR0 UDCR1 RCR0 RCR1 CCRL0 CCRH0 16-bit input/output timer free-run timer 8/16-bit up/down counter/timer (Reserved area) ROMM CCRL1 CCRH1 R/W W, R/W R/W 8/16-bit up/down counter/timer ROM mirroring function ------+1B 0X00X000B -0000000B 00000000B 8/16-bit UDC 00000000B 00000000B 0000000XB 00000000B 00000000B 00000000B 0000000XB 00000000B 00000000B 00000000B 0000000XB 00000000B 00000000B ------00B ------00B ------00B (Continued) CSR0 R, R/W (Reserved area) CSR1 R, R/W (Reserved area) PWCSR0 PWCR0 PWCSR1 PWCR1 PWCSR2 PWCR2 R, R/W PWC control/status register PWC data buffer register PWC control/status register PWC data buffer register PWC control/status register PWC data buffer register Dividing ratio control register Dividing ratio control register Dividing ratio control register PWC (ch.0) R/W R, R/W PWC (ch.1) R/W R, R/W PWC (ch.2) R/W PWC (ch.0) PWC (ch.1) PWC (ch.2) DIVR0 R/W (Reserved area) DIVR1 R/W (Reserved area) DIVR2 R/W (Reserved area) DS07-13722-11E 27 MB90480B/485B Series Abbreviated register name Address 88H* 89H* 8AH* 8BH* 8CH* 8DH 8EH* 8FH to 9BH 9CH 9DH 9EH 9FH A0H A1H A2H, A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H Register name Bus status register Bus control register Clock control register Address register Data register μPG control status register μDMAC status register lower digits μDMAC status register upper digits Program address detection control status resister Delayed interrupt source general/ cancel register Low-power consumption mode control register Clock select register μDMAC stop status register Automatic ready function select register External address output control register Bus control signal select register Watchdog timer control register Timebase timer control register Watch timer control register μDMAC enable register lower digits μDMAC enable register upper digits Flash memory control status register Read/ Write R R/W R/W R/W R/W R/W R/W R/W R/W R/W W, R/W R, R/W Resource name Initial value 00000000B 00000000B IBSR IBCR ICCR IADR IDAR PGCSR (Disabled) DSRL DSRH PACSR DIRR LPMCR CKSCR I2C --0XXXXXB -XXXXXXXB XXXXXXXXB (Reserved area) μPG μDMAC μDMAC Address match detection function Delayed interrupt generator module Low-power consumption Low-power consumption μDMAC External pins External pins External pins Watchdog timer Timebase timer Watch timer μDMAC μDMAC Flash memory interface 00000---B 00000000B 00000000B 00000000B -------0B 00011000B 11111100B (Reserved area) DSSR ARSR HACR EPCR WDTC TBTC WTC DERL DERH FMCS R/W W W W R, W W, R/W R, R/W R/W R/W W, R/W 00000000B 0011 - -00B ********B 1000*10 -B XXXXX111B 1XX00100B 10001000B 00000000B 00000000B 000X0000B (Reserved area) (Disabled) Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 W, R/W W, R/W W, R/W W, R/W W, R/W Interrupt controller W, R/W W, R/W W, R/W W, R/W XXXX0111B XXXX0111B XXXX0111B XXXX0111B XXXX0111B XXXX0111B XXXX0111B XXXX0111B XXXX0111B (Continued) 28 DS07-13722-11E MB90480B/485B Series Address B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H to FFH 100H to #H 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H Register name Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Chip select area mask register 0 Chip select area register 0 Chip select area mask register 1 Chip select area register 1 Chip select area mask register 2 Chip select area register 2 Chip select area mask register 3 Chip select area register 3 Chip select control register Chip select active level register Timer control status register 16-bit timer register/ 16-bit reload register Abbreviated register name Read/ Write W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXX0111B XXXX0111B XXXX0111B ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 CMR0 CAR0 CMR1 CAR1 CMR2 CAR2 CMR3 CAR3 CSCR CALR TMCSR TMR/TMRLR Interrupt controller XXXX0111B XXXX0111B XXXX0111B XXXX0111B 00001111B 11111111B 00001111B 11111111B Chip select function 00001111B 11111111B 00001111B 11111111B ----000*B ----0000B 00000000B ----0000B XXXXXXXXB 16-bit reload timer R/W (Reserved area) PLL output control register PLLOS W Low-power consumption ------X0B (External area) (RAM area) Program address detection register 0 (Low order address) Program address detection register 0 (Middle order address) Program address detection register 0 (High order address) Program address detection register 1 (Low order address) Program address detection register 1 (Middle order address) Program address detection register 1 (High order address) PADR1 R/W Address match detection function XXXXXXXXB PADR0 R/W Address match detection function XXXXXXXXB * : These registers are only for MB90485B series. They are used as the reserved area on MB90480B series. (Continued) DS07-13722-11E 29 MB90480B/485B Series (Continued) Descriptions for read/write R/W : Readable and writable R : Read only W : Write only Descriptions for initial value 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. : This bit is not used. * : The initial value of this bit is “1” or “0”. The value depends on the mode pin (MD2, MD1 and MD0) . + : The initial value of this bit is “1” or “0”. The value depends on the RAM area of device. 30 DS07-13722-11E MB90480B/485B Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Interrupt source Reset INT9 instruction Exception INT0 (IRQ0) INT1 (IRQ1) INT2 (IRQ2) INT3 (IRQ3) INT4 (IRQ4) INT5 (IRQ5) INT6 (IRQ6) INT7 (IRQ7) PWC1 (MB90485B series only) PWC2 (MB90485B series only) PWC0 (MB90485B series only) PPG0/PPG1 counter borrow PPG2/PPG3 counter borrow PPG4/PPG5 counter borrow 8/16-bit up/down counter/ timer (ch.0, ch.1) compare/ underflow/overflow/up/down inversion Input capture (ch.0) load Input capture (ch.1) load Output compare (ch.0) match Output compare (ch.1) match Output compare (ch.2) match Output compare (ch.3) match Output compare (ch.4) match Output compare (ch.5) match UART sending completed 16-bit free-run timer overflow, 16-bit reload timer underflow*2 UART receiving completed SIO1 (ch.0) SIO2 (ch.1) × × × Clear of EI2OS × × × μDMAC channel number ⎯ ⎯ ⎯ 0 × × × × × × × × × 1 × × × × 5 6 8 9 10 × × × 11 12 7 13 14 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH Interrupt control register Number ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 Address ⎯ ⎯ ⎯ 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H #25 FFFF98H ICR07 0000B7H #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H ICR13 0000BDH (Continued) ICR08 ICR09 ICR10 ICR11 0000B8H 0000B9H 0000BAH 0000BBH ICR12 0000BCH DS07-13722-11E 31 MB90480B/485B Series (Continued) Interrupt source I2C interface (MB90485B series only) A/D converter Flash write/erase, timebase timer, watch timer *1 Delay interrupt generator module 15 Clear of EI2OS μDMAC channel number Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H ICR15 FFFF54H 0000BFH Interrupt control register Number ICR14 Address 0000BEH : Interrupt request flag is not cleared by the interrupt clear signal. : Interrupt request flag is cleared by the interrupt clear signal. : Interrupt request flag is cleared by the interrupt clear signal (stop request present) . *1 : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time. *2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE = 1) to disable (TMCSR : INTE = 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to IL0 =111B) , then set the INTE bit to 0. Note : If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request flags at the EI2OS/μDMAC interrupt clear signal. Therefore if either of the two sources uses the EI2OS/ μDMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corresponding resource should be set to “0” and interrupt requests from that resource should be handled by software polling. 32 DS07-13722-11E MB90480B/485B Series ■ PERIPHERAL RESOURCES 1. I/O Ports The I/O ports perform the functions of either sending data from the CPU to the I/O pins, or loading information from the I/O into the CPU, according to the setting of the corresponding port data register (PDR) . The input/ output direction of each I/O pin can be set in individual bit units by the port direction register (DDR) for each I/O port. The MB90480B/485B series has 84 input/output pins. The I/O ports are port 0 through port A. (1) Port Data Registers PDR0 Address : 000000H PDR1 Address : 000001H PDR2 Address : 000002H PDR3 Address : 000003H PDR4 Address : 000004H PDR5 Address : 000005H PDR6 Address : 000006H PDR7 Address : 000007H PDR8 Address : 000008H PDR9 Address : 000009H PDRA Address : 00000AH Initial value Undefined Access R/W*1 7 P07 6 P06 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 7 P17 7 P27 6 P16 6 P26 5 P15 5 P25 4 P14 4 P24 3 P13 3 P23 2 P12 2 P22 1 P11 1 P21 0 P10 0 P20 Undefined R/W*1 Undefined R/W*1 7 P37 7 P47 7 P57 6 P36 6 P46 6 P56 5 P35 5 P45 5 P55 4 P34 4 P44 4 P54 3 P33 3 P43 3 P53 2 P32 2 P42 2 P52 1 P31 1 P41 1 P51 0 P30 0 P40 0 P50 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 7 P67 6 P66 5 P65 4 P64 3 P63 2 P62 1 P61 0 P60 Undefined R/W*1 7 P77 7 P87 7 P97 6 P76 6 P86 6 P96 5 P75 5 P85 5 P95 4 P74 4 P84 4 P94 3 P73 3 P83 3 P93 2 P72 2 P82 2 P92 1 P71 1 P81 1 P91 0 P70 0 P80 0 P90 Undefined*2 R/W*1 Undefined R/W*1 Undefined R/W*1 7 ⎯ 6 ⎯ 5 ⎯ 4 ⎯ 3 PA3 2 PA2 1 PA1 0 PA0 Undefined R/W*1 *1 : The R/W indication for I/O ports is somewhat different than R/W access to memory, and involves the following operations. • Input mode Read : Reads the corresponding signal pin level. Write : Writes to the output latch. • Output mode Read : Reads the value from the data register latch. Write : Outputs the value to the corresponding signal pin. *2 : The initial value of this bit is “11XXXXXXB” on MB90485B series. DS07-13722-11E 33 MB90480B/485B Series (2) Port Direction Registers DDR0 7 Address : 000010H DDR1 Address : 000011H DDR2 Address : 000012H DDR3 Address : 000013H DDR4 Address : 000014H DDR5 Address : 000015H DDR6 Address : 000016H DDR7 Address : 000017H DDR8 Address : 000018H DDR9 Address : 000019H DDRA Address : 00001AH D07 7 D17 7 D27 7 D37 7 D47 7 D57 7 D67 7 D77*1 7 D87 7 D97 7 ⎯ 6 D06 6 D16 6 D26 6 D36 6 D46 6 D56 6 D66 6 D76* 6 D86 6 D96 6 ⎯ 1 5 D05 5 D15 5 D25 5 D35 5 D45 5 D55 5 D65 5 D75 5 D85 5 D95 5 ⎯ 4 D04 4 D14 4 D24 4 D34 4 D44 4 D54 4 D64 4 D74 4 D84 4 D94 4 ⎯ 3 D03 3 D13 3 D23 3 D33 3 D43 3 D53 3 D63 3 D73 3 D83 3 D93 3 DA3 2 D02 2 D12 2 D22 2 D32 2 D42 2 D52 2 D62 2 D72 2 D82 2 D92 2 DA2 1 D01 1 D11 1 D21 1 D31 1 D41 1 D51 1 D61 1 D71 1 D81 1 D91 1 DA1 0 D00 0 D10 0 D20 0 D30 0 D40 0 D50 0 D60 0 D70 0 D80 0 D90 0 DA0 Initial value 00000000B Access R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B*2 R/W 00000000B R/W 00000000B R/W ----0000B R/W *1 : The value is set to “⎯” on MB90485B series only. *2 : The initial value of this bit is “XX000000B” on MB90485B series only. • When a set of pins is functioning as a port, the corresponding signal pins are controlled as follows. 0 : Input mode. 1 : Output mode. Reset to “0”. Notes : • When any of these registers are accessed using a read-modify-write type instruction (such as a bit set instruction) , the bit specified in the instruction will be set to the indicated value. However, the contents of output registers corresponding to any other bits having input settings will be rewritten to the input values of those pins at that time. For this reason, when changing any pin that has been used for input to output, first write the desired value to the PDR register before setting the DDR register for output. • P76, P77 (MB90485B series only) This port has no DDR. To use P77 and P76 as I2C pins, set the PDR value to “1” so that port data remains enabled (to use P77 and P76 for general purposes, disable I2C) . The port is an open drain output (with no P-ch) . To use it as an input port, therefore, set the PDR to “1” to turn off the output transistor and add a pull-up resistor to the external output. 34 DS07-13722-11E MB90480B/485B Series (3) Port Input Resistance Registers RDR0 7 6 Address : 00001CH RDR1 Address : 00001DH RD07 7 RD17 RD06 6 RD16 5 RD05 5 RD15 4 RD04 4 RD14 3 RD03 3 RD13 2 RD02 2 RD12 1 RD01 1 RD11 0 RD00 0 RD10 Initial value Access 00000000B R/W 00000000B R/W These registers control the use of pull-up resistance in input mode. 0 : No pull-up resistance in input mode. 1 : With pull-up resistance in input mode. In output mode, these registers have no function (no pull-up resistance) . Input/output mode settings are controlled by the setting of port direction (DDR) registers. In case of a stop (SPL = 1) , no pull-up resistance is applied (high impedance) . Using of this function is prohibited when an external bus is used. Do not write to these registers. (4) Port Output Pin Registers ODR7 7 6 Address : 00001EH OD77*1 OD76*1 ODR4 Address : 00001BH 7 OD47 6 OD46 5 OD75 5 OD45 4 OD74 4 OD44 3 OD73 3 OD43 2 OD72 2 OD42 1 OD71 1 OD41 0 OD70 0 OD40 Initial value 00000000 * B2 Access R/W 00000000B R/W *1 : The value is set to “⎯” on MB90485B series only. *2 : The initial value of this bit is “XX000000B” on MB90485B series only. These registers control open drain settings in output mode. 0 : Standard output port functions in output mode. 1 : Open drain output port in output mode. In input mode, these registers have no function (Hi-Z output) . Input/output mode settings are controlled by the setting of port direction (DDR) registers. Using of this function is prohibited when an external bus is used. Do not write to these registers. (5) Analog Input Enable Register ADER 7 6 Address : 00001FH ADE7 ADE6 5 ADE5 4 ADE4 3 ADE3 2 ADE2 1 ADE1 0 ADE0 Initial value Access 11111111B R/W This register controls the port 6 pins as follows. 0 : Port input/output mode. 1 : Analog input mode. The default value at reset is all “1”. (6) Up/down Timer Input Enable Register UDER 7 6 5 Address : 00000BH ⎯ ⎯ UDE5 4 UDE4 3 UDE3 2 UDE2 1 UDE1 0 UDE0 Initial value Access XX000000B R/W This register controls the port 3 pins as follows. 0 : Port input mode. 1 : Up/down timer input mode.The default value at reset is “0”. DS07-13722-11E 35 MB90480B/485B Series 2. UART The UART is a serial I/O port for asynchronous (start-stop synchronized) communication as well as CLK synchronized communication. • Full duplex double buffer • Transfer modes : asynchronous (start-stop synchronized) , or CLK synchronized (no start bit or stop bit) . • Multi-processor mode supported. • Embedded proprietary baud rate generator Asynchronous : 76923/38461/19230/9615/500 k/250 kbps CLK synchronized : 16 M/8 M/4 M/2 M/1 M/500 kbps • External clock setting available, allows use of any desired baud rate. • Can use internal clock feed from PPG1. • Data length : 7-bit (asynchronous normal mode only) or 8-bit. • Master/slave type communication functions (in multi-processor mode) . • Error detection functions (parity, framing, overrun) • Transfer signals are NRZ encoded. • μDMAC supported (for receiving/sending) 36 DS07-13722-11E MB90480B/485B Series (1) Register List 15 CDCR SCR SSR 8 bits 87 ⎯ SMR SIDR (R)/SODR (W) 8 bits 0 Serial mode register (SMR) 7 6 MD0 R/W 0 5 CS2 R/W 0 4 CS1 R/W 0 3 CS0 R/W 0 2 Reserved 1 SCKE R/W 0 0 SOE R/W 0 000020H MD1 R/W 0 R/W X Initial value Serial control register (SCR) 15 14 P R/W 0 13 SBL R/W 0 12 CL R/W 0 11 A/D R/W 0 10 REC W 1 9 RXE R/W 0 8 TXE R/W 0 000021H PEN R/W 0 Initial value Serial I/O register (SIDR/SODR) 7 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X 000022H D7 R/W X Initial value Serial status register (SSR) 15 14 ORE R 0 13 FRE R 0 12 RDRF R 0 11 TDRE R 1 10 BDS R/W 0 9 RIE R/W 0 8 TIE R/W 0 000023H PE R 0 Initial value Communication prescaler control register (CDCR) 15 14 SRST R/W 0 13 ⎯ ⎯ ⎯ 12 ⎯ ⎯ ⎯ 11 DIV3 R/W 0 10 DIV2 R/W 0 9 DIV1 R/W 0 8 DIV0 R/W 0 000025H MD R/W 0 Initial value DS07-13722-11E 37 MB90480B/485B Series (2) Block Diagram Control signal Receiving interrupt (to CPU) Proprietary baud rate generator PPG1 (internal connection) External clock Receiving control circuit SIN0 SCK0 Clock select circuit Sending clock Receiving clock Sending interrupt (to CPU) Sending control circuit Start bit detect circuit Receive bit counter Receiving parity counter Send start circuit Send bit counter Send parity counter SOT0 Receiving status decision circuit μDMAC receiving error generation circuit (to CPU) Receiving shifter Receiving control circuit Sending shifter Sending start SODR SIDR F2MC-16LX BUS SMR MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR PEN P SBL CL A/D REC RXE TXE SSR PE ORE FRE RDRF TDRE BDS RIE TIE Control signal 38 DS07-13722-11E MB90480B/485B Series 3. Expanded I/O Serial Interface The expanded I/O serial interface is an 8-bit × 1-channel serial I/O interface for clock synchronized data transfer. A selection of LSB-first or MSB-first data transfer is provided. There are two serial I/O operation modes. • Internal shift clock mode : Data transfer is synchronized with the internal clock signal. • External shift clock mode : Data transfer is synchronized with a clock signal input from the external clock signal pin (SCK) . In this mode the general-purpose port that shares the external clock signal pin (SCK) can be used for transfer according to CPU instructions. (1) Register List Serial mode control status register 0/1 (SMCS0, SMCS1) Address : 000027H 00002BH 15 SMD2 R/W 14 SMD1 R/W 13 SMD0 R/W 12 SIE R/W 11 SIR R/W 10 BUSY R 9 STOP R/W 8 STRT R/W Initial value 00000010B Address : 000026H 00002AH 7 ⎯ ⎯ 6 ⎯ ⎯ 5 ⎯ ⎯ 4 ⎯ ⎯ 3 MODE R/W 2 BDS R/W 1 SOE R/W 0 SCOE R/W ----0000B Serial data register 0/1 (SDR0, SDR1) Address : 000028H 00002CH 7 D7 R/W 6 D6 R/W 5 D5 R/W 4 D4 R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W XXXXXXXXB Communication prescaler control register 0/1 (SDCR0, SDCR1) Address : 000029H 00002DH 15 MD R/W 14 ⎯ ⎯ 13 ⎯ ⎯ 12 ⎯ ⎯ 11 DIV3 R/W 10 DIV2 R/W 9 DIV1 R/W 8 DIV0 R/W 0---0000B DS07-13722-11E 39 MB90480B/485B Series (2) Block Diagram Internal data bus (MSB first) D0 to D7 SIN1, SIN2 D7 to D0 (LSB first) Transfer direction selection Read Write Initial value SDR (Serial Data Register) SOT1, SOT2 SCK1, SCK2 Control circuit Shift clock counter Internal clock 2 1 0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE SMD2 SMD1 SMD0 Interrupt request Internal data bus 40 DS07-13722-11E MB90480B/485B Series 4. 8/10-bit A/D Converter The A/D converter converts analog input voltage to digital values, and provides the following features. • Conversion time : minimum 3.68 μs per channel (92 machine cycles at 25 MHz machine clock, including sampling time) • Sampling time : minimum 1.92 μs per channel (48 machine cycles at 25 MHz machine clock) • RC sequential comparison conversion method, with sample & hold circuit. • 8-bit or 10-bit resolution • Analog input selection of 8 channels Single conversion mode : Conversion from one selected channel. Scan conversion mode : Conversion from multiple consecutive channels, programmable selection of up to 8 channels. Continuous conversion mode : Repeated conversion of specified channels. Stop conversion mode : Conversion from one channel followed by a pause until the next activation allows to synchronize with conversion start. • At the end of A/D conversion, an A/D conversion completed interrupt request can be generated to the CPU. The interrupt can be used activate the μDMAC in order to transfer the results of A/D conversion to memory for efficient continuous processing. • The starting factor conversion may be selected from software, external trigger (falling edge) , or timer (rising edge) . (1) Register List ADCS2, ADCS1 (Control status register) ADCS1 7 6 5 Address : 000046H MD1 ANS2 MD0 0 R/W 0 R/W 14 INT 0 R/W 0 R/W 13 INTE 0 R/W 4 ANS1 0 R/W 12 PAUS 0 R/W 3 ANS0 0 R/W 11 STS1 0 R/W 2 ANE2 0 R/W 10 STS0 0 R/W 1 ANE1 0 R/W 9 STRT 0 W 0 ANE0 0 R/W 8 Reserved ← Initial value ← Bit attributes ADCS2 Address : 000047H 15 BUSY 0 R/W 0 R/W ← Initial value ← Bit attributes ADCR2, ADCR1 (Data register) ADCR1 7 Address : 000048H D7 X R 6 D6 X R 14 ST1 0 W 5 D5 X R 13 ST0 0 W 4 D4 X R 12 CT1 0 W 3 D3 X R 11 CT0 0 W 2 D2 X R 10 ⎯ X R 1 D1 X R 9 D9 X R 0 D0 X R 8 D8 X R ← Initial value ← Bit attributes ADCR2 Address : 000049H 15 S10 0 W ← Initial value ← Bit attributes DS07-13722-11E 41 MB90480B/485B Series (2) Block Diagram AVCC AVRH AVSS D/A converter MP AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input circuit Comparator Sequential comparison register Sample & hold circuit Decoder Data registers ADCR1, ADCR2 A/D control register 1 ADTG Trigger activation Timer activation φ A/D control register 2 ADCS1, ADCS2 Timer (PPG1 output) Operation clock Prescaler 42 Internal Data bus DS07-13722-11E MB90480B/485B Series 5. 8/16-bit PPG The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output using a pulse from the timer operation. Hardware resources include 6 × 8-bit down counters, 12 × 8-bit reload timers, 3 × 16-bit control registers, 6 × external pulse output pins, and 6 × interrupt outputs. Note that MB90480B/485B series has six channels for 8-bit PPG use, which can also be combined as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5 to operate as a three-channel 16-bit PPG. The following is a summary of functions. • 8-bit PPG output 6-channel independent mode : Provides PPG output operation on six independent channels. • 16-bit PPG output operation mode : Provides 16-bit PPG output on three channels. The six original channels are used in combination as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5. • 8 + 8-bit PPG output operation mode : Output from PPG0 (PPG2/PPG4) is used as clock input to PPG1 (PPG3/ PPG5) to provide to 8-bit PPG output at any desired period length. • PPG output operation : Produces pulse waves at any desired period and duty ratio. The PPG module can also be used with external circuits as a D/A converter. (1) Register List PPGC0/PPGC2/PPGC4 (PPG0/PPG2/PPG4 operation mode control register) 00003AH 00003CH 00003EH 7 PEN0 R/W 0 6 ⎯ ⎯ X 5 PE00 R/W 0 4 PIE0 R/W 0 3 PUF0 R/W 0 2 ⎯ ⎯ X 1 ⎯ ⎯ X 0 Reserved ⎯ 1 Read/write Initial value PPGC1/PPGC3/PPGC5 (PPG1/PPG3/PPG5 operation mode control register) 00003BH 00003DH 00003FH 15 PEN1 R/W 0 14 ⎯ ⎯ X 13 PE10 R/W 0 12 PIE1 R/W 0 11 PUF1 R/W 0 10 MD1 R/W 0 9 MD0 R/W 0 8 Reserved ⎯ 1 Read/write Initial value PPG01/PPG23/PPG45 (PPG0 to PPG5 output control register) 000040H 000042H 000044H 7 PCS2 R/W 0 6 PCS1 R/W 0 5 PCS0 R/W 0 4 PCM2 R/W 0 3 PCM1 R/W 0 2 1 0 PCM0 Reserved Reserved R/W 0 R/W 0 R/W 0 Read/write Initial value PRLL0 to PRLL5 (Reload register L) 00002EH 7 6 5 000030H D07 D06 D05 000032H R/W R/W R/W 000034H X X X 000036H 000038H PRLH0 to PRLH5 (Reload register H) 00002FH 15 14 13 000031H D15 D14 D13 000033H R/W R/W R/W 000035H X X X 000037H 000039H 4 D04 R/W X 3 D03 R/W X 2 D02 R/W X 1 D01 R/W X 0 D00 R/W X Read/write Initial value 12 D12 R/W X 11 D11 R/W X 10 D10 R/W X 9 D09 R/W X 8 D08 R/W X Read/write Initial value DS07-13722-11E 43 MB90480B/485B Series (2) Block Diagram • 8-bit PPG ch.0/2/4 block Diagram Peripheral clock × 16 Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock PPG0/2/4 output enable PPG0/2/4 A/D converter PPG0/2/4 output latch PEN0 PCNT (down counter) Count clock select “L”/“H” selector Timebase counter output main clock × 512 “L”/“H” select PRLL PRLBH PUF0 S RQ IRQ ch.1/3/5 borrow PIE0 PPGC0 (operation mode control) PRLH “L” data bus “H” data bus 44 DS07-13722-11E MB90480B/485B Series • 8-bit PPG ch.1/3/5 Block Diagram Peripheral clock × 16 Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock PPG1/3/5 output enable PPG1/3/5 UART0 PPG1/3/5 output latch PEN1 PCNT (down counter) Count clock select “L”/“H” selector Timebase counter output main clock × 512 “L”/“H” select PRLL PRLBH PUF1 S RQ IRQ PIE1 PPGC1 (operation mode control) PRLH “L” data bus “H” data bus DS07-13722-11E 45 MB90480B/485B Series 6. 8/16-bit up/down Counter/Timer 8/16-bit up/down counter/timer consists of up/down counter/timer circuits including six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, as well as the related control circuits. (1) Principal Functions • 8-bit count register enables counting in the range 0 to 256. (In 16-bit × 1 mode, counting is enabled in the range 0 to 65535) • Count clock selection provides four count modes. Count modes Timer mode Up/down count mode Phase differential down count mode ( × 2) Phase differential down count mode ( × 8) • In timer mode, there is a choice of two internal count clock signals. Count clock (at 16 MHz operation) Edge detection 125 ns (8 MHz : × 2) 0.5 μs (2 MHz : × 8) Falling edge detection Rising edge detection Both rising/falling edge detection Edge detection disabled • In phase differential count mode, to handle encoder counting for motors, the encoder A-phase, B-phase, and Z-phase are each input, enabling easy and highly accurate counting of angle of rotation, speed of rotation, etc. • The ZIN pin provides a selection of two functions. ZIN pin Counter clear function Gate functions • A compare function and reload function are provided, each for use separately or in combination. Both functions can be activated together for up/down counting in any desired bandwidth. Compare/reload function Compare function (output interrupt at compare events) Compare function (output interrupt and clear counter at compare events) Reload function (output interrupt and reload at underflow events) Compare/reload function (output interrupt and clear counter at compare events, output interrupt and reload at underflow events) Compare/reload disabled • Individual control over interrupts at compare, reload (underflow) and overflow events. • Count direction flag enables identification of the last previous count direction. • Interrupt generated when count direction changes. • In up/down count mode, there is a choice of trigger edge detection for the input signal from external pins. 46 DS07-13722-11E MB90480B/485B Series (2) Register List 15 UDCR1 RCR1 87 UDCR0 RCR0 CSR0 CCRL0 CSR1 CCRL1 8-bit 0 Reserved area CCRH0 Reserved area CCRH1 8-bit CCRH0 (Counter Control Register High ch.0) 15 14 CDCF R/W 13 CFIE R/W 12 CLKS R/W 11 CMS1 R/W 10 CMS0 R/W 9 CES1 R/W 8 CES0 R/W Address : 00006DH M16E R/W Initial value 00000000B CCRH1 (Counter Control Register High ch.1) 15 14 CDCF R/W 13 CFIE R/W 12 CLKS R/W 11 CMS1 R/W 10 CMS0 R/W 9 CES1 R/W 8 CES0 R/W Address : 000071H ⎯ Initial value -0000000B CCRL0/1 (Counter Control Register Low ch.0/ch.1) Address : 00006CH Address : 000070H 7 UDMS R/W 6 CTUT W 5 UCRE R/W 4 RLDE R/W 3 UDCC W 2 CGSC R/W 1 CGE1 R/W 0 CGE0 R/W Initial value 0X00X000B CSR0/1 (Counter Status Register ch.0/ch.1) Address : 000072H Address : 000074H 7 CSTR R/W 6 CITE R/W 5 UDIE R/W 4 CMPF R/W 3 OVFF R/W 2 UDFF R/W 1 UDF1 R 0 UDF0 R Initial value 00000000B UDCR0/1 (Up Down Count Register ch.0/ch.1) 15 14 D16 R 6 D06 R 13 D15 R 5 D05 R 12 D14 R 4 D04 R 11 D13 R 3 D03 R 10 D12 R 2 D02 R 9 D11 R 1 D01 R 8 D10 R 0 D00 R Address : 000069H D17 R 7 Initial value 00000000B Address : 000068H D07 R Initial value 00000000B RCR0/1 (Reload/Compare Register ch.0/ch.1) 15 14 D16 W 6 D06 W 13 D15 W 5 D05 W 12 D14 W 4 D04 W 11 D13 W 3 D03 W 10 D12 W 2 D02 W 9 D11 W 1 D01 W 8 D10 W 0 D00 W Address : 00006BH D17 W 7 Initial value 00000000B Address : 00006AH D07 W Initial value 00000000B DS07-13722-11E 47 MB90480B/485B Series (3) Block Diagram Internal Data bus 8-bit CGE1 CGE0 CGSC ZIN0 RCR0 (Reload/ compare register 0) CTUT Reload control Edge/level detection UCRE RLDE UDCC Counter clear 8-bit UDCR0 (Up/down count register 0) CES1 CES0 CMS1 CMS0 UDMS AIN0 BIN0 Carry UDFF OVFF CMPF Up/down count clock selection Prescaler CLKS Count clock UDF1 UDF0 CDCF CFIE CITE UDIE CSTR Interrupt output 48 DS07-13722-11E MB90480B/485B Series 7. DTP/External Interrupt The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16LX CPU to activate the extended intelligent μDMAC or interrupt processing. (1) Detailed Register Descriptions Interrupt/DTP Enable Register (ENIR : Enable Interrupt Request Register) ENIR 7 6 5 4 3 2 1 Address : 00000CH EN7 EN6 EN5 EN4 EN3 EN2 EN1 R/W R/W R/W R/W R/W R/W R/W 0 EN0 R/W Initial value 00000000B Interrupt/DTP Source Register (EIRR : External Interrupt Request Register) EIRR 15 14 13 12 11 10 9 Address : 00000DH ER7 ER6 ER5 ER4 ER3 ER2 ER1 R/W R/W R/W R/W R/W R/W R/W 8 ER0 R/W Initial value XXXXXXXXB Interrupt Level Setting Register (ELVR : External Level Register) 7 6 LA3 R/W 14 LA7 R/W 5 LB2 R/W 13 LB6 R/W 4 LA2 R/W 12 LA6 R/W 3 LB1 R/W 11 LB5 R/W 2 LA1 R/W 10 LA5 R/W 1 LB0 R/W 9 LB4 R/W 0 LA0 R/W 8 LA4 R/W Address : 00000EH LB3 R/W 15 Initial value 00000000B Address : 00000FH LB7 R/W Initial value 00000000B (2) Block Diagram F2MC-16 bus 4 Interrupt/DTP enable register Gate Source F/F Edge detection circuit 4 4 Request input 4 Interrupt/DTP source register Interrupt level setting register 8 DS07-13722-11E 49 MB90480B/485B Series 8. 16-bit Input/Output Timer The 16-bit input/output timer module is composed of one 16-bit free-run timer, six output compare and two input capture modules. These functions can be used to output six independent wave form based on the 16-bit freerun timer, enabling input pulse width measurement and external clock frequency measurement. • Register List • 16-bit free-run timer 15 0 CPCLR 000066/67H Compare-clear register 000062/63H TCDT Timer counter data register Timer counter control status register 000064/65H TCCS • 16-bit output compare 15 0 OCCP0 to OCCP5 00004A/4C/4E/50/52/54H 00004B/4D/4F/51/53/55H 000056/58/5AH 000057/59/5BH OCS1/3/5 Output compare registers Output compare control registers OCS0/2/4 • 16-bit input capture 15 0 IPCP0, IPCP1 00005C/5EH 00005D/5FH 000060H Input capture data registers ICS01 Input capture control status register 50 DS07-13722-11E MB90480B/485B Series • Block Diagram Control logic Interrupt 16-bit free-run timer 16-bit timer Clear Output compare 0 Output compare 1 Internal data Bus Output compare 2 Output compare 3 Output compare 4 Output compare 5 To each block Compare register 0 Compare register 1 TQ OUT0 TQ OUT1 Compare register 2 TQ OUT2 Compare register 3 Compare register 4 TQ OUT3 TQ OUT4 Compare register 5 TQ OUT5 Input capture 0 Input capture 1 Capture data register 0 Edge selection IN0 Capture data register 1 Edge selection IN1 DS07-13722-11E 51 MB90480B/485B Series (1) 16-bit Free Run Timer The 16-bit free-run timer is composed of a 16-bit up-down counter and control status register. The counter value of this timer is used as the base timer for the input capture and output compare. • The counter operation provides a choice of eight clock types. • A counter overflow interrupt can be produced. • A mode setting is available to initialize the counter value whenever the output compare value matches the value in the compare clear register. • Register List Compare clear register (CPCLR) 15 14 CL14 R/W 13 CL13 R/W 12 CL12 R/W 11 CL11 R/W 10 CL10 R/W 9 CL09 R/W 8 CL08 R/W 000067H CL15 R/W Initial value XXXXXXXXB 7 6 CL06 R/W 5 CL05 R/W 4 CL04 R/W 3 CL03 R/W 2 CL02 R/W 1 CL01 R/W 0 CL00 R/W 000066H CL07 R/W Initial value XXXXXXXXB Timer counter data register (TCDT) 15 14 T14 R/W 13 T13 R/W 12 T12 R/W 11 T11 R/W 10 T10 R/W 9 T09 R/W 8 T08 R/W 000063H T15 R/W Initial value 00000000B 7 6 T06 R/W 5 T05 R/W 4 T04 R/W 3 T03 R/W 2 T02 R/W 1 T01 R/W 0 T00 R/W 000062H T07 R/W Initial value 00000000B Timer counter control status register (TCCS) 15 14 ⎯ R/W 13 ⎯ R/W 12 MSI2 R/W 11 MSI1 R/W 10 MSI0 R/W 9 ICLR R/W 8 ICRE R/W 000065H ECKE R/W Initial value 0--00000B 7 6 IVFE R/W 5 STOP R/W 4 MODE R/W 3 SCLR R/W 2 CLK2 R/W 1 CLK1 R/W 0 CLK0 R/W 000064H IVF R/W Initial value 00000000B 52 DS07-13722-11E MB90480B/485B Series • Block Diagram Interrupt request IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 φ Prescaler Internal data Bus Clock 16-bit free-run timer 16-bit compare clear register Compare circuit MSI2 to MSI0 Count value output T15 to T00 ICLR ICRE Interrupt request A/D activation DS07-13722-11E 53 MB90480B/485B Series (2) Output Compare The output compare module is composed of a 16-bit compare register, compare output pin unit, and control register. When the value in the compare register in this module matches the 16-bit free-run timer, the pin output levels can be inverted and an interrupt generated. • There are six compare registers in all, each operating independently. A setting is available to allow two compare registers to be used to control output. • Interrupts can be set in terms of compare match events. • Register List Output compare registers (OCCP0 to OCCP5) 15 14 C14 R/W 13 C13 R/W 12 C12 R/W 11 C11 R/W 10 C10 R/W 9 C09 R/W 8 C08 R/W 00004BH 00004DH 00004FH 000051H 000053H 000055H C15 R/W Initial value 00000000B 7 6 C06 R/W 5 C05 R/W 4 C04 R/W 3 C03 R/W 2 C02 R/W 1 C01 R/W 0 C00 R/W 00004AH 00004CH 00004EH 000050H 000052H 000054H C07 R/W Initial value 00000000B Output compare control registers (OCS1/OCS3/OCS5) 15 14 ⎯ ⎯ 13 ⎯ ⎯ 12 CMOD R/W 11 OTE1 R/W 10 OTE0 R/W 9 OTD1 R/W 8 OTD0 R/W 000057H 000059H 00005BH ⎯ ⎯ Initial value ---00000B Output compare control registers (OCS0/OCS2/OCS4) 7 6 ICP0 R/W 5 ICE1 R/W 4 ICE0 R/W 3 ⎯ ⎯ 2 ⎯ ⎯ 1 CST1 R/W 0 CST0 R/W 000056H 000058H 00005AH ICP1 R/W Initial values 0000--00B 54 DS07-13722-11E MB90480B/485B Series • Block Diagram 16-bit timer counter value (T15 to T00) Compare control Compare register 0 (2, 4) TQ OTE0 OUT0 (2) (4) Internal data Bus 16-bit timer counter value (T15 to T00) Compare control CMOD TQ OTE1 OUT1 (3) (5) Compare register 1 (3, 5) ICP1 ICP0 ICE0 ICE0 Control unit Individual control blocks Compare 1 (3) (5) interrupt Compare 0 (2) (4) interrupt DS07-13722-11E 55 MB90480B/485B Series (3) Input Capture The input capture module performs the functions of detecting the rising edge, falling edge, or both edges of signal input from external circuits, and saving the 16-bit free-run timer value at that moment to a register. An interrupt can also be generated at the instant of edge detection. The input capture module consists of input capture registers and a control register. Each input capture module has its own external input pin. • Selection of three types of valid edge for external input signals. Rising edge, falling edge, both edges. • An interrupt can be generated when a valid edge is detected in the external input signal. • Register List Input capture data registers (IPCP0, IPCP1) 15 14 CP14 R 13 CP13 R 12 CP12 R 11 CP11 R 10 CP10 R 9 CP09 R 8 CP08 R 00005DH 00005FH CP15 R Initial value XXXXXXXXB 7 6 CP06 R 5 CP05 R 4 CP04 R 3 CP03 R 2 CP02 R 1 CP01 R 0 CP00 R 00005CH 00005EH CP07 R Initial value XXXXXXXXB Input capture control status register (ICS01) 7 6 ICP0 R/W 5 ICE1 R/W 4 ICE0 R/W 3 EG11 R/W 2 EG10 R/W 1 EG01 R/W 0 EG00 R/W 000060H ICP1 R/W Initial value 00000000B • Block Diagram Capture data register 0 Edge detection IN0 Internal data Bus 16-bit timer counter value (T15 to T00) EG11 EG10 EG01 EG00 Capture data register 1 Edge detection IN1 ICP1 ICP0 ICE1 ICE0 Interrupt Interrupt 56 DS07-13722-11E MB90480B/485B Series 9. I2C Interface (MB90485B series only) The I2C interface is a serial I/O port supporting the Inter IC BUS. Serves as a master/slave device on the I2C bus. The I2C interface has the following functions. • Master/slave transmit/receive • Arbitration function • Clock synchronization • Slave address/general call address detection function • Forwarding direction detection function • Start condition repeated generation and detection • Bus error detection function (1) Register List Bus Status Register (IBSR) 000088H 7 BB R 6 RSC R 5 AL R 4 3 2 1 0 Initial value 00000000B LRB TRX AAS GCA FBT R R R R R Bus control register (IBCR) 000089H 15 14 13 12 11 10 9 8 INT R/W Initial value 00000000B BER BEIE SCC R/W R/W R/W MSS ACK GCAA INTE R/W R/W R/W R/W Clock control register (ICCR) 00008AH 7 6 5 EN R/W 4 3 2 CS2 R/W 1 CS1 R/W 0 CS0 R/W Initial value --0XXXXXB CS4 CS3 R/W R/W Address register (IADR) 00008BH 15 14 A6 R/W 13 A5 R/W 12 A4 R/W 11 A3 R/W 10 A2 R/W 9 A1 R/W 8 A0 R/W Initial value -XXXXXXXB Data register (IDAR) 00008CH 7 D7 R/W 6 D6 R/W 5 D5 R/W 4 D4 R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W Initial value XXXXXXXXB DS07-13722-11E 57 MB90480B/485B Series (2) Block Diagram ICCR EN I2C enable Clock dividing 1 ICCR F2MC-16LX Bus Peripheral clock 8 5 6 7 CS4 CS3 CS2 CS1 CS0 Clock selection 1 Clock dividing 2 2 4 8 16 32 64 128 256 Sync Shift clock generation Clock selection 2 Change timing of shift clock edge IBSR BB RSC LRB TRX FBT AL IBCR BER BEIE Interrupt request INTE INT IBCR SCC MSS ACK GCAA Start Master ACK enable GC-ACK enable Bus busy Repeat start Last Bit Transmission/ Reception Start/stop condition detection Error First Byte Arbitration lost detection SCL IRQ SDA End Start/stop condition detection IDAR IBSR AAS GCA Slave Global call Slave address comparison IADR 58 DS07-13722-11E MB90480B/485B Series 10. 16-bit Reload Timer The 16-bit reload timer provides a choice of functions, including internal clock signals that count down in synchronization with three types of internal clock, as well as an event count mode that counts down at specified edge detection events in pulse signals input from external pins. This timer defines an underflow as a change in count value from 0000H to FFFFH. Thus an underflow will occur when counting from the value “reload register setting value + 1”. The choice of counting operations includes reload mode, in which the count setting values is reloaded and counting continues following an underflow event, and one-shot mode, in which an underflow event causes counting to stop. An interrupt can be generated at counter underflow, and the timer is DTC compatible. (1) Register List • TMCSR (Timer control status register) Timer control status register (high) (TMCSR) 15 14 ⎯ ⎯ ⎯ 13 ⎯ ⎯ ⎯ 12 ⎯ ⎯ ⎯ 11 CSL1 R/W 0 10 CSL0 R/W 0 9 MOD2 R/W 0 8 MOD1 R/W 0 0000CBH ⎯ ⎯ ⎯ Read/Write Initial value Timer control status register (low) (TMCSR) 7 6 OUTE R/W 0 5 OUTL R/W 0 4 RELD R/W 0 3 INTE R/W 0 2 UF R/W 0 1 CNTE R/W 0 0 TRG R/W 0 0000CAH MOD0 R/W 0 Read/Write Initial value • 16-bit timer register/16-bit reload register TMR/TMRLR (high) 15 14 D14 R/W X 13 D13 R/W X 12 D12 R/W X 11 D11 R/W X 10 D10 R/W X 9 D09 R/W X 8 D08 R/W X 0000CDH D15 R/W X Read/Write Initial value TMR/TMRLR (low) 7 6 D06 R/W X 5 D05 R/W X 4 D04 R/W X 3 D03 R/W X 2 D02 R/W X 1 D01 R/W X 0 D00 R/W X 0000CCH D07 R/W X Read/Write Initial value DS07-13722-11E 59 MB90480B/485B Series (2) Block Diagram Internal data bus TMRLR 16-bit reload register Reload signal TMR 16-bit timer register (down counter) CLK UF Reload control circuit Count clock generator circuit Machine clock φ 3 Gate input Prescaler Clear Valid clock detection circuit CLK Wait signal Output signal generation circuit To A/D converter Pin (TOT0) EN Inverted Pin (TIN0) Input control circuit Clock selector Output signal generation circuit External clock Function selection OUTL 3 RELD Select signal 2 Operation control circuit OUTE Timer control status register (TMCSR) 60 DS07-13722-11E MB90480B/485B Series 11. μPG Timer (MB90485B series only) The μPG timer performs pulse output in response to the external input. (1) Register List μPG control status register (PGCSR) Initial value 00008EH 7 PEN0 R/W 6 PE1 R/W 5 PE0 R/W 4 PMT1 R/W 3 PMT0 R/W 2 1 0 00000---B (2) Block Diagram MT00 MT01 MT00 Output latch MT01 Output latch Output enable Control circuit EXTC DS07-13722-11E 61 MB90480B/485B Series 12. PWC Timer (MB90485B series only) The PWC timer is a 16-bit multifunction up-count timer capable of measuring the pulse width of the input signal. A total of three channels are provided, each consisting of a 16-bit up-count timer, an input pulse divider & divide ratio control register, a measurement input pin, and a 16-bit control register. These components provide the following functions. Timer function : • Capable of generating an interrupt request at fixed intervals specified. • The internal clock used as the reference clock can be selected from among three types. Pulse width measurement function : • Measures the time between arbitrary events based on external pulse inputs. • The internal clock used as the reference clock can be selected from among three types. • Measurement modes - “H” pulse width (↑ to ↓) /“L” pulse width (↑ to ↓) - Rising cycle (↑ to ↑) /Falling cycle (↓ to ↓) - Measurement between edges (↑ or ↓ to ↓ or ↑) • The 8-bit input divider can be used for division measurement by dividing the input pulse by 22 × n (n = 1, 2, 3, 4) . • An interrupt can be generated upon completion of measurement. • One-time measurement or fast measurement can be selected. 62 DS07-13722-11E MB90480B/485B Series (1) Register list PWC control/status registers (PWCSR0 to PWCSR2) 000077H 00007BH 00007FH 15 STRT R/W 14 STOP R/W 13 EDIR R 12 EDIE R/W 11 OVIR R/W 10 OVIE R/W 9 8 Initial value 0000000XB ERR Reserved R PWC control/status registers (PWCSR0 to PWCSR2) 000076H 00007AH 00007EH 7 CKS1 R/W 6 CKS0 R/W 5 PIS1 R/W 4 PIS0 R/W 3 S/C R/W 2 1 0 Initial value 00000000B MOD2 MOD1 MOD0 R/W R/W R/W PWC data buffer registers (PWCR0 to PWCR2) 000079H 00007DH 000081H 15 D15 R/W 14 D14 R/W 13 D13 R/W 12 D12 R/W 11 D11 R/W 10 D10 R/W 9 D9 R/W 8 D8 R/W Initial value 00000000B PWC data buffer registers (PWCR0 to PWCR2) 000078H 00007CH 000080H 7 D7 R/W 6 D6 R/W 5 D5 R/W 4 D4 R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W Initial value 00000000B Dividing ratio control registers (DIVR0 to DIVR2) 000082H 000084H 000086H 7 6 5 4 3 2 1 DIV1 R/W 0 DIV0 R/W Initial value ------00B DS07-13722-11E 63 MB90480B/485B Series (2) Block Diagram PWCR read Error detection ERR Internal clock (machine clock/4) PWCR 16 Reload Data transfer 16 Overflow Clock 16-bit up count timer 22 Clock divider 2 Timer clear F2MC-16 Bus CKS1/CKS0 3 Control circuit Count enable Divider clear Control bit output Flag set etc. Start of measurement edge Start edge selection Completion edge selection Dividing ON/OFF Input wave form comparator PWC0 PWC1 Edge detection Completion of measurement edge Completion of measurement interrupt request Overflow interrupt request PIS0/PIS1 CKS0/ CKS1 8-bit divider ERR PWCSR 15 2 Dividing ratio selection DIVR 64 DS07-13722-11E MB90480B/485B Series 13. Watch Timer The watch timer is a 15-bit timer using the sub clock. This circuit can generate interrupts at predetermined intervals. Also a setting is available to enable it to be used as the clock source for the watchdog timer. (1) Register List Watch timer control register (WTC) 7 6 SCE R 0 5 WTIE R/W 0 4 WTOF R/W 0 3 WTR R/W 1 2 WTC2 R/W 0 1 WTC1 R/W 0 0 WTC0 R/W 0 0000AAH WDCS R/W 1 Read/write Initial value (2) Block Diagram Watch timer control register (WTC) WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clear 28 Sub clock Watch counter 29 210 211 212 213 210 213 214 215 214 Interval selector Interrupt generator circuit Watch timer interrupt To watchdog timer DS07-13722-11E 65 MB90480B/485B Series 14. Watchdog timer The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as a count clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated. (1) Register List Watchdog timer control register (WDTC) 7 6 Reserved 5 WRST R X 4 ERST R X 3 SRST R X 2 WTE W 1 1 WT1 W 1 0 WT0 W 1 0000A8H PONR R X ⎯ X Read/write Initial value (2) Block Diagram Watchdog timer control register (WDTC) PONR served WRST ERST SRST WTE Re- WT1 WT0 Watch mode start Timebase timer mode start Sleep mode start Hold status start 2 Watch timer control register (WTC) WDCS bit Clock select register (CKSCR) SCM bit CLR Watchdog timer Counter clear control circuit Count clock selector CLR CLR and start 2-bit counter Stop mode start Watchdog reset generator circuit 4 Internal reset generator circuit Clear Time-base counter HCLK × 2 × 21 × 22 4 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 SCLK × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 HCLK : Oscillator clock SCLK : Sub clock 66 DS07-13722-11E MB90480B/485B Series 15. Timebase Timer The timebase timer is an 18-bit free run counter (timebase counter) that counts up in synchronization with the internal count clock signal (base oscillator × 2) , and functions as an interval timer with a choice of four types of time intervals. Other functions provided by this module include timer output for the oscillator stabilization wait period, and operating clock signal feed for other timer circuits such as the watchdog timer. (1) Register List Timebase timer control register (TBTC) 0000A9H 15 RESV R/W 1 14 ⎯ ⎯ X 13 ⎯ ⎯ X 12 TBIE R/W 0 11 TBOF R/W 0 10 TBR W 1 9 TBC1 R/W 0 8 TBC0 R/W 0 Read/write Initial value (2) Block Diagram To watchdog timer To PPG timer Timebase timer counter HCLK × 2 × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF OF OF Power-on reset Stop mode start Hold status start CKSCR : MCS = 1→ 0*1 CKSCR : SCS = 0→ 1*2 Counter clear control circuit To clock control module oscillator stabilization wait time selector Interval timer selector TBOF clear TBOF set Timebase timer control register (TBTC) Timebase timer interrupt signal OF HCLK *1 *2 RESV ⎯ ⎯ TBIE TBOF TBR TBC1 TBC0 : Overflow : Oscillator clock : Switch machine clock from main clock or sub clock to PLL clock. : Switch machine clock from sub clock to main clock. DS07-13722-11E 67 MB90480B/485B Series 16. Clock The clock generator module controls the operation of the internal clock circuits that serve as the operating clock for the CPU and peripheral devices. This internal clock is referred to as the machine clock, and one cycle is referred to as a machine cycle. Also, the clock signals from the base oscillator are called the oscillator clock, and those from the PLL oscillator are called the PLL clock. (1) Register List Clock select register (CKSCR) 15 14 MCM R 1 13 WS1 R/W 1 12 WS0 R/W 1 11 SCS R/W 1 10 MCS R/W 1 9 CS1 R/W 0 8 CS0 R/W 0 0000A1H SCM R 1 Read/write Initial value PLL output select register (PLLOS) 15 14 ⎯ ⎯ ⎯ 13 ⎯ ⎯ ⎯ 12 ⎯ ⎯ ⎯ 11 ⎯ ⎯ ⎯ 10 ⎯ ⎯ ⎯ 9 ⎯ W X 8 PLL2 W 0 0000CFH ⎯ ⎯ ⎯ Read/write Initial value 68 DS07-13722-11E MB90480B/485B Series (2) Block Diagram Standby control circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Pin high-impedance control circuit Pin high-impedance control RST pin CPU intermittent operation selector Internal reset generator circuit Internal reset Intermittent cycle selection CPU clock control circuit CPU clock Interrupt release Standby control circuit Stop, sleep signals Stop signal Peripheral clock control circuit Machine clock Clock generator module Clock selector SCLK Peripheral clock Oscillator stabilization wait release PLL output select register (PLLOS) ⎯ ⎯ ⎯ ⎯ ⎯ 2 ⎯ ⎯ PLL2 Oscillator stabilization wait period selector ×4 2 PLL multiplier circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Sub clock generator circuit X0A X1A Clock select register (CKSCR) System clock generator circuit pin pin X0 ×2 × 1024 Timebase timer ×2 ×4 ×4 ×4 ×2 HCLK MCLK pin X1 pin To watchdog timer HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock DS07-13722-11E 69 MB90480B/485B Series (3) Clock Feed Map 4 Peripheral functions Watchdog timer 4 Clock generator module Watch timer X0A 8/16-bit PPG timer 0 8/16-bit PPG timer 1 8/16-bit PPG timer 2 16-bit reload timer 0 PPG0, PPG1 pins PPG2, PPG3 pin X1A pin Sub clock generator circuit ×4 Timebase timer 1 2 3 4 pins PPG4, PPG5 pins TIN0 PLL multiplier circuit X0 SCLK PCLK φ pin TOT0 pin X1 pin System clock ×2 generator HCLK MCLK circuit Clock selector pin SCK0, SIN0 pins UART0 CPU, μDMAC SOT0 pin SCK1, SCK2 SIN1, SIN2 Extended I/O serial interface, 2 channels pins SOT1, SOT2 pins AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 8/16-bit up/down counter pins CS0, CS1, CS2, CS3 Chip select 16-bit output compare 16-bit free-run timer 16-bit input capture 10-bit A/D converter HCLK MCLK SCLK PCLK φ : Oscillator clock : Main clock : Sub clock : PLL clock : Machine clock External interrupt pins OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 pins FRCK pin IN0, IN1 pins AN0 to AN7, ADTG pins IRQ0 to IRQ7 pin 3 Oscillator stabilization wait control 70 DS07-13722-11E MB90480B/485B Series 17. Low-power Consumption Mode The MB90480B/485B series uses operating clock selection and clock operation controls to provide the following CPU operating modes : • Clock modes (PLL clock mode, main clock mode, sub clock mode) • CPU intermittent operating modes (PLL clock intermittent mode, main clock intermittent mode, sub clock intermittent mode) • Standby modes (Sleep mode, timebase timer mode, stop mode, watch mode) (1) Register List Low-power consumption mode control register (LPMCR) 7 6 SLP W 0 5 SPL R/W 0 4 RST W 1 3 TMD R/W 1 2 CG1 R/W 0 1 CG0 R/W 0 0 Reserved 0000A0H STP W 0 R/W 0 Read/write Initial value DS07-13722-11E 71 MB90480B/485B Series (2) Block Diagram Standby control circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 served Re- Pin high-impedance control circuit Internal reset generator circuit Pin high-impedance control Internal reset RST pin CPU intermittent operating selector Intermittent cycle selection CPU clock control circuit CPU clock Interrupt release Standby control circuit Stop, sleep signals Stop signal Peripheral clock control circuit Machine clock Clock generator module Clock selector SCLK Peripheral clock Oscillator stabilization wait release PLL output select register (PLLOS) ⎯ ⎯ ⎯ ⎯ ⎯ 2 ⎯ ⎯ PLL2 Oscillator stabilization wait period selector ×4 2 PLL multiplier circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Sub clock generator circuit X0A X1A Clock select register (CKSCR) System clock generator circuit pin pin X0 X1 ×2 HCLK × 1024 Timebase timer ×2 ×4 ×4 ×4 ×2 MCLK pin pin To watchdog timer HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock 72 DS07-13722-11E MB90480B/485B Series (3) Status Transition Chart External reset, watchdog timer reset, software reset Power-on Reset Power-on reset SCS = 0 SCS = 1 MCS = 0 MCS = 1 SCS = 0 SCS = 1 Oscillator stabilization wait ends Main clock mode SLP = 1 PLL clock mode SLP = 1 Sub clock mode SLP = 1 Interrupt Interrupt Interrupt Main sleep mode TMD = 0 PLL sleep mode TMD = 0 Sub sleep mode TMD = 0 Interrupt Interrupt Interrupt Main timebase timer mode STP = 1 PLL timebase timer mode STP = 1 Watch mode STP = 1 Main stop mode Interrupt Oscillator stabilization wait ends PLL stop mode Interrupt Oscillator stabilization wait ends Sub stop mode Interrupt Oscillator stabilization wait ends Main clock oscillator stabilization wait PLL clock oscillator stabilization wait Sub clock oscillator stabilization wait DS07-13722-11E 73 MB90480B/485B Series 18. External Bus Pin Control Circuit The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus connections to external circuits. (1) Register List • Auto ready function select register (ARSR) Address : 0000A5H 15 IOR1 W 14 IOR0 W 13 HMR1 W 12 HMR0 W 11 ⎯ ⎯ 10 ⎯ ⎯ 9 LMR1 W 8 LMR0 W Initial value 0011--00B • External address output control register (HACR) Address : 0000A6H 7 E23 W 6 E22 W 5 E21 W 4 E20 W 3 E19 W 2 E18 W 1 E17 W 0 E16 W Initial value ********B • Bus control signal select register (EPCR) Address : 0000A7H 15 CKE W 14 RYE W 13 HDE W 12 IOBS W 11 HMBS W 10 WRE W 9 LMBS W 8 ⎯ ⎯ Initial value 1000*10-B W − * : Write only : Not used : May be either “1” or “0” (2) Block Diagram P5 P2 P3 P4 P5 P0 P1 P0 data P0 direction P0 RB Data control Address control Access control Access control 74 DS07-13722-11E MB90480B/485B Series 19. Chip Select Function Description The chip select module generates a chip select signals, which are used to facilitate connections to external memory devices. The MB90480B/485B series has four chip select output pins, each having a chip select area register setting that specifies the corresponding hardware area and select signal that is output when access to the corresponding external address is detected. • Chip select function features The chip select function uses two 8-bit registers for each output pin. One of these registers (CARx) is able to detect memory areas in 64 Kbytes units by specifying the upper 8-bit of the address for match detection. The other register (CMRx) can be used to expand the detection area beyond 64 Kbytes by masking bits for match detection. Note that during external bus holds, the CS output is set to high impedance. (1) Register List 15 CAR0 CAR1 CAR2 CAR3 CALR 87 CMR0 CMR1 CMR2 CMR3 CSCR 0 R/W R/W R/W R/W R/W Chip select area mask registers (CMRx) 0000C0H 0000C2H 0000C4H 0000C6H 7 M7 R/W 0 6 M6 R/W 0 5 M5 R/W 0 4 M4 R/W 0 3 M3 R/W 1 2 M2 R/W 1 1 M1 R/W 1 0 M0 R/W 1 Read/write Initial value Chip select area registers (CARx) 0000C1H 0000C3H 0000C5H 0000C7H 15 A7 R/W 1 14 A6 R/W 1 13 A5 R/W 1 12 A4 R/W 1 11 A3 R/W 1 10 A2 R/W 1 9 A1 R/W 1 8 A0 R/W 1 Read/write Initial value Chip select control register (CSCR) 7 6 ⎯ ⎯ ⎯ 5 ⎯ ⎯ ⎯ 4 ⎯ ⎯ ⎯ 3 OPL3 R/W 0 2 OPL2 R/W 0 1 OPL1 R/W 0 0 OPL0 R/W * 0000C8H ⎯ ⎯ ⎯ Read/write Initial value Chip select active level register (CALR) 15 14 ⎯ ⎯ ⎯ 13 ⎯ ⎯ ⎯ 12 ⎯ ⎯ ⎯ 11 ACTL3 R/W 0 10 ACTL2 R/W 0 9 ACTL1 R/W 0 8 ACTL0 R/W 0 0000C9H ⎯ ⎯ ⎯ Read/write Initial value * : The initial value of this bit is “1” or “0”. The value depends on the mode pin (MD2, MD1 and MD0) . DS07-13722-11E 75 MB90480B/485B Series (2) Block Diagram F2MC-16LX Bus CMRx CARx Chip select output pins A23 to A16 76 DS07-13722-11E MB90480B/485B Series 20. ROM Mirror Function Select Module The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read by access to 00 bank. (1) Register List • ROM mirror function select register (ROMM) Address : 00006FH 15 ⎯ 14 ⎯ 13 ⎯ 12 ⎯ 11 ⎯ 10 ⎯ 9 8 MS MI R/W R/W (+ ) Initial value ------+1B ( + ) : MB90F489B : Read only, fixed at “1” Other : Selectable, Initial value 0 - : Not used (2) Block Diagram F2MC-16LX bus ROM mirror function select Address area FF bank 00 bank ROM Note : Do not access ROM mirror function selection register (ROMM) on using the area of address 004000H to 00FFFFH (008000H to 00FFFFH) . DS07-13722-11E 77 MB90480B/485B Series 21. Interrupt Controller The interrupt control register is built in interrupt controller, and is supported for all I/O of interrupt function. This register sets corresponding peripheral interrupt level. (1) Register List Interrupt control registers Address : ICR01 ICR03 ICR05 ICR07 ICR09 ICR11 ICR13 ICR15 0000B1H 0000B3H 0000B5H 0000B7H 0000B9H 0000BBH 0000BDH 0000BFH Read/write→ Initial value→ 15 ⎯ ⎯ 14 ⎯ 13 12 ⎯ 11 10 IL2 IL1 9 IL0 8 Reserved W X W X W X W X R/W 0 R/W 1 R/W 1 R/W 1 Interrupt control registers Address : ICR00 ICR02 ICR04 ICR06 ICR08 ICR10 ICR12 ICR14 0000B0H 0000B2H 0000B4H 0000B6H 0000B8H 0000BAH 0000BCH 0000BEH Read/write→ Initial value→ 7 ⎯ ⎯ 6 ⎯ 5 ⎯ 4 3 IL2 2 IL1 1 IL0 0 Reserved W X W X W X W X R/W 0 R/W 1 R/W 1 R/W 1 Note : The use of access involving read-modify-write instructions may lead to abnormal operation, and should be avoided. 78 DS07-13722-11E MB90480B/485B Series (2) Block Diagram 3 IL2 IL1 IL0 3 32 Interrupt requests (Peripheral resources) F2MC-16LX Bus Interrupt priority setting 3 (CPU) Interrupt level DS07-13722-11E 79 MB90480B/485B Series 22. μDMAC The μDMAC is a simplified DMA module with functions equivalent to EI2OS. The μDMAC has 16 DMA data transfer channels, and provides the following functions. • Automatic data transfer between peripheral resources (I/O) and memory. • CPU program execution stops during DMA operation. • Incremental addressing for transfer source and destination can be turned on/off. • DMA transfer control from the μDMAC enable register, μDMAC stop status register, μDMAC status register, and descriptor. • Stop requests from resources can stop DMA transfer. • When DMA transfer is completed, the μDMAC status register sets a flag in the bit for the corresponding channel on which transfer was completed, and outputs a completion interrupt to the interrupt controller. (1) Register List μDMAC enable register DERH : 0000ADH 15 EN15 R/W 14 EN14 R/W 13 EN13 R/W 12 EN12 R/W 11 EN11 R/W 10 EN10 R/W 9 EN9 R/W 8 EN8 R/W Initial value 00000000B μDMAC enable register DERL : 0000ACH 7 EN7 R/W 6 EN6 R/W 5 EN5 R/W 4 EN4 R/W 3 EN3 R/W 2 EN2 R/W 1 EN1 R/W 0 EN0 R/W Initial value 00000000B μDMAC stop status register DSSR : 0000A4H 7 STP7 R/W 6 STP6 R/W 5 STP5 R/W 4 STP4 R/W 3 STP3 R/W 2 STP2 R/W 1 STP1 R/W 0 STP0 R/W Initial value 00000000B μDMAC status register DSRH : 00009DH 15 DE15 R/W 14 DE14 R/W 13 DE13 R/W 12 DE12 R/W 11 DE11 R/W 10 DE10 R/W 9 DE9 R/W 8 DE8 R/W Initial value 00000000B μDMAC status register DSRL : 00009CH 7 DE7 R/W 6 DE6 R/W 5 DE5 R/W 4 DE4 R/W 3 DE3 R/W 2 DE2 R/W 1 DE1 R/W 0 DE0 R/W Initial value 00000000B 80 DS07-13722-11E MB90480B/485B Series (2) Block Diagram Memory space IOA I/O register I/O register If transfer not ended Peripheral function (I/O) DMA transfer request μDMAC descriptor Read by DER μDMA controller If transfer is ended BAP Transfer Buffer DCT CPU Interrupt controller IOA BAP DER DCT : I/O address pointer : Buffer address pointer : μDMAC enable register (ENx selection) : Data counter DS07-13722-11E F2MC-16LX Bus 81 MB90480B/485B Series 23. Address Match Detection Function When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. (1) Register List • Program address detection register 0 (PADR0) Address PADR0 (Low order address) : 001FF0H R/W Address PADR0 (Middle order address) : 001FF1H R/W Address PADR0 (High order address) : 001FF2H R/W Address PADR1 (Low order address) : 001FF3H R/W Address PADR1 (Middle order address) : 001FF4H R/W Address PADR1 (High order address) : 001FF5H R/W Address 00009EH 7 RESV R/W R/W : Readable and writable X : Undefined RESV : Reserved bit R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 AD0E R/W R/W 0 RESV R/W Initial value 00000000 B 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 Initial value XXXXXXXX B 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 Initial value XXXXXXXX B 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 Initial value XXXXXXXX B 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 Initial value XXXXXXXX B 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 Initial value XXXXXXXX B 7 6 5 4 3 2 1 0 Initial value XXXXXXXX B • Program address detection register 1 (PADR1) • Program address detection control status register (PACSR) RESV RESV R/W R/W RESV AD1E RESV R/W R/W R/W 82 DS07-13722-11E MB90480B/485B Series (2) Block Diagram Internal data bus Address detection register Enable bit Compare Address latch INT9 instruction F2MC-16LX CPU core DS07-13722-11E 83 MB90480B/485B Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC3 Power supply voltage*1 VCC5 AVCC AVRH Input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum total output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level maximum total output current “H” level total average output current Power consumption Operating temperature Storage temperature VI VO ICLAMP Σ⏐ICLAMP⏐ IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA Tstg Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ − 40 − 55 Max VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 + 2.0 20 10 3 60 30 −10 −3 −60 −30 320 + 85 + 150 Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C *6 *6 *4 *5 *2 *2 *3 *3, *8, *9 *3 *3, *8, *9 *7 *7 *4 *5 Remarks *1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : AVCC and AVRH must not exceed VCC. Also, AVRH must not exceed AVCC. *3 : VI and V0 must not exceed VCC + 0.3 V. However, if the maximum current to/from and input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Maximum output current is defined as the peak value for one of the corresponding pins. *5 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding pins. *6 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins. *7 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3 • Use within recommended operating conditions. • Use at DC voltage (current) . • The + B signal should always be applied with a limiting resistance placed between the + B signal and the microcontroller. • The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. (Continued) 84 DS07-13722-11E MB90480B/485B Series (Continued) • Note that when the microcontroller drive current is low, such as in the power saving modes, the + B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a + B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the + B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept + B signal input. • Sample recommended circuits: • Input/Output Equivalent circuits Protective diode Limiting resistance VCC P-ch + B input (0 V to 16 V) N-ch R *8 : MB90485B series only P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. P76 and P77 is N-ch open drain pin. *9 : As for P76 and P77 (N-ch open drain pin) , even if using at 3 V simplicity (VCC3 = VCC5) , the ratings are applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS07-13722-11E 85 MB90480B/485B Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Symbol VCC3 Power supply voltage VCC5 VIH VIH2 “H” level input voltage VIHS VIHM VIHX VIL “L” level input voltage VILS VILM VILX Operating temperature TA 0.8 VCC VCC − 0.3 0.8 VCC VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 0 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 0.1 + 70 V V V V V V V °C Value Min 2.7 1.8 2.7 1.8 0.7 VCC 0.7 VCC Max 3.6 3.6 5.5 5.5 VCC + 0.3 VSS + 5.8 Unit V V V V V V Remarks During normal operation To maintain RAM state in stop mode During normal operation* To maintain RAM state in stop mode* All pins other than VIH2, VIHS, VIHM and VIHX MB90485B series only P76, P77 pins (N-ch open drain pins) Hysteresis input pins MD pin input X0A pin, X1A pin All pins other than VILS, VILM and VILX Hysteresis input pins MD pin input X0A pin, X1A pin At external bus operation * : MB90485B series only P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 86 DS07-13722-11E MB90480B/485B Series 3. DC Characteristics (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Condition VCC = 2.7 V, IOH = − 1.6 mA VCC = 4.5 V, IOH = − 4.0 mA VCC = 2.7 V, IOL = 2.0 mA VCC = 4.5 V, IOH = 4.0 mA VCC = 3.3 V, VSS < VI < VCC VCC = 3.0 V, at TA = + 25 °C ⎯ At VCC = 3.3 V, internal 25 MHz operation, normal operation At VCC = 3.3 V, internal 25 MHz operation, Flash programming At VCC = 3.3 V, internal 25 MHz operation, sleep mode At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, sub clock operation (TA = + 25 °C) At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, watch mode (TA = + 25 °C) TA = + 25 °C, stop mode, At VCC = 3.3 V ⎯ Min Value Typ ⎯ ⎯ ⎯ ⎯ ⎯ 53 0.1 45 Max ⎯ ⎯ 0.4 0.4 +10 200 10 60 Unit V V V V μA kΩ μA mA At using 5 V power supply At using 5 V power supply Remarks “H” level output voltage VOH All output pins VCC3 − 0.3 VCC5 − 0.5 ⎯ ⎯ −10 20 ⎯ ⎯ ⎯ ⎯ “L” level output voltage Input leakage current Pull-up resistance Open drain output current VOL All output pins All input pins ⎯ P40 to P47, P70 to P77 IIL RPULL Ileak ICC ⎯ 55 70 mA ICCS Power supply current ICCL ⎯ 17 35 mA ⎯ ⎯ 15 140 μA ICCT ⎯ ⎯ Other than AVCC, AVSS, VCC, VSS ⎯ ⎯ ⎯ 1.8 40 μA μA pF ICCH Input capacitance CIN 0.8 5 40 15 Notes :• MB90485B series only • P40 to P47 and P70 to P77 are N-ch open drain pins with control, which are usually used as CMOS. • P76 and P77 are open drain pins without P-ch. • For use as a single 3 V power supply products, set VCC = VCC3 = VCC5. • When the device is used with dual power supplies, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 serve as 5 V pins while the other pins serve as 3 V I/O pins. DS07-13722-11E 87 MB90480B/485B Series 4. AC Characteristics (1) Clock Timing (VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter SymPin name bol Condition ⎯ ⎯ ⎯ Clock frequency FCH X0, X1 ⎯ ⎯ ⎯ ⎯ ⎯ FCL Clock cycle time tC tCL PWH PWL PWLH PWLL tcr tcf fCP fCPL tCP tCPL X0A, X1A X0, X1 X0A, X1A X0 X0A X0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Value Min 3 3 4 3 3 3 3 3 ⎯ 20 ⎯ 5 ⎯ ⎯ 1.5 ⎯ 40.0 ⎯ Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 32.768 ⎯ 30.5 ⎯ 15.2 ⎯ ⎯ 8.192 ⎯ 122.1 Max 25 50 25 12.5 6.66 6.25 4.16 3.12 ⎯ 333 ⎯ ⎯ ⎯ 5 25 ⎯ 666 ⎯ kHz ns μs ns μs ns *2 With external clock *1 Unit Remarks External crystal oscillator External clock input 1 multiplied PLL MHz 2 multiplied PLL 3 multiplied PLL 4 multiplied PLL 6 multiplied PLL 8 multiplied PLL Input clock pulse width Input clock rise, fall time Internal operating clock frequency Internal operating clock cycle time MHz *1 kHz ns μs *1 *1 : Be careful of the operating voltage. *2 : Duty ratio should be 50 % ± 3 %. 88 DS07-13722-11E MB90480B/485B Series • X0, X1 clock timing tC X0 PWH tcf PWL tcr 0.8 VCC 0.2 VCC • X0A, X1A clock timing tCL X0A PWLH tcf PWLL tcr 0.8 VCC 0.2 VCC DS07-13722-11E 89 MB90480B/485B Series • Range of warranted PLL operation Internal operating clock frequency vs. Power supply voltage 3.6 Range of warranted PLL operation 3.0 2.7 Normal operating range Power supply voltage VCC (V) 1.5 4 16 25 Internal clock fCP (MHz) Notes: • For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics” • Only at 1 multiplied PLL, use with more than fCP = 4 MHz. Base oscillator frequency vs. Internal operating clock frequency 25 24 8 × *3 6 × *3 3 × *1 2 × *1,*2 4× *1,*2 1 × *1 No multiplied Internal clock fCP (MHz) 20 18 16 12 9 8 6 4 1.5 3 4 5 6 8 10 12.5 16 20 25 32 40 50 Base oscillator clock FCH (MHz) *1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP ≤ 25 MHz, set the PLLOS register to “DIV2 bit = 1” and “PLL2 bit = 1”. [Example] When using the base oscillator frequency of 24 MHz at 1 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : PLL2 bit = “1” [Example] When using the base oscillator frequency of 6 MHz at 3 multiplied PLL : CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : PLL2 bit = “1” *2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP ≤ 25 MHz, the following setting is also enabled. 2 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : PLL2 bit = “1” 4 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “1” PLLOS register : PLL2 bit = “1” *3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit = 0” and “PLL2 bit = 1”. [Example] When using the base oscillator frequency of 4 MHz at 6 multiplied PLL : CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : PLL2 bit = “1” [Example] When using the base oscillator frequency of 3 MHz at 8 multiplied PLL : CKSCR register : CS1 bit = “1”, CS0 bit = “1” PLLOS register : PLL2 bit = “1” 90 DS07-13722-11E MB90480B/485B Series AC standards are set at the following measurement voltage values. • Input signal wave form Hysteresis input pins 0.8 VCC 0.2 VCC • Output signal wave form Output pins 2.4 V 0.8 V • Pins other than hysteresis input/MD input 0.7 VCC 0.3 VCC DS07-13722-11E 91 MB90480B/485B Series (2) Clock Output Timing (VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Cycle time CLK↑→ CLK↓ Symbol Pin name tCYC tCHCL CLK CLK Conditions ⎯ Value Min tCP* Max ⎯ Unit ns ns ns ns at fCP = 25 MHz at fCP = 16 MHz at fCP = 5 MHz Remarks VCC = 3.0 V to 3.6 V tCP* / 2 − 15 tCP* / 2 + 15 VCC = 2.7 V to 3.3 V tCP* / 2 − 20 tCP* / 2 + 20 VCC = 2.7 V to 3.3 V tCP* / 2 − 64 tCP* / 2 + 64 * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. tCYC tCHCL 2.4 V 2.4 V 0.8 V CLK 92 DS07-13722-11E MB90480B/485B Series (3) Reset Input Standards (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Conditions ⎯ Value Min 16 tCP*1 Reset input time tRSTL RST Oscillator oscillation time*2 + 4 tCP*1 Max ⎯ ⎯ Unit ns ms Remarks Normal operation Stop mode *1 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. *2 : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several milliseconds to tens of milliseconds. For a ceramic oscillator, this is several hundred microseconds to several milliseconds. For an external clock signal the value is 0 ms. • In stop mode tRSTL RST 0.2 Vcc 0.2 Vcc X0 90 % of amplitude Internal operating clock Oscillator oscillation time 4 tCP Oscillator stabilization wait time Instruction execution Internal reset • Condition for measurement of AC standards Pin CL : Load capacitance applied to pins during testing CLK, ALE : CL = 30 pF AD15 to AD00 (address data bus) , RD, WR, A23 to A00/D15 to D00 : CL = 30 pF CL DS07-13722-11E 93 MB90480B/485B Series (4) Power-on Reset Standards (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Power rise time Power down time Symbol tR tOFF Pin name Conditions VCC VCC ⎯ Value Min 0.05 1 Max 30 ⎯ Unit ms ms * In repeated operation Remarks * : Power rise time requires VCC < 0.2 V. Notes: • The above standards are for the application of a power-on reset. • Within the device, the power-on reset should be applied by switching the power supply off and on again. tR VCC 2.7 V 0.2 V 0.2 V tOFF 0.2 V Note : Rapid fluctuations in power supply voltage may trigger a power-on reset in some cases. As shown below, when changing supply voltage during operation, it is recommended that voltage changes be suppressed and a smooth restart be applied. Main power supply voltage VCC Sub power supply voltage RAM data maintenance The slope of voltage increase should be kept within 50 mV/ms. VSS 94 DS07-13722-11E MB90480B/485B Series (5) Bus Read Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Parameter Symbol Pin name Conditions Value Min tCP* / 2 − 15 ALE pulse width tLHLL ALE ⎯ tCP* / 2 − 20 tCP* / 2 − 35 Valid address→ ALE↓ time ALE↓ → address valid time Valid address → RD↓ time Valid address → valid data input tAVLL tLLAX tAVRL tAVDV Address, ALE ALE, Address RD, Address Address, Data ⎯ ⎯ ⎯ ⎯ tCP* / 2 − 17 tCP* / 2 − 40 tCP* / 2 − 15 tCP* − 25 ⎯ ⎯ 3 tCP* / 2 − 25 Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 5 tCP* / 2 − 55 5 tCP* / 2 − 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 16 MHz < fCP ≤ 25 MHz 8 MHz < fCP ≤ 16 MHz fCP ≤ 8 MHz fCP ≤ 8 MHz fCP ≤ 8 MHz 16 MHz < fCP ≤ 25 MHz 8 MHz < fCP ≤ 16 MHz ⎯ ⎯ 3 tCP* / 2 − 55 3 tCP* / 2 − 80 RD pulse width tRLRH RD ⎯ 3 tCP* / 2 − 20 RD↓ → valid data input RD↑ → data hold time RD↑ → ALE↑time RD↑ → address valid time Valid address → CLK↑ time RD↓ → CLK↑time ALE↓ → RD↓ time tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL RD, Data RD, Data RD, ALE Address, RD Address, CLK RD, CLK RD, ALE ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 tCP* / 2 − 15 tCP* / 2 − 10 tCP* / 2 − 17 tCP* / 2 − 17 tCP* / 2 − 15 fCP ≤ 8 MHz ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. DS07-13722-11E 95 MB90480B/485B Series tAVCH 2.4 V tRLCH 2.4 V CLK tRHLH ALE 2.4 V tLHLL 2.4 V 0.8 V tRLRH 2.4 V RD 2.4 V tAVLL tLLAX tLLRL 0.8 V In multiplexed mode A23 to A16 2.4 V 0.8 V tAVRL tRLDV tRHAX 2.4 V 0.8 V tAVDV 2.4 V 2.4 V 0.7 VCC tRHDX 0.7 VCC AD15 to AD00 0.8 V Address 0.8 V 0.3 VCC Read data 0.3 VCC tRHAX In non-multiplexed mode A23 to A00 2.4 V 0.8 V tRLDV tAVDV 0.7 VCC 2.4 V 0.8 V tRHDX 0.7 VCC D15 to D00 0.3 VCC Read data 0.3 VCC 96 DS07-13722-11E MB90480B/485B Series (6) Bus Write Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Parameter Valid address → WR↓ time WR pulse width Symbol tAVWL tWLWH Pin name Address, WR WRL, WRH ⎯ Valid data output → WR↑ time tDVWH Data, WR ⎯ ⎯ WR↑ → data hold time tWHDX WR, Data ⎯ ⎯ WR↑ → address valid time WR↑ → ALE↑ time WR↓ → CLK↑ time tWHAX tWHLH tWLCH WR, Address WR, ALE WR, CLK ⎯ ⎯ ⎯ 3 tCP* / 2 − 20 3 tCP* / 2 − 15 Condition ⎯ ⎯ Value Min tCP* − 15 3 tCP* / 2 − 25 Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns Remarks 16 MHz < fCP ≤ 25 MHz 8 MHz < fCP ≤ 16 MHz 16 MHz < fCP ≤ 25 MHz 8 MHz < fCP ≤ 16 MHz fCP ≤ 8 MHz 10 20 30 tCP* / 2 − 10 tCP* / 2 − 15 tCP* / 2 − 17 * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. DS07-13722-11E 97 MB90480B/485B Series tWLCH 2.4 V CLK tWHLH ALE tWLWH 2.4 V 2.4 V WR (WRL, WRH) 0.8 V In multiplexed mode A23 to A16 2.4 V 0.8 V tAVWL tWHAX 2.4 V 0.8 V tDVWH tWHDX 2.4 V 2.4 V AD15 to AD00 0.8 V Address 2.4 V 0.8 V Write data 0.8 V tWHAX In non-multiplexed mode A23 to A00 2.4 V 0.8 V tDVWH 2.4 V 0.8 V 2.4 V 0.8 V tWHDX 2.4 V 0.8 V D15 to D00 Write data 98 DS07-13722-11E MB90480B/485B Series (7) Ready Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Parameter RDY setup time RDY hold time Symbol tRYHS tRYHH Pin name Conditions ⎯ RDY ⎯ ⎯ Value Min 35 70 0 Max ⎯ ⎯ ⎯ Unit ns ns ns at fCP = 8 MHz Remarks 2.4 V 2.4 V CLK ALE RD/WR tRYHS tRYHH RDY wait not inserted RDY wait inserted (1 cycle) 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tRYHS DS07-13722-11E 99 MB90480B/485B Series (8) Hold Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Pin floating→ HAK ↓ time HAK↓ → pin valid time Symbol tXHAL tHAHV Pin name HAK HAK Conditions ⎯ Value Min 30 tCP* Max tCP* 2 tCP* Unit ns ns * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. Note : One or more cycles are required from the time the HRQ pin is read until the HAK signal changes. HAK 0.8 V tXHAL 2.4 V 0.8 V 2.4 V tHAHV Pins Hi-Z 2.4 V 0.8 V (9) UART Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK↓ → SOT delay time Valid SIN→ SCK↑ SCK↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK↓ → SOT delay time Valid SIN → SCK↑ SCK↑ → valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL Conditions Value Min 8 tCP*2 − 80 − 120 100 200 tCP*2 4t * 4t * ⎯ ⎯ 60 120 60 120 CP 2 CP 2 Max ⎯ + 80 + 120 ⎯ ⎯ ⎯ ⎯ ⎯ 150 200 ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz *1 : CL is the load capacitance applied to pins for testing. *2 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. Note : The above rating is in CLK synchronous mode. 100 DS07-13722-11E MB90480B/485B Series • Internal shift clock mode tSCYC SCK 0.8 V tSLOV 2.4 V 2.4 V 0.8 V SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC SCK SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC DS07-13722-11E 101 MB90480B/485B Series (10) Extended I/O Serial Interface Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK↓ → SOT delay time Valid SIN → SCK↑ SCK↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK↓ → SOT delay time Valid SIN → SCK↑ SCK↑ → valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL Conditions Value Min 8 tCP*2 −80 −120 100 200 tCP*2 4t * 4t * ⎯ ⎯ 60 120 60 120 CP 2 CP 2 Max ⎯ + 80 + 120 ⎯ ⎯ ⎯ ⎯ ⎯ 150 200 ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz *1 : CL is the load capacitance applied to pins for testing. *2 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. Notes : • The above rating is in CLK synchronous mode. • Values on this table are target values. 102 DS07-13722-11E MB90480B/485B Series • Internal shift clock mode tSCYC SCK 0.8 V tSLOV 2.4 V 2.4 V 0.8 V SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC SCK SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC DS07-13722-11E 103 MB90480B/485B Series (11) Timer Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol tTIWH tTIWL Pin name TIN0, IN0, IN1, PWC0 to PWC2 Conditions Value Min 4 tCP* Max ⎯ Unit Input pulse width ⎯ ns * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. TIN0 IN0, IN1 PWC0 to PWC2 0.8 VCC 0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC (12) Timer Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter CLK↑ → TOUT change time PPG0 to PPG5 change time OUT0 to OUT5 change time Symbol Pin name TOT0, PPG0 to PPG5, OUT0 to OUT5 Conditions Load conditions 80 pF Value Min 30 Max ⎯ Unit tTO ns CLK 0.7 VCC TOT0 PPG0 to PPG5 OUT0 to OUT5 0.7 VCC 0.3 VCC tTO 104 DS07-13722-11E MB90480B/485B Series (13) I2C Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter SCL clock frequency Hold time (repeated) START condition SDA↓ → SCL↓ “L” width of the SCL clock “H” width of the SCL clock Set-up time (repeated) START condition SCL↑ → SDA↓ Data hold time SCL↓ → SDA↓↑ Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT When power supply voltage of external pull-up resistance is 5.5 V fCP*1 ≤ 20 MHz, R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fCP*1 ≤ 20 MHz, R = 1.6 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V fCP*1 > 20 MHz, R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fCP*1 > 20 MHz, R = 1.6 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 kΩ, C = 50 pF*2 Condition Standard-mode Min 0 4.0 4.7 4.0 4.7 0 Max 100 ⎯ ⎯ ⎯ ⎯ 3.45*3 Unit kHz μs μs μs μs μs 250*4 ⎯ ns Data set-up time SDA↓↑ → SCL↑ tSUDAT 200*4 ⎯ ns Set-up time for STOP condition SCL↑ → SDA↑ Bus free time between a STOP and START condition tSUSTO 4.0 ⎯ μs tBUS 4.7 ⎯ μs *1 : fCP is internal operation clock frequency. Refer to “ (1) Clock Timing”. *2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. *4 : Refer to “• Note of SDA and SCL set-up time”. Note : VCC = VCC3 = VCC5 DS07-13722-11E 105 MB90480B/485B Series • Note of SDA and SCL set-up time SDA Input data set-up time SCL 6 tcp Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied. • Timing definition SDA tBUS tLOW SCL tHDSTA tHIGH tHDDAT fSCL tSUSTA tSUSTO tSUDAT tHDSTA 106 DS07-13722-11E MB90480B/485B Series (14) Trigger Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Input pulse width Symbol tTRGH tTRGL Pin name ADTG, IRQ0 to IRQ7 Conditions ⎯ Value Min 5 tCP* 1 Max ⎯ ⎯ Unit ns μs Remarks Normal operation Stop mode * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. IRQ0 to IRQ7 ADTG 0.8 VCC 0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC (15) Up-down Counter Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter AIN input “H” pulse width AIN input “L” pulse width BIN input “H” pulse width BIN input “L” pulse width AIN↑→ BIN↑ time BIN↑→ AIN↓ time AIN↓→ BIN↑ time BIN↓→ AIN↑ time BIN↑→ AIN↑ time AIN↑→ BIN↓ time BIN↓→ AIN↑ time AIN↓→ BIN↑ time ZIN input “H” pulse width ZIN input “L” pulse width Symbol tAHL tALL tBHL tBLL tAUBU tBUAD tADBD tBDAU tBUAU tAUBD tBDAD tADBU tZHL tZLL ZIN0, ZIN1 AIN0, AIN1, BIN0, BIN1 Load conditions 80 pF Pin name Conditions Value Min 8 tCP* 8 tCP* 8 tCP* 8 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. DS07-13722-11E 107 MB90480B/485B Series tAHL 0.8 VCC 0.8 VCC 0.2 VCC tALL AIN 0.2 VCC tAUBU tBUAD tADBD tBDAU 0.8 VCC 0.8 VCC 0.2 VCC tBHL tBLL 0.2 VCC BIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC BIN tBUAU tAUBD tBDAD tADBU 0.8 VCC AIN 0.2 VCC 0.8 VCC 0.8 VCC ZIN tZHL tZLL 0.2 VCC 0.2 VCC 108 DS07-13722-11E MB90480B/485B Series (16) Chip Select Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Chip select output valid time → RD↓ Chip select output valid time→ WR↓ RD↑→ chip select output valid time WR↑→ chip select output valid time Symbol tSVRL tSVWL tRHSV tWHSV Pin name CS0 to CS3, RD CS0 to CS3, WRH, WRL RD, CS0 to CS3 WRH, WRL, CS0 to CS3 Conditions ⎯ ⎯ ⎯ ⎯ Value Min tCP* / 2 − 7 tCP* / 2 − 7 tCP* / 2 − 17 tCP* / 2 − 17 Max ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. tSVRL 2.4 V RD 0.8 V tRHSV 2.4 V 0.8 V A23 to A16 CS0 to CS3 D15 to D00 2.4 V Read data 0.8 V tSVWL tWHSV 2.4 V 0.8 V WRH, WRL D15 to D00 Undefined Write data Note : Due to the configuration of the internal bus, the chip select output signals are changed simultaneously and therefore may cause the bus conflict conditions. AC cannot be warranted between the ALE output signal and the chip select output signal. DS07-13722-11E 109 MB90480B/485B Series 5. A/D Converter Electrical Characteristics (VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH, TA = −40 °C to +85 °C) Parameter Resolution Total error Linear error Differential linearity error Zero transition voltage Full scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels Symbol Pin name ⎯ ⎯ ⎯ ⎯ VOT VFST ⎯ IAIN VAIN ⎯ IA IAH IR IRH ⎯ ⎯ ⎯ ⎯ ⎯ AN0 to AN7 AN0 to AN7 ⎯ AN0 to AN7 AN0 to AN7 AVRH AVCC AVCC AVRH AVRH AN0 to AN7 Value Min ⎯ ⎯ ⎯ ⎯ AVSS − 1.5 LSB Typ ⎯ ⎯ ⎯ ⎯ AVSS + 0.5 LSB Max 10 ± 3.0 ± 2.5 ± 1.9 AVSS + 2.5 LSB Unit bit LSB LSB LSB V V μs μA V V mA μA μA μA LSB AVRH − 3.5 LSB AVRH − 1.5 LSB AVRH + 0.5 LSB 3.68 *1 ⎯ AVSS AVSS + 2.2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.1 ⎯ ⎯ 1.4 ⎯ 94 ⎯ ⎯ ⎯ 10 AVRH AVCC 3.5 5 *2 150 5* 4 2 *1 : At machine clock frequency of 25 MHz. *2 : CPU stop mode current when A/D converter is not operating (at VCC = AVCC = AVRH = 3.0 V) . 110 DS07-13722-11E MB90480B/485B Series • About the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input equivalent circuit R Analog input During sampling : ON C Comparator Note: The values are reference values. R C MB90487B 2.5 kΩ (Max) 31.0 pF (Max) MB90F481B/F482B 1.9 kΩ (Max) 25.0 pF (Max) MB90F488B/F489B 1.9 kΩ (Max) 25.0 pF (Max) • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) MB90F481B/F482B MB90F488B/F489B 20 (External impedance = 0 kΩ to 20 kΩ) MB90F481B/F482B MB90F488B/F489B 100 90 External impedance [kΩ] 80 70 60 50 40 30 20 10 0 0 5 10 15 MB90487B/ MB90483C External impedance [kΩ] 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 MB90487B/ MB90483C 20 25 30 35 Minimum sampling time [μs] Minimum sampling time [μs] • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin. • About errors As |AVRH − AVSS| becomes smaller, values of relative errors grow larger. Note : Concerning sampling time, and compare time when 3.6 V ≥ AVCC ≥ 2.7 V, then Sampling time : 1.92 μs, compare time : 1.1 μs Settings should ensure that actual values do not go below these values due to operating frequency changes. DS07-13722-11E 111 MB90480B/485B Series • A/D Converter Glossary Resolution : Analog changes that are identifiable with the A/D converter. Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics. Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FFH 3FEH 3FDH Digital output Actual conversion value 0.5 LSB {1 LSB × (N − 1) + 0.5 LSB} 004H 003H 002H 001H 0.5 LSB AVRL Analog input AVRH VNT (Measured value) Actual conversion value Theoretical characteristics Total error for digital output N = 1 LSB (Theoretical value) = VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVR − AVss 1024 [V] [LSB] N : A/D converter digital output value VOT (Theoretical value) = AVss + 0.5 LSB [V] VFST (Theoretical value) = AVR − 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N-1) H, NH (Continued) 112 DS07-13722-11E MB90480B/485B Series (Continued) Linearity error 3FFH 3FEH 3FDH Digital output Actual conversion value {1 LSB × (N − 1) + VOT } Digital output VFST (Measured value) N + 1H Differential linearity error Theoretical characteristics Actual conversion value NH V (N + 1) T (Measured value) VNT (Measured value) N − 2H Actual conversion value 004H 003H 002H 001H AVRL VNT (Measured value) Actual conversion value Theoretical characteristics VOT (Measured value) AVRH Analog input N − 1H AVRL Analog input AVRH Linearity error of = digital output N VNT − {1 LSB × (N − 1) + VOT} 1 LSB − 1 [LSB] [V] [LSB] V (N + 1) T − VNT Differential linearity error = of digital output N 1 LSB 1 LSB = VFST − VOT 1022 N : A/D converter digital output value VOT : Voltage at transition of digital output from “000H” to “001H” VFST : Voltage at transition of digital output from “3FEH” to “3FFH” DS07-13722-11E 113 MB90480B/485B Series •Flash Memory Program/Erase Characteristics Parameter Sector erase time Chip erase time Word (16-bit) programming time Program/Erase cycle Flash Memory Data hold time ⎯ Average TA = + 85 °C TA = + 25 °C, VCC = 3.0 V Conditions Value Min ⎯ ⎯ ⎯ 10000 10 Typ 1 7 16 ⎯ ⎯ Max 15 ⎯ 3600 ⎯ ⎯ Unit s s μs cycle year * Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Excludes system-level overhead * : The value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) . • Use of the X0/X1, X0A/X1A pins When used with a crystal oscillator Pull-up resistance 1 Damping resistance 1 X1 X0 X0A X1A Internal damping resistance 0 Damping resistance 2 C1 C3 C4 C2 In normal use : Internal damping resistance 0 : Typ 600 Ω Consult with the oscillator manufacturer. Pull-up resistance 1, Damping resistance 1, 2, C1 to C4 • Sample use with external clock input X0 MB90480B/485B series OPEN X1 114 DS07-13722-11E MB90480B/485B Series ■ EXAMPLE CHARACTERISTICS • MB90F482B VOH − IOH TA = + 25 °C 1800 VOL − IOL TA = + 25 °C VCC = 2.4 V 4.0 3.5 3.0 2.5 VCC = 3.9 V VCC = 3.6 V VCC = 3.3 V 1600 1400 1200 VOL (mV) VOH (V) VCC = 3.0 V VCC = 2.7 V 1000 800 600 2.0 1.5 1.0 0.5 0.0 −1 −2 −3 −4 −5 VCC = 2.4 V 400 200 0 1 2 3 4 5 VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V VCC = 3.9 V IOH (mA) IOL (mA) CMOS input characteristics TA = + 25 °C 2.4 2.2 2.0 VIH 2.4 2.2 2.0 Hysteresis input characteristics TA = + 25 °C VIHS Hysteresis input (V) 1.8 1.8 1.6 1.4 1.2 1.0 VILS 0.8 0.6 0.4 CMOS input (V) 1.6 1.4 VIL 1.2 1.0 0.8 0.6 0.4 2.4 2.7 3.0 3.3 3.6 2.4 2.7 3.0 3.3 3.6 VCC (V) VCC (V) (Continued) DS07-13722-11E 115 MB90480B/485B Series ICC − VCC 60 f = 25 MHz 50 f = 20 MHz 40 f = 16 MHz ICC (mA) 30 f = 10 MHz 20 f = 4 MHz f = 2 MHz f = 1 MHz 2.7 3.0 VCC (V) 3.3 3.6 3.9 10 0 2.4 ICCH − VCC 1.4 1.2 1.0 ICCH (μA) 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9 ICCT − VCC 2.0 1.8 1.6 1.4 ICCT (μA) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9 (Continued) 116 DS07-13722-11E MB90480B/485B Series IA − VCC 2.0 1.8 1.6 1.4 IA (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9 R − VCC 1000 R (kΩ) 100 10 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9 (Continued) DS07-13722-11E 117 MB90480B/485B Series (Continued) ICCS − VCC 20 18 16 14 f = 20 MHz f = 16 MHz 10 8 6 4 2 0 2.4 2.7 3.0 VCC (V) 3.3 3.6 f = 4 MHz f = 2 MHz f = 1 MHz 3.9 f = 10 MHz f = 25 MHz ICCS (mA) 12 ICCL − VCC 20 18 16 14 ICCL (μA) 12 10 8 6 4 2 0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9 IR − VCC 250 200 150 IR (μA) 100 50 0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9 118 DS07-13722-11E MB90480B/485B Series ■ ORDERING INFORMATION Part number MB90F481BPF MB90F482BPF MB90487BPF MB90488BPF MB90F488BPF MB90483CPF MB90F489BPF MB90483CPMC MB90487BPMC MB90488BPMC MB90F481BPMC MB90F482BPMC MB90F488BPMC MB90F489BPMC Package 100-pin plastic QFP (FPT-100P-M06) 100-pin plastic LQFP (FPT-100P-M20) DS07-13722-11E 119 MB90480B/485B Series ■ PACKAGE DIMENSIONS 100-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 mm × 14.0 mm Gullwing Plastic mold 1.70 mm Max 0.65 g P-LFQFP100-14×14-0.50 (FPT-100P-M20) Code (Reference) 100-pin plastic LQFP (FPT-100P-M20) 16.00±0.20(.630±.008)SQ Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part INDEX 1.50 –0.10 .059 –.004 (Mounting height) 26 +0.20 +.008 100 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0°~8° "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 1 25 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M 0.145±0.055 (.006±.002) C 2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 120 DS07-13722-11E MB90480B/485B Series (Continued) 100-pin plastic QFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 14.00 × 20.00 mm Gullwing Plastic mold 3.35 mm MAX P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8° 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS07-13722-11E 121 MB90480B/485B Series ■ MAIN CHANGES IN THIS EDITION Page 86 Section ■ ELECTRICAL CHARACTERISTICS 2. Recommended Operating Conditions Change Results Corrected the “Operating temperature” as follows. Added “At external bus operation” to remarks. Corrected the value; Min: − 40→ 0 / Max: + 85 → + 70 The vertical lines marked in the left side of the page show the changes. 122 DS07-13722-11E MB90480B/485B Series MEMO DS07-13722-11E 123 MB90480B/485B Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department