MB90803

FUJITSU SEMICONDUCTOR DATA SHEET Preliminary 2004.07.22 16-bit Proprietary Microcontroller CMOS R MB90800 Series MB90803/F804/V800 s DESCRIPTION The MB90800 series is a general-purpose 16-bit microcontroller that has been developed for high-speed realtime processing required for industrial and office automation equipment and process control, etc. The LCD controller of 48 segment four common is built into. Instruction set has taken over the same AT architecture as in the F2MC*-8L and F2MC 16L, and is further enhanced to support high level languages, extend addressing mode, enhanced divide/multiply instructions with sign and enrichment of bit processing. In addition, long word processing is now available by introducing a 32-bit accumulator. * : F2MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd. s FEATURES • Clock • Built-in PLL clock frequency multiplication circuit • Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or 1 to 4 times the oscillation (at oscillation of 6.25 MHz, 6.25 MHz to 25 MHz). • Minimum instruction execution time of 40.0 ns (at oscillation of 6.25 MHz, four times the PLL clock, operation at Vcc = 3.3 V) • The maximum memory space:16 MB • 24-bit internal addressing • Bank addressing (Continued) s PACKAGE 100-pin plastic QFP (FPT-100P-M06) MB90800 Series (Continued) • Optimized instruction set for controller applications • Wide choice of data types (bit, byte, word, and long word) • Wide choice of addressing modes (23 types) • High code efficiency • Enhanced high-precision computing with 32-bit accumulator • Enhanced Multiply/Divide instructions with sign and the RETI instruction • Instruction system compatible with high-level language (C language) and multitask • Employing system stack pointer • Instruction set has symmetry and barrel shift instructions • Program Patch Function (2 address pointer) • 4-byte instruction queue • Interrupt function • The priority level can be set to programmable. • Interrupt function with 32 factors • Data transfer function • Expanded intelligent I/O service function (EI 2 OS): Maximum of 16 channels] • Low Power Consumption Mode • Sleep mode (a mode that helts CPU operating clock) • Time-base timer mode (a mode that operates oscillation clock and time-base timer) • Watch timer mode (mode in which only the subclock and watch timers operate) • Stop mode (a mode that stops oscillation clock and sub clock) • CPU blocking operation mode (operating CPU at each set cycle) • Package • LQFP-120P (FPT-100P-M06:0.65 mm pin pitch) • Process : CMOS technology 2 MB90800 Series s BUILT-IN PERIPHERAL FUNCTION (RESOURCE) • I/O port : 68 or less (sub-clocking 70 unused) • Time-base timer : 1channel • Watchdog timer : 1 channel • Watch timer : 1channel • LCD Controller • 48SEG 4COM • 8/10-bit A/D converter : 12 channels • 8-bit resolution or 10-bit resolution can be set. • 16-bit reload timer : 3 channels • Multi-functional timer • 16-bit free run timer : 1 channel • 16-bit Output Compare : 2 channels An interrupt request can be output when the count value of the 16-bit free-run timer and the setting value in the compare register match. • Input capture : 2 channels Upon detecting a valid edge of the signal input from the external input pin, the count value of the 16-bit freerun timer is loaded into the input capture data register and an interrupt request can be output. • 16-bit PPG timer : 2 channels • 16-bit reload timer : 3 channels • UART : 2 channels • Extended I/O serial interface : 2 channels • DTP/External interrupt circuit : 4 channels • Activate the extended intelligent I/O service by external interrupt input • Interrupt output by external interrupt input • Timer clock output circuit • Delay interrupt output module • Output an interrupt request for task switching • I2C Interface : 1 channel 3 MB90800 Series s PRODUCT LINEUP 1. MB90800 Series MB90F804-101/201 MB90803/S FLASH MEMORY Mask ROM Type For evaluation built-in type built-in type On-chip PLL clock multiplication method( × 1, × 2, × 3, × 4, 1/2 when PLL stops) System clock Minimum instruction execution time of 40.0 ns (at oscillation of 6.25 MHz, four times the PLL clock) ROM capacity No 256 Kbytes 128 Kbytes RAM capacity 28 Kbytes 16 Kbytes 4 Kbytes Number of basic instructions : 351 Minimum instruction execution time : 40.0 ns/6.25 MHz oscillator (When four times is used : machine clock CPU functions 25 MHz, Power supply voltage : 3.3 V ± 0.3 V) Addressing type : 23 types Program Patch Function : 2 address pointers The maximum memory space : 16MB I/O port (CMOS) 68 ports (shared with resources), (70 ports when the subclock is Ports not used) Segment driver that can drive the LCD panel (liquid crystal display) directly, and LCD controller/driver common driver 48 SEG × 4 COM 16-bit free-run 1 channel timer Overflow interrupt 16-bit input/ Output compare 2 channels output (OCU) Pin input factor: matching of the compare register timer Input capture 2 channels (ICU) Rewriting a register value upon a pin input (rising edge, falling edge, or both edges) 16-bit reload timer operation (toggle output, single shot output selectable) 16-Bit Reload Timer The event count function is optional. The event count function is optional. Three channels are built in. Output pin × 2 ports 16-bit PPG timer Operating clock frequency : fcp, fcp/22, fcp/24, fcp/26 Two channels are built in. Clock with a frequency of external input clock divided by 16/32/64/128 can be Timer clock output circuit output externally. 2C bus I I2C Interface. 1 channel is built-in. 12 channels (input multiplex) 8/10-bit A/D converter The 8-bit resolution or 10-bit resolution can be set. Conversion time : 5.9 µs (When machine clock 16.8 MHz works). Full-duplex double buffer UART Asynchronous/synchronous transmit (with start/stop bits) are supported. Two channels are built in. Extended I/O serial interface Two channels are built in. Four channel independence (A/D input and using combinedly) Interrupt delay interrupt Interrupt causes : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable 8 channels (The 8 channels include with the shared A/D input) DTP/External interrupt Interrupt causes：“L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable Low Power Consumption Mode Sleep mode/Timebase timer mode/Watch mode/Stop mode/CPU intermittent mode Process CMOS Operating voltage 2.7 V to 3.6 V 4 Part number MB90V800 MB90800 Series s PIN ASSIGNMENT (TOP VIEW) P23/SEG31 P22/SEG30 P21/SEG29 P20/SEG28 P17/SEG27 P16/SEG26 P15/SEG25 X0 X1 VSS VCC P14/SEG24 P13/SEG23 P12/SEG22 P11/SEG21 P10/SEG20 P07/SEG19 P06/SEG18 P05/SEG17 P04/SEG16 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P24/SEG32 P25/SEG33 P26/SEG34 P27/SEG35 P30/SEG36/SO3 P31/SEG37/SC3 P32/SEG38/SI3 P33/SEG39/TMCK P34/SEG40/IC0 P35/SEG41/IC1 P36/SEG42/OCU0 P37SEG43/OCU1 X0A/P90 X1A/P91 VCC VSS P40/LED0 P41/LED1 P42/LED2 P43/LED3 P44/LED4 P45/LED5/TOT0 P46/LED6/TOT1 P47/LED7/TOT2 P50/SEG44/TIN0 P51/SEG45/TIN1 P52/SEG46/TIN2/PPG0 P53/SEG47/PPG1 P54/SI0 P55/SO0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P03/SEG15 P02/SEG14 P01/SEG13 P00/SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 VSS VCC SEG1 SEG0 P84/COM3 P83/COM2 COM1 COM0 V3 V2/P82 V1/P81 V0/P80 RST MD0 MD1 MD2 P56/SO0 AVCC P57/SI1 P76 AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5/INT0 P66/AN6/INT1 P67/AN7/INT2 VSS P70/AN8/INT3 P71/AN9/SC1 P72/AN10/SO1 P73/AN11/SI2 P74/SDA/SC2 P75/SCL/SO2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (FPT-100P-M06) 5 MB90800 Series s PIN DESCRIPTION Pin No. QFP 92, 93 Pin Name Circuit Status/function Type* at reset A Oscillation status Oscillation status Port input (High-Z) Mode Pins Mode Pins Reset input LCD SEG output Description It is a terminal which connects the oscillator. When connecting an external clock, leave the x1 pin side unconnected. It is 32 kHz oscillation pin. (Dual-line model) General purpose input/output port. (Single-line model) Input pin for selecting operation mode. Connect directly to Vss. Input pin for selecting operation mode. Connect directly to Vcc. External reset input pin. A segment output terminal of the LCD controller/ driver. A segment output terminal of the LCD controller/ driver. General purpose input/output port. E A segment output terminal of the LCD controller/ driver. General purpose input/output port. E A segment output terminal of the LCD controller/ driver. General purpose input/output port. Port input (High-Z) E A segment output terminal of the LCD controller/ driver. General purpose input/output port. Serial data output pin of serial I/O channel 3. Valid when serial data output of serial I/O channel 3 is enabled. A segment output terminal of the LCD controller/ driver. E General purpose input/output port. Serial clock I/O pin of serial I/O channel 3. Valid when serial clock output of serial I/O channel 3 is enabled. X0, X1 X0A, X1A 13, 14 P90, P91 51 52, 53 54 63, 64, 67 to 72, 73 to 76 77 to 84 MD2 MD1, MD0 RST SEG0 to SEG11 SEG12 to SEG19 P00 to P07 85 to 89, 94 to 96 97 to 100, 1 to 4 SEG20 to SEG27 P10 to P17 SEG28 to SEG35 P20 to P27 SEG36 5 P30 SO3 B G M L K D E SEG37 6 P31 SC3 * : For the circuit type, see section “s I/O CIRCUIT TYPE”. (Continued) 6 MB90800 Series Pin No. QFP Pin Name SEG38 P32 Circuit Status/function Type* at reset Description A segment output terminal of the LCD controller/ driver. General purpose input/output port. 7 SI3 E Serial data input pin of serial I/O channel 3. This pin may be used at any time during serial I/O channel 3 in input mode, so do not use it as other pin function. A segment output terminal of the LCD controller/ driver. SEG39 8 P33 TMCK SEG40, SEG41 9, 10 P34, P35 IC0, IC1 SEG42, SEG43 11, 12 P36, P37 OCU0, OCU1 17 to 21 LED0 to LED4 P40 to P44 LED5 to LED7 P45 to P47 22 to 24 TOT0 to TOT2 SEG44 to SEG45 P50, P51 25, 26 TIN0, TIN1 * : For the circuit type, see section “s I/O CIRCUIT TYPE”. E F F E E E General purpose input/output port. Timer clock output pin. It is effective when permitting the power output. A segment output terminal of the LCD controller/ driver. General purpose input/output port. External trigger input pin of input capture channel 0/ channel 1. A segment output terminal of the LCD controller/ driver. General purpose input/output port. Output terminal for the Output Compares. It is a output terminal for LED (IOL = 15 mA). General purpose input/output port. It is a output terminal for LED (IOL = 15 mA). General purpose input/output port. External event output pin of reload timer channel 0 to chanel 2. It is effective when permitting the external event output. A segment output terminal of the LCD controller/ driver. General purpose input/output port. External clock input pin of reload timer channel 0, channel 1. It is effective when permitting the external clock input. Port input (High-Z) (Continued) 7 MB90800 Series Pin No. QFP Pin Name SEG46 P52 Circuit Status/function Type* at reset Description A segment output terminal of the LCD controller/ driver. General purpose input/output port. 27 TIN2 PPG0 SEG47 28 P53 PPG1 E External clock input pin of reload timer channel 2. It is effective when permitting the external clock input. PPG timer (ch0) output pin. A segment output terminal of the LCD controller/ driver. E General purpose input/output port. PPG (ch1) timer output pin. Serial data input pin of UART channel 0. This pin may be used at any time during UART channel 0 in receiving mode, so do not use it as other pin function. General purpose input/output port. Port input (High-Z) Serial clock input/output pin of UART channel 0. It is effective when permitting the serial clock output of UART channel 0. General purpose input/output port. Serial data output pin of UART channel 0. It is effective when permitting the serial clock output of UART channel 0. General purpose input/output port. Serial data input pin of UART channel 1. This pin may be used at any time during UART channel 1 in receiving mode, so do not use it as other pin function. General purpose input/output port. General purpose input/output port. Analog input pin channel 0 to channel 4 of A/D converter. Enabled when analog input setting is " enabled "(set by ADER). General purpose input/output port. 29 SIO G P54 SC0 P55 SO0 P56 30 G 31 G 33 SI1 G P57 34 P76 AN0 to AN4 P60 to P64 * : For the circuit type, see section “s I/O CIRCUIT TYPE”. G 36 to 40 I (Continued) 8 MB90800 Series Pin No. QFP Pin Name AN5 to AN7 Circuit Type* Status/function at reset Description Analog input pin channel 5 to channel 7 of A/D converter. Enabled when analog input setting is " enabled "(set by ADER). 41 to 43 P65 to P67 INT0 to INT2 AN8 I Analog input (High-Z) General purpose input/output port. Functions as an external interrupt ch0 to ch2 input pin. Analog input pin channel 8 of A/D converter. Enabled when analog input setting is " enabled "(set by ADER). General purpose input/output port. Functions as an external interrupt ch3 input pin. Analog input pin channel 9 of A/D converter. Enabled when analog input setting is " enabled "(set by ADER). 45 P70 INT3 AN9 46 P71 SC1 I I General purpose input/output port. Serial clock input/output pin of UART channel 1. It is effective when permitting the serial clock output of UART channel 1. Analog input pin channel 10 of A/D converter. Enabled when analog input setting is " enabled "(set by ADER). AN10 47 P72 SO1 I Port input (High-Z) General purpose input/output port. Serial data output pin of serial I/O channel 1. Valid when serial data output of serial I/O channel 1 is enabled. Analog input pin channel 11 of A/D converter. Enabled when analog input setting is " enabled "(set by ADER). AN11 P73 48 I General purpose input/output port. Serial data input pin of serial I/O channel 2. This pin may be used at any time during serial I/O channel 2 in input mode, so do not use it as other pin function. SI2 * : For the circuit type, see section “s I/O CIRCUIT TYPE”. (Continued) 9 MB90800 Series (Continued) Pin No. QFP Pin Name Circuit Status/function Type* at reset Description Data input/output pin of I2C Interface. This function is enabled when the operation of the I2C interface is permitted. While the I2C interface is running, the port must be set for input use. SDA 49 P74 H General purpose input/output port. (N-ch open drain) Serial clock input pin of serial I/O channel 2. Valid when serial clock output of serial I/O channel 2 is enabled. Clock input/output pin of I2C Interface. This function is enabled when the operation of the I2C interface is permitted. While the I2C interface is running, the port must be set for input use. General purpose input/output port. (N-ch open drain) Serial data output pin of serial I/O channel 2. Valid when serial data output of serial I/O channel 2 is enabled. SC2 Port input (High-Z) SCL 50 P75 H SO2 55 to 57 V0 to V2 P80 to P82 J LCD controller/driver. LCD drive power Reference power terminals of LCD controller/driver. supply input General purpose input/output port. LCD COM output Port input (Hi-Z) A common output terminal of the LCD controller/ driver. General purpose input/output port. A common output terminal of the LCD controller/ driver. A/D converter exclusive power supply input pin. A/D converter-exclusive GND power supply pin. Power supply LCD controller/driver Reference power terminals of LCD controller/driver. These are power supply input pins. GND power supply pin. 59, 60 COM0, COM1 P83, P84 COM2, COM3 AVCC AVSS V3 VCC VSS D 61, 62 32 35 58 15, 65, 90 16, 44, 66, 91 E C C J   * : For the circuit type, see section “s I/O CIRCUIT TYPE”. 10 MB90800 Series s I/O CIRCUIT TYPE Type X1 Circuit Remarks • Oscillation feedback resistance : 1 MΩ approx. Clock input Pch Nch A X0 Standby control signal • Low-rate oscillation feedback resistor, approx.10 MΩ X1A Clock input Pch Nch B X0A Standby control signal • Analog power supply input protection circuit Pch C Nch AVP • LCDC output Pch D Nch LCDC output Pch Nch E LCDC output Input signal Standby control signal • CMOS output • LCDC output • Hysteresis input (With input interception function at standby) (Continued) 11 MB90800 Series Type Circuit Remarks • CMOS output (Heavy-current IOL =15 mA for LED drive) • Hysteresis input (With input interception function at standby) Input signal Standby control signal • CMOS output • CMOS hysteresis input (With input interception function at standby) Output of input/output port and built-in resource share one output buffer. Input of input/output port and built-in resource share one input buffer. • Hysteresis input (With input interception function at standby) • N-ch open drain output Input signal Standby control signal • CMOS output • CMOS hysteresis input (With input interception function at standby) • Analog input (If the bit of analog input enable register = 1, the analog input of A/D converter is enabled.) Outp put of input/output port and built-in resource share one output buffer. Input of input/output port and built-in resource share one input buffer. Pch Nch F Pch Nch G Input signal Standby control signal Nch Nout H Pch Nch I Input signal Standby control signal A/D converter Analog input (Continued) 12 MB90800 Series (Continued) Type Circuit Remarks • CMOS output • CMOS hysteresis input (With input interception function at standby) • LCD drive power supply input Input signal Standby control signal LCD drive power supply Pch Nch J • CMOS hysteresis input with pull-up resistor. K Reset input • CMOS hysteresis input L Reset input M Input • CMOS hysteresis input with pull-down resistor 13 MB90800 Series s HANDLING DEVICES 1. Preventing Latchup, Turning on Power Supply Latchup may occur on CMOSICs under the following conditions: • If a voltage higher than VCC or lower than VSS is applied to input and output pins, • A voltage higher than the rated voltage is applied between VCC and VSS. • If the AVCC power supply is turned on before the VCC voltage. Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as VCC and the digital power supply). When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using CMOSICs, take great care to prevent the occurrence of latchup. 2. Treatment of unused pins Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down registor. If the A/D converter is not used, connect the pins under the following conditions: AVcc = Vcc and AVss = Vss. 3. About the attention when the external clock is used ・Using external clock X0 OPEN X1 4. Treatment of power supply pins (VCC/VSS) To prevent malfunctions of strobe signals due to the rise in the ground level, lower the level of unnecessary electro-magnetic emission, and prevent latchup, and conform to the total current rating in designing devices if multiple VCC or VSS pins exist. Pay attention to connect a power supply to VCC and VSS of MB90800 series device in a lowest-possible impedance. In addition, near pins of MB90800 series device, connecting a bypass capacitor is recommended at 0.1 µF across VCC and VSS. 5. Crystal oscillators circuit Noise near the X0/X1 and X0A/X1A pin may cause the device to malfunction. Design a print circuit so that X0/ X1 and X0A/X1A, a crystal oscillator (or a ceramic oscillator) , and bypass capacitor to the ground become as close as possible to each other. Furthermore, avoid wires to crossing each other as much as possible. It is highly recommended that you should use a printed circuit board artwork because you can expect stable operations from it. 6. Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. Performance of this operation, however, cannot be guaranteed. 14 MB90800 Series 7. Stabilization of Supply Power Supply A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range.Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak- to-peak values) at commercial frequencies (50 MHz/60 Mhz) fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 8. Note on Using the two-subsystem product as one-subsystem product If you are using only one subsystem of the MB90800 series that come in one two-subsystem product, use it with X0A = VSS and X1A = OPEN. 9. Write to FLASH Ensure that you must write to FLASH at the operating voltage VCC = 3.13 V to 3.6 V. Ensure that you must normal write to FLASH at the operating voltage VCC = 3.0 V to 3.6 V. 15 MB90800 Series s BLOCK DIAGRAM X0, X1 X0A∗, X1A∗ RST Clock control circuit CPU F2MC-16LX core V0/P80 V1/P81 V2/P82 V3 COM0 COM1 P83/COM2 P84/COM3 SEG0-SEG11 8 RAM (4/16/28 KB) ROM/FLASH (128/256 KB) F2MC-16LX BUS Port 8 Interrupt controller 12 P00-P07/SEG12-SEG19 Port 0 LCD Controller/ Driver 10 bits PPG A/D converter Port 6 External interrupt (4 ch) P10-P17/SEG20-SEG27 8 Port 1 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5/INT0 P66/AN6/INT1 P67/AN7/INT2 P70/AN8/INT3 P71/AN9/SC1 P72/AN10/SO1 P73/AN11/SI2 P74/SDA/SC2 P75/SCL/SO2 P76 P20-P27/SEG28-SEG35 8 Port 2 Serial I/O 2/3 Port 3 Prescaler 2/3 OCU0/1 I 2C Port 7 P30/SEG36/SO3 P31/SEG37/SC3 P32/SEG38/SI3 P33/SEG39/TMCK P34/SEG40/IC0 P35/SEG41/IC1 P36/SEG42/OCU0 P37/SEG43/OCU1 P40/LED0 P41/LED1 P42/LED2 P43/LED3 P44/LED4 P45/LED5/TOT0 P46/LED6/TOT1 P47/LED7/TOT2 P50/SEG44/TIN0 P51/SEG45/TIN1 P52/SEG46/TIN2/PPG0 P53/SEG47/PPG1 P54/SI0 P55/SC0 P56/SO0 P57/SI1 Port 9 P90∗ P91∗ Free-run timer Port 4 ICU0/1 Timer clock output ＊：X0A/X1A and P90/P91 can be switched by mask option. Reload timer 0/1/2 Port 5 PPG0/1 UART0/1 Specification of the evaluation device (MB90V800) • Built-in ROM is not exist. • The device has 28 KB built-in RAM. Prescaler 0/1 16 MB90800 Series s MEMORY MAP ROM mirror function FFFFFFH ROM area Address #2 00FFFFH 008000H 007917H 007900H ROM mirror area Extended IO area 2 Address #2 RAM area Register 000100H 0000CFH 0000C0H 0000BFH 000000H Extended IO area 1 IO area Part number MB90803 MB90F804 MB90V800 Address #1 Address #2 0010FFH 0040FFH 0070FFH FE0000H FC0000H F80000H* * : ROM is not built into V products. I must think ROM decipherment region on the tool side. Memory Map of MB90800 Series Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses ( "FF4000H to FFFFFFH" ) of bank FF is visible from the higher addresses ( " 008000H to 00FFFFH " ) of bank 00. • For setting of the ROM mirror function, see “s PERIPHERAL RESOURCE 17. ROM Mirror Function Selection Module”. Reference: • The ROM mirror function is for using the C compiler small model. • The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Note that because the ROM area of bank FF exceeds 32 K bytes, all data in the ROM area cannot be shown in mirror image in bank 00. • When the C compiler small model is used, the data table mirror image can be shown at " 008000H to 00FFFFH " by storing the data table at " FF8000H to FFFFFFH. Therefore, data tables in the ROM area can be referenced without declaring the far addressing with the pointer. 17 MB90800 Series s F2MC-16L CPUProgramming model • Dedicated Registers AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8 bit 16 bit 32 bit Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register • General purpose registers MSB 000180H + RP × 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R3 R5 R7 R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 16 bit LSB • Processor status 15 PS ILM 13 12 RP 87 CCR 0 18 MB90800 Series s I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH to 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH to 00001DH 00001EH 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H to 000027H CDCR0 ADER0 ADER1 SMR0 SCR0 S1DR0/ SODR0 SSR0 Analog input enable 0 Analog input enable 1 Mode Register ch0 Control register ch0 Input/output data register ch0 Status register ch0 Prohibited. Communication prescaler control register ch0 Prohibited R/W Prescaler 0 0 0 - - 0 0 0 0B DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Prohibited R/W R/W R/W R/W R/W R/W UART0 Port 6, A/D Port 7, A/D 1 1 1 1 1 1 1 1B - - - - 1 1 1 1B 0 0 0 0 0 - 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB 0 0 0 0 10 0 0B Register abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Prohibited R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - 0 0 0 0 0 0 0B - - - 0 0 0 0 0B - - - - - - 0 0B Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB - XXXXXXXB - - - XXXXXB - - - - - - XXB (Continued) 19 MB90800 Series Address 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H to 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH Register abbreviation SMR1 SCR1 SIDR1/ SODR1 SSR1 Register Mode Register ch1 Control register ch1 Input/output data register ch1 Status register ch1 Prohibited Communication prescaler control register ch1 Prohibited Read/ Write R/W R/W R/W R/W Resource name Initial Value 0 0 0 0 0 - 0 0B 0 0 0 0 0 1 0 0B UART1 XXXXXXXXB 0 0 0 0 1 0 0 0B CDCR1 R/W Prescaler 1 0 0 - - 0 0 0 0B ENIR EIRR ELVR ADCS0 ADCS1 ADCR0 ADCR1 ADMR CPCLR TCDT TCCSL TCCSH External interrupt enable External interrupt request External interrupt level (lower) Prohibited A/D control status register (lower) A/D control status register (upper) A/D data register (lower) A/D data register (upper) Prohibited A/D conversion channel set register Compare clear register Timer Data register Timer control status register (lower) Timer control status register (upper) Prohibited R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W 16-bit free-run timer A/D converter A/D converter External interrupt - - - - 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 00------B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 1 0 1 XXXB 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 - - 0 0 0 0 0B IPCP0 IPCP1 ICS01 Input Capture register 0 R Input Capture register 1 Input capture control status 0/1 Prohibited R/W Input Capture 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB OCCP0 OCCP1 Output Compare register 0 Output Compare register 1 R/W R/W Output compare 0 Output compare 1 (Continued) 20 MB90800 Series Address 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH Register abbreviation OCSL OCSH TMCSR0L TMCSR0H TMR0/ TMRLR0 TMCSR1L TMCSR1H TMR1/ TMRLR1 TMCSR2L TMCSR2H TMR2/ TMRLR2 LCRL LCRH LCRR Register Output compare control status (lower) Output compare control status (upper) Timer control status register 0 (lower) Timer Control Status register 0 (upper) Timer register 0/Reload register 0 Timer control status register 1 (lower) Timer control status register 1 (upper) Timer register 1/Reload register 1 Timer control status register 2 (lower) Timer control status register 2 (upper) Timer register 2/Reload register 2 LCDC control register (lower) LCDC control register (upper) LCDC range register Prohibited Serial mode control status register (ch2) Serial Data Register (ch2) Control register of clock dividing frequency (ch2) Serial mode control status register (ch3) Serial Data Register (ch3) Control register of clock dividing frequency (ch3) Prohibited Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Output Compare 0/1 Initial Value 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 1 0 0 0 0B 16-bit reload timer 0 Reload timer 1 Reload timer 2 LCD controller/ driver 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB 0 - - - 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB 0 - - - 0 0 0 0B SMCS0 SDR0 SDCR0 SMCS1 SDR1 SDCR1 R/W R/W R/W R/W R/W R/W SIO (Extended Serial I/O) Communication prescaler (SIO) SIO (Extended Serial I/O) Communication prescaler (SIO) IBSR IBCR ICCR IADR IDAR ROMM I2C bus status register I C bus control register I C bus clock selection register I2C bus address register I2C bus data register ROM mirror 2 2 R R/W R/W R/W R/W W ROM mirror IC 2 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - 0XXXXXB - XXXXXXXB XXXXXXXXB XXXXXXX1B (Continued) 21 MB90800 Series Address 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H to 000095H 000096H 000097H 000098H to 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H to 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH to 0000ADH Register abbreviation PDCRL0 PDCRH0 PCSRL0 PCSRH0 PDUTL0 PDUTH0 PCNTL0 PCNTH0 PDCRL1 PDCRH1 PCSRL1 PCSRH1 PDUTL1 PDUTH1 PCNTL1 PCNTH1 Register PPG0 down counter register PPG0 cycle set register PPG0 duty setting register PPG0 control status register PPG1 down counter register PPG1 cycle set register PPG1 duty setting register PPG1 control status register Read/ Write R W Resource name Initial Value 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB 16 bit PPG0 W R/W R W 16 bit PPG1 W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB - - 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB - - 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B (Reserved) Prohibited (Reserved) Prohibited PACSR DIRR LPMCR CKSCR ROM correction control register Delayed interrupt/release Low power consumption mode Clock selector Prohibited WDTC TBTC WTC Watchdog control Time-base timer control register Watch timer control register Prohibited R/W R/W R/W Watchdog timer Time-base timer Watch timer (Sub clock) XXXXX 1 1 1B 1 - - 0 0 1 0 0B 1 X0 1 1 0 0 0B R/W R/W R/W R/W ROM Correction Delayed interrupt Low power consumption control circuit 0 0 0 0 0 0 0 0B - - - - - - - 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B (Continued) 22 MB90800 Series (Continued) Address 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 007900H to 007917H VRAM LCD display RAM PADR1 Program address detection register 1 PADR0 Program address detection register 0 Register abbreviation FMCS TMCS ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Register Flash control register Timer clock output control register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LCD controller/ driver Address matching detection function Interrupt controller Resource name Flash I/F Timer clock devide Initial Value 0 0 0 X 0 0 0 0B XXXXX 0 0 0B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB • Read/Write R/W Readable and Writable R Read only W Write only • Initial values 0 Initial Value is “0”. 1 Initial Value is “1”. X Initial Value is Indeterminate. 23 MB90800 Series s INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS Interrupt source Reset INT 9 instruction Exceptional treatment DTP/External interrupt ch0 DTP/External interrupt ch1 Serial I/O ch2 DTP/External interrupt ch2/3 Serial I/O ch3 16-bit free-run timer Watch timer 16-Bit Reload Timer ch2 16-Bit Reload Timer ch0 16-Bit Reload Timer ch1 Input capture ch0 Input capture ch1 PPG timer ch0 counter-borrow Output compare match PPG timer ch1 counter-borrow Time-base timer UART0 reception end UART0 transmission end A/D converter conversion termination I C Interface UART1 : Reception UART1 : Transmission Flash memory status Delayed interrupt output module × × 2 EI2OS readiness × × × Interrupt vector Number* #08 #09 #10 #11 #13 08H 09H 0AH 0BH 0DH 0FH 10H 11H 12H 13H 15H 17H 18H 19H 1AH 1BH 1DH 1FH 21H 23H 24H 25H 26H 27H 28H 29H 2AH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFC8H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFA8H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF88H FFFF80H FFFF78H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register ICR    ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address    0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Priority High × × × #15 #16 #17 #18 #19 #21 #23 #24 #25 #26 #27 #29 #31 × #33 #35 #36 #37 × #38 #39 #40 #41 #42 Low : Available × : Unavailable : Available El2OS function is provided. : Available when a cause of interrupt sharing a same ICR is not used. * : When interrupts of the same level are output at the same time, the interrupt with the smallest interrupt vector number has the priority. • When there are two interrupt causes in the same interrupt control register (ICR) and use of IIOS is enabled, IIOS is started upon detection of one of the interrupt causes. As interrupts other than the start cause are masked during IIOS start, masking one of the interrupt requests is recommended when using IIOS. • For a resource that has two interrupt causes in the same interrupt control register (ICR), the interrupt flag is cleared by an IIOS interrupt clear signal. 24 MB90800 Series s PERIPHERAL RESOURCES 1. I/O port The I/O ports function to output data from the CPU to I/O pins via their port data register (PDR) and send signals input to I/O pins to the CPU. In addition, the port can randomly set the direction of the input/output of the I/O pin in bit by the port direction register (DDR). The MB90800 series has 68 (70 ports when the subclock is not used) input/output pins. Port0 to port8 (port0 to port9 when the subclock is not used) are input/output port. (1) Port data register PDR0 Address : 000000H PDR1 Address : 000001H PDR2 Address : 000002H PDR3 Address : 000003H PDR4 Address : 000004H PDR5 Address : 000005H PDR6 Address : 000006H PDR7 Address : 000007H PDR8 Address : 000008H PDR9 Address : 000009H 7 P07 15 P17 7 P27 15 P37 7 P47 15 P57 7 P67 15  7  15  6 P06 14 P16 6 P26 14 P36 6 P46 14 P56 6 P66 14 P76 6  14  5 P05 13 P15 5 P25 13 P35 5 P45 13 P55 5 P65 13 P75 5  13  4 P04 12 P14 4 P24 12 P34 4 P44 12 P54 4 P64 12 P74 4 P84 12  3 P03 11 P13 3 P23 11 P33 3 P43 11 P53 3 P63 11 P73 3 P83 11  2 P02 10 P12 2 P22 10 P32 2 P42 10 P52 2 P62 10 P72 2 P82 10  1 P01 9 P11 1 P21 9 P31 1 P41 9 P51 1 P61 9 P71 1 P81 9 P91 0 P00 8 P10 0 P20 8 P30 0 P40 8 P50 0 P60 8 P70 0 P80 8 P90 Initial Value Indeterminate Access R/W* Indeterminate R/W* Indeterminate R/W* Indeterminate R/W* Indeterminate R/W* Indeterminate R/W* Indeterminate R/W* Indeterminate R/W* Indeterminate R/W* Indeterminate R/W* When reading : Read the corresponding pin level. When writing : Write into the latch for the input/output. • Output mode When reading : Read the value of the data register latch. When writing : Write into the corresponding pin. 25 MB90800 Series (2) Port direction register DDR0 Address : 000010H DDR1 Address : 000011H DDR2 Address : 000012H DDR3 Address : 000013H DDR4 Address : 000014H DDR5 Address : 000015H DDR6 Address : 000016H DDR7 Address : 000017H DDR8 Address : 000018H DDR9 Address : 000019H 7 D07 15 D17 7 D27 15 D37 7 D47 15 D57 7 D67 15  7  15  6 D06 14 D16 6 D26 14 D36 6 D46 14 D56 6 D66 14 D76 6  14  5 D05 13 D15 5 D25 13 D35 5 D45 13 D55 5 D65 13 D75 5  13  4 D04 12 D14 4 D24 12 D34 4 D44 12 D54 4 D64 12 D74 4 D84 12  3 D03 11 D13 3 D23 11 D33 3 D43 11 D53 3 D63 11 D73 3 D83 11  2 D02 10 D12 2 D22 10 D32 2 D42 10 D52 2 D62 10 D72 2 D82 10  1 D01 9 D11 1 D21 9 D31 1 D41 9 D51 1 D61 9 D71 1 D81 9 D91 0 D 00 8 D10 0 D20 8 D30 0 D40 8 D50 0 D60 8 D70 0 D80 8 D90 Initial Value 00000000B Access R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W - 0000000B R/W - - - 00000B R/W - - - - - - 00B R/W • When each terminal functions as a port, each correspondent pin are controlled to following; 0 : Input mode 1 : Output mode This bit becomes “0” after a reset. Note : When accessing this register by using the instruction of the read modify write system (instructions such as bit set) is mode, the bit targeted by an instruction becomes the defined value, while the content of the output register set with the other. Therefore, be sure to write an expected value into PDR firstly, and then set DDR and finally change to the output when changing the input pin to the output pin is made. 26 MB90800 Series (3) Analog Input Enable register ADER0 Address : 00001EH ADER1 Address : 00001FH 7 ADE7 15  6 ADE6 14  5 ADE5 13  4 ADE4 12  3 ADE3 11 ADE11 2 ADE2 10 ADE10 1 ADE1 9 ADE9 0 ADE0 8 ADE8 Initial Value Access 11111111B R/W - - - -1111B R/W Control each pin of Port 6 as follows. 0 : Port input/output mode. 1 : Analog input mode.This bit becomes “1” after a reset. 27 MB90800 Series 2. UART UART is a serial I/O port for asynchronous (start-stop synchronization) communication or CLK synchronous communications. • With full-duplex double buffer • Clock asynchronous (start-stop synchronization) , CLK synchronous communications (no start-bit/stop-bit) can be used. • Supports multi-processor mode • Built-in dedicated baud rate generator Asynchronous : 120192/60096/30048/15024/781.25 K/390.625 Kbps CLK synchronous : 25 M/12.5 M/6.25 M/3.125 M/1.5627 M/781.25 Kbps Variable baud rate can be set by an external clock. 7-bits data length (only asynchronous normal mode) /8-bits length Master/slave type communication function (at multiprocessor mode) : The communication between one (master) to n (slave) can be operating. Error detection functions(parity, framing, overrun) Transmission signal format is NRZ • • • • • 28 MB90800 Series (1) Register list 15 CDCR SCR SSR 8 bit 87  SMR SIDR (R)/SODR (W) 8 bit 0 Serial mode register (SMR) 7 6 MD0 (R/W) (0) 5 CS2 (R/W) (0) 4 CS1 (R/W) (0) 3 CS0 (R/W) (0) 2  () () 1 SCKE (R/W) (0) 0 SOE (R/W) (0) 000020H Address : 000028H Serial control register(SCR) MD1 (R/W) (0) Initial Value 15 14 P (R/W) (0) 13 SBL (R/W) (0) 12 CL (R/W) (0) 11 A/D (R/W) (0) 10 REC (W) (1) 9 RXE (R/W) (0) 8 TXE (R/W) (0) 000021H Address : 000029H PEN (R/W) (0) Initial Value Serial input/output register (SIDR/SODR) 7 6 D6 (R/W) (X) 5 D5 (R/W) (X) 4 D4 (R/W) (X) 3 D3 (R/W) (X) 2 D2 (R/W) (X) 1 D1 (R/W) (X) 0 D0 (R/W) (X) 000022H Address : 00002AH Serial Data Register (SSR) D7 (R/W) (X) Initial Value 15 14 ORE (R) (0) 13 FRE (R) (0) 12 RDRF (R) (0) 11 TDRE (R) (1) 10 BDS (R/W) (0) 9 RIE (R/W) (0) 8 TIE (R/W) (0) 000023H Address : 00002BH PE (R) (0) Initial Value Communication prescaler control register (CDCR) 15 14 URST (R/W) (0) 13  () () 12  () () 11 Reserved 10 DIV2 (R/W) (0) 9 DIV1 (R/W) (0) 8 DIV0 (R/W) (0) 000025H Address : 00002DH MD (R/W) (0) (R/W) (0) Initial Value 29 MB90800 Series (2) Block Diagram Control signal RX interrupt (to CPU) Clock selection circuit Transmission clock Reception clock Reception control circuit Pin Start bit detection circuit Special-purpose baud-rate generator 16-bit reload timer 0 Pin TX interrupt (to CPU) Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter Reception bit counter Reception parity counter Pin Receive status decision circuit Reception error occurrence signal for EI2OS (to CPU) RX shifter Reception control circuit TX shifter Start transmission SIDR SODR F2MC-16LX BUS SMR Register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR Register PEN P SBL CL A/D REC REX TXE SSR Register PE ORE FRE RDRF TDRE BDS RIE TIE Control signal 30 MB90800 Series 3. I2C Interface I2C interface is the serial input/output port that support Inter IC BUS and functions as the master/slave device on the I2C bus. MB90800 series have 1 channel of the built-in I2C interface. It has the features of I2C interface below. • Master/slave sending and receiving • Arbitration function • Clock synchronization function • Slave address and general call address detection function • Detecting transmitting direction function • Repeat generating and detecting function of the start conditions • Bus error detection function • The forwarding rate can be supported to 100 Kbps. (1) Register list I2C status register (IBSR) Address :00006AH 7 BB R 6 RSC R 5 AL R 4 LRB R 3 TRX R 2 AAS R 1 GCA R 0 FBT R Initial Value 00000000B I2C control register (IBCR) Address :00006BH 15 BER R/W 14 BEIE R/W 13 SCC R/W 12 MSS R/W 11 ACK R/W 10 GCAA R/W 9 INTE R/W 8 INT R/W 00000000B I2C clock control register (ICCR) Address :00006CH 7   6   5 EN R/W 4 CS4 R/W 3 CS3 R/W 2 CS2 R/W 1 CS1 R/W 0 CS0 R/W XX0XXXXXB I2C data register(IDAR) Address :00006EH 15 D7 R/W 14 D6 R/W 13 D5 R/W 12 D4 R/W 11 D3 R/W 10 D2 R/W 9 D1 R/W 8 D0 R/W XXXXXXXXB I2C address register (IADR) Address :00006DH 7   6 A6 R/W 5 A5 R/W 4 A4 R/W 3 A3 R/W 2 A2 R/W 1 A1 R/W 0 A0 R/W XXXXXXXXB 31 MB90800 Series (2) Block Diagram ICCR EN I2C Enable Clock divide 1 Machine clock 5 6 7 8 ICCR CS4 Clock selector 1 CS3 CS2 CS1 248 Clock divide 2 16 32 64 128 256 Sync Generating shift clock Internal data bus CS0 Clock selector 2 Change timing of shift clock edge Bus busy Repeat start Last Bit Transfer/ reception IBSR BB RSC LRB TRX FBT AL IBCR BER Start stop Condition detection Error First Byte Arbitration lost detection SCL BEIE INTE INT IBCR SCC MSS ACK GCAA Interrupt request IRQ SDA End Start Master ACK enable GC-ACK enable Start stop Condition detection IDAR IBSR AAS GCA Slave Global call Slave address compare IADR 32 MB90800 Series 4. Extended I/O serial interface The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8 bit × 2 channel configured clock synchronization scheme. The extended I/O serial interface also has two alternatives in data transfer called LSB first and MSB sirst. The serial I/O interface operates in two modes: • Internal shift clock mode : Transfer data in sync with the internal clock. • External shift clock mode : Transfers data in sync with the clock input through an external pin (SCK) . In this mode, transfer operation performed by the CPU instruction is also available by operating the general-use port sharing an external pin (SCK) . (1) Register list Serial mode control status register(SMCS) 000060H Address : 000064H 15 SMD2 R/W 7   14 SMD1 R/W 6   13 SMD0 R/W 5   12 SIE R/W 4   11 SIR R/W 3 MODE R/W 10 BUSY R 2 BDS R/W 9 STOP R/W 1 SOE R/W 8 STRT R/W 0 SCOE R/W Initial Value 00000010B 000061H Address : 000065H ----0000B Serial Data Register (SDR) 000062H Address : 000066H 7 D7 R/W 6 D6 R/W 5 D5 R/W 4 D4 R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W XXXXXXXX Communication Prescaler control register (SDCR0, SDCR1) Address : 000063H 000067H 15 MD R/W 14   13   12   11 Reserved 10 DIV2 R/W 9 DIV1 R/W 8 DIV0 R/W 0---0000 R/W 33 MB90800 Series (2) Block Diagram Internal data bus (MSB fast) D0 to D7 SI2, SI3 Initial Value (LSB fast) D7 to D0 Transfer direction selection SDR (Serial Data Register) Read Write SO2, SO3 SC2, SC3 Control circuit Shift clock counter Internal clock 2 1 0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE SMD2 SMD1 SMD0 Interrupt request Internal data bus 34 MB90800 Series 5. 8/10-bit A/D converter A/D converter converts an analog input voltage into digital value. The feature of A/D converter is shown as follows. • conversion time : 3.1 µs minimum per 1 channel (78 machine cycle/at machine clock 25 MHz/including the sampling time) • Sampling time : 2.0 µs minimum per 1channel (50 machine cycle/at machine clock 25 MHz) • Uses RC-type successive approximation conversion method with a sample & hold circuit • 8-bit resolution or 10-bit resolution can be select. • 12 channel program-selectable analog inputs. Single conversion mode : Convert 1 specified channel Scan conversion mode : Continuous plural channels (maximum 12 channels can be programmed) are converted. Continuous conversion mode : Selected channel converted continuously. Stop conversion time : Perform conversion for one channel, then wait for the next activation trigger (synchronizes the conversion start timing) 2OS can be activated by outputting the interrupt request when the A/D conversion completes. • EI • If the A/D conversion is performed under the condition of the interrupt enable, the converting data will be protected. • Selectable conversion activation trigger : Software, or reload timer (rising edge) (1) Register list ADCS1, ADCS0 (Control status register) ADCS0 7 6 5 Address : 000034H MD1 MD0  0 R/W 0 R/W 14 INT 0 R/W   13 INTE 0 R/W 4    12 PAUS 0 R/W 3    11 STS1 0 R/W 2    10 STS0 0 R/W 1    9 STRT 0 W 0    8 Reserved ←Initial Value ←bit ADCS1 bit Address : 000035H 15 BUSY 0 R/W 0 R/W ←Initial Value ←bit ADCR1, ADCR0 (data register) ADCR0 bit 7 Address : 000036H D7 X R 6 D6 X R 14 ST1 0 W 5 D5 X R 13 ST0 1 W 4 D4 X R 12 CT1 0 W 3 D3 X R 11 CT0 1 W 2 D2 X R 10    1 D1 X R 9 D9 X R 0 D0 X R 8 D8 X R ←Initial Value ←bit ADCR1 bit Address : 000037H 15 S10 0 W ←Initial Value ←bit 35 MB90800 Series (2) Block Diagram AVCC MP AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AVR AVSS D/A converter Input circuit Sequential compare register Comparator Data bus Data register Decoder ADCR0, ADCR1 ADCS0, ADCS1, ADMR Sample & hold circuit A/D channel set register A/D Control register 0 A/D Control register 1 Timer start-up 16-Bit Reload Timer φ Operation clock Prescaler 36 MB90800 Series 6. 16 bits PPG The PPG timer consists of the prescaler, one 16-bit down-counter, one 16-bit data register with a cycle setting buffer, a 16-bit compare register with a duty setting buffer, and the pin control unit. The PPG timer can output pulses synchronized to the software trigger. The period and duty of the output pulse can be changed freely by updating two 16-bit register values. • PWM function The PPG timer can output pulses programmably by updating the values of the registers described above in synchronization to the trigger. Can also be used as a D/A converter by an external circuit. • Single shot function By detecting an edge of the trigger input, a single pulse can be output. • 16-bit down counter The counter operation clock comes from eight kinds optional. There are eight kinds of internal clocks. (φ, φ2, φ4, φ8, φ16, φ32, φ64, φ128) φ : machine clock The counter is initialized to " FFFFH " at a reset or counter borrow. • Interrupt request The PPG timer generates an interrupt request when : Timer start-up/counter borrow occurs (cycle match) /duty match occurs/counter borrow occurs (cycle match) , or duty match occurs. 37 MB90800 Series (1) Register list PCNTH (PCNTH0/1 Control Status register) 000077H 00007FH 15 CNTE (R/W) (0) 14 STGR ( R/W ) (0) 13 MDSE (R/W) (0) 12 RTRG (R/W) (0) 11 CSK2 (R/W) (0) 10 CSK1 ( R/W ) (0) 9 CSK0 ( R/W ) (0) 8 PGMS ( R/W ) (X) Read/Write Initial Value PCNTL (PCNTL0/1 Control Status register) 000076H 00007EH 7  () () 6  () () 5 IREN (R/W) (0) 4 IRQF (R/W) (0) 3 IRS1 (R/W) (0) 2 IRS0 (R/W) (0) 1 POEN (R/W) (0) 0 OSEL (R/W) (0) Read/Write Initial Value PDCRH (PDCRH0/1 PPG Down Counter Register) 000071H 000079H 15 DC15 (R) (1) 14 DC14 (R) (1) 13 DC13 (R) (1) 12 DC12 (R) (1) 11 DC11 (R) (1) 10 DC10 (R) (1) 9 DC09 (R) (1) 8 DC08 (R) (1) Read/Write Initial Value PDCRL (PDCRL0/1 PPG Down Counter Register) 000070H 000078H 7 DC07 (R) (1) 6 DC06 (R) (1) 5 DC05 (R) (1) 4 DC04 (R) (1) 3 DC03 (R) (1) 2 DC02 (R) (1) 1 DC01 (R) (1) 0 DC00 (R) (1) Read/Write Initial Value Read/Write Initial Value PCSRH (PCSRH0/1 PPG cycle set register) 000073H 00007BH 15 CS15 (W) (X) 14 CS14 (W) (X) 13 CS13 (W) (X) 12 CS12 (W) (X) 11 CS11 (W) (X) 10 CS10 (W) (X) 9 CS09 (W) (X) 8 CS08 (W) (X) PCSRL (PCSRH0/1 PPG cycle set register) 000072H 00007AH 7 CS07 (W) (X) 6 CS06 (W) (X) 5 CS05 (W) (X) 4 CS04 (W) (X) 3 CS03 (W) (X) 2 CS02 (W) (X) 1 CS01 (W) (X) 0 CS00 (W) (X) Read/Write Initial Value PDUTH (PDUTH0/1 PPG duty set register) 000075H 00007DH 15 DU15 (W) (X) 14 DU14 (W) (X) 13 DU13 (W) (X) 12 DU12 (W) (X) 11 DU11 (W) (X) 10 DU10 (W) (X) 9 DU09 (W) (X) 8 DU08 (W) (X) Read/Write Initial Value PDUTL (PDUTL0/1 PPG duty set register) 000074H 00007CH 7 DU07 (W) (X) 6 DU06 (W) (X) 5 DU05 (W) (X) 4 DU04 (W) (X) 3 DU03 (W) (X) 2 DU02 (W) (X) 1 DU01 (W) (X) 0 DU00 (W) (X) Read/Write Initial Value 38 MB90800 Series (2) Block Diagram ・16-bit G ch0/1 block diagram Prescaler 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 CK PCSR PDUT Load CMP PCNT 16-bit down counter Start Borrow PPG mask Machine clock φ S Q PPG output R Reverse bit Enable Interrupt select Interrupt Soft trigger 39 MB90800 Series 7. Delay interrupt generator module The delayed interrupt generation module outputs an interrupt request for task swiching. When the delayed interrupt generation module is used, software is allowed to output and clear task switching interrupts for the MB90800 Series CPU. (1) Register list Delayed Interrupt/release register(DIRR) DIRR 15 14 Address : 00009FH     13   12   11   10   9   8 R0 R/W Initial Value - - - - - - - 0B (2) Block diagram F2MC-16LX bus Delay interruption factor generation/ release decoder Factor latch 40 MB90800 Series 8. DTP/External interrupt DTP (Data Transfer Peripheral)/External interrupt circuit detects the interrupt request input from the external interrupt input terminal, and outputs the interrupt request. (1) Register list Interrupt/DTP enable register (ENIR : Enable Interrupt Request Register) ENIR 7 6 5 4 3 2 1 Address : 000030H     EN3 EN2 EN1     R/W R/W R/W 0 EN0 R/W Initial Value - - - - 0000B Interrupt/DTP source register (EIRR : External Interrupt Request Register) EIRR 15 14 13 12 11 10 9 Address : 000031H     ER3 ER2 ER1     R/W R/W R/W 8 ER0 R/W Initial Value - - - - XXXXB Request level setting register (ELVR : External Level Register) 7 6 LA3 R/W 5 LB2 R/W 4 LA2 R/W 3 LB1 R/W 2 LA1 R/W 1 LB0 R/W 0 LA0 R/W Address : 000032H LB3 R/W Initial Value 00000000B (2) Block diagram F2MC-16LX bus 4 Interrupt/DTP enable register Source F/F 4 4 Gate Edge detection circuit Request input 4 Interrupt/DTP source register Request level setting register 8 41 MB90800 Series 9. 16-bit input/output timer The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare and two input capture modules. This function enables six independent waveforms to be output based on the 16-bit free-run timer, and input pulse widths and external clock frequencies to be measured. ・Register list ・16-bit free-run timer 15 0 CPCLR 00003B/3AH Compare clear register Timer counter data register Timer counter control status register 00003D/3CH TCDT 00003F/3EH TCCS ・16-bit Output Compare 15 0 OCCP0 ∼ OCCP1 00004AH/00004BH/ 00004CH/00004DH 00004FH/00004EH OCSH Compare register Control status register OCSL ・16-bit Input Capture 15 0 IPCP0, IPCP1 000044H/000045H/ 000046H/000047H 000048H Data register Control status register ICS01 42 MB90800 Series ・Block diagram Control logic Interrupt 16-bit free-run timer 16-bit timer Clear Output compare 0 Bus Output compare 1 To each block Compare register 0 Compare register 1 TQ OTE0 TQ OTE1 Input capture 0 Capture register 0 Edge select IC0 Input capture 1 Capture register 1 Edge select IC1 43 MB90800 Series (1) 16-bit free-run timer The 16-bit free-run timer consists of a 16-bit up-down counter and control status register. Counter value of 16-bit free-run timer is available as base timer for input capture and output compare. • Clock for the counter operation can be selected from eight types. • The counter overflow interruption can be generated. • Setting the mode enables initialization of the counter through compare-match operation with the value of the compare clear register in the output compare. ・Register list Compare clear register (CPCLR) 15 14 CL14 (R/W) 13 CL13 (R/W) 12 CL12 (R/W) 11 CL11 (R/W) 10 CL10 (R/W) 9 CL09 (R/W) 8 CL08 (R/W) 00003BH CL15 (R/W) Initial Value XXXXXXXXB 7 6 CL06 (R/W) 5 CL05 (R/W) 4 CL04 (R/W) 3 CL03 (R/W) 2 CL02 (R/W) 1 CL01 (R/W) 0 CL00 (R/W) 00003AH CL07 (R/W) Initial Value XXXXXXXXB Timer counter data register (TCDT) 15 14 T14 (R/W) 13 T13 (R/W) 12 T12 (R/W) 11 T11 (R/W) 10 T10 (R/W) 9 T09 (R/W) 8 T08 (R/W) 00003DH T15 (R/W) Initial Value 00000000B 7 6 T06 (R/W) 5 T05 (R/W) 4 T04 (R/W) 3 T03 (R/W) 2 T02 (R/W) 1 T01 (R/W) 0 T00 (R/W) 00003CH T07 (R/W) Initial Value 00000000B Timer counter control/status register (TCCS) 15 14  (R/W) 13  (R/W) 12 MSI2 (R/W) 11 MSI1 (R/W) 10 MSI0 (R/W) 9 ICLR (R/W) 8 ICRE (R/W) 00003FH ECKE (R/W) Initial Value 0--00000B 7 6 IVFE (R/W) 5 STOP (R/W) 4 MODE (R/W) 3 SCLR (R/W) 2 CLK2 (R/W) 1 CLK1 (R/W) 0 CLK0 (R/W) 00003EH IVF (R/W) Initial Value 00000000B 44 MB90800 Series ・Block diagram φ Interrupt request IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Divider Clock Bus 16-bit free-run timer 16-bit compare clear register Compare cirMSI2 ∼ MSI0 Count value output T15 to T00 ICLR ICRE Interrupt request 45 MB90800 Series (2) Output compare The output compare consists of 16-bit compare registers, compare output pin part and a control register. It can reverse the output level for the pin and at the same time, generate an interrupt when the 16-bit free-run timer value matches a value set in one of the 16-bit compare registers of this module. • It has a total of six compare registers that can operate independently. In addition, the output can be set to be controlled by using two compare registers. • An interrupt can be set by a comparing match. ・Register list Compare register (OCCP0, OCCP1) 15 14 OP14 (R/W) 13 OP13 (R/W) 12 OP12 (R/W) 11 OP11 (R/W) 10 OP10 (R/W) 9 OP09 (R/W) 8 OP08 (R/W) 00004BH 00004DH OP15 (R/W) Initial Value 00000000B 7 6 OP06 (R/W) 5 OP05 (R/W) 4 OP04 (R/W) 3 OP03 (R/W) 2 OP02 (R/W) 1 OP01 (R/W) 0 C00 (R/W) 00004AH 00004CH Control register (OCSH) OP07 (R/W) Initial Value 00000000B 15 14  () 13  () 12 CMOD (R/W) 11 OTE1 (R/W) 10 OTE0 (R/W) 9 OTD1 (R/W) 8 OTD0 (R/W) 00004FH  () Initial Value ---00000B Control register (OCSL) 7 6 IOP0 (R/W) 5 IOE1 (R/W) 4 IOE0 (R/W) 3  () 2  () 1 CST1 (R/W) 0 CST0 (R/W) 00004EH IOP1 (R/W) Initial Value 0000--00B 46 MB90800 Series ・Block diagram 16-bit timer counter value (T15 to T00) Compare control Compare register 0 16-bit timer counter value (T15 to T00) Bus Compare control Compare register 1 ICP1 ICP0 ICE0 ICE0 TQ OTE0 CMOD TQ OTE1 Control logic Each control blocks Interrupt #29 #29 47 MB90800 Series (3) Input capture This module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge. The input capture consists of input capture and control registers. Each input capture has its corresponding external input pin. • The detection edge of an external input can be selected from among three types. Rising edge/falling edge/ both edges. • It can generate an interrupt when it detects the valid edge of the external input. ・Register list Input capture data register (IPCP0, IPCP1) 15 14 CP14 (R) 13 CP13 (R) 12 CP12 (R) 11 CP11 (R) 10 CP10 (R) 9 CP09 (R) 8 CP08 (R) 000045H 000047H CP15 (R) Initial Value XXXXXXXXB 7 6 CP06 (R) 5 CP05 (R) 4 CP04 (R) 3 CP03 (R) 2 CP02 (R) 1 CP01 (R) 0 CP00 (R) 000044H 000046H CP07 (R) Initial Value XXXXXXXXB Control status register (ICS01) 7 6 ICP0 (R/W) 5 ICE1 (R/W) 4 ICE0 (R/W) 3 EG11 (R/W) 2 EG10 (R/W) 1 EG01 (R/W) 0 EG00 (R/W) 000048H ICP1 (R/W) Initial Value 00000000B 48 MB90800 Series ・Block diagram Capture data register 0 Edge detection IC0 16-bit timer counter value (T15 to T00) Bus EG11 EG10 EG01 EG00 Capture data register 1 Edge detection IC1 ICP1 ICP0 ICE1 ICE0 Interrupt #25 Interrupt #25 49 MB90800 Series 10. 16-bit reload timer The 16-bit reload timer provides two functions either one which can be selected, the internal clock the performs the count down by synchronizing with 3-type internal clocks and the event count mode that performs the count down by detecting the arbitration. This timer defines an underflow as a transition of the count value from 0000H to FFFFH. Therefore, when the equation (counted value = reload register setting value+1) holds, an underflow occurs. Either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC. (1) Register list • TMCSRTimer control status register Timer control status register (upper) (TMCSR) 15 14  () () 13  () () 12  () () 11 CSL1 (R/W) (0) 10 CSL0 (R/W) (0) 9 MOD2 (R/W) (0) 8 MOD1 (R/W) (0) 000051H 000055H 000059H  () () Read/Write Initial Value Timer control status register (lower) (TMCSR) 7 6 OUTE (R/W) (0) 5 OUTL (R/W) (0) 4 RELD (R/W) (0) 3 INTE (R/W) (0) 2 UF (R/W) (0) 1 CNTE (R/W) (0) 0 TRG (R/W) (0) 000050H 000054H 000058H MOD0 (R/W) (0) Read/Write Initial Value • 16-bit timer register/16-bit reload register TMR/TMRLR (upper) 15 14 D14 (R/W) (X) 13 D13 (R/W) (X) 12 D12 (R/W) (X) 11 D11 (R/W) (X) 10 D10 (R/W) (X) 9 D9 (R/W) (X) 8 D8 (R/W) (X) 000053H 000057H 00005BH TMR/TMRLR (low) D15 (R/W) (X) Read/Write Initial Value 7 6 D6 (R/W) (X) 5 D5 (R/W) (X) 4 D4 (R/W) (X) 3 D3 (R/W) (X) 2 D2 (R/W) (X) 1 D1 (R/W) (X) 0 D0 (R/W) (X) 000052H 000056H 00005AH D7 (R/W) (X) Read/Write Initial Value 50 MB90800 Series (2) Block diagram Internal data bus TMRLR 16-bit reload register Reload signal TMR 16-bit timer register (down counter) CLK UF Reload control circuit Count clock generation circuit Machine clock φ 3 Gate input Prescaler Clear Valid clock identification circuit Wait signal CLK Output signal generation circuit Pin Input control circuit Clock selector External clock Reverse Output signal generation circuit Pin EN OUTL RELD Select function 3 Select signal 2 Operation control circuit OUTE Timer control status register (TMCSR) 51 MB90800 Series 11. Watch timer The watch timer is a 15-bit timer using the subclock. It can generate interval interrupts. The watch timer can also be used as the clock source of the watchdog timer by setting so. (1) Register list Watch timer control register (WTC) 7 6 SCE (R) (X) 5 WTIE (R/W) (0) 4 WTOF (R/W) (1) 3 WTR (R/W) (1) 2 WTC2 (R/W) (0) 1 WTC1 (R/W) (0) 0 WTC0 (R/W) (0) 0000AAH WDCS (R/W) (1) Initial Value (2) Block diagram Watch timer control register (WTC) WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clear 28 Sub clock Watch counter 29 210 211 212 213 210 213 214 215 214 Interval selector Interrupt generation circuit Watch timer interrupt To watchdog timer 52 MB90800 Series 12. Watchdog timer The watchdog timer is a 2-bit counter operating with an output of the timebase timer or watch timer and resets the CPU when the counter is not cleared for a preset period of time. (1) Register list Watchdog timer control register (WDTC) 7 6  () (X) 5 WRST (R) (X) 4 ERST (R) (X) 3 SRST (R) (X) 2 WTE (W) (1) 1 WT1 (W) (1) 0 WT0 (W) (1) 0000A8H PONR (R) (X) Initial Value (2) Block diagram Watchdog timer control register (WDTC) PONR ― WRST ERST SRST WTE WT1 WT0 WDCS bit of watch timer control register (WTO) SCM bit of clock selection register (CKSCR) Watch mode start Timebase timer mode start Sleep mode start Hold status start Watchdog timer Counter clear control circuit 2 CLR and start-up Count clock selector CLR CLR 2-bit counter Stop mode start Watchdog reset generation circuit Internal reset generation circuit 4 Clear Time base counter Dividing HCLK by 2 × 21 × 22 4 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 SCLK × 21 × 2 2 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 HCLK: Oscillation clock SCLK: Sub clock 53 MB90800 Series 13. Time-base timer The time-base timer has a function that enables a selection of four interval times using 18-bit free-run counter (time-base counter) with synchronizing to the internal count clock (two division of original oscillation). Furthermore, the function of timer output of oscillation stabilization wait or function supplying operation clocks for watchdog timer are provided. (1) Register list Timer base timer control register (TBTC) 15 14  () () 13  () () 12 TBIE (R/W) (0) 11 TBOF (R/W) (0) 10 TBR (W) (1) 9 TBC1 (R/W) (0) 8 TBC0 (R/W) (0) 0000A9H Reserved (R/W) (1) (2) Block diagram To PPG timer Time-base timer counter Dividing HCLK by 2 × 21 × 22 To watchdog timer × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF OF OF Power-on reset Stop mode start Hold status start CKSCR : MCS = 0*1 CKSCR : SCS = 0→1*2 Counter clear control circuit To clock controller Oscillation stabilizing Wait time selector Interval timer selector TBOF set TBOF clear Time-base timer control register (TBTC) RESV Time-base timer interrupt signal  OF HCLK *1 *2 : Unused : Overflow : Oscillation clock : The machine clock is switched from main/sub clock to PLL clock. : The machine clock is switched from sub clock to main clock.   TBIE TBOF TBR TBC1 TBC0 54 MB90800 Series 14. Clock The clock generator controls operation of the internal clock which is the operation clock for the CPU and peripheral devices. This internal clock is referred to as machine clock and its one cycle as machine cycle. In addition, the clock generated by original oscillation is referred to as oscillation clock and that by internal PLL oscillation as PLL clock. (1) Register list Clock selection register (CKSCR) 15 14 MCM (R) (1) 13 WS1 (R/W) (1) 12 WS0 (R/W) (1) 11 SCS (R/W) (1) 10 MCS (R/W) (1) 9 CS1 (R/W) (0) 8 CS0 ( R/W ) (0) 0000A1H SCM (R) (1) Initial Value 55 MB90800 Series (2) Block diagram Standby control circuit Low power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Pin High-Z control circuit Pin High-Z control RST Pin CPU intermittent operation selector Internal reset generation circuit Internal reset Intermittent cycle selection CPU clock CPU clock control circuit Stop, sleep signal Stop signal Release interrupting Standby control circuit Machine clock Clock generation block Peripheral clock control circuit Peripheral clock Oscillation stabilization wait Clock selector 2 Dividing SCLK by 4 2 Oscillation stabilization wait time selector PLL multiplying circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Sub clock generation circuit X0A X1A Clock selection register (CKSCR) System clock generation circuit Pin Pin X0 X1 Dividing by 2 Dividing by 1024 Dividing by 2 Dividing by 4 Dividing by 4 Dividing by 4 Dividing by 2 HCLK MCLK Pin Pin Time-base timer To watchdog timer HCLK : Oscillation clock MCLK : Main clock SCLK : Sub clock 56 MB90800 Series (3) Clock supply map Clock generation circuit Timer clock divider X0 X1 Oscillation circuit Watch timer Watchdog timer Internal resources X0A X1A Oscillation circuit Selector LCD controller 16-Bit Reload Timer 8/10-bit A/D converter Serial I/O Free-run timer Input capture Time-base timer 1 2 3 4 PLL multiplying circuit PCLK 2 division circuit CPU (F2MC-16LX) Selector HCLK MCLK ROM/RAM (memory) SCLK 2 division circuit HCLK MCLK PCLK SCLK : Oscillation clock frequency : Main clock frequency : PLL clock frequency : Sub clock frequency 57 MB90800 Series 15. Low power consumption mode The MB90800 Series have the following CPU operation modes by selecting the operation clock and operating the control of the clock. • Clock mode (PLL clock mode, main clock mode and sub clock mode) • CPU intermittent operation mode (PLL clock intermittent operation mode, main clock intermittent operation mode and subclock intermittent operation mode) • Standby mode (Sleep mode, time base timer mode, stop mode and watch mode) (1) Register list Low power consumption mode control register (LPMCR) 7 6 SLP (W) (0) 5 SPL (R/W) (0) 4 RST (W) (1) 3 TMD (R/W) (1) 2 CG1 (R/W) (0) 1 CG0 (R/W) (0) 0 Reserved 0000A0H STP (W) (0) (R/W) (0) Initial Value 58 MB90800 Series (2) Block diagram Standby control circuit Low power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Pin High-Z control circuit RST Pin High-Z control Internal reset Pin CPU intermittent operation selector Internal reset generation circuit Intermittent cycle selection CPU clock control circuit CPU clock Release of interrupt Standby control circuit Stop, sleep signal Stop signal Peripheral clock control Machine clock Clock generation block Clock selector 2 Dividing by 4 Peripheral clock Release of oscillation stabilization wait SCLK 2 Oscillation stabilization wait time selector Sub clock generation circuit X0A X1A PLL multiplying circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR) System clock generation circuit Dividing by 2 Pin Pin X0 X1 Dividing by 1024 Dividing by 2 Dividing by 4 Dividing by 4 Dividing by 4 Dividing by 2 HCLK MCLK Pin Pin Time-base timer To watchdog timer HCLK MCLK SCLK : Oscillation clock : Main clock : Sub clock 59 MB90800 Series (3) Figure of status transition External reset, watchdog timer reset, software reset, Power supply Power-on reset End of oscillation stabilization wait MCS = 0 Main clock mode Reset SCS = 0 SCS = 1 PLL clock mode SCS = 0 SCS = 1 MCS = 1 SLP = 1 Sub clock mode SLP = 1 SLP = 1 Interrupt Interrupt Interrupt Main sleep mode TMD = 0 PLL sleep mode TMD = 0 Sub sleep mode TMD = 0 Interrupt Interrupt Interrupt Timebase timer mode STP = 1 Timebase timer mode STP = 1 Watch mode STP = 1 Main stop mode PLL stop mode Sub stop mode Interrupt End of oscillation stabilization wait Interrupt End of oscillation stabilization wait Interrupt End of oscillation stabilization wait Main clock Oscillation stabilization wait Main clock Oscillation stabilization wait Sub clock Oscillation stabilization wait 60 MB90800 Series 16. Timer clock output The timer clock output circuit divides the oscillation clock by the time-base timer and generates and outputs the set division clock. Selectable from 32/64/128/256 division of the oscillation clock. The timer clock output circuit is inactive in reset or stop mode. Normally, it is active in run, sleep, or pseudotimer mode. Pseudo clock PLL_Run Operation status Main_Run Sleep STOP × Reset × Note : When the time-base timer is cleared while using the timer clock output circuit, the clock is not correctly output. For detail of the timebase timer’s clear condition, see the section of timebase timer in Hardware Manual. (1) Register list bit Address : 0000AFH 15  14  13  12  11  10 TEN R/W 9 TS1 R/W 8 TS0 R/W Initial Value XXXXX000B - : Unused (2) Block diagram Timer clock selection circuit Selector Timer clock output X0 X1 Oscillation circuit Time-base timer Dividing by 2 61 MB90800 Series 17. ROM mirrorring function selection module ROM mirrorring function selection module can select that FF bank where ROM is located look into 00 bank among the settings of the register. (1) Register list bit Address : 00006FH 15  14  13  12  11  10  9 8 MI R/W ― Initial Value XXXXXXX1B - : Unused (2) Block diagram F2MC-16LX bus ROM mirroring function selection Address area Address FF bank 00 bank Data ROM Note : Do not access to this register in the middle of the operation of the address 008000H to 00FFFFH. 62 MB90800 Series 18. Interrupt controller Interrupt control register is in the interrupt controller. The register corresponds to all I/O of interrupt function. The register has following functions; • Setting of Interrupt level at correspondent peripheral circuit. (1) Register list (at writing) Interrupt control register Address : ICR01 ICR03 ICR05 ICR07 ICR09 ICR11 ICR13 ICR15 0000B1H 0000B3H 0000B5H 0000B7H 0000B9H 0000BBH 0000BDH 0000BFH Read/Write → Initial Value → Bit 15 ICS3 14 ICS2 13 ICS1 12 ICS0 11 ISE 10 IL2 IL1 9 IL0 8 ICR01, 03, 05, 07, 09, 11, 13, 15 W (0) W (0) W (0) W (0) R/W (0) R/W (1) R/W (1) R/W (1) Interrupt control register Address : ICR00 ICR02 ICR04 ICR06 ICR08 ICR10 ICR12 ICR14 0000B0H 0000B2H 0000B4H 0000B6H 0000B8H 0000BAH 0000BCH 0000BEH Read/Write → Initial Value → Bit 7 ICS3 6 ICS2 5 ICS1 4 ICS0 3 ISE IL2 2 IL1 1 IL0 0 ICR00, 02, 04, 06, 08, 10, 12, 14 W (0) W (0) W (0) W (0) R/W (0) R/W (1) R/W (1) R/W (1) 63 MB90800 Series (2)Register list (at reading) Interrupt control register Address : ICR01 ICR03 ICR05 ICR07 ICR09 ICR11 ICR13 ICR15 0000B1H 0000B3H Bit 15 0000B5H 0000B7H  0000B9H 0000BBH 0000BDH 0000BFH Read/Write →  () Initial Value → 14  13 S1 12 S0 11 ISE 10 IL2 IL1 9 IL0 8 ICR01, 03, 05, 07, 09, 11, 13, 15  () R (0) R (0) R/W (0) R/W (1) R/W (1) R/W (1) Interrupt control register Address : ICR00 ICR02 ICR04 ICR06 ICR08 ICR10 ICR12 ICR14 0000B0H 0000B2H 0000B4H 0000B6H 0000B8H 0000BAH 0000BCH 0000BEH Read/Write → Initial Value → Bit  7  6 S1 5 S0 4 3 ISE IL2 2 IL1 1 IL0 0 ICR00, 02, 04, 06, 08, 10, 12, 14  ()  () R (0) R (0) R/W (0) R/W (1) R/W (1) R/W (1) Note : Do not access using the read modify write instruction because it causes a malfunction. 64 MB90800 Series (3) Block diagram 3 IL2 IL1 IL0 3 32 Interrupt request (Peripheral resources) F2MC-16LX bus Judging the priority of interrupt 3 (CPU) Interrupt level 65 MB90800 Series 19. LCD controller/driver The LCD controller/driver contains 24 × 8-bit display data memory and controls the LCD display with four common output lines and 48 segment output lines. Three duty outputs can be selected to directly drive the LCD panel (liquid crystal display). • Contains an LCD driving voltage split resistor. Moreover, the external division resistance can be connected. • A maximum of four common output lines (COM0 to COM3) and 48 segment output lines (SEG0 to SEG47) are available. • Contains 24-byte display data memory (display RAM). • For the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting). • The LCD can directly be driven. Bias 1/2 bias 1/3 bias ：Recommended mode × ：Disable (1) Register list ・LCR (LCD control register) 1/2 duty × 1/3 duty × 1/4 duty × LCD control register (higher) (LCRH) 15 SS4 14 VS0 (R/W) (0) 13 CS1 (R/W) (0) 12 CS0 (R/W) (0) 11 SS3 (R/W) (0) 10 SS2 (R/W) (0) 9 SS1 (R/W) (0) 8 SS0 (R/W) (0) 00005DH (R/W) (0) Read/Write Initial Value LCD control register (lower) (LCRL) 7 CSS 6 LCEN (R/W) (0) 5 VSEL (R/W) (0) 4 BK (R/W) (1) 3 MS1 (R/W) (0) 2 MS0 (R/W) (0) 1 FP1 (R/W) (0) 0 FP0 (R/W) (0) 00005CH (R/W) (0) Read/Write Initial Value ・LCDC range register (LCRR) 7 6 5 SE4 (R/W) (0) 4 SE3 (R/W) (0) 3 SE2 (R/W) (0) 2 SE1 (R/W) (0) 1 SE0 (R/W) (0) 0 LCR (R/W) (0) Reserved Reserved 00005EH (R/W) (0) (R/W) (0) Read/Write Initial Value 66 MB90800 Series (2) Block diagram LCDC range register (LCRR) V0 V1 V2 V3 LCD Control register (LCRL) Division resistor Main Clock Prescaler 4 Timing controller Circuit of making to exchange Common driver Internal data bus Sub clock (32 kHz) COM0 COM1 COM2 COM3 48 Display RAM 24 × 8 bit Segment driver SEG00 SEG01 SEG02 SEG03 SEG04 ∼ SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 LCD Control register (LCRH) Controller Driver 67 MB90800 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage Symbol VCC AVCC VI VO IOL11 “L” level maximum output current IOL12 IOLAV1 “L” level average output current IOLAV2 “L” level maximum total output current “L” level average total output current ΣIOL ΣIOLAV IOH11 “H” level maximum output current IOH12 “H” level average output current “H” level maximum total output current “H” level average total output current Power consumption Operating temperature Storage temperature IOHAV ΣIOH ΣIOHAV Pd TA Tstg      − 40 − 55 − 12 −3 − 120 − 60 351 + 85 + 150 mA mA mA mA mW °C °C *5     15 120 60 − 10 mA mA mA mA *5 Other than P74, P75, P40 to P47*3 P40 to P47 (Heavy-current output port) *3 *4   30 3 mA mA Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 Input voltage Output voltage VSS − 0.3 VSS − 0.3  Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 6.0 VSS + 4.0 10 Unit V V V V V mA VCC ≥ AVCC*1 *2 N-ch O.D (5 V withstand voltageI/O) *2 Other than P74, P75, P40 to P47*3 P74, P75, P40 to P47 (Heavy-current output port) *3 Other than P74, P75, P40 to P47*4 P74, P75, P40 to P47 (Heavy-current output port) *4 Remarks The Absolute Maximum Ratings is based on VSS = AVSS = 0.0 V. *1 : AVCC should not be exceeding VCC at power-on etc. *2 : VI, VO, should not exceed Vcc + 0.3 V. *3 : A peak value of an applicable one pin is specified as a maximum output current. *4 : An average current value of an applicable one pin within 100 ms is specified as an average output current. (Average value is found by multiplying operating current by operating rate.) *5 : An average current value of all pins within 100 ms is specified as an average total output current. (Average value is found by multiplying operating current by operating rate.) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 68 MB90800 Series 2. Recommended Operating Conditions Parameter Power supply voltage Symbol VCC VIH “H” level input voltage VIHS VIHM VIL “L” level input voltage Operating temperature VILS VILM TA Value Min 2.7 1.8 0.7 VCC 0.8 VCC VCC − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 40 Max 3.6 3.6 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 + 85 Unit V V V V V V V V °C Remarks At normal operating Stop operation state maintenance CMOS input pin CMOS hysteresis input pin (Resisting pressure of 5 V is VCC = 5.0 V) MD pin input CMOS input pin CMOS hysteresis input pin MD pin input The Recommended Operating Conditions is based on VSS = AVSS = 0.0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 69 MB90800 Series 3. DC Characteristics Symbol (VCC = AVCC = 3.3 V ± 0.3 V, TA = − 40 to + 85 °C) Pin name Output pins other than P40 to P47, P74, P75 P40 to P47 Output pins other than P40 to P47, P74, P75 P40 to P47 P74, P75 P74, P75 All output pin RST Conditions Value Min VCC − 0.5 Typ  Max Unit Remarks Parameter “H” level output voltage VOH IOH = − 4.0 mA Vcc V VOH1 IOH = − 8.0 mA VCC − 0.5  Vcc V Heavy-current output port VOL “L” level output voltage VOL1 VOL2 Open-drain output application voltage Input leak current Pull-up resistor Pull-down resistor Open drain output current VD1 IIL RUP IOL = 4.0 mA Vss  Vss + 0.4 V IOL = 15.0 mA IOL = 15.0 mA  VCC = 3.3 V, VSS < VI < VCC Vcc = 3.3 V, TA = + 25 °C Vcc = 3.3 V, TA = + 25 °C  Vss  Vss − 0.3 − 10 25 25   0.5   50 50 0.1 Vss + 0.6 Vss + 0.8 Vss + 5.5 10 100 100 10 V V V µA kΩ kΩ µA Heavy-current output port Open-drain pin RDOWN MD2 Ileak P74, P75 Except FLASH products The DC Characteristics is based on VSS = AVSS = 0.0 V. (Continued) 70 MB90800 Series (VCC = AVCC = 3.3 V ± 0.3 V, TA = − 40 to + 85 °C) Parameter Symbol Pin name Conditions VCC = 3.3 V, Internal frequency 25 MHz At normal operating ICC VCC = 3.3 V, Internal frequency 25 MHz At Flash writing VCC = 3.3 V, Internal frequency 25 MHz At Flash erasing ICCS VCC = 3.3 V, Internal frequency 25 MHz at sleep mode VCC = 3.3 V, Internal frequency 3 MHz at timer mode VCC = 3.3 V, Internal frequency 8 kHz at subclock operation, (TA = + 25 °C) VCC = 3.3 V, Internal frequency 8 kHz at subclock sleep operation, (TA = + 25 °C) VCC = 3.3 V, Internal frequency 8 kHz at watch mode (TA = + 25 °C) At Stop mode, (TA = + 25 °C) VCC − V3 VCC − V3 LCD division resistance RLCD V0 − V1, V1 − V2, V2 − V3 V0 − V1, V1 − V2, V2 − V3 COM0 to COM0 to COM3 RVCOM COM3 output impedance SEG00 to SEG47 SEG00 to RVSEG output impedance SEG47 At LCR = 0 setting At LCR = 1 setting At LCR = 0 setting Value Min  Typ 48 Max 60 Unit Remarks mA  60 75 mA FLASH products FLASH products  60 75 mA  22.5 30 mA Power supply current ICCTS VCC    0.75 7 mA µA mA MASK products FLASH products 15 0.5 140 0.9 ICCL ICCLS  23 40 µA ICCT  1.8 40 µA ICCH  100 12.5 50 0.8 200 25 100 40 400 50 200 µA kΩ * At LCR = 1 setting 6.25  12.5   25 kΩ kΩ 2.5 15 V1 to V3 = 3.3 V  The DC Characteristics is based on VSS = AVSS = 0.0 V. (Continued) 71 MB90800 Series (Continued) (VCC = AVCC = 3.3 V ± 0.3 V, TA = − 40 to + 85 °C) Parameter Symbol Pin name Conditions Value Min −5 Typ  Max 5 Unit Remarks V0 to V3, LCD leak current ILCDC COM0 to COM3, SEG00 to SEG47 The DC Characteristics is based on VSS = AVSS = 0.0 V.  µA * : LCD internal diveded resistor can be select two type resistor by LCR (internal diveded resistor selecting bit) of LCRR (LCDC range register) . 72 MB90800 Series 4. AC Characteristics (1) Clock timing Parameter Sym CondiPin name bol tions fCH X0, X1 (VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C) Value Min 3 3 Clock frequency 4.5 fCH X0, X1 4 4 4 fCL Clock cycle time tHCYL PWH PWL PWLH PWLL tcr tcf fCP fCP1 tCP tCP1 X0A, X1A X0, X1   40  5   1.5  40  Typ       32.768  30.5  15.2   8.192  122.1 Max 16 25 25 12.5 8.33 6.25  333    5 25  666  kHz ns µs ns µs ns MHz Set Duty ratio 50% ± 3% Set duty ratio at 30% to 70% as a guideline. At external clock When main clock is used When main clock is used When sub clock is used Unit MHz Remarks External crystal oscillation At external clock* Multiply by 1 MHz Multiply by 2 Multiply by 3 Multiply by 4 tLCYL X0A, X1A X0 X0A X0     Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time kHz When sub clock is used ns µs The Clock timing is based on VSS = AVSS = 0.0 V. * : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned in “Base oscillator frequency vs. Internal operating clock frequency”. • X0, X1 clock timing tC 0.8 VCC 0.2 VCC PWH tcf PWL tcr • X0A, X1A clock timing tCL 0.8 VCC 0.2 VCC PWLH tcf PWLL tcr 73 MB90800 Series PLL operation guarantee range Relation between internal operation clock frequency and power supply voltage PLL operation guarantee range 3.6 Power voltage V CC (V) 3.0 2.7 Normal operation assurance range 1.5 4.5 16 25 Internal clock fCP (MHz) Relation between oscillation frequency and internal operating clock frequency 25 Multiply by 4 Multiply by 3 Multiply by 2 Multiply by 1 Internal clock fCP (MHz) 16 12 8 6 4.5 4 External clock 3 4.5 4 6 8 12 16 25 Original oscillation clock fCH (MHz) Rating values of alternating current is defined by the measurement reference voltage values shown below : • Input signal waveform Hysteresis input pin 0.8 VCC 0.2 VCC • Output signal waveform Output pin 2.4 V 0.8 V 74 MB90800 Series (2) Reset input timing Symbol Conditions (VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C) Pin name Value Min Max  Unit Remarks At normal operating, at time base timer mode, at main leep mode, at PLL sleep mode At stop mode, at sub clock mode, at sub sleep mode, at watch mode Parameter 500 Reset input time tRSTL RST  Oscillation time of oscillator*+ 500 ns The Reset input timing is based on VSS = AVSS = 0.0 V. ns  µs * : Oscillation time of oscillator is time until oscillation reaches 90% of amplitude. It takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a FAR/ceramic oscillator, and 0 milliseconds on an external clock. • In normal operating, time base timer mode, main sleep mode and PLL sleep mode tRSTL RST 0.2 VCC 0.2 VCC • In stop mode, sub clock mode, sub sleep mode and watch mode tRSTL RST 0.2 VCC 0.2 VCC X0 90% of amplitude Internal operating clock Oscillation time of oscillator 500 ns Wait time for stabilization oscillator Execute instruction Internal reset 75 MB90800 Series (3) Power-on reset Conditions  (VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C) Symbol Pin name tR tOFF VCC VCC Value Min  1 Max 30  Unit ms ms Remarks At normal operating For repeated operation Parameter Power supply rising time Power supply shutdown time The Power-on reset is based on VSS = AVSS = 0.0 V. Notes : • VCC should be set under 0.2 V before power-on rising up. • These value are for power-on reset. • In the device, there are internal registers which is initialized only by a power-on reset. If these initialization is executing, power-on prosedure must be obeyed by these value. tR VCC 2.7 V 0.2 V 0.2 V tOFF 0.2 V Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, raise the power smoothly by suppressing variation of voltages as shown below. When raising the power, do not use PLL clock. However, if voltage drop is 1mV/s or less, use of PLL clock is allowed during operation. VCC Limiting the slope of rising within 50 mV/ms is recommended. 2.7 ± 0.3 V VSS RAM data hold 76 MB90800 Series (4) Serial I/O Sym bol (VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C) Pin name Conditions Value Min 8 tCP −80 100 60 4 tCP 4 tCP  60 60 Max  80     150   Unit Remarks ns ns ns ns ns ns ns ns ns Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock H pulse width Serial clock L pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time tSCYC SC0 to SC3 tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX SC0 to SC3 SO0 to SO3 Internal shift clock mode output pin : CL = 80 pF + 1TTL SC0 to SC3 SI0 to SI3 SC0 to SC3 SC0 to SC3 External shift clock SO0 to SO3 mode output pin : CL = 80 pF + 1TTL SC0 to SC3 SI0 to SI3 The Serial I/O is based on VSS = AVSS = 0.0 V. Notes : • AC rating in CLK synchronous mode. • C L is a load capacitance value on pins for testing. • tCP is machine cycle frequency (ns) . • Internal shift clock mode SC 0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V SO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SI 0.2 VCC • External shift clock mode SC 0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC SO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SI 0.2 VCC 77 MB90800 Series (5) Timer input timing (VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C) Symbol tTIWH tTIWL Pin name TIN0 to TIN2 IC0 to IC1 Conditions  Value Min 4 tCP Max  Unit ns Remarks Parameter Input pulse width The Timer input timing is based on VSS = AVSS = 0.0 V. • Timer Input Timing 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC TINx ICx tTIWH tTIWL (6) Timer output timing Symbol tTO Conditions  (VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C) Pin name TOT0 to TOT2, PPG0 to PPG1, OCU0 to OCU1 Value Min 30 Max  Unit Remarks Parameter CLK ↑ → TOUT change time ns The Timer output timing is based on VSS = AVSS = 0.0 V. • Timer Output Timing CLK 2.4 V tTO TOTx PPGx OCUx 2.4 V 0.8 V (7) Trigger Input Timing Conditions  (VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C) Symbol tTRGH tTRGL Pin name INT0 to INT3 Value Min 5 tCP 1 Max   Unit ns µs Remarks At normal operating In Stop mode Parameter Input pulse width The Trigger Input Timing is based on VSS = AVSS = 0.0 V. • Trigger Input Timing 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC INTx tTRGH tTRGL 78 MB90800 Series (8) I2C Timing (AVCC = VCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C) Parameter SCL clock frequency Hold time (repeated) START condition SDA ↓ → SCL ↓ “L” width of the SCL clock “H” width of the SCL clock Set-up time for a repeated START condition SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT When power supply voltage of external pull-up resistor is 5.0 V R = 1.0 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistor is 3.6 V R = 1.0 kΩ, C = 50 pF*2 Conditions Standardmode Unit Min Max 0 4.0 4.7 4.0 4.7 0 When power supply voltage of external pull-up resistor is 5.0 V fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2 250 When power supply voltage of external pull-up resistor is 3.6 V fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistor is 5.0 V fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2 200 When power supply voltage of external pull-up resistor is 3.6 V fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistor is 5.0 V R = 1.0 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistor is 3.6 V R = 1.0 kΩ, C = 50 pF*2 4.0 100     3.45 *3 kHz µs µs µs µs µs  ns Data set-up time SDA ↓ ↑ → SCL ↑ tSUDAT  ns Set-up time for STOP condition SCL ↑ → SDA ↑ Bus free time between a STOP and START condition The I2C trriger is based on AVSS = VSS = 0.0 V. tSUSTO  µs tBUS 4.7  µs *1 : fCP is internal operation clock frequency. Refer to “ (1) Clock timing”. *2 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. SDA tBUS tLOW SCL tSUDAT tHDSTA tHDSTA tHDDAT tHIGH tSUSTA tSUSTO 79 MB90800 Series 5. Electrical Characteristics for the A/D Converter Parameter Resolution Total error Nonlinear error Differential linear error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supplying current Interchannel disparity Symbol     VOT VFST   IAIN VAIN  IA IAH IR IRH  Pin name     AN0 to AN11 (VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C) Value Typ     Max 10 ± 3.0 ± 2.5 ± 1.9 Unit bit LSB LSB LSB mV 1 LSB = AVcc/1024 mV µs µs µA V V mA µA µA µA LSB Remarks Min     AVSS − 1.5 AVss + 0.5 AVSS + 2.5 LSB LSB LSB AVcc − 3.5 AVcc − 1.5 AVcc + 0.5 AN0 to AN11 LSB LSB LSB   AN0 to AN11 AN0 to AN11 AVcc AVcc AVcc AVcc AVcc AN0 to AN11 8.64*1 2  0 3.0           1.4  94     10 AVcc AVcc 3.5 5* 5* 4 2 150 2 The Electrical characteristics for the A/D converter is based on VSS = AVSS = 0.0 V. *1 : At operating, main clock 25 MHz. *2 : If A/D converter is not operating, a current when CPU is stopped is applicable (at Vcc − CPU = AVcc = 3.3 V) 80 MB90800 Series • A/D converter with sample and hold circuit. If the extrernal impedance is too high to keep sufficient sampling time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Analog input circuit model R Analog input C Comparator During sampling : ON R MB90803 MB90F804 MB90V800 1.9 kΩ (Max) 1.9 kΩ (Max) 1.9 kΩ (Max) C 32.3 pF (Max) 25.0 pF (Max) 32.3 pF (Max) Note : The values are reference values. • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. [External impedance = 0 kΩ to 100 kΩ] 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 MB90803/ MB90V800 MB90F804 20 [External impedance = 0 kΩ to 20 kΩ] MB90803/ MB90V800 MB90F804 → External impedance [kΩ] → External impedance [kΩ] 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 → Minimum sampling time [µs] → Minimum sampling time [µs] The relationship between external impedance and minimum sampling time • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • As | AVCC | becomes smaller, values of relative errors grow larger. 81 MB90800 Series 6. Definition of A/D Converter Terms Resolution Analog variation that is recognized by an A/D converter. The 10-bit can resolve analog voltage into 210 = 1024. Total error This shows the difference between the actual voltage and the ideal value and means a total of error because of offset error, gain error, non-linearity error and noise. Linearity error Deviation between a line across zero-transition line (00 0000 0000↔00 0000 0001) and full-scale transition line (11 1111 1110↔11 1111 1111) and actual conversion characteristics. Differential linear error Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Total error 3FF 3FE 3FD 0.5 LSB Actual conversion characteristic {1 LSB × (N − 1) + 0.5 LSB} Digital output 004 003 002 001 0.5 LSB AVSS (AVRL) AVCC (AVRH) VNT (measurement value) Actual conversion characteristics Ideal characteristics Analog input Total error of digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB} [LSB] 1 LSB 1LSB(Ideal value) = AVCC − AVSS [V] 1024 VOT(Ideal value) = AVSS + 0.5 LSB [V] VFST(Ideal value) = AVCC − 1.5 LSB [V] VNT: A voltage at which digital output transitions from (N-1) to N. (Continued) 82 MB90800 Series (Continued) Linearity error 3FF 3FE 3FD Actual conversion characteristics {1 LSB ´ (N - 1) + VOT} VFST (measurement value) Differential linear error Actual conversion characteristic N+1 Ideal characteristics Digital output Digital output N VNT 004 003 002 001 Ideal characteristics VOT (actual measurement value) AVSS (AVRL) AVCC (AVRH) (measurement value) Actual conversion characteristics N−1 (measurement value) V(N + 1)T (measurement value) N−2 VNT Actual conversion characteristics AVSS (AVRL) AVCC (AVRH) Analog input Analog input VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N + 1) T − VNT} 1 LSB VFST − VOT 1022 [V] − 1LSB Linear error in digital output N = Differential linear error in digital output N = 1 LSB = [LSB] [LSB] VOT : Voltage at which digital output transits from 000H to 001H. VFST : Voltage at which digital output transits from 3FEH to 3FFH. 83 MB90800 Series 7. FLASH MEMORY Value Min  TA = + 25 °C Vcc = 3.0 V    Average TA = + 85 °C 10,000 20 Typ 1 9 16   Max 15  3,600   Parameter Sector erase time Chip erase time Word (16 bit width) programming time Program/erase cycle Flash data retension time Conditions Unit s µs s cycle Yearss * Remarks Excludes 00 H programming prior to erasure. Excludes 00 H programming prior to erasure. Except for the over head time of the system. * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measuremunts into normalized value at + 85 °C). 84 MB90800 Series s ORDERING INFORMATION Part number MB90F804-101PF-G MB90F804-201PF-G MB90803PF MB90803SPF Package 100-pin plastic QFP (FPT-100P-M06) Remarks 85 MB90800 Series s PACKAGE DIMENSION 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 86 MB90800 Series MEMO 87 MB90800 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94088-3470, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fmk.fujitsu.com/ Preliminary 2004.07.22 © FUJITSU LIMITED Printed in Japan