MB90M405_05

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13718-2E 16-Bit Original Microcontroller CMOS F2MC-16LX MB90M405 Series Built in FL Display Controller Circuit MB90MF408/M408/M407/MF408A/ MB90M408A/M407A ■ DESCRIPTION The MB90M405 series is a general-purpose 16-bit microcontroller, developed for applications requiring fluorescent display tube panel control. Each microcontroller is equipped with 60 highly voltage-resistant output pins, needed for fluorescent display control. The command structure inherits the same AT architecture as the F2MC-8L and F2MC-16L, in order to provide enhanced C-language support, improved extended/signed multiplication/division instructions in addressing mode, and enhanced bit processing. In addition, an onboard 32-bit accumulator allows long word processing. Note : F2MC stands for FUJITSU Flexible MicroController, and is a registered trademark of Fujitsu Limited. ■ FEATURES • Clock • Internal PLL clock multiplication circuit • Oscillation clock 1/2 main oscillation clock 1 × to 4 × PLL oscillation clock (2 MHz to 16 MHz at 4 MHz oscillation) , can be set from machine clock • Minimum instruction execution time : 62.5 ns (operating at 4 MHz oscillation, 4 × PLL clock, VCC = 3 V) • Oscillation clock can generate 1/32, 1/64, 1/128, and 1/256 external clock outputs. • Maximum memory space : 16 Mbytes • Can also use 24-bit addressing (Continued) ■ PACKAGE 100-pin plastic QFP (FPT-100P-M06) MB90M405 Series • Command structure optimized for controller applications • Able to handle following data types : bit, byte, word, and long word • 23 types of addressing mode • High code efficiency (compiler) • Enhanced calculation precision using a 32-bit accumulator • Enhanced signed multiplication and division instructions and RETI instructions • Command structure supports C language/multitasking • Employs system stack pointers • Instruction set had symmetry and barrel shift instruction functions • Program patch functions (2-address pointers) • Improved execution speed • 4-byte built-in instruction queue allows instructions to be read ahead of time, speeding up execution. • Interrupt function • 8 programmable priority level settings • Incorporates powerful 32-factor interrupt function • Data transfer function • Extended intelligent I/O service function : allows up to 16 channels to be set • Low-power consumption modes • Sleep mode (CPU operation clock stops) • Timebase timer mode (oscillation clock and timebase timer operate) • Stop mode (oscillation clock stops) • CPU intermittent operation mode (CPU operates intermittently at the specified intervals) • Package • QFP-100 (FPT-100P-M06 : 0.65 mm pin pitch) • Process • CMOS technology • I/O ports : Maximum 26 (26 ports, also used for internal resources) • Timebase timer : 1 channel • Watchdog timer : 1 channel • 16-bit reload timer : 3 channels • 16-bit freerun timers : 1 channel • Output compare : 1 channel • If the count value of the 16-bit freerun timer and compare register setting match, an interrupt request can be output • Input capture : 2 channels • By detecting a valid edge in a signal input from the external input pin, it is possible to read the 16-bit freerun timer count into the input capture data register, and output an interrupt request. • Serial I/O : 2 channels • UART : 2 channels • Includes full-duplex double buffer (8 bits length) • Can be set to clock-asynchronous transfer or clock-synchronized serial transfer (I/O extended serial) • DTP/external interrupt (4 channels) • Extended intelligent I/O service can be started via external input • It is possible to generate an internal hardware interrupt via external input • Delayed interrupt generation module • It is possible to output task switching interrupt requests • 8/10 bit A/D converter (16 channels) • Choice of 8 and 10-bit resolution selectable (Continued) 2 MB90M405 Series (Continued) • FL control circuit • FL driver control enabled (up to 32 digits and up to 60 segments with automatic display control) - Any number between 1 and 32 digits can be set - Dimmer setting possible • LED driver control enabled (up to 16 with automatic display control) - Up to 16 automatic display control possible at 1/2 duty • Time clock output circuit • Can be set to 1/32, 1/64, 1/128, or 1/256 of oscillation clock 3 MB90M405 Series ■ PRODUCT LINEUP Part Number Classification ROM size RAM size Emulator power supply* 3 MB90MF408*1 MB90MF408A*2 Internal flash memory type MB90M408*1 MB90M408A*2 MB90M407*1 MB90M407A*2 MB90MV405 Evaluation None onboard 4 Kbytes Included Internal mask ROM type 96 Kbytes 4 Kbytes ⎯ 128 Kbytes 4 Kbytes Number of basic instructions Minimum instruction execution time Addressing modes Program patch function Maximum memory space CPU functions : 351 : 62.5 ns/4 MHz (with x4 multiplier) : 23 : 2 address pointers : 16 Mbytes Ports FL-control circuit 26 (CMOS) I/O ports (26 ports, also used for resources) 60 FL outputs possible (during LED control, 43 FL output and 17 LED control) FL and LED driver control enabled During FL driver control, both digit and segment dimmer setting possible Includes full-duplex double buffer Clock-synchronized/asynchronous settings available Can also be used as clock synchronized extended I/O serial Also equipped with dedicated baud rate generator Serial I/O: 2 channels, UART: 2 channels 16-bit reload timer operation (can be set to toggle or one-shot output) Event count function can be set 3 channels built in One 16-bit output comparison channel (for clearing freerun timer) Two 16-bit input capture channels 16 channels (input multiplex) Choice of 8 and 10-bit resolution available Conversion time : 6.125 µs (when machine clock operating at 16 MHz) Possible to divide external input oscillation clock and output externally Programmable divisions : 32/64/128/256 One I2C interface channel built in 4 independent channels (also used with A/D input) Interrupt factors : can be set to “L”→“H” edge/“H”→“L” edge/“L” level/“H” level Sleep mode/timebase timer mode, stop mode, and intermittent CPU mode CMOS QFP-100 (0.65 mm pitch) 3.3 V ± 0.3 V (16 MHz : 4 MHz 4x) PGA256 Serial I/O (UART) 16-bit reload timers 16-bit I/O timer 8/10 bit A/D converter Time clock output circuit I2C*4 Bus DTP/external interrupt Low-power modes Process Package Operating voltage *1 : All FL-output pins (FIP0 to FIP59) have pull downs *2 : Some FL-output pins (FIP0 to FIP16) do not have pull downs. The remaining FL-output pins (FIP17 to FIP59) have pull downs. *3 : Setting of DIP Switch (S2) when using emulation pod (MB2145-507) . Refer to “2.7 Dedicated Emulator Power Supply” in the “MB2145-507 Hardware Manual” for details. *4 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 4 MB90M405 Series ■ PIN ASSIGNMENTS (TOP VIEW) FIP15/LED15 FIP14/LED14 FIP13/LED13 FIP12/LED12 FIP11/LED11 FIP10/LED10 FIP9/LED9 FIP8/LED8 FIP7/LED7 FIP6/LED6 FIP5/LED5 FIP4/LED4 FIP3/LED3 FIP2/LED2 FIP1/LED1 FIP0/LED0 VCC-CPU X1 X0 VSS-CPU 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 FIP16/LED16 FIP17 FIP18 FIP19 FIP20 FIP21 FIP22 FIP23 FIP24 FIP25 VSS-IO FIP26 FIP27 FIP28 FIP29 FIP30 FIP31 FIP32 FIP33 FIP34 FIP35 FIP36 VDD-FIP FIP37 FIP38 FIP39 FIP40 FIP41 FIP42 FIP43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB7/AN15/INT3 PB6/AN14/INT2 PB5/AN13/SO2/TO0 RST PB4/AN12/SC2/TIN0 PB3/AN11/SI2 PB2/AN10 PB1/AN9 PB0/AN8 PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0/TMCK AVSS AVCC P91/SCL/SC3 P90/SDA/SO3 P87/SO1 P86/SC1 P85/SI1 P84/SO0 P83/SC0 P82/SI0 P81/IC1/INT1 P80/IC0/INT0 MD2 FIP44 FIP45 FIP46 FIP47 FIP48 FIP49 FIP50 FIP51 FIP52 FIP53 FIP54 VSS-IO FIP55 FIP56 FIP57 FIP58 FIP59 VKK MD0 MD1 (FPT-100P-M06) 5 MB90M405 Series ■ PIN DESCRIPTIONS Pin No. QFP-100 82, 83 77 85 to 100 1 2 to 10 12 to 19 20 to 22 24 to 41 43 to 47 Pin Name X0, X1 RST FIP0 to FIP15 LED0 to LED15 FIP16 LED16 FIP17 to FIP33 C VKK Pull-down output Circuit Type A B State/ Function at Reset Oscillating Reset input Description Oscillation Input/Output pin When connected to external clock, please free pin X1 External reset input pin Set when FL driver authorized Set when LED driver authorized Set when FL driver authorized Set when LED driver authorized (If pull-down resistance Dedicated FL driver output pin is set) D I/O port Input capture ch 0 is external trigger input pin External interrupt input ch 0 is external factor input pin Accepted when bit EN0 set to enabled I/O port Input capture ch 1 is external trigger input pin External interrupt input ch 1 is external factor input pin Accepted when bit EN1 set to enabled I/O port Serial data input pin for serial I/O ch 0 During input operation by serial I/O ch 0, pin is used continuously, so do not use as a different pin I/O port Serial clock I/O pin for serial I/O ch 0 Effective when serial clock output for serial I/O ch 0 enabled I/O port Serial data output pin for serial I/O ch 0 Effective when serial data output for serial I/O ch 0 enabled I/O port Serial data input pin for serial I/O ch 1 During input operation by serial I/O ch 1, pin is used continuously, so do not use as a different pin (Continued) FIP34 to FIP59 P80 52 IC0 INT0 P81 53 IC1 INT1 P82 54 SI0 E P83 Port input (Hi-z) 55 SC0 P84 56 SO0 P85 57 SI1 6 MB90M405 Series Pin No. QFP-100 Pin Name P86 58 SC1 P87 59 SO1 P90 SDA 60 SO3 P91 State/ Circuit Function at Type Reset I/O port Description E Serial clock I/O pin for serial I/O ch 1 Effective when serial clock output for serial I/O ch 1 enabled I/O port Serial data output pin for serial I/O ch 1 Effective when serial data output for serial I/O ch 1 enabled I/O port (however, Nch open drain) Port input (Hi-z) I2C interface data I/O pin. This function is effective when I2C interface operation is enabled. While the I2C interface is operating, set the port to input (DDR9 : bit 8 = 0) . Serial data output pin for serial I/O ch 3 Effective when serial data output for serial I/O ch 3 enabled I/O port (however, Nch open drain) I2C interface clock I/O pin. This function is effective when I2C interface operation is enabled. While the I2C interface is operating, set the port to input (DDR9 : bit 9 = 0) . Serial clock I/O pin for serial I/O ch 3 Effective when serial clock output for serial I/O ch 3 enabled I/O port Ch 0 of A/D converter analog input pin Effective when analog input setting enabled (set with ADER) Time clock output pin. Effective when output enabled. Note that this is not effective when analog input enabled via ADER. I/O port Analog input Ch 1 to ch 10 of A/D converter analog input pin Effective when analog input setting enabled (set with ADER) I/O port Ch 11 of A/D converter analog input pin Effective when analog input setting enabled (set with ADER) Serial data input pin for serial I/O ch 2 During input operation by serial I/O ch 2, pin is used continuously, so do not use as a different pin (Continued) 7 G SCL 61 G SC3 PA0 AN0 64 TMCK PA1 to PB2 65 to 74 AN1 to AN10 PB3 AN11 75 SI2 F MB90M405 Series (Continued) Pin No. QFP-100 Pin Name PB4 AN12 76 SC2 Circuit Type State/ Function at Reset I/O port Description Ch 12 of A/D converter analog input pin Effective when analog input setting enabled (set with ADER) Serial clock I/O pin for serial I/O ch 2 Effective when serial clock output for serial I/O ch 2 enabled External clock input pin of reload timer ch 0 Effective when external clock input enabled (ADER is prioritized) I/O port Ch 13 of A/D converter analog input pin Effective when analog input setting enabled (set with ADER) Serial data output pin for serial I/O ch 2 Effective when serial data output for serial I/O ch 2 enabled External event output pin of reload timer ch 0 Effective when external event output enabled (ADER is prioritized) I/O port Ch 14 and ch 15 of A/D converter analog input pin Effective when analog input setting enabled (set with ADER) External interrupt input ch 2 and ch 3 are external factor input pins Accepted when bits EN2 and EN3 set to enabled H Power input ⎯ Vcc power input pin of analog macro Vss power input pin of analog macro Power pin of pull-down side during high voltage resistant output Input pin for specifying operating mode. Connect to VCC. Additionally, when flash boot program is being used, be sure to switch to VSS. B Mode pins Input pin for specifying operating mode. Connect to VCC. Input pin for specifying operating mode. Connect to VSS. Additionally, when flash boot program is being used, be sure to switch to VCC. I/O power (0 V : GND) input pin ⎯ Power input FIP power (3 V : VCC) input pin Control circuit power (0 V : GND) input pin Control circuit power (3 V : VCC) input pin TIN0 PB5 AN13 F 78 SO2 Analog input TO0 PB6, PB7 AN14, AN15 79, 80 INT2, INT3 62 63 48 AVCC AVSS VKK 49 50 51 11, 42 23 81 84 MD0 MD1 MD2 VSS−IO VDD−FIP VSS−CPU VCC−CPU 8 MB90M405 Series ■ I/O CIRCUITS Type Circuit Remarks • Oscillation circuit Oscillation return resistance = approx. 1 MΩ X1 Nch Pch Nch Pch Xout A X0 Standby control signal • Hysteresis input pin Built-in pull-up resistance (Rp) B Rp • Pch open drain output - High voltage resistance port output IOL = −23 mA Pch Pout C RKK VKK When used as normal port, connect a diode clamp or the like to prevent voltage VKK from being applied to the pin during “L” level output. (See “■ HANDLING DEVICES”) • Pch open drain output - High voltage resistance port output IOL = −12 mA Pch Pout D RKK VKK When used as normal port, connect a diode clamp or the like to prevent voltage VKK from being applied to the pin during "L" level output. (See "■ HANDLING DEVICES") • CMOS hysteresis I/O pin - CMOS output - CMOS hysteresis input (Equipped with function to block input during standby) IOL = 4 mA Pch Pout E Nch R Nout CMOS hysteresis input Standby control (Continued) 9 MB90M405 Series (Continued) Type Circuit Remarks • Analog/CMOS hysteresis I/O pin - CMOS output - CMOS hysteresis input (Equipped with function to block input during standby) - Analog input (When ADER-compatible bit is “1” analog input is enabled) IOL = 4 mA Pch Pout Nch Nout F R CMOS hysteresis input Standby control Analog input Nch Nout • Nch open drain output - CMOS hysteresis input (Equipped with function to block input during standby) Unlike the CMOS I/O pin, there is no Pch transistor. Therefore, when the device power is shut off, there will be no flow of current to the device power (VCC-IO/VCC-CPU) , even if external voltage is applied to the pin. • Analog power input protection circuit G R CMOS hysteresis input Standby control Pch H Nch IN 10 MB90M405 Series ■ HANDLING DEVICES This section contains important information on handling the device, regarding the following : • Do not exceed maximum rated voltage (to prevent latch-up) • Supply voltage stability • Power-on precautions • Treatment of unused pins • Treatment of A/D converter power supply pin • Notes on using external clock • Power supply pin • Sequence for applying power analog input of A/D converter • Output of high-voltage output pin (circuit types C & D) • Do not exceed maximum rated voltage (to prevent latch-up) • With a CMOS IC, if voltage above VCC or below VSS is applied to an output or input pin other than a medium/ high voltage resistance pin, or if voltage between VCC and VSS, but exceeding the rated voltage, is applied, a latch-up state could be generated. In the event of a latch-up, the power current will increase drastically, possibly destroying the chip due to overheating. For this reason, make sure not to exceed the maximum rating. • When applying or shutting off analog power, make sure that the analog power (AVCC) and analog input voltage do not exceed the digital power voltage (VCC) . • Supply voltage stability Even within the scope of operational protection for VCC power voltage, a sudden increase in power voltage could cause the unit to malfunction. For this reason, please stabilize the VCC power voltage. The standard for stabilizing voltage is a VCC ripple fluctuation (peak to peak value) of no more than 10% of standard VCC power voltage at commercial power frequencies (50 Hz to 60 Hz) , and an excess fluctuation rate of no more than 0.1 V/ms for instantaneous changes when switching power. • Power-on precautions When turning on the power, ensure that the power voltage (VCC) power-up time is at least 50 µs (0.2 V to 2.7 V) , in order to keep the built-in step-down circuit from malfunctioning. • Treatment of unused pins Leaving unused input pins free could cause permanent damage due to malfunctions and latch-ups. For this reason, set unused input pins to pull-up or pull-down via resistance of 2 kΩ or more. Additionally, if there are unused I/O pins, either set them to output and leave them free, or set them to input and treat them as input pins. • Notes on using external clock When using an external clock, please drive pin X1 only, and free pin X1. An example of using an external clock is shown in the figure below: X0 OPEN X1 MB90M405 series 11 MB90M405 Series • Power supply pin • When there are multiple VCC/VSS, in order to prevent latch-ups and other malfunctions, then from design considerations, although pins of the same potential are connected device-internally, make sure to connect the VCC and VSS pins to power and grounds, in order to reduce unneeded radiation, and prevent strobe signal malfunctions due to rises in ground level. • Connect VCC and VSS to MB90M405 series devices from a current supply source at low impedance. • Connect an approximately 0.1 µF capacitor as a bypass capacitor between the VCC and VSS, near the VCC and Vss pins, in order to combat power-source noise in MB90M405 series devices. • Crystal Oscillation Circuit • Noise to the X0 and X1 pins can cause MB90M405 series devices to malfunction. Design the printed circuit board so that pins X0 and X1, and the crystal oscillator (or ceramic oscillator) and the capacitor to the ground, are near pins X0 and X1, and not crossing the X0 and X1, or other wiring. • Stable operation can be expected from PCB artwork that surrounds pins X0 and X1 with grounds. • Sequence for applying power analog input of A/D converter • Always make sure to apply voltage to the digital power pin (VCC) before applying voltage to the A/D converter power pin (AVCC) and analog input pins (AN0 to AN15) . • When shutting off the power, shut off digital power (VCC) after shutting off A/D converter power and analog input. • If a port pin also used for analog input is used as an input port, make sure that the analog input voltage does not exceed AVCC (there is no problem with simultaneously applying and cutting analog and digital power) . • Pin handling when not using A/D converter • When not using the A/D converter, connect so that AVCC = VCC and AVSS = VSS. • Output of high-voltage resistance output pin (circuit types C & D) If using high voltage-resistance output (circuit types C & D) as the ordinary output port, when outputting “L” level, a value of pull-down for VKK pin voltage is output. In this case, the VKK level voltage is applied to the external circuit, so add a diode clamp circuit as shown in the figure below: Diode clamp circuit Pch Pout RKK VKK • Notes on PLL clock mode If the oscillator is disconnected, or clock input stops, when the PLL clock is selected on the microcontroller, the microcontroller may continue to operate, using the free-run frequency of the PLL-internal self-exciting oscillation circuit. This operation is not guaranteed. 12 MB90M405 Series ■ BLOCK DIAGRAM CPU control circuit part X0, X1 RST MD2, MD1, MD0 ROM (96/128 KB) RAM (4 KB) FIP0/LED0 to FIP16/LED16 V-RAM FIP17 to FIP59 VKK VCC/VSS AVCC/AVSS FL control circuit Internal data bus Clock control circuit Time clock output circuit PA0/AN0/TMCK PA1/AN1 PA2/AN2 8/10-bit A/D Converter Port A Port B Port 8 PA3/AN3 PA4/AN4 PA5/AN5 Serial I/O (ch 2) External interrupts input control 16-bit freerun timer PA6/AN6 PA7/AN7 PB0/AN8 PB1/AN9 PB2/AN10 PB3/AN11/SI2 PB4/AN12/SC2/TIN0 PB5/AN13/SO2/TO0 PB6/AN14/INT2 PB7/AN15/INT3 16-bit input capture (ch 0, ch 1) 16-bit output Compare Serial I/O (ch 3) P90/SDA/SO3 P91/SCL/SC3 Port 9 16-bit reload timer (ch 0 to ch 2) P80/IC0/INT0 P81/IC1/INT1 P82/SI0 P83/SC0 P84/SO0 I2C Interface UART (ch 0, ch 1) P85/SI1 P86/SC1 P87/SO1 13 MB90M405 Series ■ MEMORY MAP Single chip mode (with ROM miror function) FFFFFFH ROM area Address #1 010000H Address #2 ROM area (image oh FF bank) Address #3 000100H 0000C0H Peripherals 000000H : Access prohibited RAM area Registers Model MB90M407/A MB90M408/A MB90MF408/A MB90MV405 Address #1 FE8000H FE0000H FE0000H F80000H* Address #2 004000H 004000H 004000H 004000H Address #3 001100H 001100H 001100H 001100H * : V products have no built-in ROM. Show the ROM decode area on the tool side. The purpose of the ROM mirror function is to use a small C compiler model. The lower 16-bit address of the FF bank is the same as the lower 16-bit address of the 00 bank. However, as the ROM area of the FF bank exceeds 48 Kbytes, a mirror image of all the data in the ROM area cannot be shown in the 00 bank. When using a small C compiler model, storing a data table in “FF4000H to FFFFFFH” allows a mirror image of the data table to be shown in “004000H to 00FFFFH”. Consequently, it is possible to refer to the data table in the ROM area without declaring a far pointer. • When setting the ROM mirror function register, a mirror image of the data in the upper side of bank FF (“FF4000H to FFFFFFH”) can be seen in the upper side of bank 00 (“004000H to 00FFFFH”) . • See “■ PERIPHERAL FUNCTIONS 15. ROM Mirror Function Selection Module” for details on setting the ROM mirror function. 14 MB90M405 Series ■ I/O MAP Address 000000H to 000007H 000008H 000009H 00000AH 00000BH 00000CH to 000017H 000018H 000019H 00001AH 00001BH 00001CH to 00001DH 00001EH 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H ADER0 ADER1 SMR0 SCR0 SIDR0 SODR0 SSR0 SMR1 SCR1 SIDR1 SODR1 SSR1 CDCR0 CDCR1 DDR8 DDR9 DDRA DDRB Port 8 direction register Port 9 direction register Port A direction register Port B direction register PDR8 PDR9 PDRA PDRB Port 8 data register Port 9 data register Port A data register Port B data register Abbreviated Register Name. Register name Read/ Write Resource Name Initial Value Access prohibited R/W R/W R/W R/W Access prohibited R/W R/W R/W R/W Access prohibited Analog input enable register 0 Analog input enable register 1 Mode register ch 0 Control register ch 0 Input data register ch 0 Output data register ch 0 Status register ch 0 Mode register ch 1 Control register ch 1 Input data register ch 1 Output data register ch 1 Status register ch 1 Communication prescaler control register ch 0 Communication prescaler control register ch 1 R/W R/W R/W R/W R W R/W R/W R/W R W R/W R/W R/W Communication prescaler 0 Communication prescaler 1 UART ch1 UART ch0 Port A, A/D Port B, A/D 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 0 0 0 0 0 X 0 0B 0 0 0 0 0 1 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 0 0 0B 0 0 0 0 0 X 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB 0 0 0 0 1 0 0 0B 0 XXX 0 0 0 0B 0 XXX 0 0 0 0B (Continued) Port 8 Port 9 Port A Port B 0 0 0 0 0 0 0 0B XXXXXX 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Port 8 Port 9 Port A Port B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 15 MB90M405 Series Abbreviated Register Name. IBSR IBCR ICCR IADR IDAR ISEL ENIR EIRR ELVR ADCS0 ADCS1 ADCR0 ADCR1 2 2 Address 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH to 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH, 00004FH 16 Register name I2C status register I C control register I C clock control register I2C address register I2C data register I C port selection register DTP/external interrupt enable register DTP/external interrupt factor register Request level setting register A/D control status register 0 (low-order) A/D control status register 1 (high-order) A/D data register 0(low-order) A/D data register 1 (high-order) 2 Read/ Write R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource Name Initial Value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XX 0 XXXXXB XXXXXXXXB XXXXXXXXB XXXXXXX 0B XXXX 0 0 0 0B I2C interface DTP/external interrupt circuit XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 XXXXXXB Access prohibited 8/10 bit A/D converter XXXXXXXXB XXXXXXXXB 0 0 0 0 0 XXXB Access prohibited ADMR A/D conversion channel setting register R/W 8/10 bit A/D converter 0 0 0 0 0 0 0 0B Access prohibited TCCS Timer counter control status register R/W 16-bit free-run timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB Input capture XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB Output compare XXXXXXXXB XX 0 0 XXX 0B Access prohibited TCDT IPC0 IPC1 ICS01 Timer counter data register Input capture data register ch 0 Input capture data register ch 1 Input capture control status register R/W R R R/W 16-bit free-run timer Access prohibited OCCP0 OCS0 Output compare register Output compare control status register Reserved Access prohibited (Continued) R/W R/W MB90M405 Series Abbreviated Register Name. TMCSR0 TMR0/ TMRLR0 TMCSR1 TMR1/ TMRLR1 TMCSR2 TMR2/ TMRLR2 Address 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH to 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH Register name Read/Write Resource Name Initial Value 0 0 0 0 0 0 0 0B Timer control status register ch 0 16-bit timer register ch 0 (R) 16-bit reload register ch 0 (W) Timer control status register ch 1 16-bit timer register ch 1 (R) 16-bit reload register ch 1 (W) Timer control status register ch 2 16-bit timer register ch 2 (R) 16-bit reload register ch 2 (W) R/W TMR0 : R TMRLR0 : W R/W TMR1 : R TMRLR1 : W R/W TMR2 : R TMRLR2 : W 16-bit reload timer ch 2 16-bit reload timer ch 1 16-bit reload timer ch 0 XXXX 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B XXXX 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B XXXX 0 0 0 0B XXXXXXXXB XXXXXXXXB Access prohibited XXXX 0 0 0 0B Serial I/O ch 2 0 0 0 0 0 0 1 0B XXXXXXXXB XXXX 0 0 0 0B Serial I/O ch 3 0 0 0 0 0 0 1 0B XXXXXXXXB XXXXXX 0 0B FL control circuit 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XX 1 XXX 0 0B 0 0 XXXXXXB SMCS2 SDR2 Serial mode control status register ch 2 Serial shift data register ch 2 R/W R/W Access prohibited SMCS3 SDR3 FLC1 FLC2 FLDG FLDC Serial mode control status register ch 3 Serial shift data register ch 3 Display control register 1 Display control register 2 Digit setting register Digit number register Access prohibited FLST Status register/definition register Access prohibited ROMM ROM mirror function selection register W ROM mirror function XXXXXXX 1B selection module (Continued) R W FL control circuit R/W R/W W W W W Access prohibited 17 MB90M405 Series Abbreviated Register Name. Address Register name Read/ Write W W W W Resource Name Initial Value 000070H SEGD0 to 7 Segment dimmer setting register to 000077H 000078H FLPD0 FIP36 to 43 000079H 00007AH 00007BH to 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H to 0000A7H 0000A8H 0000A9H 0000AAH to 0000AD 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H FMCS TMCS ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 Flash memory control status register Time clock output control register PACSR DIRR LPMCR CKSCR FLPD1 FLPD2 Port register FIP44 to 51 FIP52 to 59 XXXXXXXXB FL control circuit 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Access prohibited Program address detection control status register Delayed interrupt factor generation/cancel register Low-power mode control register Clock selection register R/W R/W R/W R/W Access prohibited WDTC TBTC Watchdog timer control register Timebase timer control register R/W R/W Watchdog timer Timebase timer XXXXX 1 1 1B 1 XX 0 0 1 0 0B Address match detection function Delayed interrupt generation module Low-power control circuit 0 0 0 0 0 0 0 0B XXXXXXX 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B Access prohibited R/W R/W 1 Mbit flash memory 0 0 0 0 0 0 0 0B Clock division for time clock XXXXX 0 0 0B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B Interrupt XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B (Continued) Interrupt control register 00 (for writing) W, R/W Interrupt control register 00 (for reading) R, R/W Interrupt control register 01 (for writing) W, R/W Interrupt control register 01 (for reading) R, R/W Interrupt control register 02 (for writing) W, R/W Interrupt control register 02 (for reading) R, R/W Interrupt control register 03 (for writing) W, R/W Interrupt control register 03 (for reading) R, R/W Interrupt control register 04 (for writing) W, R/W Interrupt control register 04 (for reading) R, R/W Interrupt control register 05 (for writing) W, R/W Interrupt control register 05 (for reading) R, R/W 18 MB90M405 Series Address Abbreviated Register Name. ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Register name Interrupt control register 06 (for writing) Interrupt control register 06 (for reading) Interrupt control register 07 (for writing) Interrupt control register 07 (for reading) Interrupt control register 08 (for writing) Interrupt control register 08 (for reading) Interrupt control register 09 (for writing) Interrupt control register 09 (for reading) Interrupt control register 10 (for writing) Interrupt control register 10 (for reading) Interrupt control register 11 (for writing) Interrupt control register 11 (for reading) Interrupt control register 12 (for writing) Interrupt control register 12 (for reading) Interrupt control register 13 (for writing) Interrupt control register 13 (for reading) Interrupt control register 14 (for writing) Interrupt control register 14 (for reading) Interrupt control register 15 (for writing) Interrupt control register 15 (for reading) Read/ Write W, R/W R, R/W W, R/W R, R/W W, R/W R, R/W W, R/W R, R/W W, R/W R, R/W W, R/W R, R/W W, R/W R, R/W W, R/W R, R/W W, R/W R, R/W W, R/W R, R/W Resource Name Initial Value 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XX 0 0 0 1 1 1B 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Interrupt 0000C0H to 0000FFH 000100H to 0010FFH 001100H FL000 to 255 Data RAM for display to 0011FFH 001200H to 001FEFH Unused area RAM area R/W FL control circuit XXXXXXXXB Reserved area (Continued) 19 MB90M405 Series (Continued) Abbreviated Address Register Name. 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 001FF6H to 001FFFH Read/Write symbols used : R/W : Read/write enabled R : Read only W : Write only Default value symbols used : 0 : Default value is “0” 1 : Default value is “1” X : Default value is undefined PADR1 PADR0 Register name Program address detection register (low-order) Program address detection register (middle-order) Program address detection register (high-order) Program address detection register (low-order) Program address detection register (middle-order) Program address detection register (high-order) Read/ Write R/W R/W R/W R/W R/W R/W Resource Name Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Address match detection function Unused area 20 MB90M405 Series ■ INTERRUPT, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Interrupt Reset INT9 instruction Exception DTP/external interrupt ch 0 DTP/external interrupt ch 1 Serial I/O ch 2 DTP/external interrupt ch 2/3 Serial I/O ch 3 16-bit free-run timer Reserved 16-bit reload timer ch 2 16-bit reload timer ch 0 16-bit reload timer ch 1 Input capture ch 0 Input capture ch 1 Reserved Output comparison match Reserved Timebase timer Reserved UART0 reception complete UART0 transmission complete A/D converter conversion complete I C interface UART1 reception complete UART1 transmission complete Flash memory status Delayed interrupt output module × × 2 EI2OS Support × × × Interrupt Vector NO.* #08 #09 #10 #11 #13 #15 #16 #17 #18 08H 09H 0AH 0BH 0DH 0FH 10H 11H 12H ⎯ 15H 17H 18H 19H 1AH ⎯ 1DH ⎯ 21H ⎯ 23H 24H 25H 26H 27H 28H 29H 2AH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFC8H FFFFC0H FFFFCCH FFFFB8H FFFFB4H FFFFACH FFFFA8H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF88H FFFF80H FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF6CH FFFF58H FFFF54H Interrupt Control Register ICR ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address ⎯ ⎯ ⎯ 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Priority High ⎯ #20 #21 #23 #24 #25 #26 ⎯ × ⎯ × ⎯ #27 #29 #31 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 Low : Supported × : Not supported : Supported, includes EI2OS stop function : Available if interrupt that shares the same ICR is not used * : If two interrupts of the same level are output simultaneously, the interrupt with the lower interrupt vector number has priority. 21 MB90M405 Series ■ PERIPHERAL FUNCTIONS 1. I/O Ports There are a maximum of 26 I/O ports (parallel I/O ports) , which are also used as resource I/O pins (peripheral function I/O pins) . • I/O Port Functions There are two kinds of I/O port : port direction registers (DDRs) and port data registers (PDRs) . The port direction register (DDR) can set port pin I/O at the bit level. The port data register (PDR) sets output data to the port pins. If the port direction register (DDR) sets the I/O port pin to input, the port pin level value can be read by reading the port data register (PDR) . If the port direction register (DDR) sets the I/O port pin to output, the port data register (PDR) value is output to the port pin. Below is a list of the functions of each I/O port, and dual use resources. • Port 8 : I/O port/resource use (external interrupt input pin, ICU, UART) • Port 9 : I/O port/resource use (I2C, serial I/O ch3) • Port A : I/O port/resource use (A/D converter, time clock output) • Port B : I/O port/resource use (A/D converter, serial I/O ch2, external interrupt input pin, reload timer ch0) I/O Port Name Port 8 Input Format Output Function Format I/O Port P80 to P87 CMOS P87 P86 SC1 ⎯ ⎯ PA6 AN6 PB6 P85 SI1 ⎯ ⎯ PA5 AN5 PB5 SO2 TO0 P84 SO0 ⎯ ⎯ PA4 AN4 PB4 SC2 TIN0 P83 SC0 ⎯ ⎯ PA3 AN3 PB3 P82 SI0 ⎯ ⎯ PA2 AN2 PB2 P81 IC1 INT1 P91 SCL SC3 PA1 AN1 PB1 P80 IC0 INT0 P90 SDA SO3 PA0 AN0 TMCK PB0 AN8 ⎯ Pin Name Resource SO1 I/O Port Resource I/O Port ⎯ ⎯ PA7 Port 9 P90/SDA/ SO3, P91/ SCL/SC3 PA0/AN0/ TMCK to PA7/AN7 CMOS (hysteresis) N-ch open drain Port A Resource AN7 CMOS I/O Port Resource PB7 Port B PB0/AN8 to PB7/AN15/ INT3 AN15 AN14 AN13 AN12 AN11 AN10 AN9 INT3 INT2 SI2 ⎯ ⎯ Note: If port A and port B are also used as analog input pins, and are being used as I/O ports, then in addition to the ports A and B direction registers (DDR A/B) and ports A and B data registers (PDR A/B) , set both analog input enable register 0 and 1 (ADER 0/1) to “00H”. Upon reset, analog input enable registers 0 and 1 are set to “FFH” by default. 22 MB90M405 Series • Block Diagram for Port 8 Pins Resource input Internal data bus PDR8 read PDR8 PDR8 write I/O selection circuit Input buffer Output buffer Port 8 pin DDR8 I/O control circuit Resource output Standby control (LPMCR : SPL = "1") • Block Diagram for Port 9 Pins Internal data bus PDR9 read PDR9 PDR9 write I/O selection circuit Output buffer Port 9 pin DDR9 Standby control (LPMCR : SPL = "1") 23 MB90M405 Series • Block Diagram for Port A Pins ADER0 A/D converter Analog input signal Internal data bus PDRA read PDRA PDRA write I/O selection circuit Input buffer Output buffer Port A pin DDRA Standby control (LPMCR : SPL = "1") • Block Diagram for Port B Pins Resource input ADER1 A/D converter Analog input signal Internal data bus PDRB read PDRB PDRB write I/O selection circuit Input buffer Output buffer Port B pin DDRB I/O control circuit Resource output Standby control (LPMCR : SPL = "1") 24 MB90M405 Series 2. Serial I/O Serial I/O allows data transfer via synchronization with a clock consisting of two 8-bit channels. In addition, LSB first or MSB first can be selected for data transfer. • Overview of Serial I/O There are two types of serial I/O operation mode : • Internal shift clock mode Data is transferred in synchronization with internal clock (communication prescaler) • External shift clock mode Data is transferred in synchronization with clock input from external pin (SC) . In this mode, it is also possible to transfer data via CPU instructions (port inversion instruction execution timing) by manipulating the generalpurpose port sharing the external pin (SC) . • Block Diagram of Serial I/O Internal data bus (MSB first) D0 to D7 D0 to D7 (LSB first) Transference direction selection SI0, SI1 SDR (serial data register) SO0, SO1 Read Write SC0, SC1 Control circuit Internal clock (Communication prescaler control register (CDCR) ) 2 1 0 SIR BUSY STOP STRT MODE BDS Interrupt request Internal data bus SOE SCOE Shift clock counter SMD2 SMD1 SMD0 SIE 25 MB90M405 Series 3. Timebase Timer The timebase timer is a 18-bit free-run counter that counts up in synchronization with the main clock. The timer has an interval timer function capable of setting four different intervals, and a function for supplying clocks to the oscillator stabilization standby timer, watchdog timer, and time clock output circuit. • Interval timer function The interval timer function sends an interrupt request at set intervals. • When the timebase timer counter’s interval timer counter overflows, an interrupt request is output. • One of four intervals can be set for the interval timer. Main Clock Cycle Interval Times 212/HCLK (Approx. 1.02 ms) 2/HCLK (0.5 µs) 214/HCLK (Approx. 4.09 ms) 216/HCLK (Approx. 16.38 ms) 219/HCLK (Approx. 131.1 ms) HCLK : Oscillator clock frequency Values in parentheses ( ) are when oscillator clock frequency is 4 MHz. • Clock Supply Function The clock supply function supplies operation clocks to the oscillation stabilization standby timer and some peripheral functions. Clock Supply Destination Clock Cycles 213/HCLK (Approx. 2.05 ms) Oscillation stabilization standby 215/HCLK (Approx. 8.2 ms) 218/HCLK (Approx. 65.53 ms) 212/HCLK (Approx. 1.02 ms) Watchdog timer 214/HCLK (Approx. 4.1 ms) 216/HCLK (Approx. 16.38 ms) 219/HCLK (Approx. 131.07 ms) HCLK : Oscillator clock frequency Values in parentheses ( ) are when oscillator clock frequency is 4 MHz. Reference : Immediately after oscillation begins, the oscillation cycles are unstable; oscillation stabilization standby is a rough measure of the time for oscillation to become stable. Count-up clock for watchdog timer Remarks Oscillation stabilization standby for ceramic oscillator Oscillation stabilization standby for crystal oscillator 26 MB90M405 Series • Block Diagram of Timebase Timer To PPG timer Timebase timer counter Main clock × 21 × 22 × 23 To watchdog timer × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF OF OF Clock controller Wait for oscillator stabilization To time selector Power-on reset Transition to stop mode CKSCR : MCS = "1" "0"*1 Counter clear circuit Interval timer selector TBOF set TBOF clear Timebase timer register Reser(TBTC) ved Timebase timer interrupt signal #34 (22H)*2 ⎯ ⎯ TBIE TBOF TBR TBC1 TBC0 ⎯ OF *1 *2 : Undefined bit : Overflow : Switching of machine clock from main clock to PLL clock : Interrupt number 27 MB90M405 Series 4. Watchdog Timer The watchdog timer is a two-bit timer that uses the output of the timebase timer as a count clock. When the watchdog timer is started, if it is not cleared within the set interval, the CPU is reset. • Watchdog Timer Function The watchdog timer detects runaway programs. When the watchdog timer is started, it must be cleared within a set interval. If a program enters an infinite loop, or for some other reason the watchdog timer is not cleared within the minimum time, a watchdog reset is generated to the CPU, sending it to a reset state. The watchdog timer interval is set by the interval time setting bits (WT1 and WT0) of the watchdog timer control register (WDTC) . WT1 0 0 1 1 WT0 0 1 0 1 Interval Times Minimum* Approx. 3.59 ms Approx. 14.33 ms Approx. 57.34 ms Maximum* Approx. 4.61 ms Approx. 18.43 ms Approx. 73.74 ms Oscillator clock cycles 214 ± 211 cycles 216 ± 213 cycles 218 ± 215 cycles 221 ± 218 cycles Approx. 458.76 ms Approx. 589.82 ms * : When oscillator clock frequency is 4 MHz. Reference : After the watchdog timer is started, it can be halted via a power-on reset, or a reset by the watchdog timer. While an external reset, internal reset, setting the watchdog control bit (WTE) of the watchdog timer control register (WDTC) , or going to sleep or stop mode can clear the watchdog timer, these actions will not change the watchdog function setting, or halt the watchdog timer. Note: The watchdog timer is made up of a two-bit timer that counts the carry signal of the timebase timer. Because the watchdog timer uses the carry signal of the timebase timer, if the timebase timer is cleared, then the watchdog reset interval may be longer than the set time. • Block Diagram of Watchdog Timer Watchdog timer control register (WDTC) PONR ⎯ WRST ERST SRST WTE WT1 WT0 Watchdog timer 2 Clear and start Over flow Clear Sleep mode start Hold status start Stop mode start Timer clear control circuit Count clock selector 2-bit counter Clear Watchdog reset generation circuit To inter reset generation circuit Clear 4 (Timebase timer counter) Main clock × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 ⎯ : Undefined bit 28 MB90M405 Series 5. 16-bit Reload Timer The MB90M405 series has 3 built-in 16-bit reload timer channels. They can be configured with the following clock modes and counter operation modes : • • • • • • • Clock Modes Internal Clock Mode : In this mode, the timer counts down in synchronization with the internal clock Event Count Mode : In this mode, the timer counts down in accordance with external input pulses Counter Operation Modes Reload Mode : In this mode, the count setting is reloaded, and the count is repeated One-shot Mode : In this mode, the count is halted due to an underflow 16-bit Reload Timer Operation Modes Clock Mode Counter Operation Mode Operation Mode Reload mode Internal Clock Mode Event Count Mode (External Clock Mode) • Internal Clock Mode When the count clock setting bits (CSL1, CSL0) of the timer control status register (TMCSR) are set to “00B”, “01B”, or “10B”, the mode is set to internal clock mode. In internal clock mode, the following operation modes can be set : • Software trigger operation If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to “1”, setting the software trigger bit (TRG) to “1” will initiate count operation. • External trigger input operation If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to “1”, then when a valid edge (rising, falling, or both edges can be set) set beforehand in the operation mode setting bits (MOD2, MOD1, MOD0) is input to the TIN pin, count operation is initiated. • External gate input operation If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to “1”, then count operation is conducted while a valid gate input level (“L” or “H” can be set) set beforehand in the operation mode setting bits (MOD2, MOD1, MOD0) is input to the TIN pin. • Event Count Mode (External Clock Mode) When the count clock setting bits (CSL1, CSL0) of the timer control status register (TMCSR) are set to “11B”, the mode is set to event count mode (external clock) . If the count enable bit (CNTE) is set to “1”, then when a valid edge (rising, falling, or both edges can be set) set in the operation mode setting bits (MOD2, MOD1, MOD0) is input to the TIN pin, count operation is initiated. If an external clock is input at set intervals, then it can also be used as an interval timer. One-shot mode Reload mode One-shot mode Software trigger operation External trigger operation External gate input operation Software trigger operation 29 MB90M405 Series • Counter Operation • Reload mode When the 16-bit down counter underflows (“0000H” to “FFFFH”) , the value of the 16-bit reload register (TMRLR) is loaded into the 16-bit down counter, and count operation is conducted. In addition, when an underflow occurs an interrupt request is output, so this can also be used as an interval timer. It is possible to output the inverted toggle waveform from the TO pin with each underflow. Count Clock Count Clock Cycle Interval Time 21/φ (0.125 µs) Internal Count Clock External Count Clock 2 /φ (0.5 µs) 3 5 0.125 µs to 8.192 ms 0.5 µs to 32.768 ms 2.0 µs to 131.1 ms 0.5 µs + 2 /φ (2.0 µs) 23/φ+ (0.5 µs) φ : Machine clock frequency Values in parentheses ( ) are when machine clock frequency is 16 MHz. • One-shot mode When the 16-bit down counter underflows (“0000H” to “FFFFH”) , count operation is halted. Reference : • 16-bit reload timer 0 can be used to create the UART baud rate. • 16-bit reload timer 1 can be used as the start trigger for the A/D converter. • 16-bit Reload Timer Interrupts and EI2OS When the 16-bit down counter underflows (“0000H” to “FFFFH”) , an interrupt request is output. Interrupt Control Register Vector Table Address Interrupt Channel No. Register Name Address Lower Upper Bank 16-bit reload timer 0 #23 (17H) 16-bit reload timer 1 #24 (18H) ICR06 0000B6H FFFFA0H FFFF9CH FFFFA8H FFFFA1H FFFF9DH FFFFA9H FFFFA2H FFFF9EH FFFFAAH EI2OS 16-bit reload timer 2 #21 (15H) ICR05 0000B5H : Available if interrupt factors sharing ICR are not used 30 MB90M405 Series • Block Diagram of 16-bit Reload Timer Internal data bus TMRLR 16-bit reload register Reload signal TMR 16-bit timer register (down counter) CLK Count clock generation circuit Machine clock φ Gate input Effective clock decision circuit CLK UF Reload control circuit Prescaler Clear 3 Wait signal UART*1 To A/D converter*2 Output control circuit Internal clock Pin Input control circuit 3 Function selection Clock selector External clock 2 Select signal Output signal Re- generation circuit verse Pin EN Operation control circuit ⎯ ⎯ ⎯ ⎯ CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TMCSR) *1 : ch 0 *2 : ch 1 Interrupt request signal 31 MB90M405 Series 6. 16-bit I/O Timers The 16-bit I/O timer can perform dual independent waveform output, input pulse width measurement, and external clock cycle measurement, based on the 16-bit freerun timer. • 16-bit freerun timer (1 channel) The 16-bit freerun timer is made up of a 16-bit up counter (timer counter data register (TCDT) ) , timer counter control status register (TCCS) , and prescaler. The counter output value of the 16-bit freerun timer is used as the base timer for output comparison and input capture. • Counter operation clock (4 different settings available) 4 internal clock types : φ/4, φ/16, φ/32, φ/64 φ : Machine clock frequency • Interrupt An interrupt can be output to the CPU when the counter value overflows, or when it matches the value of comparison register 0. • Initialize When a reset is input, if the software reset bit is cleared to “0”, or if the values of comparison register 0 and the freerun timer count match, the counter value can be initialized to “0000H”. • Output compare (1 channel) The output comparison module consists of a 1-channel 16-bit comparison register, and control register. If the value of the 16-bit freerun timer and that of the compare register match, an interrupt request can be output to the CPU. • Input capture (2 channels) The input capture module consists of a capture register and a control register. Both support two independent external input pin channels. The capture register can store the value of the 16-bit freerun timer. Additionally, the register can detect signal input edges from external pins, and simultaneously output interrupts to the CPU. • The detection edge of the external input signal can be configured (rising edge, falling edge, both edges) • The two input capture channels can operate independently Interrupts can be output upon detection of a valid edge in an external input signal • Input capture interrupts start the extended intelligent I/O service 32 MB90M405 Series • Block Diagram of 16-bit I/O Timer Interrupt request φ IVF IVFE STOP MODE CLR CLK1 CLK0 (TCCS) Comparator 0 Divider 16-bit freerun timer (Timer counter data register TCDT) Count value output (T15 to T00) Compare control Internal data bus Clock Compare register 0 (2) ⎯ ICP0 ⎯ ICE0 Compare 0 (2) interrupt Controller Each control block Capture data register 0 Edge detection IC0 EG11 EG10 EG01 EG00 Capture data register 1 Edge detection IC1 ICP1 ICP0 ICE1 ICE0 Capture interrupt Capture interrupt 33 MB90M405 Series 7. UART The UART is a general-purpose serial data communications interface for both synchronous and asynchronous (start-stop synchronization) communications with external devices. Two types of communication are available: two-way communication (normal mode) and master/slave communication (multiprocessor mode; only the master side is supported) . • UART Functions The UART is a general-purpose serial data communications interface for sending and receiving serial data to and from other CPUs and peripheral devices. It provides the following functions: Function Data Buffer Transfer Mode Full-duplex double buffer • Clock-synchronous (no start/stop bit) • Clock-asynchronous (start-stop synchronization) • • • • • Max 2 MHz (with machine clock at 16 MHz) Baud rate via dedicated baud rate generator Baud rate via external clock (SC pin input clock) Baud rate via internal clock (clock supplied from 16-bit reload timer) Total of 8 types of baud rate may be set Baud Rate Data Length Signal Format Receive Error Detection • 7 bits (in asynchronous normal mode only) • 8 bits NRZ (Non Return to Zero) • Framing errors • Overrun errors • Parity errors (undetectable in multiprocessor mode) • Receive interrupts (receive complete, receive error detection) • Send interrupts (send complete) • Extended intelligent I/O service (EI2OS) supported for both sending and receiving Interrupt Requests Master/Slave Enables 1 (master) to n (slave) communication Communications Function (Only master side supported) (Multiprocessor Mode) Note : The UART does not add a start or stop bit during clock-synchronous transfer. Only the data is forwarded. Data Length No Parity 8 + 1*1 8 With Parity ⎯ ⎯ 7 bits or 8 bits Operation Mode 0 1 Normal Mode Multiprocessor Mode Synchronization Stop Bit Length Asynchronous Asynchronous Synchronous 1 bit or 2 bits*2 None 2 Normal Mode ⎯ : Not available *1 : “+1” is the address/data setting bit (A/D) used for communications control. *2 : During reception, only a stop bit length of 1 can be detected. 34 MB90M405 Series • Block Diagram of UART Control bus Receive interrupt signal Dedicated baud rate generator 16-bit reload timer 0 Clock selector Receive clock Pin Receive control circuit Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter Pin Transmit clock Transmission interrupt signal Start bit detection circuit Receive bit counter Receive parity counter Pin Receive shift register Receive complete SIDR0/SIDR1 Receive status evaluation circuit Transmission shift register Transmission start SODR0/SODR1 Receive error detection signal for EI2OS (to CPU). Internal data bus SMR0/ SMR1 Register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0/ SCR1 Register PEN P SBL CL A/D REC RXE TXE SSR0/ SSR1 Register PE ORE FRE RDRF TDRE BDS RIE TIE 35 MB90M405 Series 8. DTP/External Interrupt Circuit The DTP (Data Transfer Peripheral) /external interrupt circuit detects interrupt requests input from the external interrupt input pin, and outputs interrupt requests. • DTP/External Interrupt Function The DTP/external interrupt circuit outputs interrupt requests upon detection of an edge input from the external interrupt input pin, or a level signal. Interrupt requests are accepted by the CPU, and if extended intelligent I/O service (EI2OS) is enabled, the CPU conducts automated data transfer (DTP function) via EI2OS, then branches into an interrupt processing routine. If EI2OS is disabled, the CPU branches into an interrupt processing routine, without starting automated data transfer (DTP function) via EI2OS. External Interrupt Function Input pins Interrupt conditions Interrupt number Interrupt control Interrupt flag Processing selection Operation 4 channels (P80/INT0, P81/INT1, PB6/INT2, PB7/INT3) The level or edge to detect can be set independently for each pin in the detection level setup register (ELVR) “L” level/“H” level input #11 (0BH), #13 (0DH) , #16(10H) Enable/disable interrupt request output in the DTP/external interrupt enable register (ENIR) The DTP/interrupt factor register (EIRR) stores interrupt conditions. Set EI2OS to disabled (ICR : ISE = “0”) Branch to interrupt processing routine Set EI2OS to enabled (ICR : ISE = “1”) Branch to interrupt processing routine after automatic data transfer by EI2OS completes. Rising edge/falling edge input DTP Function ICR : Interrupt Control Register • DTP/External Interrupt Circuit Interrupts and EI2OS Channel INT0 INT1 INT2 INT3 Interrupt No. #11 (0BH) #13 (0DH) #16 (10H) Interrupt Control Register Register Name ICR00 ICR01 ICR02 Address 0000B0H 0000B1H 0000B2H Vector Table Address Lower FFFFD0H FFFFC8H FFFFBCH Upper FFFFD1H FFFFC9H FFFFBDH Bank FFFFD2H FFFFCAH FFFFBEH EI2OS 36 MB90M405 Series • Block Diagram of DTP/External Interrupt Circuit Request level setting register (ELVR) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Selector Pin INT0 Selector Pin INT1 Selector Pin INT2 Selector Internal data bus Pin INT3 ⎯ ⎯ ⎯ ⎯ ER3 ER2 ER1 ER0 Interrupt request ⎯ ⎯ ⎯ ⎯ EN3 EN2 EN1 EN0 • DTP/External Interrupt Input Detection Circuit If a signal input to the external interrupt input pin matches the level set in the request level setting register (ELVR) or edge, the DTP/external interrupt factor flag bit (EIRR : ER3 to ER0) corresponding to the external interrupt input pin is set to “1”. • Request Level Setting Register (ELVR) The interrupt request detection conditions (level or edge) are set for each external interrupt input pin • DTP/External Interrupt Factor Register (EIRR) Stores and clears interrupt factors • DTP/External Interrupt Enable Register (ENIR) Interrupt requests are enabled/disabled for each external interrupt input pin. 37 MB90M405 Series 9. I2C Interface The I2C interface is a serial I/O port that supports the Inter IC BUS. It operates as a master/slave device on an I2C bus, with the following features : • I2C Interface Features The MB90M405 series has one I2C interface channel. Below are features of the I2C interface : • Master/slave send/receive • Arbitration function • Clock synchronization function • Slave address/general call address detection function • Transfer direction detection function • Start condition loop generation and detection function • Bus error detection function • Transfer rates of up to 100 Kbps supported 38 MB90M405 Series • Block Diagram of I2C Interface ICCR EN I2C enable 5 Clock divider 1 6 7 8 Clock selection 1 Clock divider 2 16 32 64 128 256 Clock selection 2 Shift clock edge change timing Bus busy BB RSC LRB TRX Internal data bus FBT AL IBCR BER BEIE Interrupt request INTE INT IBCR SCC MSS ACK GCAA Start Master ACK permission GC-ACK permission Machine clock ICCR CS4 CS3 CS2 CS1 CS0 248 Sync Shift clock generation IBSR Repeat start Last bit Transmission/ Receive Start stop condition detection Error First Byte Arbitration lost detection SCL SDA IRQ End Start stop condition generation IDAR IBSR AAS GCA Slave Global call Slave address compare IADR 39 MB90M405 Series 10. 8/10 Bit A/D Converter The 8/10 bit A/D converter has a function to convert analog input voltage to a 10 or 8-bit value using the RC successive approximation conversion method. • 8/10 Bit A/D Converter Functions Below are the functions of the 8/10 bit A/D converter : • The minimum conversion time is 6.125 µs (with machine clock frequency of 16 MHz, including sampling time) • The minimum sampling time is 2 µs (with machine clock frequency of 16 MHz) • The RC successive approximation conversion method with sample-hold circuit is used for conversion • Resolution can be set to 10 or 8 bits • Input signal programmable from 8-channel analog input pins • When A/D conversion is completed, it is possible to output an interrupt request, and start EI2OS • In an interrupt-enabled state, when A/D conversion is executed, a conversion data protection function is invoked • The conversion start factor can be set to software or 16-bit reload timer 1 output (rising edge) The following 4 conversion modes are available : Conversion Mode Single Conversion Operation One-shot Conversion Mode 1 One-shot Conversion Mode 2 Scan Conversion Operation The set channel performs conversion Multiple linked channels (up to 16 channels can once, then stops be set) perform conversion once, then stop Continuous Conversion The set channel performs conversion Multiple linked channels (up to 16 channels can Mode repeatedly be set) perform conversion repeatedly Stop Conversion Mode The set channel performs conversion Multiple linked channels (up to 16 channels can once, then pauses, and goes into be set) perform conversion once, then pause, standby until started again and go into standby until started again • 8/10 Bit A/D Converter Functions Interrupts and EI2OS Interrupt No. #37 (25H) : Available Interrupt Control Register Register Name ICR13 Address 0000BDH Lower FFFF68H Vector Table Address Upper FFFF69H Bank FFFF6AH EI2OS 40 MB90M405 Series • Block Diagram of 8/10 Bit A/D Converter A/D control status register (ADCS0/ADCS1) Interrupt request signal #37 (25H) * A/D cmversion channel setting register (ADMR) BUSY INT INTE PAUS STS1 STS0 STRT Rese- MD1 MD0 ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 rved 8 2 16-bit reload timer 1 output Clock selector Decoder φ Comparator Sample hold Circuit PB7/AN15 to PA0/AN0 A/D data register (ADCR0/ADCR1) Analog channel selector AVR AVCC AVSS 2 D/A converter 2 Control circuit S10 ST1 ST0 CT1 CT0 ⎯ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 φ : Machine clock * : Interrupt signal • A/D control status register 0/1 (ADCS0/ADCS1) The A/D control status register 1 (ADCS1) has functions to set the A/D conversion start factor, enable/disable interrupt requests, check the status of interrupt requests, and check whether A/D conversion is halted/ongoing. • A/D data register (ADCR0/ADCR1) This register stores the results of A/D conversion. It has functions to set the A/D conversion resolution, A/D conversion sampling time, and A/D conversion comparison time. • A/D conversion channel setting register (ADMR) Provides a function to set the A/D conversion start/stop channel • Clock selector This selector sets the A/D conversion start clock. The 16-bit reload timer 1 output can be set in the start clock. • Decoder This circuit sets the analog input pin to use from the setting of the A/D conversion end channel setting bit (ANE0 to ANE3) and A/D conversion start channel setting bit (ANS0 to ANS3) of the A/D control status register (ADCS0) . Internal data bus 41 MB90M405 Series 11. FL-control Circuit The FL control circuit has a fluorescent tube automated display function and an LED automated display function. The fluorescent tube automated display function is capable of up to 32 digits, and 60 combined segment and digit automated display. The LED automated display function can output LED1 pin to LED16 pin at 1/2 duty, with LED0 pin as common output. • High voltage resistance output pins • There are 60 onboard high voltage resistance output pins (FIP0 pin to FIP59 pin) . • There are 34 high-current output pins (FIP0 pin to FIP33 pin) and 26 mid-current output pins (FIP34 pin to FIP59 pin) . • Pull-down resistance can be set for all high voltage-resistance output. Alternately, they can be combined. • Fluorescent tube automated display function • Has 32 × 60-bit display data RAM. • The display timing can be set to between 1 and 32. • 60 bits can be set for both digits and segments for each timing. • The digit pins are FIP0 pin to FIP31 pin; from the pin set for digit start, the digits can be set in series for the number of pins set in the digit number register. • Segments can control up to 59 outputs. • There are 4 types of display scan cycle (segment width) . • Digit dimmer control controls the T on both sides of the digit for segment output. Adjustment is available in 7 steps (dimmer applied to all digits) . • All digit and segment can be inverted. • Segment output of an arbitrary timing is capable of gradated display (segment dimmer) . The T of both sides of the segment are as follows : Digit Dimmer Control Digit output Segment output T T T T T Segment Dimmer Control Digit output "H" Output "L" Output Segment output example T T T Note : Dimmer can be applied to a defined segment in the setup timing. 42 MB90M405 Series • LED automated display function • Pins between LED0 pin and LED16 pin not set to digits can be set as LED pins. • As shown in the figure below, LED0 pin becomes common output, and LED1 pin to LED16 pin become LED segment output. • When LED0 pin is set to “H”, the values corresponding to LED1 pin to LED16 pin are output at the timing T1 in display data RAM; when LED0 pin is set to “L”, the values corresponding to LED1 pin to LED16 pin are output at the timing T2 in display data RAM. • 1/2 duty LED output can be obtained by externally inverting the LED0 pin common output. • As shown below, the output timing of LED1 pin to LED16 pin from LED0 pin and the inverted signal of LED0 pin is 5.12 ms for LED0 pin, and 4.096 ms for LED1 pin to LED16 pin (when machine clock (peripheral operation clock) frequency is 16 MHz) . LED automated display timing 5.12 ms 5.12 ms 4.096 ms 1.024 ms 4.096 ms LED0 pin common output Inverting output created outside device LED segment output from LED1 pin to LED16 pin T1 T2 T1 T2 43 MB90M405 Series • Block Diagram of FL Control Circuit FLST Control circuit FLC1 S W S W LED controller FIP controller FLC2 Width setting Inverting output, timing No. setup Internal data bus Digit Dimmer width setting Start pin setting FLDC Number setting Segment FLDG Dimmer width setting SEGD Dimmer applicable segment setting RAM for display data 32 × 60 bit 34 large current Pch Tr Timing selection for setting segment dimmer SEGDT 32 × 1 bit Two intermediate current Pch Tr FLPD 24 44 MB90M405 Series 12. Time Clock Output The time clock output circuit divides the oscillator clock by means of the timebase timer, and outputs the set division clock. Can be set to 1/32, 1/64, 1/128, or 1/256 of oscillator clock. • Time clock output circuit The timer clock output circuit is disabled in reset and stop modes. It is enabled in normal run modes, sleep mode, and pseudo clock mode. PLL_Run Main_Run Sleep Pseudo Clock STOP Reset Operating State × × If the timebase timer is cleared while the time clock output circuit is in use, clock output cannot be conducted normally. • Block Diagram of Time Clock Output Circuit Time clock selection circuit X0 Oscillator X1 Selector Time clock output Timebase timer Divide-by-two circuit 45 MB90M405 Series 13. Delayed Interrupt Generation Module The delayed interrupt generation module outputs task switching interrupt requests. When the delayed interrupt generation module is used, it is possible to output interrupt requests and releases to an MB90M405 series CPU via the software for task switching. • Block Diagram of Delayed Interrupt Generation Module Delayed interrupt request generation/reset decoder Internal data bus Interrupt factor latch 46 MB90M405 Series 14. Address Match Detection Function If a program address matches the value set in the address match detection register, the instruction code read into the CPU is changed to an INT9 instruction code. It is possible to realize a program patch assignment function by processing an INT #9 interrupt routine. • Block Diagram of Address Match Detection Function Internal data bus Address latch Address detection register Acknowledge bit Compare MB90M405 Series CPU core 47 MB90M405 Series 15. ROM Mirror Function Selection Module The ROM Mirror Function Selection Module allows the ROM data of bank FF to be viewed from bank 00, by setting the ROM mirror function selection module register. Using the ROM mirror function makes it possible to access the corresponding area (“FF4000H” to “FFFFFFH”) from the I/O and RAM areas, without crossing banks. • Block Diagram of ROM Mirror Function Selection Module ROM mirror function selection register (ROM) Internal data bus Address space Address FF bank 00 bank Data ROM 48 MB90M405 Series 16. 1 Mbit Flash Memory The 1 Mbit flash memory is arrayed on the CPU memory map in banks FEH to FFH. It allows read and program access from the CPU in the same manner as mask ROM. Data is written to and deleted from flash memory by means of instructions from the CPU, via the flash memory interface circuit. This allows the implementation state to be overwritten via onboard CPU control, allowing programs and data to be modified efficiently. • • • • • • • • 1 Mbit Flash Memory Length 128 Kword × 8/64 Kword × 16 bit (16 K + 8 K + 8 K + 32 K + 64 K) sector configuration. Automated program algorithm (same as Embedded Algorithm* : MBM29F400TA) Built-in deletion pause/resume function Write/deletion completion detection by CPU interrupt JEDEC standard command compatible Sector-by-sector deletion possible (sectors can be combined freely) Write/deletion guaranteed through 10,000 iterations * : Embedded Algorithm is a trademark of Advanced Micro Device. • Method for Writing to and Deleting Flash Memory There are two methods for writing to/deleting from flash memory : 1. Dedicated serial writer (YDC AF220) YDC: Yokogawa Digital Computer 2. Writing/deletion via program execution It is not possible to simultaneously write to and read from flash memory. When writing to/deleting from flash memory, programs in flash memory are temporarily copied to RAM, and run from there; this allows data to be written to flash memory. 49 MB90M405 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS-CPU = VSS-IO = AVSS = 0.0 V) Parameter Signal VCC-CPU VDD-FIP Power Supply Voltage AVCC VKK Input Voltage Output Voltage “L” Level Maximum Output Current “L” Level Average Output Current “L” Level Maximum Overall Output Current “L” Level Average Overall Output Current “H” Level Maximum Output Current “H” Level Average Output Current “H” Level Maximum Overall Output Current “H” Level Average Overall Output Current VI VI2 VO VO2 IOL IOLAV Σ IOL Σ IOLAV IOH IOHFIP1 IOHFIP2 IOHAV Σ IOH Σ IOHAV Σ IOHFIPAV PD_CPU PD_FL Ta Tstg Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VCC − 45 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 −55 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VCC + 0.3 VSS + 4.0 VSS + 5.5 VSS + 4.0 VSS + 5.5 15 4 100 50 −15 −27 −14 −4 −100 −50 −180 300 1176 +85 +150 Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mW mW °C °C Remarks Control circuit power pin FIP power pin VCC ≥ AVCC*1 Power supply pin of pull-down side during high voltage resistant output *2 *3 *2 *3 (open drain output) *4, *5 Average value (operating current × operating rate) *5 *5 Average value (operating current × operating rate) *5 *4, *5 FIP0 to FIP33 pins FIP34 to FIP59 pins Average value (operating current × operating rate) *5 *5 Average value (operating current × operating rate) *5 Average value (operating current × operating rate) *6 During CPU_Chip independent operation During FL_Chip independent operation Consumption Power Operating Temperature Storage Temperature *1 : Make sure that AVcc does not exceed VCC when applying power, etc. *2 : VI, VO must not exceed VCC + 0.3 V. *3 : 5 V voltage resistant pin for I2C. Only applies to P90/SDA and P91/SCL. *4 : The standard for maximum output current is the peak value of a single corresponding pin. *5 : Excludes current at pins FIP0 to FIP59. 50 MB90M405 Series *6 : Corresponds to pins FIP0 to FIP59. Note : VCC in the standard signifies VDD-FIP = VCC-CPU. Also, use the 3 pins on the left at the same power level. Here, VSS signifies VSS-IO = VSS-CPU. Please connect this pin to GND as well. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 2. Recommended Operating Conditions (VSS-IO = VSS-CPU = AVSS = 0.0 V) Parameter Symbol VCC-CPU Power Voltage VDD-FIP VCC VHIS Input “H ” Voltage VHIS2 VHIM VILS Input “ L” Voltage Operating Temperature VILS2 VILM Ta Values Min 3.0 3.0 2.5 0.8 VCC 0.8 VCC VCC − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −40 Max 3.6 3.6 3.6 VCC + 0.3 VSS + 5.0 VCC + 0.3 0.2 VCC 0.2 VCC VSS + 0.3 +85 Unit V V V V V V V V V °C Remarks During normal operation During normal operation Save stop operation status CMOS hysteresis input pin except I2C I2C CMOS hysteresis input pin (5 V voltage resistant) MD pin input CMOS hysteresis input pin except I2C I2C CMOS hysteresis input pin (5 V voltage resistant) MD pin input Note : VCC in the standard signifies VDD-FIP = VCC-CPU. Also, use the 3 pins on the left at the same power level. Here, Vss signifies VSS-IO = VSS-CPU. Please connect this pin to GND as well. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 51 MB90M405 Series 3. DC Standard (Ta = −40 °C to +85 °C, VDD-FIP = VCC-CPU = AVCC = 3.0 V to 3.6 V, VSS-IO = VSS-CPU = AVSS = 0 V) Value Sym Pin Name Conditions Unit Remarks Parameter bol Min Typ Max VOH5 VOH4 Output “H ” Voltage VOH3 VOH2 VOH1 VOH0 Output “ L” Voltage Input Leak Voltage Output Leak Voltage VOL1 VOL IIL ILO3 ILO2 FIP0 - FIP33 FIP34 - FIP59 SDA/SCL IOH5 = −23 mA IOH4 = −12 mA IOH3 = −12 mA IOH2 = −5 mA IOH1 = −4 mA VCC − 2.5 VCC − 1.3 VCC − 2.0 VCC − 1.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 5.5 ⎯ 0.8 0.4 +5 20 10 V V V V V V V V µA µA µA mA MB90M407/A* MB90M408/A* MB90M407/A* MB90M408/A* MB90MF408/A MB90MV405* MB90MF408/A MB90MV405* Open drain pin All output pins exIOH = −2.0 mA cept for the above SDA/SCL IOL = 15 mA All output pins exIOL = 2.0 mA cept for the above VCC = 3.0 V All input pins except FIP0 - FIP59 (VSS < V1 < VCC) FIP0 - FIP33 FIP34 - FIP59 VKK = VCC to VCC − 43 VKK = VCC to VCC − 43 VCC − 0.5 VCC − 0.3 ⎯ ⎯ −5 ⎯ ⎯ ⎯ 0.5 0.2 −1 ⎯ ⎯ 32 VCC = 3.3 V Internal frequency 16 MHz During normal operation VCC = 3.3 V Internal frequency 16 MHz During A/D operation ICC Power Current VCC VCC = 3.3 V Internal frequency 16 MHz During normal operation VCC = 3.3 V Internal frequency 16 MHz During A/D operation Flash memory During write/deletion ICCS ICCH Pull-up Resistance Pull-down Resistance RUP RDW1 RDW1 VCC = 3.3 V Internal frequency 16 MHz During sleep During stop, Ta = +25 °C RST MD2 FIP0 - FIP59 ⎯ ⎯ When set 40 ⎯ 37 45 mA ⎯ 40 50 mA ⎯ ⎯ ⎯ ⎯ 20 20 80 45 55 mA 40 50 mA MB90MF408/A 15 15 65 65 120 20 20 200 200 160 mA * µA kΩ kΩ kΩ * : The standard current values do not include current consumption by the high voltage resistance pins. This indicates the current consumption of the internal circuit. 52 MB90M405 Series Notes: • VCC in the standard signifies VDD-FIP = VDD-VFT = VCC-CPU. Also, use the 3 pins on the left at the same power level. Here, VSS signifies VSS-IO = VSS-CPU. Please connect this pin to GND as well. • Current values are subject to change without notice, in order to affect improvements in characteristics, etc. The power current measurement condition is the external clock. • Scope of Guaranteed PLL Operation Relationship between Internal Operation Clock Frequency and Power Voltage PLL guaranteed operation range 3.6 Power supply voltage VCC (V) 3.0 1.5 3 Internal operating clock frequency fCP (MHz) 16 Relationship between Source Oscillation Clock Frequency and Internal Operating Clock Frequency Internal operating clock frequency fCP (MHz) ×4 ×3 ×2 ×1 16 12 9 8 6 4 3 2 1.5 3 4 6 8 12 16 No multiplier Source oscillation clock fCH (MHz) 53 MB90M405 Series 4. AC Characteristics (1) Clock Timings (Ta = −40 °C to +85 °C, VDD-FIP = VCC-CPU = AVCC = 3.0 V to 3.6 V, VSS-IO = VSS-CPU = AVSS = 0 V) Value Sym CondiParameter Pin Name Unit Remarks bol tion Min Typ Max 3 3 Clock frequency fC X0, X1 3 3 3 3 Clock cycle time Input clock pulse width Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time • X0 and X1 clock timing tHCYL 0.8 VCC 16 16 ⎯ 16 8 5.33 4 ⎯ ⎯ ⎯ ⎯ ⎯ 333 ⎯ 5 16 666 ns ns ns MHz ns Recommended duty ratio = 30% to 70% When using an external clock × 1/2 (When PLL stops) MHz PLL × 1 PLL × 2 PLL × 3 PLL × 4 tHCYL PWH PWL tcr tcf fCP tCP X0, X1 X0 X0 ⎯ ⎯ ⎯ 62.5 10 ⎯ 1.5 62.5 X0 0.2 VCC PWH tcf PWL tcr 54 MB90M405 Series (2) Reset (Ta = −40 °C to +85 °C, VDD-FIP = VCC-CPU = AVCC = 3.0 V to 3.6 V, VSS-IO = VSS-CPU = AVSS = 0 V) Parameter Symbol Pin Name Condition Value Min 16 tCP Reset input time tRSTL RST ⎯ Oscillator oscillation time* + 16 tCP Max ⎯ ⎯ Unit ns ms Remarks In normal operation In stop mode *: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several dozen ms; for a FAR/ceramic oscillator, this is several hundred µs to a few ms, and for an external clock this is 0 ms. • In normal operation tRSTL RST 0.2 VCC 0.2 VCC • In stop mode tRSTL RST 0.2Vcc 90 % of amplitude 0.2Vcc X0 Internal operation clock Oscillator oscillation time 16 tCP Oscillator stabilization wait time Execution of the instruction Internal reset 55 MB90M405 Series (3) Power-On Reset (Ta = −40 °C to +85 °C, VDD-FIP = VCC-CPU = AVCC = 3.0 V to 3.6 V, VSS-IO = VSS-CPU = AVSS = 0 V) Parameter Power supply rise time Power supply cutoff time Symbol tR tOFF Pin Name VCC* VCC Condition ⎯ Value Min 0.05 4 Max 30 ⎯ Unit ms ms For repeated operation Remarks * : VCC must be less than 0.2 V before power-on. Notes : • The above rating values are for generating a power-on reset. • Some internal registers are only initialized by a power-on reset. Always apply the power supply in accordance with the above ratings if you wish to initialize these registers. tR VCC 2.7 V 0.2 V 0.2 V tOFF 0.2 V Sudden changes in the power supply voltage may cause a power-on reset. The recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly as shown below. Also, changes to the supply voltage should be performed when the PLL clock is not in use. The PLL clock may be used, however, if the rate of voltage change is 1 V/s or less. VCC Recommended rate of voltage rise is 50 mV/ms or less. 2.5 V Maintain RAM data VSS 56 MB90M405 Series (4) Serial I/O (Ta = −40 °C to +85 °C, VDD-FIP = VCC-CPU = AVCC = 3.0 V to 3.6 V, VSS-IO = VSS-CPU = AVSS = 0 V) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin Name SC0 to SC3 SC0 to SC3 SO0 to SO3 Internal shift clock mode, output pin SC0 to SC3 load is SI0 to SI2 CL = 80 pF + 1 TTL SC0 to SC3 SI0 to SI2 SC0 to SC3 SC0 to SC3 SC0 to SC3 SO0 to SO3 SC0 to SC3 SI0 to SI3 SC0 to SC3 SI0 to SI2 External shift clock mode, output pin load is CL = 80 pF + 1 TTL Condition Value Min 8 tCP −80 100 60 4 tCP 4 tCP ⎯ 60 60 Max ⎯ 80 ⎯ ⎯ ⎯ ⎯ 150 ⎯ ⎯ Unit Remarks ns ns ns ns ns ns ns ns ns Notes : • Above rating is the case of CLK synchronous mode. • CL is the load capacitor connected to the pin for testing. • tCP is the machine cycle period (unit = ns) 57 MB90M405 Series • Internal shift clock mode SC 0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V SO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SI 0.2 VCC • External shift clock mode SC 0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC SO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SI 0.2 VCC 58 MB90M405 Series (5) Timer Input Timings (Ta = −40 °C to +85 °C, VDD-FIP = VCC-CPU = AVCC = 3.0 V to 3.6 V, VSS-IO = VSS-CPU = AVSS = 0 V) Value CondiParameter Symbol Pin Name Unit Remarks tion Min Max Input pulse width tTIWH, tTIWL TIN0 ⎯ 4 tCP ⎯ ns 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC TIN0 tTIWH tTIWL (6) Timer Output Timings (Ta = −40 °C to +85 °C, VDD-FIP = VCC-CPU = AVCC = 3.0 V to 3.6 V, VSS-IO = VSS-CPU = AVSS = 0 V) Value Parameter Symbol Pin Name Condition Unit Remarks Min Max CLK ↑ → TOUT change time tTO TO0 ⎯ 30 ⎯ ns CLK 2.4 V tTO TO0 2.4 V 0.8 V (7) Trigger Input Timings (Ta = −40 °C to +85 °C, VDD-FIP = VCC-CPU = AVCC = 3.0 V to 3.6 V, VSS-IO = VSS-CPU = AVSS = 0 V) Parameter Input pulse width Symbol tTRGL Pin Name INT0 to INT3 Condition ⎯ Value Min 5 tCP 1 Max ⎯ ⎯ Unit ns µs Remarks In normal operation In stop mode 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC INT0 to INT3 tTRGH tTRGL 59 MB90M405 Series 5. Electrical Characteristics of A/D Converter Parameter Resolution Total Error Non-linear Error Differential Linear Error Zero Transition Voltage (Ta = −40 °C to +85 °C, VCC-CPU ≤ AVCC = 3.0 V to 3.6 V, VSS-CPU = VSS-IO = AVSS = 0 V) Value SymPin Name Unit Remarks bol Min Typ Max ⎯ ⎯ ⎯ ⎯ VOT ⎯ ⎯ ⎯ ⎯ AN0 to AN15 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10 ±3.0 ±2.5 ±1.9 bit LSB LSB LSB AVSS AVSS AVSS mV − 1.5 LSB + 0.5 LSB + 2.5 LSB Full-scale Transition Voltage VFST Conversion Time (sampling + comparison) Sampling Time Comparison Time Analog Port Input Voltage Analog Input Voltage Reference Voltage Power Current Reference Voltage Supply Current Inter-channel Variance ⎯ ⎯ ⎯ IAIN VAIN ⎯ IA IAH IR IRH ⎯ AVCC AVCC AVCC AN0 to AN15 mV − 3.5 LSB − 1.5 LSB + 0.5 LSB ⎯ ⎯ ⎯ AN0 to AN15 AN0 to AN15 AVCC AVCC AVCC AVCC AVCC AN0 to AN15 98 tCP*2 32 tCP*2 66 tCP*2 ⎯ 0 3.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 ⎯ 100 ⎯ ⎯ ⎯ ⎯ ⎯ 10 AVCC AVCC 5 5 200 5 4 ns ns ns µA V V mA µA µA µA LSB 1 LSB = AVCC/1024 16 MHz Operation 16 MHz Operation 16 MHz Operation *1 *1 *1 : When the A/D converter is not operating, voltage when CPU stopped (at VCC-CPU = AVCC = 3.3 V) *2 : tCP signifies 1/internal operating frequency. With tCP at internal 16 MHz, 1/16 MHz = 62.5 ns. Notes: • Reference “L” side set permanently to AVSS, and reference “H” side set permanently to AVCC. As AVCC decreases, relative error increases. • Please use the output impedance of the external analog input circuit under the following conditions : External circuit output impedance ≤ 10 kΩ • An overly high external circuit output impedance could cause a lack of analog voltage sampling time. • Analog Input Circuit Equivalent Circuit Diagram RON C Comparator Analog input MB90M407/A,MB90M408/A RON = approx. 1.5 kΩ C = approx. 30 pF MB90MF408/A, MB90MV405 RON = approx. 3.0 kΩ C = approx. 65 pF Note : Please use the figures given here as a rough guide. 60 MB90M405 Series ■ SAMPLE CHARACTERISTICS (1) “H” level output voltage (VCC − VOH) − IOH 1.0 0.9 0.8 VCC - VOH (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 −1 −2 −3 IOH (mA) −4 VCC = 2.7 V VCC = 3 V VCC = 3.3 V VCC = 3.6 V VCC = 3.9 V −5 VOL (V) TA = +25 °C 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1 2 3 IOL (mA) 4 5 TA = +25 °C (2) “L” level output voltage VOL − IOL VCC = 2.7 V VCC = 3 V VCC = 3.3 V VCC = 3.6 V VCC = 3.9 V (3) “H” level input voltage/ “L” level input voltage (CMOS input) VIN − VCC 2.5 TA = +25 °C (4) “H” level input voltage/ “L” level input voltage (hysteresis input) VIN − VCC 2.5 TA = +25 °C 2 VIH 2 VIH VIN (V) VIN (V) 1.5 VIL 1.5 VIL 1 1 0.5 0.5 0 2.7 3 3.3 VCC (V) 3.6 3.9 0 2.7 3 3.3 VCC (V) 3.6 3.9 61 MB90M405 Series ■ ORDERING INFORMATION Part NO. MB90MF408PF MB90M408PF MB90M407PF MB90MF408APF MB90M408APF MB90M407APF Package Remarks All FL output pins (FIP0 to FIP59) have pull downs 100-pin plastic QFP (FPT-100P-M06) Some FL output pins (FIP0 to FIP16) do not have pull downs. The remaining FL output pins (FIP17 to FIP59) have pull downs. 62 MB90M405 Series ■ PACKAGE DIMENSIONS 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. 63 MB90M405 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0508 © 2005 FUJITSU LIMITED Printed in Japan