MB91F314

FUJITSU SEMICONDUCTOR DATA SHEET DS07-16802-1E 32-bit Microcontroller CMOS FR60 MB91314A Series MB91314A/MB91F314 ■ DESCRIPTION The FR family* is a line of single-chip microcontrollers based on the 32-bit high-performance RISC CPU while integrating a variety of I/O resources for embedded control applications which require high-performance, highspeed CPU processing. The FR family contains multiple channels of data slicer and communication macros, best suited for embedded applications such as TV control. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited. ■ FEATURES 1. FR CPU 32-bit RISC, load/store architecture with a five-stage pipeline Operating frequency 33 MHz [PLL used : Oscillation frequency 16.5 MHz : Doubled] 16-bit fixed length instructions (basic instructions), 1 instruction per cycle Instruction set optimized for embedded applications : Memory-to-memory transfer, bit manipulation, barrel shift instructions etc. • Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store instructions • Register interlock functions : Facilitating coding in assemblers • On-chip multiplier supported at the instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles (Continued) • • • • Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2007 FUJITSU LIMITED All rights reserved MB91314A Series • • • • Interrupt (PC, PS save) : 6 cycles, 16 priority levels Harvard architecture allowing program access and data access to be executed simultaneously Instruction prefetch feature added by a 4-word queue in the CPU Instruction set compatible with FR family 2. Simple External Bus interface Capable of functioning 8-bit or 16-bit multiplex bus by setting with program • Operating frequency : Max 16.5 MHz • 8/16-bit data/address multiplex I/O • Capable of chip-select signal output for completely independent four areas settable in 64 Kbytes minimum • Basic bus cycle : 2 cycles • Programmable automatic wait cycle generator capable of inserting wait cycles for each area 3. Internal Memory MB91314A : 256 Kbytes Mask ROM, RAM 32 Kbytes MB91F314 : 512 Kbytes Flash, RAM 32 Kbytes 4. DMAC (DMA Controller) • • • • • 5 channels Two forwarding factors (internal peripheral/software) Addressing mode 20/24-bit address selection (increment/decrement/fixed) Transfer modes (burst transfer/step transfer/block transfer) Selectable transfer data size : 8, 16, or 32 bits 5. Bit Search Module (for REALOS) Search for the position of the bit 1/0-changed first in one word from the MSB 6. Reload Timer (Including 1 Channel for REALOS) • 16-bit timer ch.6 • The internal clock is optional from 2/8/32 division 7. Multi function Serial Interface • 11 channels • Full duplex double buffer • Capable of selecting communication mode : asynchronous (Start-Stop synchronous) communication, clock synchronous communication (8.25 Mbps Max), I2C* standard mode (100 kbps Max), high-speed mode (400 kbps Max) • Parity on/off selectable • Baud rate generator per channel • Abundant error detection functions are provided (parity, frame, and overrun) • External clock can be used as transfer clock • Ch.0 to ch.2 correspond to DMA transfer. • Ch.0 to ch.2 have a pair of 16 bytes FIFO buffers for transmission and reception. • I2C bridge feature (among channels 0, 1, and 2) • SPI mode (Continued) 2 MB91314A Series 8. Interrupt Controller • • • • A total of 24 external interrupt lines (external interrupt pins INT23 to INT0) Interrupt from internal peripheral Programmable 16 priority levels Available for wakeup from STOP mode 9. A/D converter • • • • 10-bit resolution, 10 channels Successive approximation type : conversion time : About 8.0 µs Conversion mode (Single-shot conversion mode, scan conversion mode) Startup sources (software/external trigger) 10. PPG • • • • • 4 channels 16-bit down counter, 16-bit data register with cycle setting buffer The internal clock is optional from 1/4/16/64 division Support for automatic cycle setting by DMA transfer Function for supporting remote control transmission 11. PWC • 1 channel (1 input) • 16-bit up counter • Simple digital lowpass filter 12. Multi-function timer • • • • • • 4 channels Lowpass filter eliminating noise below a pre-set clock frequency Capable of pulse width measurement using seven types of clock signals Pin input event count function Interval timer function using seven types of clock signals and external input clock Internal HSYNC counter mode 13. Closed caption decoder feature • 1 channel • CC decoder function • ID-1 (480i/480p) decoder function 14. Other interval timers • Watch timer (32 kHz, Count up to 2 seconds) • Watchdog timer 15. I/O port Max 78 ports (Continued) 3 MB91314A Series (Continued) 16. Other features • • • • • Internal oscillator circuit as a clock source INIT is prepared as a reset terminal Watchdog timer reset and software reset are available Stop and sleep modes supported as low-power consumption modes Gear function • Built-in time base timer • 5 V tolerant I/O (some pins) • Package LQFP-120, 0.50 mm pitch, 16.0 mm × 16.0 mm • CMOS technology (0.18µm) • Power supply voltage 3.3 V ± 0.3 V, 1.8 V ± 0.15 V dual-power * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 4 MB91314A Series ■ PIN ASSIGNMENT (TOP VIEW) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 VDDE P22/SCK0/SCL0 (I2C bridge) P21/SOT0/SDA0 (I2C bridge) P20/SIN0 P57/WR1 P56/WR0 P55/RD P54/AS P53/CS3/PPG3 P52/CS2/PPG2 P51/CS1/PPG1 P50/CS0/PPG0 P17/D15 P16/D14/SCK7/SCL7 P15/D13/SOT7/SDA7 P14/D12/SIN7 P13/D11/SCK6/SCL6 P12/D10/SOT6/SDA6 P11/D09/SIN6 P10/D08/SCK5/SCL5 P07/D07/SOT5/SDA5/INT15 P06/D06/SIN5/INT14 P05/D05/SCK4/SCL4/INT13 P04/D04/SOT4/SDA4/INT12 P03/D03/SIN4/INT11 P02/D02/SCK3/SCL3/INT10 P01/D01/SOT3/SDA3/INT9 P00/D00/SIN3/INT8 VDDI VSS VSS VDDI P23/SIN1 P24/SOT1/SDA1 (I2C bridge) P25/SCK1/SCL1 (I2C bridge) P26/SIN2 P27/SOT2/SDA2 (I2C bridge) P30/SCK2/SCL2 (I2C bridge) P31/TOT0 P32/TOT1 P33/TOT2 P34/TIN0 P35/TIN1 P36/TIN2 P37/RIN P40/TMO0/INT16 P41/TMO1/INT17 P42/TMO2/INT18 P43/TMO3/INT19 P44/TMI0/INT20 P45/TMI1/INT21/SIN10 P46/TMI2/INT22/SOT10/SDA10 P47/TMI3/INT23/SCK10/SCL10 P60/TOT3/TRG2 P61/TOT4/TRG3 P62/TOT5/RDY P63/TIN3/CLK P64/TIN4 P65/TIN5 VDDE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDDE IBREAK ICLK ICS2 ICS1 ICS0 ICD3 ICD2 ICD1 ICD0 TRST PC7/TRG1 PC6/TRG0 PC5/PPGB PC4/PPGA PC3 PC2/SCK9/SCL9 PC1/SOT9/SDA9 PC0/SIN9 PE7/SCK8/SCL8/INT7 PE6/SOT8/SDA8/INT6 PE5/SIN8/INT5 PE4/PPG3/INT4 MD2 MD1 MD0 VDDI X0 X1 VSS VSS VDDC VSSC VIN VCI CPO VDDP VSSP HSYNC VDDE VSS AVSS AVRH AVCC PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 PE0/AN8/INT0 PE1/AN9/PPG0/INT1 PE2/PPG1/INT2/ATRG PE3/PPG2/INT3 VDDE INIT X0A X1A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 (FPT-120P-M21) 5 MB91314A Series ■ PIN DESCRIPTION Pin no. 1 2 3 Pin name VSS VDDI P23 SIN1 P24 4 SOT1/SDA1 (I2C bridge) P25 5 SCK1/SCL1 (I2C bridge) P26 SIN2 P27 7 SOT2/SDA2 (I2C bridge) P30 8 SCK2/SCL2 (I2C bridge) P31 TOT0 P32 TOT1 P33 TOT2 P34 TIN0 P35 TIN1 P36 TIN2 P37 RIN P40 16 TMO0 INT16 P41 17 TMO1 INT17 B B L L L L I/O circuit type* ⎯ ⎯ D GND pin 1.8 V power supply General-purpose I/O port Multi function serial 1 serial data input pin General-purpose I/O port Multi function serial 1 serial data output pin I2C data I/O pin General-purpose I/O port Multi function serial 1 serial communication clock I/O pin I2C clock I/O pin General-purpose I/O port Multi function serial 2 serial data input pin General-purpose I/O port Multi function serial 2 serial data output pin I2C data I/O pin General-purpose I/O port Multi function serial 2 serial communication clock I/O pin I2C clock I/O pin General-purpose I/O port Output pin for reload timer General-purpose I/O port Output pin for reload timer General-purpose I/O port Output pin for reload timer General-purpose I/O port Event input pin for reload timer General-purpose I/O port Event input pin for reload timer General-purpose I/O port Event input pin for reload timer General-purpose I/O port PWC input pin General-purpose I/O port Multifunction timer output External interrupt request input pin General-purpose I/O port Multifunction timer output External interrupt request input pin (Continued) 6 Description 6 D 9 10 11 12 13 14 15 D D D D D D D MB91314A Series Pin no. 18 Pin name P42 TMO2 INT18 P43 I/O circuit type* B Description General-purpose I/O port Multifunction timer output External interrupt request input pin General-purpose I/O port 19 TMO3 INT19 P44 B Multifunction timer output External interrupt request input pin General-purpose I/O port 20 TMI0 INT20 P45 TMI1 INT21 SIN10 P46 TMI2 B Multifunction timer input External interrupt request input pin General-purpose I/O port Multifunction timer input External interrupt request input pin Multi function serial 10 serial data input pin General-purpose I/O port Multifunction timer input 21 B 22 INT22 SOT10/SDA10 P47 TMI3 B External interrupt request input pin Multi function serial 10 serial data output pin I2C data I/O pin General-purpose I/O port Multifunction timer input 23 INT23 SCK10/SCL10 P60 B External interrupt request input pin Multi function serial 10 serial communication clock I/O pin I2C clock I/O pin General-purpose I/O port 24 TOT3 TRG2 P61 C Output pin for reload timer PPG trigger input General-purpose I/O port 25 TOT4 TRG3 P62 C Output pin for reload timer PPG trigger input General-purpose I/O port 26 TOT5 RDY P63 C Output pin for reload timer External ready input pin General-purpose I/O port 27 TIN3 CLK P64 TIN4 C Event input pin for reload timer External clock output pin General-purpose I/O port Event input pin for reload timer (Continued) 7 28 C MB91314A Series Pin no. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin name P65 TIN5 VDDE VSS VDDC VSSC VIN VCI CPO VDDP VSSP HSYNC VDDE VSS AVSS AVRH AVCC PD0 AN0 PD1 AN1 PD2 AN2 PD3 AN3 PD4 AN4 PD5 AN5 PD6 AN6 PD7 AN7 PE0 AN8 INT0 I/O circuit type* C ⎯ ⎯ ⎯ ⎯ N N N ⎯ ⎯ M ⎯ ⎯ ⎯ ⎯ ⎯ L L L L L L L L Description General-purpose I/O port Event input pin for reload timer 3.3 V power supply GND pin Data slicer power supply Data slicer ground Data slicer input VCO control voltage input Charge pump output Dot clock PLL power supply Dot clock PLL ground Horizontal synchronous input 3.3 V power supply Ground pin Analog ground pin for A/D converter Analog reference power voltage input pin for A/D converter Analog power supply input pin for A/D converter General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin External interrupt request input pin (Continued) 53 L 8 MB91314A Series Pin no. Pin name PE1 AN9 PPG0 INT1 PE2 PPG1 INT2 ATRG PE3 I/O circuit type* Description General-purpose I/O port A/D converter analog input pin Output pin for PPG External interrupt request input pin General-purpose I/O port Output pin for PPG External interrupt request input pin Trigger input pin for A/D converter General-purpose I/O port 54 L 55 B 56 57 58 59 60 61 62 63 64 65 66 67 68 PPG2 INT3 VDDE INIT X0A X1A VSS X1 X0 VDDI MD0 MD1 MD2 PE4 PPG3 INT4 PE5 B ⎯ G A A ⎯ A A ⎯ F F F Output pin for PPG External interrupt request input pin 3.3 V power supply Initial reset pin Sub clock input Sub clock I/O Ground pin Main clock I/O Main clock input 1.8 V power supply Input pins for specifying the operating mode General-purpose I/O port B Output pin for PPG External interrupt request input pin General-purpose I/O port 69 SIN8 INT5 PE6 B Multi function serial 8 serial data input pin External interrupt request input pin General-purpose I/O port Multi function serial 8 serial data output pin I2C data I/O pin External interrupt request input pin General-purpose I/O port Multi function serial 8 serial communication clock I/O pin I2C clock I/O pin External interrupt request input pin General-purpose I/O port Multi function serial 9 serial data input pin (Continued) 9 70 SOT8/SDA8 INT6 PE7 B 71 SCK8/SCL8 INT7 B 72 PC0 SIN9 B MB91314A Series Pin no. 73 Pin name PC1 SOT9/SDA9 PC2 I/O circuit type* B Description General-purpose I/O port Multi function serial 9 serial data output pin I2C data I/O pin General-purpose I/O port Multi function serial 9 serial communication clock I/O pin I2C clock I/O pin General-purpose I/O port General-purpose I/O port Output pin for PPG General-purpose I/O port Output pin for PPG General-purpose I/O port PPG trigger input General-purpose I/O port PPG trigger input Reset pin for development tool 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SCK9/SCL9 PC3 PC4 PPGA PC5 PPGB PC6 TRG0 PC7 TRG1 TRST ICD0 ICD1 ICD2 ICD3 ICS0 ICS1 ICS2 ICLK IBREAK VDDE VSS VDDI P00 D00 SIN3 INT8 P01 D01 B B B B B B G K K K K H H H H I ⎯ ⎯ ⎯ Data pin for development tool Status pin for development tool Clock pin for development tool Break pin for development tool 3.3 V power supply GND pin 1.8 V power supply General-purpose I/O port External address/ data bus I/O pin Multi function serial 3 serial data input pin External interrupt request input pin General-purpose I/O port External address/ data bus I/O pin 93 C 94 SOT3/SDA3 INT9 C Multi function serial 3 serial data output pin I2C data I/O pin External interrupt request input pin (Continued) 10 MB91314A Series Pin no. Pin name P02 D02 I/O circuit type* Description General-purpose I/O port External address/ data bus I/O pin 95 SCK3/SCL3 INT10 P03 D03 SIN4 INT11 P04 D04 C Multi function serial 3 serial communication clock I/O pin I2C clock I/O pin External interrupt request input pin General-purpose I/O port External address/ data bus I/O pin Multi function serial 4 serial data input pin External interrupt request input pin General-purpose I/O port External address/ data bus I/O pin 96 C 97 SOT4/SDA4 INT12 P05 D05 C Multi function serial 4 serial data output pin I2C data I/O pin External interrupt request input pin General-purpose I/O port External address/ data bus I/O pin 98 SCK4/SCL4 INT13 P06 D06 SIN5 INT14 P07 D07 C Multi function serial 4 serial communication clock I/O pin I2C clock I/O pin External interrupt request input pin General-purpose I/O port External address/ data bus I/O pin Multi function serial 5 serial data input pin External interrupt request input pin General-purpose I/O port External address/ data bus I/O pin 99 C 100 SOT5/SDA5 INT15 P10 D08 SCK5/SCL5 P11 C Multi function serial 5 serial data output pin I2C data I/O pin External interrupt request input pin General-purpose I/O port External address/ data bus I/O pin Multi function serial 5 serial communication clock I/O pin I2C clock I/O pin General-purpose I/O port 101 C 102 D09 SIN6 P12 D10 SOT6/SDA6 C External address/ data bus I/O pin Multi function serial 6 serial data input pin General-purpose I/O port External address/ data bus I/O pin Multi function serial 6 serial data output pin I2C data I/O pin (Continued) 11 103 C MB91314A Series Pin no. Pin name P13 D11 SCK6/SCL6 I/O circuit type* Description General-purpose I/O port External address/ data bus I/O pin Multi function serial 6 serial communication clock I/O pin I2C clock I/O pin General-purpose I/O port 104 C P14 105 D12 SIN7 P15 106 D13 SOT7/SDA7 P16 107 D14 SCK7/SCL7 108 P17 D15 P50 109 CS0 PPG0 P51 110 CS1 PPG1 P52 111 CS2 PPG2 P53 112 CS3 PPG3 113 114 115 116 P54 AS P55 RD P56 WR0 P57 WR1 C C C C C C C C C C C C External address/ data bus I/O pin Multi function serial 7 serial data input pin General-purpose I/O port External address/ data bus I/O pin Multi function serial 7 serial data output pin I2C data I/O pin General-purpose I/O port External address/ data bus I/O pin Multi function serial 7 serial communication clock I/O pin I2C clock I/O pin General-purpose I/O port External address/ data bus I/O pin General-purpose I/O port External chip select Output pin for PPG General-purpose I/O port External chip select Output pin for PPG General-purpose I/O port External chip select Output pin for PPG General-purpose I/O port External chip select Output pin for PPG General-purpose I/O port External address strobe output pin General-purpose I/O port External read strobe output pin General-purpose I/O port External data bus write strobe output pin General-purpose I/O port External data bus write strobe output pin (Continued) 12 MB91314A Series (Continued) Pin no. 117 Pin name P20 SIN0 P21 SOT0/SDA0 (I2C bridge) P22 SCK0/SCL0 (I2C bridge) VDDE I/O circuit type* D Description General-purpose I/O port Multi function serial 0 serial data input pin General-purpose I/O port Multi function serial 0 serial data output pin I2C data I/O pin General-purpose I/O port Multi function serial 0 serial communication clock I/O pin I2C clock I/O pin 3.3 V power supply 118 D 119 120 D ⎯ * : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”. 13 MB91314A Series ■ I/O CIRCUIT TYPE Type Circuit type Clock input Remarks • Oscillation circuit • Built-in feedback resistance X0 pin − X1 pin : 1 MΩ X0A pin − X1A pin : No A Standby control • CMOS level output IOH = 4mA • CMOS level hysteresis input VIH = 0.7 × VDDE • With standby control • 5 V tolerant P-ch Digital output B N-ch Digital output Digital input Standby control • CMOS level output IOH = 4 mA • CMOS level hysteresis input VIH = 0.8 × VDDE • With standby control • With pull-up resistor (33 kΩ) P-ch P-ch Digital output C N-ch Digital output Digital input Standby control (Continued) 14 MB91314A Series Type Circuit type Remarks • CMOS level output IOH = 4 mA • CMOS level hysteresis input VIH = 0.8 × VDDE • With standby control • Without pull-up resistor P-ch Digital output D N-ch Digital output Digital input Standby control • CMOS level input • Without standby control P-ch F N-ch Digital input • CMOS hysteresis input • With pull-up resistor P-ch P-ch G N-ch Digital input CMOS level output P-ch Digital output H Digital output N-ch (Continued) 15 MB91314A Series Type Circuit type Remarks • CMOS hysteresis input • With pull-down resistor • Without standby control P-ch I N-ch N-ch Digital input • • • • CMOS level output CMOS level input Without standby control With pull-down resistor P-ch Digital output K N-ch N-ch Digital output Digital input • CMOS level output CMOS level hysteresis input • With standby control • Analog input with switch P-ch Digital output Digital output N-ch L Analog input Control Digital input Standby control (Continued) 16 MB91314A Series (Continued) Type Circuit type Remarks • CMOS level hysteresis input • Without standby control P-ch M N-ch Digital input Analog pin P-ch N N-ch 17 MB91314A Series ■ HANDLING DEVICES • Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage greater than VDDE or VDDI, or less than VSS is applied to input and output pins or if an above-rating voltage is applied between VDDE or VDDI pins and VSS pin. A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. • Treatment of Unused Input Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. • About power supply pins If more than one VDDE or VDDI or VSS pin exists, those that must be kept at the same potential are designed to be connected to one other inside the device to prevent malfunctions such as latch-up. Be sure to connect the pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation, prevent strobe signal malfunctions due to an increase in ground level, and conform to the total output current rating. Given consideration to connecting the current supply source to VDDE or VDDI and VSS pin of the device at the lowest impedance possible. It is also recommended that a ceramic capacitor of around 0.1 µF be connected between VDDE or VDDI and VSS pin at circuit points close to the device as a bypass capacitor. • About Crystal oscillator circuit Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, X0A and X1A pins the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. • About Mode pins (MD0 to MD2) These pins should be connected directly to VDDE or VSS pins. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VDDE or VSS pins is as short as possible and the connection impedance is low. • Operation at start-up Always use the INIT pin to perform a setting initialization reset (INIT) after turning on the power. Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the stabilization wait time required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value). • Source oscillation input at power on When turning on the power, always input the clock for the duration of the oscillation stabilization delay time. 18 MB91314A Series • Notes on the turning on/off VDDI pin (1.8 V internal power supply) and VDDE pin (3.3 V external pin power supply) Do not apply only VDDE pin (external) voltage continuously (more than one minute) with VDDI pin (internal) disconnected as it adversely affects the reliability of the LSI. When VDDE pin (external) returns from the OFF state to the ON state, the circuit may fail to hold its internal state, for example, due to power supply noise. Power on Power off VDD pin (internal) → Analog → VDDE pin (external) → signal Signal → VDDE pin (external) → Analog → VDDI pin (internal) When the power is turned on, the output pin may remain unstable until the internal power supply becomes stable. • About the attention when the external clock is used To use an external clock, in principle, supply the X1 (X1A) pin with a clock signal inverted in phase from the X0 (X0A) pin at the same time. However, in this case the stop mode (oscillator stop mode) must not be used. (This is because the X1 (X1A) pin stops at “H” output in STOP mode.) At 12.5 MHz or less, the device can be used only with the X0 (X0A) pin supplied with clock signals. Using an External Clock (Normal Method) X0, X0A X1, X1A MB91314A Series The STOP mode (oscillation stop mode) cannot be used. Using an External Clock (available at 12.5 MHz or less) X0, X0A X1, X1A Open MB91314A Series Note : With respect to the X0 (X0A) signal, design X1 such that the delay is within 15 ns at 10 MHz. 19 MB91314A Series • AVCC pin The device has an internal A/D converter. A capacitor of approximately 0.1µF must be connected between the AVCC pin and AVSS pin. AVCC 0.1µF MB91314A Series AVSS • Notes when the emulator is not used To operate the evaluation MCU on the user system without connecting the emulator, treat each input pin on the evaluation MCU connected to the emulator interface on the user system as shown below. Emulator Interface Pin Treatment Evaluation MCU pin name Pin operation TRST INIT Others Connected to the reset output circuit on the user system. Connected to the reset output circuit on the user system. Open • Note on operation with the PLL clock selected On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. 20 MB91314A Series ■ RESTRICTIONS 1) Clock control block Take the oscillation stabilization wait time during “L” level input to the INIT pin. 2) Bit Search Module The bit search data register for 0-detection (BSD0), and bit search data register for 1-detection (BSD1), and bit search data register for change point detection (BSDC) are only word-accessible. 3) I/O port Ports are accessed only in bytes. 4) Low Power Consumption Mode • To place the device in standby mode, use the synchronous standby mode (set with bit 8 (SYNCS bit) of the timebase counter control register, TBCR) and be sure to use the following sequence: (ldi #value_of_standby, r0) (ldi #_STCR, r12) stb r0, @r12 // set STOP/SLEEP bit ldub @r12, r0 // Must read STCR ldub @r12, r0 // after reading, go into standby mode nop // Must insert NOP *5 nop nop nop nop • Please do not do the following when the monitor debugger is used. • Setting of the break point to the above-mentioned instruction row. • Execution of the step for the above-mentioned instruction row. 21 MB91314A Series 5) Notes on the PS register Since some instructions write the information to PS register early time, the following exception operations may cause a break to occur in an interrupt processing routine when using the debugger or the updating of the PS flag. In either case, the processing is conducted properly again after return from an EIT, the operations before and after the EIT are designed to perform as specified. • The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S instruction results in (a) acceptance of a user interrupt, (b) single-stepping, or (c) a break in response to a data event or emulator menu: (1) D0 and D1 flags are updated in advance. (2) An EIT handling routine (user interrupt, NMI, or emulator) is executed. (3) Upon returning from the EIT, the DIV0U/DIV0S instructions are executed and the D0/D1 flags are updated back to the original value held before step (1). • When a user interrupt source exists, executing either of the OR CCR, ST LIM and MOV Ri and PS instructions to enable the interrupt results in the following operations: (1) The PS register is updated in advance. (2) An EIT handling routine (user interrupt) is executed. (3) Upon returning from the EIT, the above instructions are executed and the PS registers are updated back to the original value held before step (1). 6) Watchdog timer The watchdog timer integrated in this model monitors the program to check that it delays a reset within a certain period of time and, if the program runs out of control and fails to delay the reset, resets the CPU in place. Once the watchdog timer is enabled, it keeps running until reset. As an exception, the watchdog timer delays the reset automatically when a condition which stops program execution by the CPU develops. For those conditions which correspond to this exception, refer to the function description of the watchdog timer in “HARDWARE MAN UAL”. A watchdog reset may not be generated in the above situation caused by the system running out of control. In that case, please reset (INIT) by external INIT terminal. 7) Notes on using the A/D converter Although this series contains an A/D converter, do not apply a higher voltage to AVCC pin than to VDDE pin. 8) Software reset in synchronous mode When using the software reset in synchronous mode, the following two conditions should be satisfied before setting “0” to the SRST bit in STCR (standby control register) . • Set the interrupt enable flag (I-Flag) to the interrupt disable (I-Flag = 0) . • Do not use NMI. 22 MB91314A Series ■ BLOCK DIAGRAM FR CPU CORE 32 32 Mask ROM 256 Kbytes/ Flash 512 Kbytes Bit search module RAM 32 Kbytes Bus converter DMAC 5 channels 32 ↔ 16 adapter Simple external bus I/F 8/16-bit multiplex bus Clock control Interrupt controller External interrupt Multi function Serial interface UART/SIO/I2C 11 channels A/D converter 10 channels Closed caption decoder 1 channel Ports PWC 1 channel PPG 4 channels Reload timer 6 channels Multifunction timer 4 channels 23 MB91314A Series ■ CPU AND CONTROL UNIT Internal architecture The FR family of CPUs is a line of high-performance cores providing advanced instructions for embedded applications based on the RISC architecture. 1. Features • RISC architecture adopted. Basic instructions : Executed at one instruction per cycle • 32-bit architecture General purpose registers : 32 bits × 16 • Four Gbytes of linear memory space • Multiplier integrated 32-bit × 32-bit multiplication : 5 cycles 16-bit × 16-bit multiplication : 3 cycles • Enhanced interrupt servicing High-speed response (6 cycles) Multi-level interrupt support Level mask feature (16 levels) • Enhanced I/O manipulation instructions Memory-to-memory transfer instructions Bit manipulation instructions • High code efficiency Basic instruction word length : 16 bits • Lower-power consumption Sleep mode/stop mode Gear function 24 MB91314A Series 2. Internal architecture The FR family of CPUs has a Harvard architecture in which the instruction bus and data bus are separated. The 32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the CPU and peripheral resources. The Harvard ↔ Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface between the CPU and the bus controller. FRex CPU D-bus I-bus 32 I address 32 External address Harvard 24 I data D address 32 External data Princeton bus converter 16 Data RAM D data 32 32-bit 16-bit bus converter Address Data 32 32 16 R-bus F-bus Peripheral resources Internal I/O Bus converter 25 MB91314A Series 3. Programming model • Programming model 32 bits [Initial Value] R0 R1 ... ... ... ... XXXX XXXXH ... ... ... ... AC FP SP ... XXXX XXXXH 0000 0000H General purpose registers R12 R13 R14 R15 Program counter Program status Table base register Return pointer System stack pointer User stack pointer PC PS TBR RP SSP USP ILM SCR CCR Multiply and divide result register MDH MDL 26 MB91314A Series 4. Register • General purpose registers 32 bits [Initial Value] R0 R1 ... ... R12 R13 R14 R15 AC FP SP ... ... XXXX XXXXH ... ... ... ... ... XXXX XXXXH 0000 0000H Registers R0 to R15 are general purpose registers. The registers are used as the accumulator and memory access pointers for CPU operations. Of these 16 registers, the registers listed below are intended for special applications, for which some instructions are enhanced. • R13 : Virtual accumulator (AC) • R14 : Frame pointer (FP) • R15 : Stack pointer (SP) The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000H (SSP value). • PS (Program Status) This register holds the program status and is divided into the ILM, SCR, and CCR. All of undefined bits are reserved bits. Reading these bits always returns 0. Writing to them has no effect. bit 31 bit 20 bit 16 bit 10 bit 8 bit 7 bit 0 ILM SCR CCR 27 MB91314A Series • CCR (Condition Code Register) bit 7 bit 6 bit 5 S bit 4 I bit 3 N bit 2 Z bit 1 V bit 0 C [Initial Value] --00XXXXB S : Stack flag • Cleared to 0 at a reset. • Set the flag to 0 for execution of the RETI instruction. I : Interrupt Enable flag Cleared to 0 at a reset. N : Negative flag Initial state by reset is irregular. Z : Zero flag Initial state by reset is irregular. V : Overflow flag Initial state by reset is irregular. C : Carrying flag Initial state by reset is irregular. • SCR (System Condition code Register) bit 10 D1 bit 9 D0 bit 8 T [Initial Value] XX0B D1, D0 : Flag for step division Stores intermediate data for stepwise division operations. T : Step trace trap flag A flag specifying whether the step trace trap function is enabled or not. • The emulator uses the step trace trap function. The function cannot be used by the user program when using the emulator. • ILM (Interrupt Level Mask Register) bit 20 ILM4 bit 19 ILM3 bit 18 ILM2 bit 17 ILM1 bit 16 ILM0 [Initial Value] 01111B This register stores the interrupt level mask value. The value in the ILM register is used as the level mask. Initialized to 15 (01111B) by a reset. 28 MB91314A Series • PC (Program Counter) bit 31 bit 0 [Initial Value] XXXXXXXXH The program counter contains the address of the instruction currently being executed. The initial value after a reset is indeterminate. • TBR (Table Base Register) bit 31 bit 0 [Initial Value] 000FFC00H The table base register contains the start address of the vector table used for servicing EIT events. The initial value after a reset is 000FFC00H. • RP (Return Pointer) bit 31 bit 0 [Initial Value] XXXXXXXXH The return pointer contains the address to which to return from a subroutine. When the CALL instruction is executed, the value in the PC is transferred to the RP. When the RET instruction is executed, the value in the RP is transferred to the PC. The initial value after a reset is indeterminate. • SSP (System Stack Pointer) bit 31 bit 0 [Initial Value] 00000000H The SSP is the system stack pointer. The SSP functions as R15 when the S flag is “0”. The SSP can be explicitly specified. The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event occurs. The initial value after a reset is 00000000H. 29 MB91314A Series • USP (User Stack Pointer) bit31 bit0 [Initial Value] XXXXXXXXH The USP is the user stack pointer. The USP functions as R15 when the S flag is “1”. The USP can be explicitly specified. The initial value after a reset is indeterminate. This pointer cannot be used by the RETI instruction. • MDH, MDL (Multiply & Divide result register) bit 31 MDH MDL bit 0 These registers hold the results of a multiplication or division. Each of them is 32-bit long. The initial value after a reset is indeterminate. 30 MB91314A Series ■ MODE SETTINGS The FR family sets the operation mode using mode pins (MD2, MD1, and MD0) and a mode register (MODR). 1. Mode Pins The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed. Mode Pins Mode name Reset vector access area MD2 MD1 MD0 0 0 0 Internal ROM mode vector Internal Note: Values other than those listed in the table are prohibited. 2. Mode Register (MODR) • Detailed explanation of register MODR 0007FDH bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 1 bit 1 WTH1 bit 0 WTH0 [Initial Value] XXXXXXXXB Operation mode setting bits Data written to the mode register by mode vector fetch is referred to as mode data. When the mode register is set, the operation mode set in this register is used for operation. The mode register is set when any reset source occurs. Mode data cannot be written by the user program. Note : Conventionally, the address (000007FFH) of the mode register for the FR family holds nothing. The register can be updated in emulator mode. In this case, please use the instruction of the data transfer for the 8-bit length. Any 16/32-bit length transfer instruction cannot be used to write data to the mode register. • Detailed explanation of mode data bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 1 bit 1 WTH1 bit 0 WTH0 [Initial Value] XXXXXXXXB Operation mode setting bits [bit 7 to bit 2] Reserved bits Be sure to set these bits to “000001B”. Setting the bits to any value other than “000001B” may result in an unpredictable operation. 31 MB91314A Series [bit 1, bit 0] WTH1, WTH0 (bus width setting bits) Used to set the bus width to be used in external bus mode. When the operation mode is the external bus mode, this value is set in bits BW1 and BW0 in AMD0 (CS0 area). WTH1 WTH0 Function Remarks 0 0 1 1 0 1 0 1 8-bit bus width 16-bit bus width ⎯ Single chip mode External bus mode External bus mode Setting disabled Single chip mode 32 MB91314A Series ■ MEMORY SPACE 1. Memory space The FR family has 4 Gbytes of logical address space (232 addresses) linearly accessible to the CPU. Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The direct area varies depending on the size of data to be accessed as follows: → Byte data access → Word data access : 000H to 0FFH : 000H to 3FFH → Half word data access : 000H to 1FFH 2. Memory Map Single chip mode Internal ROM external bus mode I/O I/O 0000 0000H I/O 0000 0400H I/O 0001 0000H 0003 8000H Direct addressing area Refer to “ ■ I/O Map”. Access disallowed Internal RAM 32 Kbytes 0004 0000H Access disallowed Internal RAM 32 Kbytes Access disallowed External area Access disallowed 0005 0000H 0008 0000H 0010 0000H 0020 0000H 007F FFFFH FFFF FFFFH Internal Flash 512 Kbytes Access disallowed Internal Flash 512 Kbytes Access disallowed External area Access disallowed (MB91F314) 33 MB91314A Series Single chip mode Internal ROM external bus mode I/O I/O 0000 0000H I/O 0000 0400H I/O 0001 0000H 0003 8000H Direct addressing area Refer to “ ■ I/O Map”. Access disallowed Internal RAM 32 Kbytes 0004 0000H Access disallowed Internal RAM 32 Kbytes Access disallowed External area Access disallowed 0005 0000H 0008 0000H Mask ROM 256 Kbytes 000C 0000H 0020 0000H 007F FFFFH FFFF FFFFH Mask ROM 256 Kbytes Access disallowed External area Access disallowed Access disallowed (MB91314A) 34 MB91314A Series ■ I/O MAP The following table shows the correspondence between the memory space area and each register of the peripheral resource. [How to read the table] Address Register +0 PDR0 [R/W] XXXXXXXX +1 PDR1 [R/W] XXXXXXXX Read/Write attribute Initial value after a reset Register name (First-column register at address 4n; second-column register at address 4n + 1) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data. Note : The bit values in the register represent the following initial values: • “1” : initial values“1” • “0” : initial values“0” • “X” : initial values“X” • “-” : No physical register at this location Access is barred with an undefined data access attribute. +2 PDR2 [R/W] XXXXXXXX +3 PDR3 [R/W] XXXXXXXX Block T-unit Port data register 000000H 35 MB91314A Series Address 000000H 000004H 000008H 00000CH 000010H to 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H 000038H to 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H Register 0 PDR0 [R/W] B, H XXXXXXXX PDR4 [R/W] B, H XXXXXXXX PDRC [R/W] B, H XXXXXXXX 1 PDR1 [R/W] B, H XXXXXXXX PDR5 [R/W] B, H XXXXXXXX ⎯ PDRD [R/W] B, H XXXXXXXX ⎯ ADCTH[R/W] XXXXXX00 ADCTL[R/W] 00000X00 ADCH[R/W] 00000000 00000000 ADAT1[R] XXXXXX00 00000000 ADAT3[R] XXXXXX00 00000000 ADAT5[R] XXXXXX00 00000000 ADAT7[R] XXXXXX00 00000000 ADAT9[R] XXXXXX00 00000000 ⎯ EIRR0 [R/W] 00000000 DICR [R/W] 00000000 ENIR0 [R/W] 00000000 HRCL [R, R/W] 0--11111 ELVR0 [R/W] 00000000 00000000 ⎯ TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R, RW] 00000000 00000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R, RW] 00000000 00000000 PDRE [R/W] B, H XXXXXXXX ⎯ 2 PDR2 [R/W] B, H XXXXXXXX PDR6 [R/W] B, H --XXXXXX 3 PDR3 [R/W] B, H XXXXXXXX ⎯ Block Port data register Reserved ADAT0[R] XXXXXX00 00000000 ADAT2[R] XXXXXX00 00000000 ADAT4[R] XXXXXX00 00000000 ADAT6[R] XXXXXX00 00000000 ADAT8[R] XXXXXX00 00000000 10-bit A/D converter Reserved Ext. INT 0 to INT7 DLY / I-unit TMRLR0 [W] XXXXXXXX XXXXXXXX ⎯ TMRLR1 [W] XXXXXXXX XXXXXXXX ⎯ Reload timer 0 Reload timer 1 (Continued) 36 MB91314A Series Address 000058H 00005CH 000060H 000064H 000068H 00006CH Register 0 1 2 3 TMRLR2 [W] XXXXXXXX XXXXXXXX ⎯ SCR0 [R, R/W] 0--00000 SMR0 [W, R/W] 00000000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R, RW] 00000000 00000000 SSR0 [R, R/W] 0-000011 BGR01 [R/W] 00000000 FCR01 [R/W] 00000000 ⎯ SSR1 [R, R/W] 0-000011 BGR11 [R/W] 00000000 FCR11 [R/W] 00000000 ⎯ SSR2 [R, R/W] 0-000011 BGR21 [R/W] 00000000 FCR21 [R/W] 00000000 ⎯ SSR3 [R, R/W] 0-000011 BGR31 [R/W] 00000000 ⎯ ⎯ ESCR3/IBSR3 [R/W] --000000 BGR30 [R/W] 00000000 ESCR2/IBSR2 [R/W] --000000 BGR20 [R/W] 00000000 FCR20 [R/W] 00000000 ESCR1/IBSR1 [R/W] --000000 BGR10 [R/W] 00000000 FCR10 [R/W] 00000000 ESCR0 [R/W] --000000 BGR00 [R/W] 00000000 FCR00 [R/W] 00000000 Block Reload timer 2 RDR0/TRD0 [R/W] -------0 00000000 ISMK0 [R/W] 01111110 FBYTE01 [R/W] 00000000 SCR1/IBCR1 [R, R/W] 0--00000 IBSA [R/W] 00000000 FBYTE00 [R/W] 00000000 SMR1 [W, R/W] 00000000 Multi function Serial interface 0 FIFO0 000070H 000074H 000078H 00007CH RDR1/TRD1 [R/W] -------0 00000000 ISMK1 [R/W] 01111110 FBYTE11 [R/W] 00000000 SCR2/IBCR2 [R, R/W] 0--00000 IBSA1 [R/W] 00000000 FBYTE10 [R/W] 00000000 SMR2 [W, R/W] 00000000 Multi function Serial interface 1 FIFO1 000080H 000084H 000088H 00008CH RDR2/TRD2 [R/W] -------0 00000000 ISMK2 [R/W] 01111110 FBYTE21 [R/W] 00000000 SCR3/IBCR3 [R, R/W] 0--00000 IBSA2 [R/W] 00000000 FBYTE20 [R/W] 00000000 SMR3 [W, R/W] 00000000 Multi function Serial interface 2 000090H 000094H 000098H 00009CH RDR3/TRD3 [R/W] -------0 00000000 ISMK3 [R/W] 01111110 IBSA3 [R/W] 00000000 Multi function Serial interface 3 (Continued) 37 MB91314A Series Address Register 0 SCR4/IBCR4 [R, R/W] 0--00000 1 SMR4 [W, R/W] 00000000 2 SSR4 [R, R/W] 0-000011 BGR41 [R/W] 00000000 ⎯ ⎯ SCR5/IBCR5 [R, R/W] 0--00000 SMR5 [W, R/W] 00000000 SSR5 [R, R/W] 0-000011 BGR51 [R/W] 00000000 ⎯ ⎯ EIRR1 [R/W] 00000000 EIRR2 [R/W] 00000000 ENIR1 [R/W] 00000000 ENIR2 [R/W] 00000000 ⎯ PWCCL[R/W] 0000--00 PWCCH[R/W] 00-00000 ⎯ ⎯ ELVR1 [R/W] 00000000 00000000 ELVR2 [R/W] 00000000 00000000 ESCR5/IBSR5 [R/W] --000000 BGR50 [R/W] 00000000 3 ESCR4/IBSR4 [R/W] --000000 BGR40 [R/W] 00000000 Block 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H RDR4/TRD4 [R/W] -------0 00000000 ISMK4 [R/W] 01111110 IBSA4 [R/W] 00000000 Multi function Serial interface 4 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H to 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H to 0000ECH 0000F0H 0000F4H RDR5/TRD5 [R/W] -------0 00000000 ISMK5 [R/W] 01111110 IBSA5 [R/W] 00000000 Multi function Serial interface 5 Ext. INT 8 to INT15 Ext. INT 16 to INT23 Reserved PWCD[R] XXXXXXXX XXXXXXXX PWCC2[R/W] 000----Reserved PWC ⎯ ⎯ ⎯ Reserved T0TCR [R/W] 00000000 T0R [R/W] ---00000 PWCUD[R/W] XXXXXXXX XXXXXXXX T0LPCR [R/W] -----000 T0CCR [R/W] 0-010000 T0DRR [R/W] XXXXXXXX XXXXXXXX T0CRR [R/W] XXXXXXXX XXXXXXXX Multifunction timer (Continued) 38 MB91314A Series Address 0000F8H 0000FCH 000100H 000104H 000108H 00010CH 000110H 000114H to 00011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H to 000144H 000148H 00014CH Register 0 T1LPCR [R/W] -----000 1 T1CCR [R/W] 0-000000 2 T1TCR [R/W] 00000000 3 T1R [R/W] ---00000 Block T1DRR [R/W] XXXXXXXX XXXXXXXX T2LPCR [R/W] -----000 T2CCR [R/W] 0-000000 T1CRR [R/W] XXXXXXXX XXXXXXXX T2TCR [R/W] 00000000 T2R [R/W] ---00000 Multifunction timer T2DRR [R/W] XXXXXXXX XXXXXXXX T3LPCR [R/W] -----000 T3CCR [R/W] 0-000000 T2CRR [R/W] XXXXXXXX XXXXXXXX T3TCR [R/W] 00000000 T3R [R/W] ---00000 T3DRR [R/W] XXXXXXXX XXXXXXXX TMODE [R/W] -------- -----0-⎯ PDUT0[W] XXXXXXXX XXXXXXXX PTMR0[R] 11111111 11111111 PDUT1[W] XXXXXXXX XXXXXXXX PTMR1[R] 11111111 11111111 PDUT2[W] XXXXXXXX XXXXXXXX PTMR2[R] 11111111 11111111 PDUT3[W] XXXXXXXX XXXXXXXX PTMR3[R] 11111111 11111111 ⎯ TMRLR3 [W] XXXXXXXX XXXXXXXX ⎯ T3CRR [R/W] XXXXXXXX XXXXXXXX ⎯ Reserved PCSR0[W] XXXXXXXX XXXXXXXX PCNH0[R/W] 00000000 PCNL0[R/W] 00000000 PPG0 PCSR1[W] XXXXXXXX XXXXXXXX PCNH1[R/W] 00000000 PCNL1[R/W] 00000000 PPG1 PCSR2[W] XXXXXXXX XXXXXXXX PCNH2[R/W] 00000000 PCNL2[R/W] 00000000 PPG2 PCSR3[W] XXXXXXXX XXXXXXXX PCNH3[R/W] 00000000 PCNL3[R/W] 00000000 PPG3 Reserved TMR3 [R] XXXXXXXX XXXXXXXX TMCSR3 [R, RW] 00000000 00000000 Reload timer 3 (Continued) 39 MB91314A Series Address 000150H 000154H 000158H 00015CH 000160H to 00019CH 0001A0H 0001A4H 0001A8H to 0001ACH 0001B0H Register 0 1 2 3 TMRLR4 [W] XXXXXXXX XXXXXXXX ⎯ TMRLR5 [W] XXXXXXXX XXXXXXXX ⎯ ⎯ PLLREG0[R/W] H ---00000 ---00000 PLLREG2[R/W] H -------- 0000--0⎯ SCR6/IBCR6 [R, R/W] 0--00000 SMR6 [W, R/W] 00000000 SSR6 [R, R/W] 0-000011 BGR61 [R/W] 00000000 ⎯ ⎯ SCR7/IBCR7 [R, R/W] 0--00000 SMR7 [W, R/W] 00000000 SSR7 [R, R/W] 0-000011 BGR71 [R/W] 00000000 ⎯ ⎯ SCR8/IBCR8 [R, R/W] 0--00000 SMR9 [W, R/W] 00000000 SSR8 [R, R/W] 0-000011 BGR81 [R/W] 00000000 ⎯ ⎯ ESCR8/IBSR8 [R/W] --000000 BGR80 [R/W] 00000000 ESCR7/IBSR7 [R/W] --000000 BGR70 [R/W] 00000000 ESCR6/IBSR6 [R/W] --000000 BGR60 [R/W] 00000000 PLLREG1[R/W] H ----0000 00000000 PLLREG3[R/W] H 0000---- ----00-0 TMR4 [R] XXXXXXXX XXXXXXXX TMCSR4 [R, RW] 00000000 00000000 TMR5 [R] XXXXXXXX XXXXXXXX TMCSR5 [R, RW] 00000000 00000000 Block Reload timer 4 Reload timer 5 Reserved PLL of high multiplication Reserved 0001B4H 0001B8H 0001BCH 0001C0H RDR6/TRD6 [R/W] -------0 00000000 ISMK6 [R/W] 01111110 IBSA6 [R/W] 00000000 Multi function Serial interface 6 0001C4H 0001C8H 0001CCH 0001D0H RDR7/TRD7 [R/W] -------0 00000000 ISMK7 [R/W] 01111110 IBSA7 [R/W] 00000000 Multi function Serial interface 7 0001D4H 0001D8H 0001DCH 40 RDR8/TRD8 [R/W] -------0 00000000 ISMK8 [R/W] 01111110 IBSA8 [R/W] 00000000 Multi function Serial interface 8 (Continued) MB91314A Series Address Register 0 SCR9/IBCR9 [R, R/W] 0--00000 1 SMR9 [W, R/W] 00000000 2 SSR9 [R, R/W] 0-000011 BGR91 [R/W] 00000000 ⎯ ⎯ SCRA/IBCRA [R, R/W] 0--00000 SMRA [W, R/W] 00000000 SSRA [R, R/W] 0-000011 BGRA1 [R/W] 00000000 ⎯ ⎯ DMACA0 [R/W] 00000000 00000000 00000000 00000000 DMACB0 [R/W] 00000000 00000000 00000000 00000000 DMACA1 [R/W] 00000000 00000000 00000000 00000000 DMACB1 [R/W] 00000000 00000000 00000000 00000000 DMACA2 [R/W] 00000000 00000000 00000000 00000000 DMACB2 [R/W] 00000000 00000000 00000000 00000000 DMACA3 [R/W] 00000000 00000000 00000000 00000000 DMACB3 [R/W] 00000000 00000000 00000000 00000000 DMACA4 [R/W] 00000000 00000000 00000000 00000000 DMACB4 [R/W] 00000000 00000000 00000000 00000000 ⎯ DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX ESCRA/IBSRA [R/W] --000000 BGRA0 [R/W] 00000000 3 ESCR9/IBSR9 [R/W] --000000 BGR90 [R/W] 00000000 Block 0001E0H 0001E4H 0001E8H 0001ECH 0001F0H RDR9/TRD9 [R/W] -------0 00000000 ISMK9 [R/W] 01111110 IBSA9 [R/W] 00000000 Multi function Serial interface 9 0001F4H 0001F8H 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H RDRA/TRDA [R/W] -------0 00000000 ISMKA [R/W] 01111110 IBSAA [R/W] 00000000 Multi function Serial interface 10 DMAC Reserved DMAC (Continued) 41 MB91314A Series Address 000244H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H to 00041CH 000420H 000424H 000428H 00042CH 000430H 000434H to 00043CH Register 0 1 ⎯ BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0 [R/W] B, H 00000000 DDR4 [R/W] B, H 00000000 DDRC [R/W] B, H 00000000 DDR1 [R/W] B, H 00000000 DDR5 [R/W] B, H 00000000 ⎯ DDRD [R/W] B, H 00000000 ⎯ ⎯ PFR0 [R/W] B, H 00000000 PFR4 [R/W] B, H 00000000 PFRC [R/W] B, H 00000000 PFR1 [R/W] B, H 00000000 PFR5 [R/W] B, H 00000000 ⎯ PFRD [R/W] B, H 00000000 ⎯ ⎯ PFRE [R/W] B, H 00000000 ⎯ PFR2 [R/W] B, H 00000000 PFR6 [R/W] B, H --000000 PFR3 [R/W] B, H 00000000 ⎯ DDRE [R/W] B, H 00000000 ⎯ DDR2 [R/W] B, H 00000000 DDR6 [R/W] B, H --000000 DDR3 [R/W] B, H 00000000 ⎯ 2 3 Block Reserved Bit search Data direction register Reserved Port function register Reserved (Continued) 42 MB91314A Series Address 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H 000484H 000488H 00048CH Register 0 ICR00 [R, R/W] ---11111 ICR04 [R, R/W] ---11111 ICR08 [R, R/W] ---11111 ICR12 [R, R/W] ---11111 ICR16 [R, R/W] ---11111 ICR20 [R, R/W] ---11111 ICR24 [R, R/W] ---11111 ICR28 [R, R/W] ---11111 ICR32 [R, R/W] ---11111 ICR36 [R, R/W] ---11111 ICR40 [R, R/W] ---11111 ICR44 [R, R/W] ---11111 1 ICR01 [R, R/W] ---11111 ICR05 [R, R/W] ---11111 ICR09 [R, R/W] ---11111 ICR13 [R, R/W] ---11111 ICR17 [R, R/W] ---11111 ICR21 [R, R/W] ---11111 ICR25 [R, R/W] ---11111 ICR29 [R, R/W] ---11111 ICR33 [R, R/W] ---11111 ICR37 [R, R/W] ---11111 ICR41 [R, R/W] ---11111 ICR45 [R, R/W] ---11111 ⎯ RSRR [R, R/W] 10000000 CLKR [R/W] 00000000 ⎯ WPCR [R/W] B 00---000 OSCR [R/W] 00000000 OSCT [R/W] XXXXXXXX ⎯ STCR [R/W] 00110011 WPR [W] XXXXXXXX TBCR [R/W] 00XXXX00 DIVR0 [R/W] 00000011 OSCCR [R/W] XXXXXXXX ⎯ ⎯ CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000 ⎯ 2 ICR02 [R, R/W] ---11111 ICR06 [R, R/W] ---11111 ICR10 [R, R/W] ---11111 ICR14 [R, R/W] ---11111 ICR18 [R, R/W] ---11111 ICR22 [R, R/W] ---11111 ICR26 [R, R/W] ---11111 ICR30 [R, R/W] ---11111 ICR34 [R, R/W] ---11111 ICR38 [R, R/W] ---11111 ICR42 [R, R/W] ---11111 ICR46 [R, R/W] ---11111 3 ICR03 [R, R/W] ---11111 ICR07 [R, R/W] ---11111 ICR11 [R, R/W] ---11111 ICR15 [R, R/W] ---11111 ICR19 [R, R/W] ---11111 ICR23 [R, R/W] ---11111 ICR27 [R, R/W] ---11111 ICR31 [R, R/W] ---11111 ICR35 [R, R/W] ---11111 ICR39 [R, R/W] ---11111 ICR43 [R, R/W] ---11111 ICR47 [R, R/W] ---11111 Block Interrupt control unit Reserved Clock control unit Clock Timer Main clock oscillation waits until stable timer Reserved (Continued) 43 000490H 000494H to 0004FCH MB91314A Series Address 000500H 000504H 000508H to 000510H 000514H to 00051CH 000520H 000524H 000528H 00052CH 000530H 000534H to 00056CH 000570H 000574H 000578H 00057CH to 00063CH 000640H 000644H 000648H Register 0 PCR0 [R/W] B, H 00000000 ⎯ 1 PCR1 [R/W] B, H 00000000 PCR5 [R/W] B, H 00000000 ⎯ PCR6 [R/W] B, H --000000 2 ⎯ ⎯ 3 Block Port Pull-up control register ⎯ EPFR0 [R/W] B, H EPFR1 [R/W] B, H EPFR2 [R/W] B, H 00000000 00000000 11111111 EPFR4 [R/W] B, H EPFR5 [R/W] B, H EPFR6 [R/W] B, H 11111111 11111111 --001000 ⎯ EPFRC [R/W] B, H EPFRD [R/W] B, H EPFRE [R/W] B, H 00000000 00000000 00000000 ⎯ ⎯ ADER[R/W] H 00000000 00000000 ⎯ NSF[R/W] -----000 00000000 ⎯ ASR0 [R/W] 00000000 00000000 ASR1 [R/W] XXXXXXXX XXXXXXXX ASR2 [R/W] XXXXXXXX XXXXXXXX ACR0 [R/W] 1111XX00 00000000 ACR1 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX ⎯ ⎯ ⎯ EPFR3 [R/W] B, H 11111111 ⎯ Reserved Extend Port Control Register Special Port Function Register Reserved EXT/I2C/ A/D converter Reserved I2C noise filter Reserved T-Unit (Continued) 44 MB91314A Series Address 00064CH 000650H to 00065CH 000660H 000664H 000668H to 00067CH 000680H 000684H 000688H to 0007F8H 0007FCH 000800H to 000AFCH 000B00H 000B04H 000B08H 000B0CH 000B10H Register 0 1 2 3 ASR3 [R/W] XXXXXXXX XXXXXXXX ⎯ AWR0 [R/W] B, H, W 01111111 11111111 AWR2 [R/W] B, H, W XXXXXXXX XXXXXXXX ⎯ CSER[R/W]B, H, W 00000001 ⎯ ⎯ ⎯ MODR [W] XXXXXXXX ⎯ ESTS0 [R/W] B X0000000 ECTL0 [R/W] B 0X000000 ECNT0 [W] B XXXXXXXX ESTS1 [R/W] B XXXXXXXX ECTL1 [R/W] B 00000000 ECNT1 [W] B XXXXXXXX ESTS2 [R] B 1XXXXXXX ECTL2 [W] B 000X0000 EUSA [W] B XXX00000 ⎯ ECTL3 [R/W] B 00X00X11 EDTC [W] B 0000XXXX ⎯ ⎯ AWR1 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR3 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX Block T-Unit Unused ⎯ Unused DSU EWPT [R] H 00000000 00000000 EDTR0 [W] H XXXXXXXX XXXXXXXX ECTL4[R]([R/W])B ECTL5[R]([R/W])B -0X00000 ----000X EDTR1 [W] H XXXXXXXX XXXXXXXX (Continued) 45 MB91314A Series Address 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H 000B64H Register 0 1 ⎯ EIA0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTM [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 2 3 Block DSU (Continued) 46 MB91314A Series (Continued) Address 000B68H 000B6CH 000B70H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 006FFCH 007000H 007004H FLCR[R/W] 01101000 FLWC[R/W] 00110011 Register 0 1 2 3 EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ⎯ DMASA0 [R/W] 00000000 00000000 00000000 00000000 DMADA0 [R/W] 00000000 00000000 00000000 00000000 DMASA1 [R/W] 00000000 00000000 00000000 00000000 DMADA1 [R/W] 00000000 00000000 00000000 00000000 DMASA2 [R/W] 00000000 00000000 00000000 00000000 DMADA2 [R/W] 00000000 00000000 00000000 00000000 DMASA3 [R/W] 00000000 00000000 00000000 00000000 DMADA3 [R/W] 00000000 00000000 00000000 00000000 DMASA4 [R/W] 00000000 00000000 00000000 00000000 DMADA4 [R/W] 00000000 00000000 00000000 00000000 ⎯ ⎯ Flash I/F ⎯ Reserved Block DSU Reserved DMAC 47 MB91314A Series ■ VECTOR TABLE Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction System reserved System reserved Step trace trap NMI request (tool) Undefined instruction exception System reserved External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0 RX/I2C states UART0 TX UART1 RX/I C states UART1 TX UART2 RX/I2C states UART2 TX UART3 RX/TX/I C states 2 2 Interrupt number Decimal Hexadecimal Interrupt level ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH 378H TBR default DMA transfer address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DMAC STOP factor 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 STOP STOP STOP (Continued) 48 MB91314A Series Interrupt source UART4 RX/TX/I2C states UART5 RX/TX/I2C states UART6 RX/TX/I C states UART7 RX/TX/I C states UART8 RX/TX/I2C states UART9 RX/TX/I2C states UART10 RX/TX/I C states A/D converter PPG0 PWC CCD Watch timer Main oscillation wait Timebase timer Reload timer 3 Reload timer 4 Reload timer 5 PPG1 PPG2 PPG3 DMA0 DMA1 DMA2 DMA3 DMA4 External interrupt 8 to 15 External interrupt 16 to 23 Multi-function timer 0, 1 Multi-function timer 2, 3 Delay interrupt source bit System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved 2 2 2 Interrupt number Decimal Hexadecimal Interrupt level ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 ⎯ ⎯ ⎯ Offset 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H TBR default DMA transfer address 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DMAC STOP factor 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 (Continued) 49 MB91314A Series (Continued) Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction Interrupt number Decimal Hexadecimal Interrupt level ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Offset 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H TBR default DMA transfer address 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DMAC STOP factor 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF 50 MB91314A Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage Analog power supply voltage Input voltage Analog pin input voltage Output voltage Storage temperature Symbol VDDE (3.3 V) VDDI (1.8 V) AVCC VI VIA VO Tstg Rating Min Vss − 0.5 Vss − 0.3 Vss − 0.5 Vss − 0.5 Vss − 0.5 Vss − 0.5 Vss − 0.5 − 40 Max Vss + 4.0 Vss + 2.5 Vss + 4.0 Vcc + 0.5 Vss + 6.0 AVcc + 0.5 Vcc + 0.5 + 125 Unit V V V V V V V °C 5 V tolerant pin Remarks WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 2. Recommended Operating Conditions Parameter Operating temperature Power supply voltage Analog power supply voltage 5 V tolerant pin input voltage Symbol Ta VDDE (3.3 V) VDDI (1.8 V) AVCC VI Value Min − 10 3.0 1.65 3.0 ⎯ Max + 70 3.6 1.95 VDDE VSS + 5.5 Unit °C V V V WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 51 MB91314A Series 3. DC Characteristics (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter Symbol Pin name ⎯ ICCT ⎯ ⎯ ICC ⎯ ⎯ ICCS ⎯ ⎯ ICCL ⎯ ⎯ ICCH ⎯ ⎯ ⎯ P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57, P60 to P65, PD0 to PD7, PE0, PE1 PE2 to PE7, PC0 to PC7, P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57, P60 to P65, PD0 to PD7, PE0, PE1, HSYNC PE2 to PE7, PC0 to PC7, P40 to P47 “H” level output voltage “L” level output voltage VOH VOL P00 to PE1 P00 to PE1 VDDE = 3.3 V, IOH = − 4 mA VDDE = 3.3 V, IOL = 4 mA Conditions Clock mode Ta = + 25 °C, fclk = 32 kHz During normal operation Ta = + 25 °C, fcp = 33 MHz, fcpp = 33 MHz Main sleep mode Ta = + 25 °C, fcp = 33 MHz, fcpp = 33 MHz Sub RUN mode Ta = + 25 °C, fclk = 32 kHz Main Stop mode Ta = + 25 °C, fclk = 0 Ta = + 70 °C, fclk = 0 Value Min ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VDDE × 0.8 VDDE = 3.3 V VDDE × 0.7 ⎯ VDDE V Typ 300 700 100 70 60 60 400 900 160 40 900 240 ⎯ Max 700 1000 120 100 80 90 1000 1300 600 80 4000 400 µA µA µA mA mA µA Unit Current Consumption (upper : 1.8 V lower : 3.3 V) “H” level input voltage VDDE V VIH “L” level input voltage VSS VDDE = 3.3 V VSS VDDE − 0.5 VSS ⎯ VDDE × 0.2 V VIL ⎯ ⎯ ⎯ VDDE × 0.3 VDDE 0.4 V V V (Continued) 52 MB91314A Series (Continued) (Ta = −10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V) Symbol Pin name Other than PD0 to PD7, PE0, PE1 PD0 to PD7, PE0, PE1 I2C bus switch connection resistance Between P21 and P24 Between P22 and P25 Between P24 and P27 Between P25 and P30 ⎯ Conditions Value Min −5 − 10 ⎯ Typ ⎯ ⎯ ⎯ Max +5 + 10 130 Unit µA µA Ω Parameter Input leak current IIL ⎯ RBS 53 MB91314A Series 4. AC Characteristics (1) Clock Timing (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter Symbol Pin name Conditions Value Min Typ Max Unit Remarks Clock frequency fC X0, X1 ⎯ 10 16.5 33 PLL clock (self-oscillation 16.5 MHz doubled via MHz PLL : internal operation at 33 MHz max.) kHz MHz CPU MHz Peripheral MHz External bus Sub clock frequency Internal operating clock frequency fclk fCP fCPP fCPT X0A, X1A ⎯ ⎯ ⎯ ⎯ 32.768 ⎯ ⎯ ⎯ ⎯ 33 33 16.5 ⎯ ⎯ ⎯ (2) Clock Output Timing (VDDE = AVCC = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = AVSS = 0 V, Ta = −10 °C to + 70 °C) Parameter Cycle time CLK ↑ → CLK ↓ CLK ↓ → CLK ↑ Symbol tCYC tCHCL tCLCL Pin name CLK CLK CLK ⎯ Conditions Value Min 60.7 1/2 × tCYC − 3 1/2 × tCYC − 3 Max ⎯ 1/2 × tCYC + 3 1/2 × tCYC + 3 Unit Remarks ns ns ns *1 *2 *3 *1 : tCYC is the frequency of one clock cycle after gearing. *2 : The following ratings are for the gear ratio set to × 1. For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation. (1/2 × 1/n) × tCYC − 10 *3 : The following rating are for the gear ratio set to × 1. tCYC tCHCL VOH tCLCL VOH CLK VOL (3) PLL Oscillation Stabilization Wait Time (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter PLL oscillation stabilization wait time 54 Symbol tLOCK Value Min 600 Max ⎯ Unit µs Remarks The length of time to wait for the PLL oscillations to stabilize. MB91314A Series (4) Reset Input (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter INIT input time (at power-on) INIT input time (other than power-on) INIT input time (Stop recovery time) tINTL INIT ⎯ Symbol Pin name Conditions Value Min Oscillation stabilization delay time of oscillator + tcp × 10 tcp × 10 Oscillation stabilization delay time of oscillator + tcp × 10 Max ⎯ ⎯ ⎯ Unit µs ns µs tINTL INIT 0.2 VCC 55 MB91314A Series (5) Multiplex Bus Access Read/Write Operation (VDDE = AVCC = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = AVSS = 0 V, Ta = −10 °C to + 70 °C) Parameter CS0 to CS3 setup D31 to D16 address setup time → CLK ↑ CLK ↑→ D31 to D16 address hold time D31 to D16 address setup time → AS ↑ AS ↑→ D31 to D16 address hold time WR0, WR1 delay time WR0, WR1 delay time WR0, WR1 minimum pulse width Data setup → WRx ↑ WRx ↑ → Data hold time RD delay time RD delay time RD ↓ → Valid data input time Data setup → RD ↑ Time RD ↑ → Data hold time RD minimum pulse width AS setup AS hold Symbol tCSLCH Pin name CLK CS0 to CS3 Conditions Value Min 3 Max ⎯ ⎯ Unit ns Remarks tASCH tCHAX CLK D31 to D16 (Address) 3 ns 3 tCYC / 2 + 6 ns tASASH tASHAX tCHWL tCHWH tWLWH tDSWH tWHDX tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tASLCH tASHCH AS D31 to D16 (Address) 12 ⎯ ns *1 tCYC − 3 ⎯ ⎯ ⎯ tCYC − 3 tCYC 5 ⎯ ⎯ ⎯ tCYC + 3 6 6 ⎯ ⎯ ⎯ 6 6 tCYC − 15 ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 CLK WR0, WR1 WR0, WR1 WR0, WR1 D15 to D00 CLK RD *2 RD D15 to D00 15 0 RD CLK AS tCYC − 3 3 3 *1 : At CSx → RD/WRx setup extension = 1 *2 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of cycles added for the delay) to this rating. 56 MB91314A Series • At CSx → RD/WRx setup extension = 1 tCYC BA1 BA1W BA2 BA3 CLK tASLCH tASHCH AS tASASH tCSLCH tASHAX CS0 to CS3 tASCH tCHAX D15 to D00 Address Read data tDSRH tRLDV tRHDX RD tRLRH tCHRL tCHRH D15 to D00 Address Write data tDSWH tWHDX WR0, WR1 tWLWH tCHWL tCHWH 57 MB91314A Series • At CSx → RD/WRx setup extension = 0 tCYC BA1 BA2 BA3 CLK AS tASLCH tASHCH tCSLCH CS0 to CS3 tASCH tCHAX D15 to D00 Address Read data tDSRH tRLDV tRHDX RD tRLRH tCHRL tCHRH D15 to D00 Address Write data tDSWH tWHDX WR0, WR1 tWLWH tCHWL tCHWH 58 MB91314A Series (6) Ready Input Timings (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter RDY setup time → CLK ↓ CLK ↓ → RDY hold time Symbol tRDYS tRDYH Pin name CLK, RDY CLK, RDY Conditions ⎯ ⎯ Value Min 25 0 Max ⎯ ⎯ Unit ns ns tCYC CLK VOL VOH VOL VOH tRDYS tRDYH tRDYS tRDYH RDY wait applied VOH VOL VOL VOH RDY wait not applied VOH VOL VOH VOL 59 MB91314A Series (7) UART timing (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK0 to SCK10 SCK0 to SCK10 SOT0 to SOT10 SCK0 to SCK10 SIN0 to SIN10 SCK0 to SCK10 SIN0 to SIN10 SCK0 to SCK10 SCK0 to SCK10 SCK0 to SCK10 SOT0 to SOT10 SCK0 to SCK10 SIN0 to SIN10 SCK0 to SCK10 SIN0 to SIN10 External shift clock operation Conditions Value Min 4 tCYCP − 20 Internal shift clock operation 30 20 2 tCYCP 2 tCYCP ⎯ 20 20 Max ⎯ + 20 ⎯ ⎯ ⎯ ⎯ 30 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns Notes : • The above standards apply to the CLK synchronous mode. • tCYCP indicates the peripheral clock cycle time. 60 MB91314A Series • Internal shift clock mode tSCYC SCK0 to SCK10 VOL tSLOV VOH VOL SOT0 to SOT10 VOH VOL tIVSH tSHIX VOH VOL SIN0 to SIN10 VOH VOL • External shift clock mode tSLSH tSHSL VOH VOH SCK0 to SCK10 VOL tSLOV VOL SOT0 to SOT10 VOH VOL tIVSH tSHIX VOH VOL SIN0 to SIN10 VOH VOL 61 MB91314A Series (8) Reload timer clock, PPG timer input, multi-function timer input timing, interrupt input timing (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter Symbol Pin name TIN0 to TIN5 TRG0 to TRG3 TMI0 to TMI3 INT0 to INT23 Note : tCYCP indicates the peripheral clock cycle time. Conditions Value Min 2 tCYCP 3 tCYCP 1.0 Max ⎯ ⎯ ⎯ Unit Remarks ⎯ ⎯ ns ns µs At stop Input pulse width tTIWH tTIWL TIN0 to TIN5 TRG0 to TRG3 TMI0 to TMI3 INT0 to INT23 tTIWH tTIWL (9) Trigger Input Timing (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter A/D activation trigger input time Symbol tATRG Pin name ATRG Conditions ⎯ Value Min 5 tCYCP Max ⎯ Unit ns Note : tCYCP indicates the peripheral clock cycle time. tATRG ATRG 62 MB91314A Series (10) External circuit for data slicer (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter Video signal input level VIN pin coupling capacitor Resistance for clamp VIN pin input resistance VIN lowpass filter capacitor Symbol VVIN CVIN RCL RIN C1 Pin name VIN VIN VIN VIN ⎯ VDDC VSSC ⎯ ⎯ ⎯ Value Min 1.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10 Max 1.5 0.1 1 0 82 Unit Vp-p µF MΩ Ω pF µF kΩ kΩ kΩ Ceramic capacitor with an error of 10% exceeding B-characteristics Error 5% Error 5% Ceramic capacitor with an error of 10% exceeding B-characteristics Ceramic condenser Error 5% Error 5% Error 5% Remarks Power supply bypass capacitor Video signal input buffer resistance Video signal level correction resistance Video signal level correction resistance CBP R1 R2 R3 0.1 2.2 4.7 12 63 MB91314A Series • Input composite video signals are DC-clamped. 3.3 V VDDC 32 CBP 5V VSSC 33 R1 RIN CVIN VIN 34 RCL 2SB709A equivalent R3 C1 R2 Composite video signals (2Vp-p) • Input composite video signals are not DC-clamped. 3.3 V VDDC 32 Add this resistance CBP 5V VSSC 33 R1 RIN CVIN 10 kΩ (Error 5%) VIN 34 RCL 2SB709A equivalent R3 C1 R2 Composite video signals (2Vp-p) External recommended circuit for data slicer 64 MB91314A Series (11) I2C timing • At master mode operating (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter SCL clock frequency “L” period of SCL clock “H” period of SCL clock Bus free time between “STOP condition” and “START condition” SCL ↓ → SDA output delay time Repeated START condition setup time SCL ↑ → SDA ↓ Repeated START condition hold time SDA ↓ → SCL ↓ STOP condition setup time SCL ↑ → SDA ↑ SDA data input hold time (vs. SCL ↓) SDA data input setup time (vs. SCL ↑) Symbol Conditions fSCL tLOW tHIGH tBUS Typical mode Min 0 4.7 4.0 4.7 ⎯ R = 1 kΩ, C = 50 pF*4 4.7 Max 100 ⎯ ⎯ ⎯ 5 × M*1 ⎯ ⎯ ⎯ ⎯ ⎯ High-speed mode*3 Min 0 1.3 0.6 1.3 ⎯ 0.6 Max 400 ⎯ ⎯ ⎯ 5 × M*1 ⎯ ⎯ ⎯ ⎯ ⎯ kHz µs µs µs ns µs µs µs µs ns The first clock pulse is generated after this. Unit Remarks tDLDAT tSUSTA tHDSTA 4.0 0.6 tSUSTO tHDDAT tSUDAT 4.0 2 × M*1 250 0.6 2 × M*1 100*2 65 MB91314A Series • At slave mode operating (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter SCL clock frequency “L” period of SCL clock “H” period of SCL clock SCL ↓ → SDA output delay time Bus free time between “STOP condition” and “START condition” SDA data input hold time (vs. SCL ↓) SDA data input setup time (vs. SCL↑) Repeated START condition setup time SCL ↑ → SDA ↓ Repeated START condition hold time SDA ↓ → SCL ↓ STOP condition setup time SCL ↑ → SDA ↑ Symbol Conditions fSCL tLOW tHIGH tDLDAT Typical mode Min 0 4.7 4.0 ⎯ 4.7 2 × M*1 R = 1 kΩ, C = 50 pF*4 250 Max 100 ⎯ ⎯ 5 × M*1 ⎯ ⎯ ⎯ ⎯ High-speed mode*3 Min 0 1.3 0.6 ⎯ 1.3 2 × M*1 100*2 Max 400 ⎯ ⎯ 5 × M*1 ⎯ ⎯ ⎯ ⎯ kHz µs µs ns µs µs ns µs The first clock pulse is generated after this. Unit Remarks tBUS tHDDAT tSUDAT tSUSTA 4.7 0.6 tHDSTA 4.0 ⎯ ⎯ 0.6 ⎯ ⎯ µs µs tSUSTO 4.0 0.6 *1 : M = Resource clock cycle (ns) *2 : A high-speed mode I2C bus device can be used for a typical mode I2C bus system as long as the device satisfies a requirement of “tSUDAT ≥ 250 ns”. When a certain device does not extend the “L” period of the SCL signal, the next data must be output to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released. *3 : For use at over 100 kHz, set the resource clock to 6 MHz or higher. *4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines, respectively. 66 MB91314A Series 5. Electrical Characteristics for the A/D Converter (1)Electrical Characteristics (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −10 °C to + 70 °C) Parameter Resolution Total error *1 Nonlinear error *1 Differential linear error *1 Zero transition voltage * 1 Full transition voltage*1 Conversion time Power supply current (analog + digital) Reference power supply current (between AVRH and AVRL) Analog input capacitance Interchannel disparity *1 : Measured in the CPU sleep state *2 : Depending on the clock cycle supplied to peripheral resources RIN Value Min ⎯ ⎯ ⎯ ⎯ − 4.0 AVRH − 5.5 7.94*2 ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max 10 ± 5.5 ± 3.5 ± 2.0 + 6.0 AVRH + 3.0 ⎯ 3 100 21 4 Unit bit LSB LSB LSB LSB LSB µs mA µA pF LSB Remarks AVcc = 3.3 V, AVRH = 3.3 V (CPU sleep) AVRH = 3.0 V, AVRL = 0.0 V Comparator AN9 to AN0 Analog input pin CIN RIN = 5 kΩ CIN = 21 pF • The relationship between external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 MB91314A (External impedance = 0 kΩ to 20 kΩ) 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 MB91314A External impedance [kΩ] 20 25 30 35 External impedance [kΩ] 5 6 7 8 Minimum sampling time [µs] Minimum sampling time [µs] 67 MB91314A Series (2) Definition of terms Resolution Linearity error : Analog variation that is recognized by an A/D converter. : The deviation between the actual conversion characteristics and a straight line connecting the device's zero transition point (“0000000000” ←→ “0000000001”) and full scale transition point (“1111111110” ←→ “1111111111”). Differential linear error : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Total error : This error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error Linearity error 3FFH 3FEH {1 LSB' (N − 1) + VOT} 3FDH Actual conversion characteristics Differential linearity error Actual conversion characteristics (N + 1)H Digital output Digital output VFST (measurement value) 004H 003H 002H 001H VNT (measurement value) Actual conversion characteristics Ideal characteristics Ideal characteristics NH (N − 1)H V(N + 1)T (measurement value) VNT (measurement value) Actual conversion characteristics AVRH (N − 2)H VOT (measurement value) AVRH AVSS AVSS Analog input Analog input VNT − {1 LSB' × (N − 1) + VOT} [LSB] 1 LSB' V (N+1) T − VNT Differential linear error in digital output N = −1[LSB] 1 LSB' VFST − VOT 1 LSB = [V] 1022 Linear error in digital output N = N VOT VFST VNT : A/D converter digital output value : A voltage at which digital output transits from (000) H to (001) H : A voltage at which digital output transits from (3FE) H to (3FF) H : A voltage at which digital output transitions from (N−1) H to NH 68 MB91314A Series Total error 3FFH 3FEH 3FDH 1.5 LSB' Actual conversion characteristics {1 LSB' (N - 1) + 0.5 LSB'} Digital output 004H 003H 002H 001H 0.5 LSB' AVSS (measurement value) VNT Actual conversion characteristics Ideal characteristics AVRH Analog input 1LSB' (ideal value) = AVRH − AVSS [V] 1024 VNT − {1 LSB' × (N − 1) + 0.5 LSB'} Total error of digital output N = 1 LSB' N : A/D converter digital output value VNT : A voltage at which digital output transits from (N + 1) H to NH VOT' (ideal value) = AVSS + 0.5 LSB' [V] VFST' (ideal value) = AVRH − 1.5 LSB' [V] 69 MB91314A Series 6. Flash Memory Write/Erase Characteristics (Ta = + 25 °C, VCC = 3.3 V) Parameter Sector erase time Byte write time Chip write time Erase/write cycle Value Min ⎯ ⎯ ⎯ 10000 Typ 0.5 6 1.8 ⎯ Max 2.0 100 29.5 ⎯ Unit s µs s cycle Remarks Excludes internal programming prior erasure. Excludes system-level overhead. Excludes system-level overhead. 70 MB91314A Series ■ ORDERING INFORMATION Part number MB91314APMC-GE1 MB91F314PMC-GE1 Package 120-pin plastic LQFP (FPT-120P-M21) 71 MB91314A Series ■ PACKAGE DIMENSION 120-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 16.0 × 16.0 mm Gullwing Plastic mold 1.70 mm MAX 0.88 g P-LFQFP120-16×16-0.50 (FPT-120P-M21) Code (Reference) 120-pin plastic LQFP (FPT-120P-M21) Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.25(.010) MAX(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 18.00±0.20(.709±.008)SQ * 16.00 –0.10 .630 +.016 SQ –.004 90 61 +0.40 91 60 0.08(.003) Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 0~8˚ 120 31 "A" 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) LEAD No. 1 30 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) M 0.145 .006 +0.05 –0.03 +.002 –.001 0.60±0.15 (.024±.006) C 2002 FUJITSU LIMITED F120033S-c-4-4 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 72 MB91314A Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept. F0705