FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16503-4E
32-bit Microcontroller
CMOS
FR60 MB91350A Series
MB91F355A/F353A/F356B/F357B/355A/354A/ MB91353A/352A/351A/V350A
■ DESCRIPTION
The FR family* is a series of standard single-chip microcontrollers that feature a variety of built-in I/O resources and bus control functions, and that employ a high-performance 32-bit RISC CPU for embedded control applications that demand powerful and fast CPU processing capabilities. This product is one of the FR60 family based on the FR30/40 family CPU with enhanced bus access. The FR60 family is a line of single-chip oriented microcontrollers that incorporate a wealth of peripheral resources. The FR60 family is optimized for embedded control applications that require high CPU processing power, such as DVD players, navigation equipment, high performance fax machines, and printer controllers. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURES
1. FR CPU
32-bit RISC, load/store architecture with a five-stage pipeline Maximum operating frequency : 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz) 16-bit fixed length instructions (basic instructions), 1 instruction per cycle Instruction set optimized for embedded applications : Memory-to-memory transfer, bit manipulation, barrel shift etc. • Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store instructions • Register interlock functions : Facilitate coding in assemblers (Continued) • • • •
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright©2003-2007 FUJITSU LIMITED All rights reserved
MB91350A Series
• On-chip multiplier supported at the instruction level. Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles • Interrupt (PC, PS save) : 6 cycles, 16 priority levels • Harvard architecture allowing program access and data access to be executed simultaneously • Instructions compatible with the FR family
2. Bus interface
• Maximum operating frequency : 25 MHz • 24-bit address full output (16 Mbyte address space) capability (21-bit address full output (2 Mbyte address space) capability : MB91F353A/353A/352A/351A) • 8,16-bit data output • Built-in prefetch buffer • Unused data and address pins can be used as general I/O ports. • Able to output chip-select for 4 completely independent areas that can be configured in units of 64 Kbytes • Support for various memory interfaces : SRAM, ROM/Flash page mode Flash ROM, page mode ROM interface • Basic bus cycle : 2 cycles • Programmable automatic wait cycle generator capable of inserting wait cycles for each area • RDY input for external wait cycles • DMA support of fly-by transfer capable of wait control for independent I/O (The MB91F353A/353A/352A/351A does not support fly-by transfer.)
3. Built-in memory
D-bus memory ROM RAM (Stack) RAM (Execute instruction) MB91F353A MB91353A MB91V350A MB91F355A MB91F356B MB91355A MB91F357B No 16 Kbytes 16 Kbytes 512 Kbytes 16 Kbytes 8 Kbytes 256 Kbytes 16 Kbytes 8 Kbytes 512 Kbytes 16 Kbytes 8 Kbytes MB91352A MB91354A 384 Kbytes 8 Kbytes 8 Kbytes MB91351A 384 Kbytes 16 Kbytes 8 Kbytes
4. DMAC (DMA Controller)
• Capable of simultaneous operation of up to 5 channels (external → external : 3 channels) • 3 transfer sources (external pin, internal peripheral or software) : Activation sources are software-selectable (transfer can be activated by UART0/1/2). • Addressing using 32-bit full addressing mode (increment, decrement, fixed) • Transfer modes (demand transfer, burst transfer, step transfer, block transfer) • Fly-by transfer support (between external I/O and memory) • Selectable transfer data size : 8, 16, or 32-bit • Multi-byte transfer capability (selected by software) • DMAC descriptor in IO areas (200H to 240H, 1000H to 1024H) (The MB91F353A/353A/352A/351A does not have an external interface.) External pin transfer is not supported. Demand transfer and fly-by transfer cannot be used.
5. Bit search module (for REALOS)
• Search a single word starting from the MSB for the position of the first bit changed from 1 to 0. (Continued)
2
MB91350A Series
6. Various timers
• 4 channels of 16-bit reload timer (including 1 channel for REALOS) : Internal clock frequency divider selectable from 2/8/32 (division by 64/128 selectable only for ch.3) • 16-bit free-run timer : 1 channel Output compare : 8 channels (MB91F353A/353A/352A/351A : 2 channels) Input capture : 4 channels • 16-bit PPG timer : 6 channels (MB91F353A/353A/352A/351A : 3 channels)
7. UART
• • • • • • • UART full duplex double buffer : 5 channels (MB91F353A/353A/352A/351A : 4 channels) Selectable parity on/off Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable Built-in dedicated baud rate timer External clock can be used as transfer clock Assorted error detection functions (for parity, frame, and overrun errors) Support for 115 kbps
8. SIO
• 8-bit data serial transfer : 3 channels (MB91F353A/353A/352A/351A : 2 channels) • Shift clock selectable from among three internal and one external • Shift direction selectable (transfer from LSB or MSB)
9. Interrupt controller
• Total number of external interrupts : 17 (MB91F353A/353A/352A/351A : 9) (One non-maskable interrupt pin and 16/8 ordinary interrupt pins that can be used for wakeup in stop mode.) • Interrupts from internal peripherals • Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt
10. D/A converter
• 8-bit resolution : 3 channels (MB91F353A/353A/352A/351A : 2 channels)
11. A/D converter
• • • • 10-bit resolution : 12 channels (MB91F353A/353A/352A/351A : 8 channels) Serial/parallel conversion type Conversion time : 1.48 µs Conversion mode (one shot conversion mode, continuous conversion mode) Activation source (software, external trigger, peripheral interrupt)
12. Other interval timer/counter
• 8/16-bit up/down counter The MB91F353A/353A/352A/351A supports only an 8-bit up/down counter. • 16-bit timer (U-TIMER) : 5 channels (MB91F353A/353A/352A/351A : 4 channels) • Watch dog timer
13. I2C bus interface* (supports 400 kbps)
• 1 channel master/slave transmission and reception • Arbitration and clock synchronization functions
14. I/O ports
• 3 V I/O ports (5 V input is supported for those ports that are also used for external interrupts (16 ports, MB91F353A/353A/ 352A/351A : 8 ports). • Up to 126 ports (MB91F353A/353A/352A/351A : Up to 84 ports) (Continued)
3
MB91350A Series
(Continued)
15. Other features
• Internal oscillator circuit as clock source, and PLL multiplication can be selected • INIT pin provided as a reset pin (the oscillation stabilization wait time when the INIT pin is reset is clock cycle × 2.) • Watch dog timer reset and software reset are also provided. • Support for stop and sleep modes for low power consumption, capable of saving power by operating the CPU at 32 kHz. • Gear function • Built-in time base timer • Package : MB91F355A/F356B/355A/354A/F357B : LQFP-176 (lead pitch 0.50 mm) MB91F353A/353A/352A/351A : LQFP-120 (lead pitch 0.50 mm) • CMOS technology(0.35 µm) • Power supply voltage : 3.3 V ± 0.3 V 2.7 V to 3.6 V (MB91F356B/F357B only) * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
4
MB91350A Series
■ PIN ASSIGNMENTS
• MB91F353A/353A/352A/351A (TOP VIEW)
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS AVSS/AVRL AVRH AVCC DAVC DAVS DA0 DA1 PH5/SCK3 PH4/SO3 PH3/SI3 PH2/SCK2 PH1/SO2 PH0/SI2 PO2/OC2 PO0/OC0 VSS VCC PI5/SCK1 PI4/SO1 PI3/SI1 PI2/SCK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 P40/A00 VSS VCC P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 P50/A08 P51/A09 P52/A10 P53/A11
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PI1/SO0 PI0/SI0 PK7/INT7/ATG PK6/INT6/FRCK PK5/INT5 PK4/INT4 PK3/INT3 PK2/INT2 PK1/INT1 PK0/INT0 PM5/SCK7 PM4/SO7/TRG4 PM3/SI7/TRG3 VCC VSS PM2/SCK6/ZIN0/TRG2 PM1/SO6/BIN0/TRG1 PM0/SI6/AIN0/TRG0 PN4/PPG4 PN2/PPG2 PN0/PPG0 PA3/CS3 PA2/CS2 PA1/CS1 PA0/CS0 P94/AS P93 P91 P90/SYSCLK X1A
P54/A12 P55/A13 P56/A14 P57/A15 P60/A16 P61/A17 P62/A18 P63/A19 P64/A20 VSS PL1/SCL PL0/SDA VSS VCC P80/IN0/RDY P81/IN1/BGRNT P82/IN2/BRQ P83/RD P84/WR0 P85/IN3/WR1 NMI MD2 MD1 MD0 INIT VCC X1 X0 VSS X0A
(FPT-120P-M21)
5
6
MB91350A Series
• MB91F355A/F356B/F357B/355A/354A
PG5/SCK5 NMI X1A VSS X0A MD2 MD1 MD0 X0 VCC X1 INIT VSS VCC PC0/DREQ2 PC1/DACK2 PC2/DSTP2/DEOP2 PB0/DREQ0 PB1/DACK0 PB2/DSTP0/DEOP0 PB3/DREQ1 PB4/DACK1 PB5/DSTP1/DEOP1 PB6/IOWR PB7/IORD PA0/CS0 PA1/CS1 PA2/CS2 PA3/CS3 VSS VCC P80/IN0/RDY P81/IN1/BGRNT P82/IN2/BRQ P83/RD P84/WR0 P85/IN3/WR1 P90/SYSCLK P91 P92/MCLK P93 P94/AS VSS VCC 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
(TOP VIEW)
(FPT-176P-M02)
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 PM1/SO6/BIN0/TRG1 PM0/SI6/AIN0/TRG0 PN5/PPG5 PN4/PPG4 PN3/PPG3 PN2/PPG2 PN1/PPG1 PN0/PPG0 VCC VSS PO7/OC7 PO6/OC6 PO5/OC5 PO4/OC4 PO3/OC3 PO2/OC2 PO1/OC1 PO0/OC0 PP3/TOT3 PP2/TOT2 PP1/TOT1 PP0/TOT0 VCC VSS AVSS/AVRL AVRH AVCC AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 DA2 DA1 DA0 DAVC DAVS
P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 VSS VCC P40/A00 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 P50/A08 P51/A09 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS VCC P60/A16 P61/A17 P62/A18 P63/A19 P64/A20 P65/A21 P66/A22 P67/A23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PG4/SO5 PG3/SI5 PG2/SCK4 PG1/SO4 PG0/SI4 PH5/SCK3 PH4/SO3 PH3/SI3 PH2/SCK2 PH1/SO2 PH0/SI2 PI5/SCK1 PI4/SO1 PI3/SI1 PI2/SCK0 PI1/SO0 PI0/SI0 VCC VSS PJ7/INT15 PJ6/INT14 PJ5/INT13 PJ4/INT12 PJ3/INT11 PJ2/INT10 PJ1/INT9 PJ0/INT8 PK7/INT7/ATG PK6/INT6/FRCK PK5/INT5 PK4/INT4 PK3/INT3 PK2/INT2 PK1/INT1 PK0/INT0 VCC VSS PL1/SCL PL0/SDA VSS PM5/SCK7/ZIN1/TRG5 PM4/SO7/BIN1/TRG4 PM3/SI7/AIN1/TRG3 PM2/SCK6/ZIN0/TRG2
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
MB91350A Series
■ PIN DESCRIPTION
Pin no. LQFP*1 1 to 8 LQFP*2 1 to 8 Pin name D16 to D23 P20 to P27 9 to 16 9 to 16 D24 to D31 P30 to P37 19 to 26 17, 20 to 26 A00 to A07 P40 to P47 27 to 34 27 to 34 A08 to A15 P50 to P57 A16 to A20 37 to 41 35 to 39 P60 to P64 A21 to A23 42 to 44 ⎯ P65 to P67 47, 48 49 50 to 57 58 to 61 106,105 ⎯ 113 to 120 ⎯ DA0, DA1 DA2 AN0 to AN7 AN8 to AN11 TOT0 to TOT3 67 to 70 ⎯ PP0 to PP3 OC0 71 97 PO0 D D ⎯ ⎯ G G C C C C C I/O circuit type*3 C Function Bit 16 to bit 23 of the external data bus. Valid only in external bus mode. Can be used as ports while in external bus 8-bit mode. Bit 24 to bit 31 of the external data bus. Valid only in external bus mode. Can be used as ports while in single-chip mode. Bit 0 to bit 7 of the external address bus. Valid only in external bus mode. Can be used as ports while in single-chip mode. Bit 8 to bit 15 of the external address bus. Valid only in external bus mode. Can be used as ports while in single-chip mode. Bit 16 to bit 20 of the external address bus. Valid only in external bus mode. Can be used as ports while in single-chip mode or when the external address bus is not used. Bit 21 to bit 23 of the external address bus. Valid only in external bus mode. Can be used as ports while in single-chip mode or when the external address bus is not used. D/A converter output pins D/A converter output pin Analog input pins Analog input pins Reload timer output ports. This pin is valid when timer output is enabled. General-purpose I/O ports. This pin is valid when the timer output function is disabled. Output compare output pin General-purpose I/O port. This pin can be used as a port when the output compare output is not used. (Continued)
7
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name OC1 72 ⎯ PO1 OC2 73 98 PO2 OC3 to OC7 74 to 78 ⎯ PO3 to PO7 PPG0 81 70 PN0 PPG1 82 ⎯ PN1 PPG2 83 71 PN2 PPG3 84 ⎯ PN3 PPG4 85 72 PN4 PPG5 86 ⎯ PN5
I/O circuit type*3
Function Output compare output pin
D
General-purpose I/O port. This pin can be used as a port when the output compare output is not used. Output compare output pin General-purpose I/O port. This pin can be used as a port when the output compare output is not used. Output compare output pins General-purpose I/O ports. These pins can be used as ports when the output compare outputs are not used. PPG timer output pin General-purpose I/O port. This pin can be used as a port when the PPG timer output is not used. PPG timer output pin General-purpose I/O port. This pin can be used as a port when the PPG timer output is not used. PPG timer output pin General-purpose I/O port. This pin can be used as a port when the PPG timer output is not used. PPG timer output pin General-purpose I/O port. This pin can be used as a port when the PPG timer output is not used. PPG timer output pin General-purpose I/O port. This pin can be used as a port when the PPG timer output is not used. PPG timer output pin General-purpose I/O port. This pin can be used as a port when the PPG timer output is not used. (Continued)
D
D
D
D
D
D
D
D
8
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name
I/O circuit type*3
Function Data input for serial I/O6. Since this input is always used when serial I/O6 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. Input for the up/down counter. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 0. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This pin can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. Data output from serial I/O6. This function is valid when data output from serial I/O6 is enabled. Input for the up/down counter. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 1. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This pin can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. Clock I/O for serial I/O 6. This function is valid when clock output from serial I/O6 is enabled or when an external shift clock input is used. Input for the up/down counter. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 2. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This pin can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. (Continued)
SI6
AIN0 87 73 TRG0 D
PM0
SO6
BIN0 88 74 TRG1 D
PM1
SCK6
ZIN0 89 75 TRG2 D
PM2
9
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name
I/O circuit type*3
Function Data input for serial I/O7. Since this input is always used when serial I/O7 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. Input for the up/down counter. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 3. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This pin can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. Data output from serial I/O7. This function is valid when data output from serial I/O7 is enabled. Input for the up/down counter. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 4. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This pin can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. Clock I/O for serial I/O7. This function is valid when clock output from serial I/O7 is enabled or when an external shift clock input is used. Input for the up/down counter. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 5. Since this input is always used when input is enabled, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This pin can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. (Continued)
SI7
AIN1* 90 78
4
D TRG3
PM3
S07
BIN1*4 91 79 TRG4 D
PM4
SCK7
ZIN1* 92 80
4
D TRG5*
4
PM5
10
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name
I/O circuit type*3
Function DATA I/O pin for the I2C bus. This pin is valid when standard mode I2C operation is enabled. Output using the port must be stopped beforehand unless this operation is intended (open drain output). General-purpose I/O port. This pin can be used as a port when I2C operation is disabled (open drain output). Clock I/O pin for the I2C bus. This pin is valid when standard mode I2C operation is enabled. Output using the port must be stopped beforehand unless this operation is intended (open drain output). General-purpose I/O port. This pin can be used as a port when I2C operation is disabled (open drain output). External interrupt inputs. Since these inputs are always used when the corresponding external interrupts are enabled, output using the ports must be stopped beforehand unless this operation is the intended operation. General-purpose I/O ports External interrupt input. Since this input is always used when the corresponding external interrupt is enabled, output using the port must be stopped beforehand unless this operation is the intended operation.
SDA 94 42 PL0 F
SCL 95 41 PL1 F
98 to 103
81 to 86
INT0 to INT5
E
PK0 to PK5
INT6
104
87 FRCK
E
External clock input pin for the free-run timer. Since this input is always used when it is selected as the external clock input for the free-run timer, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port External interrupt input. Since this input is always used when the corresponding external interrupt is enabled, output using the port must be stopped beforehand unless this operation is the intended operation.
PK6
INT7
105
88 ATG
E
External trigger for the A/D converter. Since this input is always used when it is selected as the A/D activation source, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port (Continued) 11
PK7
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name
I/O circuit type*3
Function External interrupt inputs. Since these inputs are always used when the corresponding external interrupts are enabled, output using the ports must be stopped beforehand unless this operation is the intended operation. General-purpose I/O ports Data input for UART0. Since this input is always used when UART0 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port Data output from UART0. This function is valid when UART0 data output is enabled. General-purpose I/O port. This function is valid when UART0 data output is disabled. Clock I/O for UART0. This function is valid when UART0 clock output is enabled or when an external clock input is used. General-purpose I/O port. This function is valid when UART0 clock output is disabled or when an external clock input is not used. Data input for UART1. Since this input is always used when UART1 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port Data output from UART1. This function is valid when UART1 data output is enabled. General-purpose I/O port. This function is valid when UART1 data output is disabled. Clock I/O for UART1. This function is valid when UART1 clock output is enabled or when an external clock input is used. General-purpose I/O port. This function is valid when UART1 clock output is disabled or when an external clock input is not used. Data input for UART2. Since this input is always used when UART2 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port (Continued)
106 to 113
⎯
INT8 to INT15
E
PJ0 to PJ7
116
89
SI0
D
PI0 SO0 117 90 PI1 D
SCK0 118 91 PI2 D
119
92
SI1
D
PI3 SO1 120 93 PI4 D
SCK1 121 94 PI5 D
122
99
SI2
D
PH0
12
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name SO2 123 100 PH1
I/O circuit type*3
Function Data output from UART2. This function is valid when UART2 data output is enabled.
D
General-purpose I/O port. This function is valid when UART2 data output is disabled or when an external shift clock input is used. Clock I/O for UART2. This function is valid when UART2 clock output is enabled or when an external clock input is used. General-purpose I/O port. This function is valid when UART2 clock output is disabled or when an external clock input is not used. Data input for UART3. Since this input is always used when UART3 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port Data output from UART3. This function is valid when UART3 data output is enabled. General-purpose I/O port. This function is valid when UART3 data output is disabled. Clock I/O for UART3. This function is valid when UART3 clock output is enabled or when an external clock input is used. General-purpose I/O port. This function is valid when UART3 clock output is disabled or when an external clock input is not used. Data input for UART4. Since this input is always used when UART4 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port Data output from UART4. This function is valid when serial I/O4 data output is enabled. General-purpose I/O port. This function is valid when serial I/O4 data output is disabled. (Continued)
SCK2 124 101 PH2 D
125
102
SI3
D
PH3 SO3 126 103 PH4 D
SCK3 127 104 PH5 D
128
⎯
SI4
D
PG0 SO4 129 ⎯ PG1 D
13
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name
I/O circuit type*3
Function Clock I/O for UART4. This function is valid when serial I/O4 clock output is enabled or when an external clock input is used. General-purpose I/O port. This function is valid when serial I/O4 clock output is disabled or when an external clock input is not used. Data input for serial I/O5. Since this input is always used when serial I/O5 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port Data output from serial I/O5. This function is valid when serial I/O5 data output is enabled. General-purpose I/O port. This function is valid when serial I/O5 data output is disabled. Clock I/O for serial I/O5. This function is valid when serial I/O5 clock output is enabled or when an external shift clock input is used. General-purpose I/O port. This function is valid when serial I/O5 clock output is disabled or when an external clock input is not used. NMI (non-maskable interrupt) input Clock (oscillation) output (sub clock) Clock (oscillation) input (sub clock) Mode pins 2 to 0. These pins set the basic operating mode. Connect the pins to VCC or VSS. Input circuit type : The production version (MASK ROM version) is the "H" type. The Flash ROM version is the "J" type. Clock (oscillation) input (main clock) Clock (oscillation) output (main clock) External reset input DMA external transfer request input. Since this input is always used when it is selected as the DMA activation source, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port (Continued)
SCK4 130 ⎯ PG2 D
131
⎯
SI5
D
PG3 SO5 132 ⎯ PG4 D
SCK5 133 ⎯ PG5 134 135 137 51 61 60 NMI X1A X0A H B B H 138 to 140 52 to 54 MD2 to MD0 D
J
141 143 144
58 57 55
X0 X1 INIT
A A I
147
⎯
DREQ2
C
PC0
14
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name
I/O circuit type*3
Function DMA external transfer request acceptance output. This function is valid when DMA transfer request acceptance output is enabled. General-purpose I/O port. This function is valid when DMA transfer request acceptance output is enabled. DMA external transfer end output. This function is valid when DMA external transfer end output is enabled.
DACK2 148 ⎯ PC1 C
DEOP2
149
⎯
DSTP2
C
DMA external transfer stop input. This function is valid when DMA external transfer stop input is enabled. General-purpose I/O port. This function is valid when DMA external transfer end output and external transfer stop input are disabled. DMA external transfer request input. Since this input is always used when it is selected as the DMA activation source, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port DMA external transfer request acceptance output. This function is valid when DMA transfer request acceptance output is enabled. General-purpose I/O port. This function is valid when DMA transfer request acceptance output is disabled. DMA external transfer end output. This function is valid when DMA external transfer end output is enabled.
PC2
150
⎯
DREQ0
C
PB0 DACK0 151 ⎯ PB1 C
DEOP0
152
⎯
DSTP0
C
DMA external transfer stop input. This function is valid when DMA external transfer stop input is enabled. General-purpose I/O port. This function is valid when DMA external transfer end output and external transfer stop input are disabled. DMA external transfer request input. Since this input is always used when it is selected as the DMA activation source, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. (Continued)
PB2
153
⎯
DREQ1
C
PB3
15
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name
I/O circuit type*3
Function DMA external transfer request acceptance output. This function is valid when DMA transfer request acceptance output is enabled. General-purpose I/O port. This function is valid when DMA external transfer request acceptance output is disabled. DMA external transfer end output. This function is valid when DMA external transfer end output is enabled.
DACK1 154 ⎯ PB4 C
DEOP1
155
⎯
DSTP1
C
DMA external transfer stop input. This function is valid when DMA external transfer stop input is enabled. General-purpose I/O port. This function is valid when DMA external transfer end output and external transfer stop input are disabled. Write strobe output for DMA fly-by transfer. This function is valid when write strobe output for DMA fly-by transfer is enabled. General-purpose I/O port. This function is valid when write strobe output for DMA fly-by transfer is disabled. Read strobe output for DMA fly-by transfer. This function is valid when read strobe output for DMA fly-by transfer is enabled. General-purpose I/O port. This function is valid when read strobe output for DMA fly-by transfer is disabled. Chip select 0 output. This function is valid in external bus mode. General-purpose I/O port. This function is valid in single-chip mode. Chip select 1 output. This function is valid when chip select 1 output is enabled. General-purpose I/O port. This function is valid when chip select 1 output is disabled. Chip select 2 output. This function is valid when chip select 2 output is enabled. General-purpose I/O port. This function is valid when chip select 2 output is disabled. (Continued)
PB5
IOWR 156 ⎯ PB6 C
IORD 157 ⎯ PB7 C
CS0 158 66 PA0 CS1 159 67 PA1 CS2 160 68 PA2 C C C
16
MB91350A Series
Pin no. LQFP*1 LQFP*2 Pin name CS3 161 69 PA3 RDY
I/O circuit type*3
Function Chip select 3 output. This function is valid when chip select 3 output is enabled. General-purpose I/O port. This function is valid when chip select 3 output is disabled. External ready input. This function is valid when external ready input is enabled. Input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This function is valid when external ready input is disabled. External bus open acceptance output. Outputs an “L” level when the external bus is open. This function is valid when output is enabled. Input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This function is valid when external bus open acceptance is disabled. External bus open request input. A high level is input to this pin to request for the external bus to be made open. This function is valid when input is enabled.
C
164
45
IN0
D
P80
BGRNT
165
46
IN1
D
P81
BRQ
166
47
IN2
D
Input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This function is valid when external bus open request is disabled. External bus read strobe output. This function is valid in external bus mode. General-purpose I/O port. This function is valid in single-chip mode. (Continued)
P82
RD 167 48 P83 D
17
MB91350A Series
(Continued) Pin no. LQFP*1 LQFP*2 Pin name WR0 168 49 P84 D
I/O circuit type*3
Function External bus write strobe output. This function is valid in external bus mode. General-purpose I/O port. This function is valid in single-chip mode. External bus write strobe output. This function is valid when WR1 output in external bus mode is enabled. Input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This function is valid when external bus write enable output is disabled. System clock output. This function is valid when system clock output is enabled. A clock having the same frequency as the external bus operating frequency is output (stopped in stop mode). General-purpose I/O port. This function is valid when system clock output is disabled.
WR1
169
50
IN3
D
P85
SYSCLK 170 62 P90 171 63 P91 C C
General-purpose I/O port Memory clock output. This function is valid when memory clock output is enabled. A clock having the same frequency as the external bus operating frequency is output (stopped in sleep mode). General-purpose I/O port. This function is valid when memory clock output is disabled.
MCLK 172 ⎯ P92 173 64 P93 AS 174 65 P94 *1 : FPT-176P-M02 *2 : FPT-120P-M21 C C C
General-purpose I/O port Address strobe output. This function is valid when address strobe output is enabled. General-purpose I/O port. This function is valid when address load output is disabled.
*3 : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types. *4 : These functions are not supported on the FPT-120P-M21.
18
MB91350A Series
[Power supply and GND pins] Pin number Pin name LQFP*1 17, 35, 65, 79, 93, 96, 114, 136, 145, 162, 175 18, 36, 66, 80, 97, 115, 142, 146, 163, 176 45 46 62 63 64 *1 : FPT-176P-M02 *2 : FPT-120P-M21 LQFP*2 18, 40, 43, 59, 76, 96, 112 19, 44, 56, 77, 95 107 108 109 110 111 VSS VCC DAVS DAVC AVCC AVRH AVSS/AVRL GND pins. Use the same potential for all pins. 3.3 V power supply pins. Use the same potential for all pins. D/A converter GND pin D/A converter power supply pin A/D converter analog power supply pin A/D converter reference power supply pin A/D converter analog GND pin Function
19
MB91350A Series
■ I/O CIRCUIT TYPE
Type
X1
Circuit type
Remarks Oscillation feedback resistance : approx. 1 MΩ
Clock input
A
X0
Standby control
X1A
Clock input
Oscillation feedback resistance for low speed (sub clock oscillation) : approx. 7 MΩ
B
X0A
Standby control
Pull-up control
P-ch P-ch
• CMOS level output • CMOS level input
Digital output
N-ch
C
Digital output
With standby control With pull-up control
Digital input
Standby control
Pull-up control
P-ch P-ch
• CMOS level output • CMOS level hysteresis input
Digital output
N-ch
D
Digital output
With standby control With pull-up control
Digital input
Standby control
(Continued)
20
MB91350A Series
Type
P-ch
Circuit type
Remarks • CMOS level output • CMOS level hysteresis input
Digital output
P-ch
E
N-ch
Digital output Digital input
Withstand voltage of 5 V
N-ch
• N-ch (Open drain input) • CMOS level hysteresis input Digital output
F Digital input
Standby control
With standby control Withstand voltage of 5 V
P-ch N-ch
Analog input With switch
G Analog input
Control
CMOS level hysteresis input
P-ch N-ch
H
Digital input CMOS level hysteresis input With pull-up resistor
P-ch
P-ch
I
Digital input (Continued) 21
MB91350A Series
(Continued) Type
N-ch N-ch
Circuit type
Remarks • CMOS level input • MB91F353A/F355A/F356B/F357B only
J
N-ch N-ch
Control signal Mode input Diffused resistor
N-ch
22
MB91350A Series
■ HANDLING DEVICES
• Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC and VSS. A latch-up,if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, don’t exceed the absolute maximum rating. • Treatment of Unused Pins Do not leave unused input pins open, as this may cause a malfunction. Handle by using a pull-up or pull-down resistor. • Power Supply Pins In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to the external power supply and ground lines in order to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source to the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins near this device. • Crystal Oscillator Circuit Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, X0A, X1A, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0, X1, X0A and X1A pins are surrounded by ground plane, as stable operation can be obtained by using this layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. • Notes on Using an External Clock When using an external clock, as a general rule you should simultaneously supply the clock signal to X0 and a clock signal with the reverse phase to X1. However, the stop mode (oscillator stop mode) must not be used under this configuration (This is because the X1 pin stops at High level output in STOP mode) . Using an external clock (normal)
X0
X1
MB91350A series
Note : STOP mode (oscillation stop mode) cannot be used. • Clock Control Block Hold the signal for the oscillation stabilization wait time when inputting a Low level to the INIT pin.
23
MB91350A Series
• Notes on Using the Sub Clock When the X0A and X1A pins are not connected to an oscillator, pull down the X0A pin and leave the X1A pin open. Using an external clock (normal)
X0
OPEN
X1
MB91350A series
• Treatment of NC and OPEN Pins Pins marked as NC and OPEN must be left open. • Mode Pins (MD0 to MD2) These pins should be connected directly to the VCC or VSS pins. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS pins is as short as possible and the connection impedance is low. • Operation at Start-up The INIT pin must be at Low level when the power supply is turned on. Immediately after the power supply is turned on, the Low level input needs to be held to the INIT pin for the oscillation stabilization wait time of the oscillator circuit to ensure that the oscillator has time to settle (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value). • Oscillation Input at Power On When the power is turned on, maintain the clock input until the device is released from the oscillation stabilization wait state. • Precautions While Operating in PLL Clock Mode On this microcontroller, if the crystal oscillator is disconnected or the external reference clock input stops while PLL clock mode is selected, the microcontroller may continue to operate at the free-run frequency of the selfoscillating circuit within the PLL. However, Fujitsu does not guarantee this operation. • External Bus Setting This model guarantees an external bus frequency of 25 MHz. If the base clock frequency is set to 50 MHz when the DIVR1 (external bus base clock division setting register) register is still set to the default value, the external bus frequency will be set to 50 MHz. When you change the base clock frequency, change the base clock frequency after setting the external bus within 25 MHz. • MCLK and SYSCLK The difference between MCLK and SYSCLK is that MCLK stops in SLEEP/STOP mode but SYSCLK stops only in STOP mode. Use the clock that is appropriate for each application. Upon initialization, MCLK is disabled (PORT) and SYSCLK is enabled. To use MCLK, the port function register (PFR) needs to be set to enable the use of the clock.
24
MB91350A Series
• Pull-up Control If a pull-up resistor is provided to a pin that is used as an external bus pin, there is no guarantee that the pin will conform to the specifications given in “■ ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4) Normal Bus Access Read/Write Operation, (5) Multiplex Bus Access Read/Write operation and (7) Hold Timing”. Furthermore, even if a port has been configured to use a pull-up resistance, this setting is invalid during stop mode with HIZ=1 and during hardware standby mode. • Sub Clock Select At least one NOP instruction needs to be executed immediately after switching the clock source from main clock mode to sub clock mode. (Idi (Idi stb nop #0x0b, r0) #_CLKR, r12) r0, @r12 // sub-clock mode // Must insert NOP instruction
• Bit Search Module The BSD0, BSD1, and BDSC registers can only be accessed in words. • D-bus Memory Do not set the code area to memory on the D-bus because instructions cannot be fetched from the D-bus. Executing an instruction fetch to the D-bus area will cause incorrect data to be interpreted as code, possibly causing the device to run out of control. • Low Power Consumption Mode When entering sleep or stop mode, be sure to read the standby control register (STCR) immediately after writing to it. More specifically, use the following sequence. Furthermore, after recovering from standby mode, set the I flag, ILM, and ICR registers such that the CPU branches to the interrupt handler for the interrupt that triggered the controller to recover from standby mode. (Idi #value_of_standby, r0) (Idi #_STCR, r12) stb r0, @r12 // set STOP/SLEEP bit Idub @r12, r0 // Must read STCR Idub @r12, r0 // after reading, go into standby mode NOP // Must insert NOP × 5 NOP NOP NOP NOP • Switching the Function of Shared Ports Use the Port Function Register (PFR) to switch between using an external pin as a port or a shared pin. Note, however, that bus pins are switched depending on the external bus settings.
25
MB91350A Series
• Prefetch If prefetch is enabled in a area that is configured as little endian, limit access to the corresponding area to word-length (32-bit) access. Byte or halfword does not allow a proper access to data. • I/O Port Access Ports can only be accessed in bytes. • Built-in RAM Immediately after a reset is released, the internal RAM capacity restriction function begins operating, allowing only 4 Kbytes to be used for both data and program execution irrespective of the on-chip RAM capacity. Update the setting to clear the restriction function. At least one NOP instruction is required immediately after updating this setting. Please refer to the “MB91350A Series HARDWARE MANUAL CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS” for the details. • Flash Memory In programming mode, Flash memory cannot be used for the interrupt vector table (However, a reset can be performed) . • Notes on the PS Register As the PS register is processed in advance by some instructions, when the debugger is being used, the following exception handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, the operation before and after the EIT always proceeds according to specification. 1. The following behavior may occur if any of the following occurs in the instruction immediately after a DIVOU/ DIVOS instruction : (a) a user interrupt or NMI is accepted; (b) single-step execution is performed; or (c) execution breaks due to a data event or from the emulator menu. • The D0 and D1 flags are updated in advance. • An EIT handling routine (user interrupt, NMI, or emulator) is executed. • Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as in (1). 2. The following behavior occurs when an ORCCR, STILM, MOV Ri or PS instruction is executed to enable a user interrupt or NMI source while that interrupt is in the active state. • The PS register is updated in advance. • The EIT handling routine (user interrupt, NMI, or emulator) is executed. • Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1).
26
MB91350A Series
[Note on Debugger] • Single-Step Execution of the RETI Command If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base timer interrupt handler) . Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debugging. • Break Function If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user program actually contains data access instructions. To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware break (including event breaks). • Internal ROM area Do not set DMAC transfer destination to an address in the internal ROM area. • Simultaneous Occurrence of a Software Break (INTE instruction) and a User Interrupt/NMI When a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may react as follows. • The debugger stops pointing to a location other than a programmed breakpoint. • The program does not resume execution correctly after breaking. If this symptom occurs, use a hardware break in place of the software break. When using a monitor debugger, do not set a break at the relevant location. • A malfunction may occur if the stack pointer is in an area that is configured for DSU operand break. Do not set a data event breaks that apply to accesses to an area that contains the address of the system stack pointer.
27
MB91350A Series
■ BLOCK DIAGRAMS
• MB91F353A/353A/352A/351A
FR CPU
32
32 DMAC 5 channels
Bit search RAM 16 Kbytes(stack)*
ROM 512 Kbytes* Bus Converter 32 32
A20 to A00 D31 to D16 RD WR1, WR0 RDY BRQ BGRNT SYSCLK
RAM 8 Kbytes
External memory I/F
X0, X1 MD0 to MD2 INIT X0A, X1A
Clock control Clock timer Interrupt Controller
32↔16 Adapter
16 PORT PORT
3 channels PPG 4 channels Reload timer
TRG0 to TRG4 PPG0, PPG2, PPG4
INT0 to INT7 NMI SI0 to SI3 SO0 to SO3 SCK0 to SCK3
8 channels External interrupt
4 channels UART
Free-run timer
4 channels U-timer
FRCK
4 channels Input capture
IN0 to IN3
SI6, SI7 SO6, SO7 SCK6, SCK7 AN0 to AN7 ATG AVRH, AVCC AVSS/AVRL DA0, DA1 DAVC, DAVS
2 channels SIO
2 channels Output compare
OC0, OC2
8 channels A/D converter
1 channel I2C
SDA SCL
2 channels D/A converter
1 channel 8-bit up/down counter
AIN0 BIN0 ZIN0
* : MB91352A : RAM 8 Kbytes (stack) , ROM 384 Kbytes MB91351A : RAM 16 Kbytes (stack) , ROM 384 Kbytes 28
MB91350A Series
• MB91F355A/F356B/F357B/355A/354A
FR CPU
32
32
Bit search RAM (stack)
ROM/Flash RAM (Execute instruction) Bus Converter
32 32
DMAC 5 channels
DREQ0 to DREQ2 DACK0 to DACK2 DEOP0/DSTP0 to DEOP2/DSTP2 IOWR IORD
A23 to A00 D31 to D16 RD WR1, WR0 RDY BRQ BGRNT SYSCLK
External memory I/F
X0, X1 MD0 to MD2 INIT X0A, X1A
Clock control
Clock timer
32 ↔ 16 Adapter
16
PORT
PORT
Interrupt Controller
INT0 to INT15 NMI SI0 to SI4 SO0 to SO4 SCK0 to SCK4
6 channels PPG 4 channels reload timer
TRG0 to TRG5 PPG0 to PPG5
16 channels External interrupt
5 channels UART
TOT0 to TOT3
Free-run timer
5 channels U-Timer
FRCK
4 channels input capture
IN0 to IN3
SI5 to SI7 SO5 to SO7 SCK5 to SCK7
3 channels SIO
8 channels output compare
OC0 to OC7
AN0 to AN11 ATG AVRH, AVCC AVSS/AVRL DA0 to DA2 DAVC, DAVS
12 channels A/D converter 1 channel I2C 3 channels D/A converter
SDA SCL
2 channels 8/16-bit up/down counter MB91F356B 256 Kbytes (Flash) 16 Kbytes 8 Kbytes
AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1
ROM/Flash RAM (stack) RAM (Execute instruction)
MB91F355A/MB91F357B 512 Kbytes (Flash) 16 Kbytes 8 Kbytes
MB91355A 512 Kbytes 16 Kbytes 8 Kbytes
MB91354A 384 Kbytes 8 Kbytes 8 Kbytes
29
MB91350A Series
■ CPU AND CONTROL UNIT
Internal architecture The FR family CPU is a high performance core based on a RISC architecture while incorporating advanced instructions for embedded controller applications.
1. Features
• RISC architecture Basic instructions : Executed at 1 instruction per cycle • 32-bit architecture General-purpose registers : 32-bit × 16 registers • 4GB linear memory space • Built-in multiplier 32-bit × 32-bit multiplication : 5 cycles 16-bit × 16-bit multiplication : 3 cycles • Enhanced interrupt handling Fast response speed (6 cycles) Multiple interrupts supported Level masking (16 levels) • Enhanced I/O manipulation instructions Memory-to-memory transfer instructions Bit manipulation instructions • High code efficiency Basic instruction word length : 16-bit • Low-power consumption Sleep mode and stop mode • Gear function
30
MB91350A Series
2. Internal architecture
The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated. A 32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus), providing an interface between the CPU and peripheral resources. A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus, providing an interface between the CPU and the bus controller.
FR CPU D-bus I-bus
32 I address 32 I data D address 32 Princeton bus converter External data 16 Harvard External address 24
Data RAM
D data
32
Address 32-bit 16-bit bus converter Data
32
32
16
R-bus
F-bus
Peripheral resources
Internal I/O
bus controller
31
MB91350A Series
3. Programming model
• Basic programming model 32-bit [Initial Value]
R0 R1 XXXX XXXXH
GENERAL PURPOSE REGISTERS
R12 R13 R14 R15
AC FP SP
XXXX XXXXH 0000 0000 H
Program counter Program status Table base register Return pointer System stack pointer User stack pointer
PC PS TBR RP SSP USP
⎯
ILM
⎯
SCR
CCR
Multiplication and division MDH result registers
MDL
32
MB91350A Series
4. Registers
• General purpose registers
32-bit [Initial Value]
R0 R1 XXXX XXXXH
R12 R13 R14 R15
AC FP SP
XXXX XXXXH 0000 0000 H
Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory access pointers for CPU operations. Of these 16 registers, the registers listed below are intended for special applications. Some instructions have been enhanced for this purpose.
R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000H (SSP value). • PS (Program Status) This register holds the program status and is divided into the ILM, SCR, and CCR. The undefined bits in the following illustration are all reserved bits. Reading these bits always returns “0”. Writing to them has no effect.
bit 31 bit 20 ⎯ bit 16 ⎯ bit 10 bit 8 bit 7 bit 0
PS
ILM
SCR
CCR
33
MB91350A Series
• CCR (Condition Code Register)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial Value - - 00XXXXB
CCR
⎯
⎯
S
I
N
Z
V
C
S I N Z V C
: Stack flag. Cleared to “0” by a reset. : Interrupt enable flag. Cleared to “0” by a reset. : Negative flag. The initial value after a reset is indeterminate. : Zero flag. The initial value after a reset is indeterminate. : Overflow flag. The initial value after a reset is indeterminate. : Carry flag. The initial value after a reset is indeterminate.
• SCR (System Condition Code Register)
bit 10 bit 9 bit 8
Initial Value XX0B
SCR Flag for stepwise division
D1
D0
T
Stores intermediate data for stepwise division operations. Step trace trap flag A flag specifying whether the step trace trap function is enabled or not. The step trace trap function is used by the emulator. This function cannot be used by a user program while using the emulator. • ILM
bit 20 bit 19 bit 18 bit 17 bit 16
Initial Value 01111B
ILM ILM4 ILM3 ILM2 ILM1 ILM0
This register stores the interrupt level mask value. The value in the ILM register is used as the level mask. Initialized to “15” (01111B) by a reset. • PC (Program Counter)
bit 31 PC bit 0
Initial Value XXXXXXXXH
The program counter contains the address of the instruction currently being executed. The initial value after a reset is indeterminate. • TBR (Table Base Register)
bit 31 TBR bit 0
Initial Value 0 0 0 FFC0 0 H
The table base register contains the start address of the vector table used for handling EIT events. The initial value after a reset is 000FFC00H. 34
MB91350A Series
• RP (Return Pointer)
bit 31 RP bit 0
Initial Value XXXXXXXXH
The return pointer contains the address to which to return from a subroutine. When the CALL instruction is executed, the value in the PC is transferred to the RP. When the RET instruction is executed, the value in the RP is transferred to the PC. The initial value after a reset is indeterminate. • SSP (System Stack Pointer)
bit 31 SSP bit 0
Initial Value 00000000H
The SSP is the system stack pointer and functions as R15 when the S flag is “0”. The SSP can be specified explicitly. The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event occurs. The initial value after a reset is 00000000H. • USP (User Stack Pointer)
bit 31 USP bit 0
Initial Value XXXXXXXXH
The USP is the user stack pointer and functions as R15 when the S flag is “1”. The USP can be specified explicitly. The initial value after a reset is indeterminate. This pointer cannot be used by the RETI instruction. • Multiply & Divide Registers
bit 31 MDH MDL bit 0
These registers are 32-bit wide registers that store the results of multiplication and division operations. The initial value after a reset is indeterminate.
35
MB91350A Series
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode.
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed. Mode Pins Reset vector access Mode name area MD2 MD1 MD0 0 0 0 0 0 1 internal ROM mode vector external ROM mode vector Internal External The bus width is specified by the mode register.
Remarks
Values other than those listed in the table are prohibited.
2. Mode Register (MODR)
The data that is written to the mode register from the address at 000F FFF8H by the mode vector fetch is called the mode data. After the mode register (MODR) , has been set, the device operates according to the configured operating mode. The mode register is set by all of the reset sources. User programs cannot write to the mode register. Note : No data exists at the address (0000 07FFH) of the mode register in the previous FR family. [Register description] MODR 000F FFF8H
bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 ROMA bit 1 WTH1 bit 0 WTH0
Initial Value XXXXXXXXB
Operating mode setting bits [bit7-bit3] Reserved bit Always set these bits to “00000B”. Operation is not guaranteed if these bits are set to a value other than “00000B”. [bit2] ROMA (internal ROM enable bit) The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas. ROMA Function Remarks 0 1 External ROM mode Internal ROM mode Internal F-bus RAM is valid; the area (8 0000H to 10 0000H) of internal ROM is used as an external area. Internal F-bus RAM and F-bus ROM are valid.
[bit1, bit0] WTH1, WTH0 (Bus width setting bits) Used to set the bus width to be used in external bus mode. In external bus mode, the BW1 and BW0 bits of AMD0 (CS0 area) are set to the value of these bits. WTH1 WTH0 function Remarks 0 0 1 1 36 0 1 0 1 single chip mode 8-bit bus width 16-bit bus width ⎯ external bus mode Setting prohibited single chip mode
MB91350A Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. • Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas. The addresses of operands in these areas can be specified directly within an instruction. The size of the directly addressable areas depends on the size of the data being accessed as shown below. → Byte data access → Half word data access → Word data access : 000H to 0FFH : 000H to 1FFH : 000H to 3FFH
2. Memory Map
Memory Map of MB91F355A/F353A/F357B/355A/353A
Single chip mode
0000 0000 H I/O 0000 0400 H I/O 0001 0000 H 0003 E000 H
Internal ROM external bus mode
I/O I/O
External ROM external bus mode
I/O I/O
Direct addressing area Refer to “■ I/O MAP”.
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
0004 0000 H 0004 4000 H 0005 0000 H 0008 0000 H
Built-in RAM 16 Kbytes (Stack)
Built-in RAM 16 Kbytes (Stack)
Built-in RAM 16 Kbytes (Stack)
Access disabled
Access disabled External area Built-in ROM 512 Kbytes
Access disabled
Built-in ROM 512 Kbytes
0010 0000 H
External area
Access disabled
FFFF FFFFH
External area
• Each mode is set depending on the mode vector fetch after INIT is negated. • The available area of internal RAM is restricted immediately after a reset is released. At least one NOP instruction is required immediately after overwriting the setting for the available RAM area.
37
MB91350A Series
Memory Map of MB91354A
Single chip mode
0000 0000 H I/O 0000 0400 H I/O 0001 0000 H 000 3 E000 H
Internal ROM external bus mode
I/O I/O
External ROM external bus mode
I/O I/O
Direct addressing area Refer to “■ I/O MAP”.
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Built-in RAM 8 Kbytes (Stack)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Built-in RAM 8 Kbytes (Stack)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Built-in RAM 8 Kbytes (Stack)
0004 0000 H 0004 2000 H 0005 0000 H 000 8 0 000 H 000A 0000 H
Access disabled
Access disabled
Access disabled
External area
Access disabled
Built-in ROM 384 Kbytes Access disabled
Built-in ROM 384 Kbytes External area
External area
0010 0000 H
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated. • The available area of internal RAM is restricted immediately after a reset is released. At least one NOP instruction is required immediately after overwriting the setting for the available RAM area.
38
MB91350A Series
Memory Map of MB91352A
Single chip mode
0000 0000 H I/O 0000 0400 H I/O 0001 0000 H 0003 E000 H
Internal ROM external bus mode
I/O I/O
External ROM external bus mode
I/O I/O
Direct addressing area Refer to “■ I/O MAP”.
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
0004 0000 H 0004 2000 H 0005 0000 H 000A 0000 H
Built-in RAM 8 Kbytes (Stack)
Built-in RAM 8 Kbytes (Stack)
Built-in RAM 8 Kbytes (Stack)
Access disabled
Access disabled External area Built-in ROM 384 Kbytes
Access disabled
Built-in ROM 384 Kbytes
0010 0000 H
External area
Access disabled
FFFF FFFFH
External area
• Each mode is set depending on the mode vector fetch after INIT is negated. • The available area of internal RAM is restricted immediately after a reset is released. At least one NOP instruction is required immediately after overwriting the setting for the available RAM area.
39
MB91350A Series
Memory Map of MB91351A
Single chip mode
0000 0000 H I/O 0000 0400 H I/O 0001 0000 H 0003 E000 H
Internal ROM external bus mode
I/O I/O
External ROM external bus mode
I/O I/O
Direct addressing area Refer to “■ I/O MAP”.
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
0004 0000 H 0004 4000 H 0005 0000 H 000A 0000 H
Built-in RAM 16 Kbytes (Stack)
Built-in RAM 16 Kbytes (Stack)
Built-in RAM 16 Kbytes (Stack)
Access disabled
Access disabled External area Built-in ROM 384 Kbytes
Access disabled
Built-in ROM 384 Kbytes
0010 0000 H
External area
Access disabled
FFFF FFFFH
External area
• Each mode is set depending on the mode vector fetch after INIT is negated. • The available area of internal RAM is restricted immediately after a reset is released. At least one NOP instruction is required immediately after overwriting the setting for the available RAM area.
40
MB91350A Series
Memory Map of MB91F356B
Single chip mode
0000 0000 H I/O 0000 0400 H I/O 0001 0000 H 000 3 E000 H
Internal ROM external bus mode
I/O I/O
External ROM external bus mode
I/O I/O
Direct addressing area Refer to “■ I/O MAP”.
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Built-in RAM 16 Kbytes (Stack)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Built-in RAM 16 Kbytes (Stack)
Access disabled
Built-in RAM 8 Kbytes (Execute instruction)
Built-in RAM 16 Kbytes (Stack)
0004 0000 H 0004 4000 H 0005 0000 H 000 8 0 000 H 000C 0000 H 0010 0000 H
Access disabled
Access disabled
Access disabled
External area
Access disabled
Built-in ROM 256 Kbytes Access disabled
Built-in ROM 256 Kbytes External area
External area
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated. • The available area of internal RAM is restricted immediately after a reset is released. At least one NOP instruction is required immediately after overwriting the setting for the available RAM area.
41
MB91350A Series
■ I/O MAP
This shows the locations of each of the registers for the peripheral resources in memory space. [How to read the table] Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block diagram T-unit Port Data Register
Read/write attribute, Access unit (B : Byte, H : Half Word, W : Word) Initial value after a reset Register name (First-column register at address 4n; second-column register at address 4n + 2) Location of left-most register (When using word access, the register in column 1 is the MSB side of the data.) Note : Initial values of register bits are represented as follows : “1” : Initial value is “1”. “0” : Initial value is “0”. “X” : Initial value is “X”. “−” : No physical register at this location
42
MB91350A Series
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H 000038H 00003CH 000040H
Register +0 ⎯⎯⎯⎯ PDR4[R/W]B XXXXXXXX PDR8[R/W]B --XXXXXX PDRC[R/W]B*3 -----XXX PDRG[R/W]B*3 --XXXXXX PDRK[R/W]B XXXXXXXX PDRO[R/W]B XXXXXXXX ⎯⎯⎯⎯ PDRH[R/W]B --XXXXXX PDRL[R/W]B ------XX PDRP[R/W]B*3 ----XXXX ⎯⎯⎯⎯ ⎯⎯⎯⎯
3
+1 ⎯⎯⎯⎯ PDR5[R/W]B XXXXXXXX PDR9[R/W]B ---XXXXX
+2 PDR2[R/W]B XXXXXXXX PDR6[R/W]B XXXXXXXX PDRA[R/W]B ----XXXX ⎯⎯⎯⎯ PDRI[R/W]B --XXXXXX PDRM[R/W]B --XXXXXX ⎯⎯⎯⎯
+3 PDR3[R/W]B XXXXXXXX ⎯⎯⎯⎯ PDRB[R/W]B*3 XXXXXXXX
Block
T-unit port data register*3
PDRJ[R/W]B*3 XXXXXXXX PDRN[R/W]B --XXXXXX ⎯⎯⎯⎯ R-bus port data register*3
⎯⎯⎯⎯ SES5[R/W]B* ------00 SES6[R/W]B ------00 SES7[R/W]B ------00 CDCR5[R/W]B*3 0---1111 CDCR7[R/W]B 0---1111 SRCL6[W]B -------⎯⎯⎯⎯
3
⎯⎯⎯⎯ SDR5[R/W]B* XXXXXXXX SDR6[R/W]B XXXXXXXX SDR7[R/W]B XXXXXXXX ⎯⎯⎯⎯ *1 ⎯⎯⎯⎯ *1 SRCL7[W]B -------⎯⎯⎯⎯
3
Reserved SIO5*3 SIO6 SIO7 SIO prescaler 5*3 SIO prescaler 6, 7 SIO5 to SIO7*3 Reserved External interrupts (INT0 to INT7) Delay interrupt Reload timer 0 (Continued)
SMCS5[R/W]B,H* 00000010_----00-SMCS6[R/W]B,H 00000010_----00-SMCS7[R/W]B,H 00000010_----00-⎯⎯⎯⎯ CDCR6[R/W]B 0---1111 ⎯⎯⎯⎯ ⎯⎯⎯⎯ EIRR0[R/W]B,H,W 00000000 DICR[R/W]B,H,W -------0
⎯⎯⎯⎯ ⎯⎯⎯⎯ *1 SRCL5[W]B*3 -------⎯⎯⎯⎯ ENIR0[R/W]B,H,W 00000000 HRCL[R/W]B,H,W 0--11111
ELVR0[R/W]B,H,W 00000000 ⎯⎯⎯⎯ TMR[R]H,W XXXXXXXX_XXXXXXXX TMCSR[R/W]B,H,W ----0000_00000000
000044H 000048H 00004CH
TMRLR[W]H,W XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯
43
MB91350A Series
Address 000050H 000054H 000058H 00005CH 000060H 000064H
Register +0 +1 +2 +3 TMRLR[W]H,W XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ TMRLR[W]H,W XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ SSR[R/W]B,H,W 00001000 SIDR[R/W]B,H,W XXXXXXXX TMR[R]H,W XXXXXXXX_XXXXXXXX TMCSR[R/W]B,H,W ----0000_00000000 TMR[R]H,W XXXXXXXX_XXXXXXXX TMCSR[R/W]B,H,W ----0000_00000000 SCR[R/W]B,H,W 00000100 DRCL[W]B -------SCR[R/W]B,H,W 00000100 DRCL[W]B -------SCR[R/W]B,H,W 00000100 DRCL[W]B -------SMR[R/W]B,H,W 00--0--UTIMC[R/W]B 0--00001 SMR[R/W]B,H,W 00--0--UTIMC[R/W]B 0--00001 SMR[R/W]B,H,W 00--0--UTIMC[R/W]B 0--00001
Block
Reload timer 1
Reload timer 2
UART0 U-TIMER/ UART0 UART1 U-TIMER/ UART1 UART2 U-TIMER/ UART2 A/D converter successive approximations
UTIM[R]H(UTIMR[W]H) 00000000_00000000 SSR[R/W]B,H,W 00001000 SIDR/SODR [R/W]B,H,W XXXXXXXX
000068H
00006CH 000070H 000074H 000078H 00007CH 000080H
UTIM[R]H(UTIMR[W]H) 00000000_00000000 SSR[R/W]B,H,W 00001000 SIDR[R/W]B,H,W XXXXXXXX
UTIM[R]H(UTIMR[W]H) 00000000_00000000 ADCS2[R/W]B,H,W ADCS1[R/W]B,H,W X000XX00 000X0000 ADTH0[R]B,H,W XXXXXXXX ADTH2[R]B,H,W XXXXXXXX ⎯⎯⎯⎯ ADTL0[R]B,H,W 000000XX ADTL2[R]B,H,W 000000XX DACR2 [R/W]B,H,W*3 -------0 DADR2 [R/W]B,H,W*3 XXXXXXXX ⎯⎯⎯⎯ ⎯⎯⎯⎯ IBSR[R]B,H,W 00000000
ADCT[R/W]H,W XXXXXXXX_XXXXXXXX ADTH1[R]B,H,W XXXXXXXX ADTH3[R]B,H,W XXXXXXXX ADTL1[R]B,H,W 000000XX ADTL3[R]B,H,W 000000XX
000084H
DACR1[R/W]B,H,W DACR0[R/W]B,H,W -------0 -------0 DADR1[R/W]B,H,W DADR0[R/W]B,H,W XXXXXXXX XXXXXXXX ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ *1
D/A converter*3
000088H 00008CH 000090H 000094H 000098H 00009CH
⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ IBCR[R/W]B,H,W 00000000
Reserved Reserved
ITBA[R/W]B,H,W ------00_00000000 ISMK[R/W]B,H,W 01111111 ICCR[R/W]B,H,W 0-011111 ISBA[R/W]B,H,W -0000000 IDBL[R/W]B,H,W -------0 (Continued) I2C interface
ITMK[R/W]B,H,W 00----11_11111111 ⎯⎯⎯⎯ *2 IDAR[R/W]B,H,W 00000000
44
MB91350A Series
Address 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH
Register +0 ⎯⎯⎯⎯ ⎯⎯⎯⎯ +1 ⎯⎯⎯⎯*1 ⎯⎯⎯⎯ *1 +2 ⎯⎯⎯⎯ ⎯⎯⎯⎯ *1 +3 ⎯⎯⎯⎯ *1 ⎯⎯⎯⎯ *1
Block Reserved
TMRLR[W]H,W XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ RCR1[W]B,H,W*3 00000000 CCRH0[R/W]B,H,W 00000000 RCR0[W]B,H,W 00000000 CCRL0[R/W]B,H,W 00001000
TMR[R]H,W XXXXXXXX_XXXXXXXX TMCSR[R/W]B,H,W ----0000_00000000 UDCR1[R]B,H,W*3 00000000 ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ SCR[R/W]B,H,W 00000100 ⎯⎯⎯⎯ UDCR0[R]B,H,W 00000000 CSR0[R/W]B,H,W 00000000 CSR1[R/W]B,H,W*3 00000000 ⎯⎯⎯⎯ SMR[R/W]B,H,W 00--0--UTIMC[R/W]B 0--00001
Reload timer 3
CCRH1[R/W]B,H,W*3 CCRL1[R/W]B,H,W*3 00000000 00001000 ⎯⎯⎯⎯ SSR[R/W]B,H,W 00001000 ⎯⎯⎯⎯ SIDR[R/W]B,H,W XXXXXXXX
8/16-bit Up/Down counter 0, 1*3 Reserved UART3 U-TIMER/ UART3 UART4*3 U-TIMER/ UART4*3 External interrupts (INT8 to INT15)*3 16-bit free-run timer
UTIM[R]H(UTIMR[W]H) 00000000_00000000 SSR[R/W]B,H,W*3 00001000 SIDR[R/W]B,H,W*3 XXXXXXXX
SCR[R/W]B,H,W*3 SMR[R/W]B,H,W*3 00000100 00--0--⎯⎯⎯⎯ UTIMC[R/W]B*3 0--00001
UTIM[R]H(UTIMR[W]H)*3 00000000_00000000 EIRR1[R/W]B,H,W*3 00000000 ENIR1[R/W]B,H,W*3 00000000
0000D0H
ELVR1[R/W]B,H,W*3 00000000
0000D4H
TCDT[R/W]H,W 00000000_00000000 IPCP1[R]H,W XXXXXXXX_XXXXXXXX IPCP3[R]H,W XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ ICS23[R/W]B,H,W 00000000
⎯⎯⎯⎯
TCCS[R/W]B,H,W 00000000
0000D8H 0000DCH 0000E0H
IPCP0[R]H,W XXXXXXXX_XXXXXXXX IPCP2[R]H,W XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ ICS01[R/W]B,H,W 00000000 (Continued) 16-bit input capture
45
MB91350A Series
Address 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H to 000114H 000118H 00011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H 000144H
Register +0 +1 +2 +3 OCCP1[R/W]H,W*3 XXXXXXXX_XXXXXXXX OCCP3[R/W]H,W*3 XXXXXXXX_XXXXXXXX OCCP5[R/W]H,W*3 XXXXXXXX_XXXXXXXX OCCP7[R/W]H,W*3 XXXXXXXX_XXXXXXXX OCS23[R/W]B,H,W 11101100_00001100 OCS67[R/W]B,H,W*3 11101100_00001100 ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ OCCP0[R/W]H,W XXXXXXXX_XXXXXXXX OCCP2[R/W]H,W XXXXXXXX_XXXXXXXX OCCP4[R/W]H,W*3 XXXXXXXX_XXXXXXXX OCCP6[R/W]H,W*3 XXXXXXXX_XXXXXXXX OCS01[R/W]B,H,W 11101100_00001100 OCS45[R/W]B,H,W*3 11101100_00001100 ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ GCN20[R/W]B 00000000 ⎯⎯⎯⎯ PCSR0[W]H,W XXXXXXXX_XXXXXXXX PCNH0[R/W]B,H,W 00000000 PCNL0[R/W]B,H,W 00000000
Block
16-bit output compare*3
Reserved Reserved
GCN10[R/W]H 00110010_00010000 ⎯⎯⎯⎯ PTMR0[R]H,W 11111111_11111111 PDUT0[W]H,W XXXXXXXX_XXXXXXXX PTMR1[R]H,W*3 11111111_11111111 PDUT1[W]H,W*3 XXXXXXXX_XXXXXXXX PTMR2[R]H,W 11111111_11111111 PDUT2[W]H,W XXXXXXXX_XXXXXXXX PTMR3[R]H,W*3 11111111_11111111 PDUT3[W]H,W*3 XXXXXXXX_XXXXXXXX PTMR4[R]H,W 11111111_11111111 PDUT4[W]H,W XXXXXXXX_XXXXXXXX
PPG control 0 Reserved
PPG0
PCSR1[W]H,W*3 XXXXXXXX_XXXXXXXX PCNH1[R/W]B,H,W*3 PCNL1[R/W]B,H,W*3 00000000 00000000 PCSR2[W]H,W XXXXXXXX_XXXXXXXX PCNH2[R/W]B,H,W 00000000 PCNL2[R/W]B,H,W 00000000
PPG1*3
PPG2
PCSR3[W]H,W*3 XXXXXXXX_XXXXXXXX PCNH3[R/W]B,H,W*3 PCNL3[R/W]B,H,W*3 00000000 00000000 PCSR4[W]H,W XXXXXXXX_XXXXXXXX PCNH4[R/W]B,H,W 00000000 PCNL4[R/W]B,H,W 00000000
PPG3*3
PPG4
(Continued)
46
MB91350A Series
Address 000148H
Register +0 +1 +2 +3 PTMR5[R]H,W*3 11111111_11111111 PDUT5[W]H,W*3 XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ DMACA0[R/W]B,H,W *4 00000000_0000XXXX_XXXXXXXX_XXXXXXXX DMACB0[R/W]B,H,W 00000000_00000000_XXXXXXXX_XXXXXXXX DMACA1[R/W]B,H,W *4 00000000_0000XXXX_XXXXXXXX_XXXXXXXX DMACB1[R/W]B,H,W 00000000_00000000_XXXXXXXX_XXXXXXXX DMACA2[R/W]B,H,W *4 00000000_0000XXXX_XXXXXXXX_XXXXXXXX DMACB2[R/W]B,H,W 00000000_00000000_XXXXXXXX_XXXXXXXX DMACA3[R/W]B,H,W *4 00000000_0000XXXX_XXXXXXXX_XXXXXXXX DMACB3[R/W]B,H,W 00000000_00000000_XXXXXXXX_XXXXXXXX DMACA4[R/W]B,H,W *4 00000000_0000XXXX_XXXXXXXX_XXXXXXXX DMACB4[R/W]B,H,W 00000000_00000000_XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ ⎯⎯⎯⎯ DMACR[R/W]B 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ FRLR[R/W]B,H,W*2 ------01 PCSR5[W]H,W*3 XXXXXXXX_XXXXXXXX PCNH5[R/ W]B,H,W*3 00000000 PCNL5[R/ W]B,H,W*3 00000000
Block
PPG5*3
00014CH 000150H to 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H 00022CH to 00023CH 000240H 000244H to 00027CH 000280H
Reserved
DMAC
Reserved
DMAC
Reserved Limit on F-bus RAM capacity (Continued)
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
47
MB91350A Series
Address 000284H to 00038CH 000390H 000394H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H 000424H 000428H 00042CH to 00043CH
Register +0 +1 ⎯⎯⎯⎯ DRLR[R/W]B,H,W*2 ------01 ⎯⎯⎯⎯ ⎯⎯⎯⎯ BSD0[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX BSD1[R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX BSDC[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX BSRR[R] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DDRG[R/W]B*3 --000000 DDRK[R/W]B 00000000 DDRO[R/W]B 00000000 PFRG[R/W]B* --00-00⎯⎯⎯⎯ PFRO[R/W]B 00000000 PCRG[R/W]B* --000000 ⎯⎯⎯⎯ PCRO[R/W]B 00000000
3 3
+2
+3
Block
Reserved ⎯⎯⎯⎯ ⎯⎯⎯⎯ Limit on D-bus RAM capacity Reserved
Bit search module
DDRH[R/W]B --000000 DDRL[R/W]B ------00 DDRP[R/W]B*3 ----0000
DDRI[R/W]B --000000 DDRM[R/W]B --000000
DDRJ[R/W]B*3 00000000 DDRN[R/W]B --000000 R-bus data direction register*3
⎯⎯⎯⎯
⎯⎯⎯⎯ PFRH[R/W]B --00-00PFRL[R/W]B ------00 PFRP[R/W]B*3 ----0000 ⎯⎯⎯⎯ PCRH[R/W]B --000000 ⎯⎯⎯⎯ PCRP[R/W]B*3 ----0000 ⎯⎯⎯⎯ PCRI[R/W]B --000000 PCRM[R/W]B --000000 ⎯⎯⎯⎯ ⎯⎯⎯⎯ PCRN[R/W]B --000000 ⎯⎯⎯⎯ Reserved (Continued) R-bus pull-up control register*3 PFRI[R/W]B --00-00PFRM[R/W]B --00-00⎯⎯⎯⎯ PFRN[R/W]B --000000 R-bus port function register*3
⎯⎯⎯⎯ Reserved
48
MB91350A Series
Address 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H 000484H 000488H 00048CH
Register +0 ICR00[R/W]B,H,W ---11111 ICR04[R/W]B,H,W ---11111 ICR08[R/W]B,H,W ---11111 ICR12[R/W]B,H,W ---11111 ICR16[R/W]B,H,W ---11111 ICR20[R/W]B,H,W ---11111 ICR24[R/W]B,H,W ---11111 ICR28[R/W]B,H,W ---11111 ICR32[R/W]B,H,W ---11111 ICR36[R/W]B,H,W ---11111 ICR40[R/W]B,H,W ---11111 ICR44[R/W]B,H,W ---11111 +1 ICR01[R/W]B,H,W ---11111 ICR05[R/W]B,H,W ---11111 ICR09[R/W]B,H,W ---11111 ICR13[R/W]B,H,W ---11111 ICR17[R/W]B,H,W ---11111 ICR21[R/W]B,H,W ---11111 ICR25[R/W]B,H,W ---11111 ICR29[R/W]B,H,W ---11111 ICR33[R/W]B,H,W ---11111 ICR37[R/W]B,H,W ---11111 ICR41[R/W]B,H,W ---11111 ICR45[R/W]B,H,W ---11111 +2 ICR02[R/W]B,H,W ---11111 ICR06[R/W]B,H,W ---11111 ICR10[R/W]B,H,W ---11111 ICR14[R/W]B,H,W ---11111 ICR18[R/W]B,H,W ---11111 ICR22[R/W]B,H,W ---11111 ICR26[R/W]B,H,W ---11111 ICR30[R/W]B,H,W ---11111 ICR34[R/W]B,H,W ---11111 ICR38[R/W]B,H,W ---11111 ICR42[R/W]B,H,W ---11111 ICR46[R/W]B,H,W ---11111 +3 ICR03[R/W]B,H,W ---11111 ICR07[R/W]B,H,W ---11111 ICR11[R/W]B,H,W ---11111 ICR15[R/W]B,H,W ---11111 ICR19[R/W]B,H,W ---11111 ICR23[R/W]B,H,W ---11111 ICR27[R/W]B,H,W ---11111 ICR31[R/W]B,H,W ---11111 ICR35[R/W]B,H,W ---11111 ICR39[R/W]B,H,W ---11111 ICR43[R/W]B,H,W ---11111 ICR47[R/W]B,H,W ---11111
Block
Interrupt controller unit
⎯⎯⎯⎯ RSRR[R/W]B,H,W 10000000 CLKR[R/W]B,H,W 00000000 STCR[R/W]B,H,W 00110011 WPR[W]B,H,W XXXXXXXX TBCR[R/W]B,H,W 00XXXX00 DIVR0[R/W]B,H,W 00000011 OSCCR[R/W]B XXXXXXX0 ⎯⎯⎯⎯ ⎯⎯⎯⎯ CTBR[W]B,H,W XXXXXXXX DIVR1[R/W]B,H,W 00000000 ⎯⎯⎯⎯ ⎯⎯⎯⎯ Clock timer Main clock oscillation stabilization wait timer Peripheral stop control (Continued) 49 Clock control unit
⎯⎯⎯⎯ WPCR[R/W]B 00---000 OSCR[R/W]B 00---000 RSTOP0[W]B 00000000
000490H
⎯⎯⎯⎯ RSTOP1[W]B 00000000
⎯⎯⎯⎯ RSTOP2[W]B 00000000
⎯⎯⎯⎯ RSTOP3[W]B -----000
000494H
MB91350A Series
Address 000498H 00049CH to 0005FCH 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H 00062CH 000630H to 00063CH
Register +0 ⎯⎯⎯⎯ +1 ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ DDR4[R/W]B 00000000 DDR8[R/W]B --000000 DDRC[R/W]B*3 -----000 ⎯⎯⎯⎯ ⎯⎯⎯⎯ PFR8[R/W]B --1--0-PFRB2[R/W]B*3 00----00 ⎯⎯⎯⎯ PCR4[R/W]B 00000000 PCR8[R/W]B --000000 PCRC[R/W]B*3 -----000 ⎯⎯⎯⎯ ⎯⎯⎯⎯ PFR9[R/W]B ---010-1 PFRC[R/W]B*3 ---00000 ⎯⎯⎯⎯ PCR5[R/W]B 00000000 PCR9[R/W]B 00000000 ⎯⎯⎯⎯ ________ ⎯⎯⎯⎯ DDR5[R/W]B 00000000 DDR9[R/W]B ---00000 DDR2[R/W]B 00000000 DDR6[R/W]B 00000000 DDRA[R/W]B ----0000 ⎯⎯⎯⎯ ⎯⎯⎯⎯ PFR6[R/W]B 11111111 PFRA[R/W]B ----1111 ⎯⎯⎯⎯ PCR2[R/W]B 00000000 PCR6[R/W]B 00000000 PCRA[R/W]B 00000000 ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ PFRB1[R/W]B*3 00000000 ⎯⎯⎯⎯ PCR3[R/W]B 00000000 ⎯⎯⎯⎯ PCRB[R/W]B*3 00000000 ⎯⎯⎯⎯ DDR3[R/W]B 00000000 ⎯⎯⎯⎯ DDRB[R/W]B*3 00000000 +2 ⎯⎯⎯⎯ +3 ⎯⎯⎯⎯
Block Reserved Reserved
T-unit data direction register*3
T-unit port function register*3
T-unit pull-up control register*3
Reserved (Continued)
50
MB91350A Series
Address 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H to 0007F8H 0007FCH 000800H to 000AFCH
Register +0 +1 +2 +3 ASR0[R/W]H,W 00000000_00000000 ASR1[R/W]H,W 00000000_00000000 ASR2[R/W]H,W 00000000_00000000 ASR3[R/W]H,W 00000000_00000000 ASR4[R/W]H,W 00000000_00000000 ASR5[R/W]H,W 00000000_00000000 ASR6[R/W]H,W 00000000_00000000 ASR7[R/W]H,W 00000000_00000000 AWR0[R/W]B,H,W 01111111_11111111 AWR2[R/W]B,H,W XXXXXXXX_XXXXXXXX AWR4[R/W]B,H,W XXXXXXXX_XXXXXXXX AWR6[R/W]B,H,W XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ ⎯⎯⎯⎯ IOWR0[R/W]B,H,W IOWR1[R/W]B,H,W IOWR2[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX ⎯⎯⎯⎯ CSER[R/W]B,H,W 00000001 ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ MODR[W] *5 XXXXXXXX ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ TCR[W]B,H,W 0000XXXX ⎯⎯⎯⎯ ACR0[R/W]B,H,W 1111XX00_00000000 ACR1[R/W]B,H,W XXXXXXXX_XXXXXXXX ACR2[R/W]B,H,W XXXXXXXX_XXXXXXXX ACR3[R/W]B,H,W XXXXXXXX_XXXXXXXX ACR4[R/W]B,H,W XXXXXXXX_XXXXXXXX ACR5[R/W]B,H,W XXXXXXXX_XXXXXXXX ACR6[R/W]B,H,W XXXXXXXX_XXXXXXXX ACR7[R/W]B,H,W XXXXXXXX_XXXXXXXX AWR1[R/W]B,H,W XXXXXXXX_XXXXXXXX AWR3[R/W]B,H,W XXXXXXXX_XXXXXXXX AWR5[R/W]B,H,W XXXXXXXX_XXXXXXXX AWR7[R/W]B,H,W XXXXXXXX_XXXXXXXX
Block
T-unit
Reserved
Mode register
Reserved (Continued)
51
MB91350A Series
Address 000B00H 000B04H 000B08H 000B0CH 000B10H 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H 000B4CH 000B50H
Register +0 ESTS0[R/W] X0000000 ECTL0[R/W] 0X000000 ECNT0[W] XXXXXXXX +1 ESTS1[R/W] XXXXXXXX ECTL1[R/W] 00000000 ECNT1[W] XXXXXXXX +2 ESTS2[R] 1XXXXXXX ECTL2[W] 000X0000 EUSA[W] XXX00000 ⎯⎯⎯⎯ EDTR1[W] XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ EIA0[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EIA1[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EIA2[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EIA3[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EIA4[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EIA5[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EIA6[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EIA7[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EDTA[R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EDTM[R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EOA0[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EOA1[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EPCR[R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX +3 ⎯⎯⎯⎯ ECTL3[R/W] 00X00X11 EDTC[W] 0000XXXX
Block
EWPT[R] 00000000_00000000 EDTR0[W] XXXXXXXX_XXXXXXXX
DSU (EVA chip only)
(Continued)
52
MB91350A Series
Address 000B54H 000B58H 000B5CH 000B60H 000B64H 000B68H 000B6CH 000B70H to 000BFCH 000C00H 000C04H to 000C14H 000C18H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH
Register +0 +1 +2 +3 EPSR[R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EIAM0[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EIAM1[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EOAM0/EODM0[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EOAM1/EODM1[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EOD0[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX EOD1[W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ Test register (access is not allowed.)
Block
DSU (EVA chip only)
Reserved Interrupt controller unit R-bus test
Test register (access is not allowed.)
⎯⎯⎯⎯ DMASA0[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA0[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA1[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA1[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA2[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA2[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA3[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA3[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
Reserved
DMAC
(Continued) 53
MB91350A Series
(Continued) Address 001020H 001024H 001028H to 001FFCH 007000H 007004H 007008H 00700CH 007010H 007014H to 0070FFH *1 : This is a test register. Access is disabled. *2 : The available area of internal RAM is restricted immediately after a reset is released. This setting therefore needs to be changed before using the internal RAM. In addition, at least one NOP instruction is required immediately after overwriting the setting for the available RAM area. *3 : This register does not exist on the MB91F353A/353A/352A/351A. Access is disabled. *4 : The 16 low-order bits (DTC [15 : 0]) of DMACA0 to DMACA4 cannot be byte-accessed. *5 : This register is accessed by the mode vector fetch. It cannot be accessed during normal operation. FLCR[R/W] 0110X000 FLWC[R/W] 00010011 ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Register +0 +1 +2 +3 DMASA4[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA4[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Reserved Flash memory Block
DMAC
Reserved
54
MB91350A Series
3. Vector table
Interrupt number
Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction System reserved System reserved Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0 (Reception completed) UART1 (Reception completed) UART2 (Reception completed) UART0 (Transmission completed) UART1 (Transmission completed) UART2 (Transmission completed) DMAC0 (end, error) DMAC1 (end, error)
10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22
Interrupt level ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18
Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH 378H 374H
TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H
Resource number ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6 7 11 ⎯ ⎯ ⎯ ⎯ ⎯ 8 9 10 0 1 2 3 4 5 ⎯ ⎯ (Continued) 55
MB91350A Series
Interrupt source DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) A/D IC System reserved System reserved SIO 6 SIO 7 UART3 (Reception completed) UART3 (Transmission completed) Reload timer 3/main oscillation stabilization wait timer Timebase timer overflow System reserved Clock counter U/D Counter 0 System reserved PPG 0 PPG 2 PPG 4 16-bit free-run timer ICU 0 (capture) ICU 1 (capture) ICU 2/3 (capture) OCU 0 (match) OCU 2 (match) System reserved System reserved Interrupt delay source bit System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved System reserved System reserved
2
Interrupt number
10 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
16 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44
Interrupt level ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 ⎯ ⎯ ⎯ ⎯ ⎯
Offset 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H 2F0H 2ECH
TBR default Resource address number 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH ⎯ ⎯ ⎯ 15 ⎯ ⎯ 12 13 14 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Continued)
56
MB91350A Series
(Continued) Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction
Interrupt number
10 69 70 71 72 73 74 75 76 77 78 79 80 to 255
16 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF
Interrupt level ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Offset 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H
TBR default Resource address number 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
57
MB91350A Series
■ PERIPHERAL RESOURCES
1. Interrupt Controller
(1) Description The interrupt controller manages interrupt reception and arbitration. Hardware configuration This module consists of the following components : • ICR register • Interrupt priority determination circuit • Interrupt level and interrupt number (vector) generator • HOLD request removal request generator • Main functions This module has the following major functions : • Detect NMI and interrupt requests • Prioritize interrupts (according to level and number) • Notify interrupt level of selected interrupt request (to CPU) • Notify interrupt number of selected interrupt request (to CPU) • Request (to the CPU) to return from stop mode in response to an NMI or interrupt request with interrupt level other than "11111B" • Issue requests to the bus master to cancel HOLD requests
58
MB91350A Series
(2) Register list Interrupt Control Register (ICR)
bit 7 bit 6 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ bit 5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ bit 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 bit 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 bit 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 bit 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 bit 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
(Continued)
59
MB91350A Series
(Continued)
bit 7
bit 6 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
bit 5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
bit 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4
bit 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3
bit 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2
bit 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1
bit 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0
ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Hold request cancel request register (HRCL)
HRCL
MHALTI ⎯ ⎯ LVL4 LVL3 LVL2 LVL1 LVL0
60
MB91350A Series
(3) Block diagram
UNMI
WAKEUP
("1" when LEVEL ≠ 11111B)
Determine order of priority
5 NMI LEVEL4 to LEVEL0
LEVEL determination
RI00 ICR00
VECTOR determination
6
LEVEL, VECTOR Generation
HLDREQ Cancel NMI request
MHALTI
VCT5 to VCT0
R-bus
61
MB91350A Series
2. External Interrupt/NMI Control
(1) Description The external interrupt control unit is the block that controls external interrupt requests input to NMI and INT0 to INT15. The level that is detected as a request can be selected from “H”, “L”, rising edge, or falling edge (except for NMI). Note : The MB91F353A/353A/352A/351A does not have INT8 to INT15. (2) Register list External interrupt enable register (ENIR)
bit 7 EN7 bit 6 EN6 bit 5 EN5 bit 4 EN4 bit 3 EN3 bit 2 EN2 bit 1 EN1 bit 0 EN0
External interrupt request register (EIRR)
bit 15 ER7 bit 14 ER6 bit 13 ER5 bit 12 ER4 bit 11 ER3 bit 10 ER2 bit 9 ER1 bit 8 ER0
Request level setting register (ELVR)
bit 15 LB7 bit 7 LB3 bit 14 LA7 bit 6 LA3 bit 13 LB6 bit 5 LB2 bit 12 LA6 bit 4 LA2 bit 11 LB5 bit 3 LB1 bit 10 LA5 bit 2 LA1 bit 9 LB4 bit 1 LB0 bit 8 LA4 bit 0 LA0
The above registers (for 8 channels) are available in 2 sets; there are a total of 16 channels.
(3) Block diagram
R-bus 8
Interrupt enable register
Edge detection circuit
17 INT0 to INT15 NMI
Interrupt request
17
Gate
Request F/F
8
Interrupt source register
16
Interrupt level setting register
62
MB91350A Series
3. REALOS-related Hardware
REALOS-related hardware is used by the real-time OS. Therefore, it cannot be used by user programs when REALOS is used. • Delay interrupt module (1) Description The delayed interrupt module generates a task switching interrupt. This module enables software to issue or cancel an interrupt request to the CPU. (2) Register list Delayed Interrupt Control Register (DICR)
bit 7 ⎯ bit 6 ⎯ bit 5 ⎯ bit 4 ⎯ bit 3 ⎯ bit 2 ⎯ bit 1 ⎯ bit 0 DLYI
(3) Block diagram
R-bus
DLYI
Interrupt request
63
MB91350A Series
• Bit Search Module (1) Description The bit search module searches data written to an input register for “0”, “1”, or a change point and returns the detected bit position. (2) Register list
bit 31 bit 0
0 detection data register (BSD0) 1 detection data register (BSD1) Data register for transition detection (BSDC) Detection result register (BSRR)
(3) Block diagram
D-bus
Input latch
Address decoder
Input detection mode
Creating 1 detection data
Input bit search circuit
Search results
64
MB91350A Series
4. 8/16-bit Up/Down Counter
(1) Description This block is the up/down counter/timer consisting of six event input pins, two 8-bit up/down counter, two 8-bit reload/compare registers, and their control circuit. The MB91F355A/F356B/F357B/355A/354A/V350A contains 2 channels of 8-bit up/down counter in this block. The MB91F353A/353A/352A/351A contains 1 channel of 8-bit up/down counter in this block. It is not possible to use in 16-bit mode. This module has the following features. • 8-bit count register enabling counting from (0)d to (255)d (enabling counting from (0)d to (65535)d in 16 bits × 1 operation mode) • Four different count modes available with selectable count clocks Count mode Timer mode Up/down count mode Phase difference count mode (2 Multiplication) Phase difference count mode (4 Multiplication) • In timer mode, the ability to select the count clock input to use from among two internal clock circuits Count clock 80 ns (12.5 MHz : Frequency division by 2) (When operating at 320 ns (3.125 MHz : Frequency division by 8) 25 MHz) • In up/down count mode, the ability to select the edge detection of the external pin input signals Detection edge Falling edge detection Rising edge detection Detection at rising edge, falling edge, or both edges Edge detection disabled • The phase difference count mode is suitable for counting encoders such as motor encoders, and facilitates to count the angle of revolution and number of revolutions to a high precision by inputting the A phase, B phase, and Z phase outputs from the encoder • ZIN pin has two selectable functions (valid in all modes) ZIN pin Counter clear function Gate function • Compare and reload functions that can be used separately or in combination. When both functions are used in combination, up/down counting can be performed at an arbitrary width. Compare/reload Compare function (output interrupt request on compare match) function Compare function (output interrupt request and clear counter on compare match) Reload function (output interrupt request and reload on underflow) Compare/reload function (output interrupt request and clear counter on compare match; output interrupt request and reload on underflow) Compare/reload disabled • Count direction flag used to identify the preceding count direction • Capable of independently controlling the generation of interrupts for compare match, reload (underflow), overflow, or on count direction change 65
MB91350A Series
(2) Register list • Up/down count register (UDCR) Up/down count register ch.0 (UDCR0)
bit 7 D07 bit 6 D06 bit 5 D05 bit 4 D04 bit 3 D03 bit 2 D02 bit 1 D01 bit 0 D00
Up/down count register ch.1 (UDCR1)*
bit 15 D15 bit 14 D14 bit 13 D13 bit 12 D12 bit 11 D11 bit 10 D10 bit 9 D09 bit 8 D08
• Reload compare register (RCR) Reload compare register ch.0 (RCR0)
bit 7 D07 bit 6 D06 bit 5 D05 bit 4 D04 bit 3 D03 bit 2 D02 bit 1 D01 bit 0 D00
Reload compare register ch.1 (RCR1)*
bit 15 D15 bit 14 D14 bit 13 D13 bit 12 D12 bit 11 D11 bit 10 D10 bit 9 D09 bit 8 D08
• Counter status register (CSR) Counter status register ch.0, ch.1 (CSR0, CSR1*)
bit 7 CSTR bit 6 CITE bit 5 UDIE bit 4 CMPF bit 3 OVFF bit 2 UDFF bit 1 UDF1 bit 0 UDF0
• Counter control register (CCRL) Counter control register ch.0, ch.1 (CCRL0, CCRL1*)
bit 7
Reserved
bit 6 CTUT
bit 5 UCRE
bit 4 RLDE
bit 3 UDCC
bit 2 CGSC
bit 1 CGE1
bit 0 CGE0
• Counter control register (CCRH) Counter control register ch.0 (CCRH0)
bit 15 M16E bit 14 CDCF bit 13 CFIE bit 12 CLKS bit 11 CMS1 bit 10 CMS0 bit 9 CES1 bit 8 CES0
• Counter control register ch.1 (CCRH1)*
bit 15
Reserved
bit 14 CDCF
bit 13 CFIE
bit 12 CLKS
bit 11 CMS1
bit 10 CMS0
bit 9 CES1
bit 8 CES0
* : Access to the UDCR1, RCR1, CSR1, CCRL1, CCRH1 registers is prohibited on the MB91F353A/353A/ 352A/351A.
66
MB91350A Series
(3) Block diagram • 8/16-bit up/down counter (ch.0) Data bus
CGE1 CGE0 CGSC
RCR0 (Reload compare register ch.0)
CTUT
M16E
To ch.1
ZIN0
Edge/level detection
UCRE
Reload control
Carry
RLDE
UDCC
Counter clear
CES1
CES0
UDCR0 (up/down UDCR0 counter register ch.0)
CMPF UDFF OVFF
CMS1 CMS0
AIN0 BIN0
Up/down count clock select
Count Clock
CSTR UDF1 UDF0 CDCF
UDIE
Prescaler
CITE
CLKS
CFIE
Interrupt output
67
MB91350A Series
•8/16-bit up/down counter (ch.1) Data bus
8 bits CGE1 CGE0 CGSC
RCR1 (Reload compare register ch.1)
CTUT
ZIN0, ZIN1
Edge/level detection
UCRE
Reload control
RLDE
UDCC
Counter clear
8 bits
CES1
CES0
UDCR1 (up/down counter register ch.1)
CMPF UDFF OVFF
CMS1 CMS0
AIN1 BIN1
Up/down count clock select Prescaler
Count Clock
CSTR UDF1 UDF0 CDCF
UDIE
CITE
CLKS
CFIE
Interrupt output
68
MB91350A Series
5. 16-bit Reload Timer
(1) Description The 16-bit timer consists of a 16-bit down counter, 16-bit reload register, internal clock, clock generation prescaler, and control register. The clock source can be selected from among three internal clocks (prepared by frequency dividing the machine clock by 2/8/32, and also by 64/128 only for ch.3) and an external event. The interrupt can be used to initiate a DMA transfer. The MB91F353A/353A/352A/351A does not have timer outputs (TOT0 to TOT3). This timer has 4 built-in channels. (2) Register list Control status register (TMCSR)
bit 15 ⎯ bit 14 ⎯ bit 13
Reserved
bit 12 CSL2
bit 11 CSL1
bit 10
bit 9
bit 8
CSL0 Reserved Reserved
(ch.3 only)
bit 7
Reserved
bit 6 ⎯
bit 5 OUTL
bit 4 RELD
bit 3 INTE
bit 2 UF
bit 1 CNTE
bit 0 TRG
16-bit timer register (TMR)
bit 15 bit 0
16-bit reload register (TMRLR)
bit 15 bit 0
69
MB91350A Series
(3) Block diagram
16 7
16-bit reload register (TMRLR)
Reload
16
16-bit timer register (TMR) UF Count enable
CSL2 R-bus
RELD OUTL OUT CTL. INTE UF IRQ
Re-trigger
Clock selector
CNTE TRG
CSL1 CSL0 External timer output (TOT0 to TOT3) IN CTL. EXCK TOE0 to TOE3
3 φ φ φ φ φ
21 23 25
Prescaler clear (ch.3 only)
26 27
Machine clock input
Note : The MB91F353A/353A/352A/351A does not have external timer outputs (TOT0 to TOT3).
70
MB91350A Series
6. PPG (Programmable Pulse Generator)
The PPG can efficiently output highly precise PWM wave forms. The MB91F353A/353A/352A/351A contains 3 channels of PPG timer. The MB91F355A/F356B/F357B/355A/354A/V350A contains 6 channels of PPG timer. (1) Description Each channel consists of a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare register with duty ratio setting buffer, and pin control unit. The count clocks for the 16-bit down counter can be selected from the following 4 types : (peripheral clock φ, φ/4, φ/16, φ/64) The counter is initialized to "FFFFH" at a reset or counter borrow. PPG outputs (PPG0 to PPG5) are provided for each channel. Note : The MB91F353A/353A/352A/351A contains 3 channels of PPG outputs PPG (0, 2, 4). There is no PPG (1, 3, 5). (2) Register list
bit 15 bit 0
General control register 10 (GCN10) General control register 20 (GCN20) Timer register (PTMR0 to PTMR5) Cycle setting register (PCSR0 to PCSR5) Duty setting register (PDUT0)
71
MB91350A Series
(3) Block diagram (overall configuration for 1 channel) 16-bit reload timer ch.0 TRG input PPG timer ch.0 TRG input PPG timer ch.1 TRG input PPG timer ch.2
4 PPG0
16-bit reload timer ch.1 General control register 10 (resource select) General control register 20
PPG1
PPG2
External TRG0 to TRG3
TRG input PPG timer ch.3
PPG3
External TRG4
TRG input PPG timer ch.4
PPG4
External TRG5
TRG input PPG timer ch.5
PPG5
Note : The MB91F353A/353A/352A/351A does not have PPG1, PPG3, PPG5 and external TRG5.
72
MB91350A Series
7. U-TIMER (16-bit timer for UART baud rate generation)
(1) Description The U-TIMER is a 16-bit timer for generating the baud rate for the UART. An arbitrary baud rate can be set depending on the combination of the chip operating frequency and U-TIMER reload value. The MB91F353A/353A/352A/351A contains 4 channels of this timer. The MB91F355A/F356B/F357B/355A/354A/V350A contains 5 channels of this timer. (2) Register list
bit 15
bit 8 bit 7
bit 0
U-TIMER register (UTIM) Reload register (UTIMR) U-TIMER control register (UTIMC)
(3) Block diagram
bit 15 UTIMR (reload register) load bit 15 UTIM (U-TIMER)
bit 0
bit 0
clock
φ (Peripheral clock)
underflow control
f.f.
to UART
73
MB91350A Series
8. UART
(1) Description The UART is a serial I/O port for asynchronous (start-stop) or CLK synchronous communication. This module has the features listed below. The MB91F353A/353A/352A/351A contains 4 channels of UART. The MB91F355A/F356B/F357B/355A/354A/V350A contains 5 channels of UART. • • • • • • • • • Full duplex double buffer Asynchronous (start-stop synchronized) or CLK synchronized transmission Supports multi-processor mode Completely programmable baud rate. Arbitrary baud rate set by built-in timer (Refer to the section for "U-timer".) Variable baud rate can be input from an external clock. Error detection functions(parity, framing, overrun) Transmission signal format is NRZ UART (ch.0 to ch.2) can start DMA transfers using interrupts (ch.3 and ch.4 cannot start DMA transfers). Capable of clearing DMAC interrupt source by writing to DRCL register
(2) Register list Serial input register/serial output register (SIDR/SODR)
bit 7 D7 bit 6 D6 bit 5 D5 bit 4 D4 bit 3 D3 bit 2 D2 bit 1 D1 bit 0 D0
Serial status register (SSR)
bit 7 PE bit 6 ORE bit 5 FRE bit 4 RDRF bit 3 TDRE bit 2 BDS bit 1 RIE bit 0 TIE
Serial mode register (SMR)
bit 7 MD1 bit 6 MD0 bit 5 ⎯ bit 4 ⎯ bit 3 CS0 bit 2 ⎯ bit 1 ⎯ bit 0 ⎯
Serial control register (SCR)
bit 7 PEN bit 6 P bit 5 SBL bit 4 CL bit 3 A/D bit 2 REC bit 1 RXE bit 0 TXE
DRCL register (DRCL)
bit 7 ⎯ bit 6 ⎯ bit 5 ⎯ bit 4 ⎯ bit 3 ⎯ bit 2 ⎯ bit 1 ⎯ bit 0 ⎯
74
MB91350A Series
(3) Block diagram Control signal
RX interrupt (to CPU) Transmission clock Clock selection circuit
Reception clock
From U-TIMER
SCK (clock) TX interrupt (to CPU)
External clock SCK SI (Receive data)
Reception control circuit
Start bit detection circuit Received bit Counter Received parity Counter
Transmission control circuit
Transmission start Transmission bit Counter Transmission parity Counter
SO (Send data)
Receive status decision circuit
RX shifter
RX complete
SIDR
TX shifter
Start transmission
SODR
For DMA received error generating signal (to DMAC)
R - bus
MD1 MD0
SMR Register
CS0
SCR Register
PEN P SBL CL A/D REC RXE TXE
SSR Register
PE ORE FRE RDRF TDRE BDS RIE TIE
Control signal
75
MB91350A Series
9. Extended I/O serial interface (SIO)
(1) Description This block is an 8-bit × 1 channel serial I/O interface that allows data transfer using clock synchronization. LSB-first or MSB-first transfer mode can be selected for data transfer. The MB91F353A/353A/352A/351A contains 2 channels of this SIO. The MB91F355A/F356B/F357B/355A/354A/V350A contains 3 channels of this SIO. The serial I/O interface operates in 2 modes : • Internal shift clock mode : Data is transferred synchronized with the internal clock. • External shift clock mode : Data is transferred synchronized with a clock supplied via the external pin (SCK). In this mode, data can also be transferred using CPU instructions by operating the general-purpose port that shares the external pin (SCK) . (2) Register list Serial mode control status register (SMCS)
bit 15 SMD2 bit 7 ⎯ bit 14 SMD1 bit 6 ⎯ bit 13 SMD0 bit 5 ⎯ bit 12 SIE bit 4 ⎯ bit 11 SIR bit 3 MODE bit 10 BUSY bit 2 BDS bit 9 STOP bit 1 ⎯ bit 8 STRT bit 0 ⎯
SIO test register (SES)
bit 15 ⎯ bit 14 ⎯ bit 13 ⎯ bit 12 ⎯ bit 11 ⎯ bit 10 ⎯ bit 9 TST1 bit 8 TST0
SDR (Serial Data Register) (SDR)
bit 7 D7 bit 6 D6 bit 5 D5 bit 4 D4 bit 3 D3 bit 2 D2 bit 1 D1 bit 0 D0
SIO prescaler control register (CDCR)
bit 15 MD bit 14 ⎯ bit 13 ⎯ bit 12 ⎯ bit 11 DIV3 bit 10 DIV2 bit 9 DIV1 bit 8 DIV0
DMAC interrupt source clear register (SRCL)
bit 7 ⎯ bit 6 ⎯ bit 5 ⎯ bit 4 ⎯ bit 3 ⎯ bit 2 ⎯ bit 1 ⎯ bit 0 ⎯
76
MB91350A Series
(3) Block diagram
Internal data bus (MSB first) D0 to D7
SI6, SI7
Initial Value
(LSB first) D0 to D7 Select transmitting direction Read Write
SDR (Serial Data Register)
SO6, SO7
SCK6, SCK7
Control circuit
Shift clock counter
Internal clock
2
1
0 SIE SIR BUSY STOP STRT MODE BDS SCE
SMD2 SMD1 SMD0
Interrupt request
PFR Register
Internal data bus
77
MB91350A Series
10. 16-bit free-run timer
(1) Description The 16-bit free-run timer consists of a 16-bit up counter, control register, and status register. The count values of this timer are used as the base timer for the output compare and input capture modules. • Four count clock frequencies are available. • An interrupt can be generated on counter overflow. • The counter can be initialized upon a match with compare register 0 of the output compare unit, depending on the mode.
(2) Register list Timer data register (upper) (TCDT)
bit 15 T15 bit 14 T14 bit 13 T13 bit 12 T12 bit 11 T11 bit 10 T10 bit 9 T9 bit 8 T8
Timer data register (lower) (TCDT)
bit 7 T07 bit 6 T06 bit 5 T05 bit 4 T04 bit 3 T03 bit 2 T02 bit 1 T01 bit 0 T00
Timer control status register (lower) (TCCS)
bit 7 ECLK bit 6 IVF bit 5 IVFE bit 4 STOP bit 3 MODE bit 2 CLR bit 1 CLK1 bit 0 CLK0
(3) Block diagram Interrupt
ECLK IVF IVFE STOP MODE CLR CLK1 CLK0
Divider
Clock select
φ FRCK
R-bus
Timer data register (TCDT)
Clock
To internal circuit (T15 to T00)
Comparator
78
MB91350A Series
11. Input Capture
(1) Description This module detects the rising or falling edge or both edges of an external input signal and then, stores the value of the 16-bit free-run timer in a register. In addition, the module can generate an interrupt upon detection of an edge. The input capture module consists of input capture data registers and a control register. Each input capture unit has a corresponding external input pin. • The detection edge of the external input can be selected from among 3 types. Rising edge Falling edge Both edges • An interrupt can be generated upon detection of a valid edge in the external input.
(2) Register list Input capture data register (upper) (IPCP)
bit 15 CP15 bit 14 CP14 bit 13 CP13 bit 12 CP12 bit 11 CP11 bit 10 CP10 bit 9 CP09 bit 8 CP08
Input capture data register (lower) (IPCP)
bit 7 CP07 bit 6 CP06 bit 5 CP05 bit 4 CP04 bit 3 CP03 bit 2 CP02 bit 1 CP01 bit 0 CP00
Input capture control register (ICS23)
bit 7 ICP3 bit 6 ICP2 bit 5 ICE3 bit 4 ICE2 bit 3 EG31 bit 2 EG30 bit 1 EG21 bit 0 EG20
Input capture control register (ICS01)
bit 7 ICP1 bit 6 ICP0 bit 5 ICE1 bit 4 ICE0 bit 3 EG11 bit 2 EG10 bit 1 EG01 bit 0 EG00
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MB91350A Series
(3) Block diagram
16-bit timer counter value (T15 to T00) Input capture data register ch.0, ch.2
Edge detection
IN0, IN2 Input pin
EG11 R-bus
EG10 EG30
EG01 EG21
EG00 EG20
16-bit timer counter value (T15 to T00) Input capture data register ch.1, ch.3
ICP1 ICP3
EG31
Edge detection
IN1, IN3 Input pin
ICE0 ICE2
ICP0 ICP2
ICE1 ICE3
Interrupt Interrupt
80
MB91350A Series
12. Output Compare
(1) Description The output compare module consists of a 16-bit compare register, compare output latch, and control register. When the 16-bit free-run timer value matches the compare register value, the output level is inverted and an interrupt is issued. The MB91F353A/353A/352A/351A contains 2 channels of this block. The MB91F355A/F356B/F357B/355A/354A/V350A contains 8 channels of this block. This module has the following features. • The output compare is able to operate independent of each of 8 compare register. There are output pins and interrupt flags corresponding to each of the compare registers. • A pair of compare registers can be used to control the output terminal. The output terminal is reversed by using two compare registers. • Capable of setting the initial value for each output pin. • Interrupts can be generated upon a compare match. • The ch.0 compare register is used as the compare clear register for the 16-bit free-run timer.
(2) Register list Compare register (OCCP)
bit 15 C15 bit 14 C14 bit 13 C13 bit 12 C12 bit 11 C11 bit 10 C10 bit 9 C09 bit 8 C08
Compare register (OCCP)
bit 7 C07 bit 6 C06 bit 5 C05 bit 4 C04 bit 3 C03 bit 2 C02 bit 1 C01 bit 0 C00
Output control register (OCS01)
bit 15 ⎯ bit 14 ⎯ bit 13 ⎯ bit 12 CMOD bit 11 ⎯ bit 10 ⎯ bit 9 OTD1 bit 8 OTD0
Output control register (OCS23)
bit 7 ICP1 bit 6 ICP0 bit 5 ICE1 bit 4 ICE0 bit 3 ⎯ bit 2 ⎯ bit 1 CST1 bit 0 CST0
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MB91350A Series
(3) Block diagram
(Only ch.0 is used as a free-run timer clear register.)
Output compare register
OTD1
OTD0
Compare circuit
Output compare register
Compare output latch
CMOD
OTE0, OTE2, OTE4, OTE6
Output (ch.0, ch.2, ch.4, ch.6)
OTE0 and OTE7 exist in PFR0.
Compare output latch
OTE1, OTE3, OTE5, OTE7
R-bus
Compare circuit
Output (ch.1, ch.3, ch.5, ch.7)
CST1
CST0
ICP1
ICP0
ICE1
ICE0
16-bit free-run timer
Interrupt output Interrupt output
82
MB91350A Series
13. I2C Interface
(1) Description The I2C interface is a serial I/O port supporting the Inter-IC bus, operating as a master/slave device on the I2C bus. It has the following features : • Master/slave transmission and reception • Arbitration function • Clock sync function • Slave address and general call address detection function • Transmission direction detection function • Repeated start condition generation and detection function • Bus error detection function • 10-bit/7-bit slave address • Slave address receive acknowledge control when in master mode • Support for composite slave addresses • Capable of interrupt when a transmission or bus error occurs • Standard mode (Max 100 kbps)/High speed mode (Max 400 kbps) supported
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MB91350A Series
(2) Register list Bus control register (IBCR)
bit 15 BER bit 14 BEIE bit 13 SCC bit 12 MSS bit 11 ACK bit 10 GCAA bit 9 INTE bit 8 INT
Bus status register (IBSR)
bit 7 BB bit 6 RSC bit 5 AL bit 4 LRB bit 3 TRX bit 2 AAS bit 1 GCA bit 0 ADT
10-bit slave address resister (ITBA)
bit 15 ⎯ bit 7 TA7 bit 14 ⎯ bit 6 TA6 bit 13 ⎯ bit 5 TA5 bit 12 ⎯ bit 4 TA4 bit 11 ⎯ bit 3 TA3 bit 10 ⎯ bit 2 TA2 bit 9 TA9 bit 8 TA8
bit 1 TA1
bit 0 TA0
10-bit slave address mask resister (ITMK)
bit 15 ENTB bit 14 RAL bit 13 ⎯ bit 5 TM5 bit 12 ⎯ bit 4 TM4 bit 11 ⎯ bit 3 TM3 bit 10 ⎯ bit 2 TM2 bit 9 TM9 bit 8 TM8
bit 7 TM7
bit 6 TM6
bit 1 TM1
bit 0 TM0
7-bit slave address resister (ISBA)
bit 7 ⎯ bit 6 SA6 bit 5 SA5 bit 4 SA4 bit 3 SA3 bit 2 SA2 bit 1 SA1 bit 0 SA0
7-bit slave address mask resister (ISMK)
bit 15 ENSB bit 14 SM6 bit 13 SM5 bit 12 SM4 bit 11 SM3 bit 10 SM2 bit 9 SM1 bit 8 SM0
D/A data register (IDAR)
bit 7 D7 bit 6 D6 bit 5 D5 bit 4 D4 bit 3 D3 bit 2 D2 bit 1 D1 bit 0 D0
Clock control register (ICCR)
bit 15 TEST bit 14 ⎯ bit 13 EN bit 12 CS4 bit 11 CS3 bit 10 CS2 bit 9 CS1 bit 8 CS0
Clock disable register (IDBL)
bit 7 ⎯ bit 6 ⎯ bit 5 ⎯ bit 4 ⎯ bit 3 ⎯ bit 2 ⎯ bit 1 ⎯ bit 0 DBL
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MB91350A Series
(3) Block diagram
ICCR EN IDBL DBL ICCR CS4 CS3 CS2 CS1 CS0 IBSR BB RSC LRB TRX ADT AL
I2C operation enable Clock enable Clock divide 2
2345 32 Sync CLKP
Shift clock generation
Clock selector 2 (1/12) Shift clock edge changing timing
Bus busy Start
Last Bit
Sending/ receiving
Start stop condition detection Error
First byte
Arbitration lost detection
SCL
R- bus
IBCR BER BEIE INTE INT IBCR SCC MSS ACK GCAA
Interrupt request
IRQ
SDA
Start Master ACK enable GC-ACK enable
End
Start stop condition generation
IDAR IBSR AAS GCA ISMK ENSB ITMK ENTB RAL ITBA ITMK ISBA ISMK
Slave Global call Slave address compare
85
MB91350A Series
14. A/D converter
(1) Description The A/D converter converts the analog input voltage into a digital value. It has the following features : • Conversion time : 1.48 µs minimum per channel • Employing serial / parallel conversion type for sample and hold circuit. • 10-bit resolution (switchable between 8 and 10 bits) • Programmatic selection of the analog input from among 12 channels (The MB91F353A/353A/352A/351A are input 8 channels.) • Conversion mode Single conversion mode : Converts 1 selected channel a single time. Scan conversion mode : Scanning conversion of up to 4 channels. • Converted data is stored in a data buffer (a total of 4 data buffers) . • An interrupt request to the CPU can be generated upon completion of A/D conversion. The interrupt can be used to start a DMA transfer. • The startup source can be selected from among software, external trigger (falling edge), and reload timer ch.2 (rising edge).
(2) Register list
bit 15 bit 8 bit 7 ADCS2 ADCS1 bit 0
Control status register (ADCS2/ADCS1) Conversion time setting register (ADCT) Converted data register 0 (ADTH0/ADTL0) Converted data register 1 (ADTH1/ADTL1) Converted data register 2 (ADTH2/ADTL2) Converted data register 3 (ADTH3/ADTL3)
ADTH0 ADTH1 ADTH2 ADTH3
ADTL0 ADTL1 ADTL2 ADTL3
86
MB91350A Series
(3) Block diagram
Analog input
AVCC, AVRH, AVSS/AVRL
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11
S/H
ADT2 ADT3
Control logic
Interrupt
16-bit reload timer ch.2 External input
Note : The MB91F353A/353A/352A/351A does not have inputs AN8 to AN11.
R-bus
M P X
ADT0 10-bit A/D Convertor M P X ADT1
87
MB91350A Series
15. 8-bit D/A converter
(1) Description This block contains 3 channels of 8-bit D/A converters and D/A converter registers that can be used to control the independent output of each channel. The block has the following features. • Power saving function • 3.3 V interface Note : The MB91F353A/353A/352A/351A contains 2 channels of D/A converter. (2) Register list D/A data register 0 to 2 (DADR0 to DADR2)
bit 7 DA7 bit 6 DA6 bit 5 DA5 bit 4 DA4 bit 3 DA3 bit 2 DA2 bit 1 DA1 bit 0 DA0
D/A control register 0 to 2 (DACR0 to DACR2)
bit 7 ⎯ bit 6 ⎯ bit 5 ⎯ bit 4 ⎯ bit 3 ⎯ bit 2 ⎯ bit 1 ⎯ bit 0 DAE
Note : The MB91F353A/353A/352A/351A does not have DADR2, DACR2. (3) Block diagram
R-bus
D/A control
D/A
D/A
D/A
DAE0 PD STOP
DAE1 PD STOP
DAE2 PD STOP
D/A converter
D/A converter
D/A converter
D/A output 0
D/A output 1
D/A output 2
88
MB91350A Series
16. DMAC (DMA Controller)
(1) Description This module provides direct memory access (DMA) transfers in the FR family devices. The DMAC enables high speed transfers for various data without CPU intervention, thereby improving system performance. • Hardware configuration The main components of this module are as follows : • Independent DMA channels × 5 channels • 5 channels independent access control circuits • 32-bit address registers (Supports reloading : 2 per channel) • 16-bit transfer count registers (Supports reloading : 1 per channel) • 4-bit block count registers (1 per channel) • External transfer request input pins : DREQ0, DREQ1, and DREQ2. For ch.0 to ch.2 only Note : The MB91F353A/353A/352A/351A do not have an external interface. • External transfer request acceptance output pins : DACK0, DACK1, and DACK2. For ch.0 to ch.2 only Note : The MB91F353A/353A/352A/351A do not have an external interface. • DMA end output pins : DEOP0, DEOP1, and DEOP2. For ch.0 to ch.2 only Note : The MB91F353A/353A/352A/351A do not have an external interface. • Fly-by transfer (memory to I/O and I/O to memory). For ch.0 to ch.2 only Note : The MB91F353A/353A/352A/351A do not support fly-by transfer. • 2-cycle transfer • Main functions This module has the following major functions for data transfer : • Supports data transfer over multiple independent channels (5 channels) (1) Priority order (ch.0 > ch.1 > ch.2 > ch.3 > ch.4) (2) Order can be reversed for ch.0 and ch.1 (3) DMAC activation triggers • External dedicated pin input (edge detection/level detection for ch.0 to ch.2 only) Note : The MB91F353A/353A/352A/351A do not have an external interface. • Internal peripheral request (Interrupt request sharing, including external interrupts) • Software request (register write) (4)Transmission mode • Demand transfer, burst transfer, step transfer, or block transfer • Addressing mode : 32-bit full addressing (increment, decrement, or fixed) (address increment can be in the range - 255 to + 255) • Data length : Byte, halfword, or word • Single-shot or reload operation selectable
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MB91350A Series
(2) Register Description
bit 31 bit 0
ch.0 Control/status ch.1 Control/status ch.2 Control/status ch.3 Control/status ch.4 Control/status Overall control register ch.0 Transfer source address register ch.1 Transfer source address register ch.2 Transfer source address register ch.3 Transfer source address register ch.4 Transfer source address register
Register A Register B Register A Register B Register A Register B Register A Register B Register A Register B
(DMACA0) (DMACB0) (DMACA1) (DMACB1) (DMACA2) (DMACB2) (DMACA3) (DMACB3) (DMACA4) (DMACB4) (DMACR)
(DMASA0) (DMADA0) (DMASA1) (DMADA1) (DMASA2) (DMADA2) (DMASA3) (DMADA3) (DMASA4) (DMADA4)
90
MB91350A Series
(3) Block diagram
Counter DMA transfer request to bus controller Buffer Selector
Write back
DTC two-stage register DTCR
DMA start source select circuit & request acceptance control
Peripheral start request/ Stop input External pin start request/ Stop input
Counter
DSS [3:0]
Buffer
Read Write
Priority circuit
To interrupt controller
IRQ [4:0] MCLREQ
Read/write control
Selector
BLK register
ERIR, EDIR
Bus control block
Selector
DDNO
DDNO register
Counter buffer
To bus controller
DMA control
Selector DSAD two-stage register
SADM, SASZ [7:0] SADR
Address counter
Access address
Write back
Counter buffer
Selector
DDAD two-stage register
DADM, DASZ [7:0] DADR
Write back
5-channel DMAC block diagram
Bus control block
X-bus
State transition circuit
Clear peripheral interrupt
TYPE, MOD, WS
91
MB91350A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter Power supply voltage*1 Analog power supply voltage* Analog reference voltage*1 Input voltage*1 Input voltage (N-ch open-drain) * Analog pin input voltage* Output voltage*
1 1 1 1
Symbol VCC DAVC AVCC AVRH VI VIND VIA VO ICLAMP Σ|ICLAMP| IOL IOLND IOLAV IOLAVND ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD Ta TSTG
Rating Min VSS − 0.5 VSS − 0.5 VSS − 0.5 VSS − 0.5 VSS − 0.5 VSS − 0.5 VSS − 0.5 VSS − 0.5 − 2.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ − 40 ⎯ Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VCC + 0.5 VSS + 5.5 AVCC + 0.5 VCC + 0.5 + 2.0 20 10 20 8 15 100 50 − 10 −4 − 50 − 20 850 + 85 + 125
Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mW °C °C
Remarks *2 *3 *3 *3 *8 *8 *7 *7 *4
Analog power supply voltage*1
Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level maximum output current (N-ch open-drain) “L” level average output current “L” level average output current (N-ch open-drain) “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature
*5
*6 *4 *5 *6
*1 : The parameter is based on VSS = DAVS = AVSS = 0 V. *2 : VCC must not be lower than VSS − 0.3 V. *3 : Be careful not to exceed "VCC + 0.3 V" , for example, when the power is turned on. *4 : The maximum output current is the peak value for a single pin. *5 : The average output current is the average current for a single pin over a period of 100 ms. *6 : The total average output current is the average current for all pins over a period of 100 ms. (Continued)
92
MB91350A Series
(Continued) *7 : • Relevant pins : Ports 2, 3, 4, 5, 6, 8, 9, A, H, I, K, M, N, O and AN (A/D input) : MB91F353A/353A/352A/351A Ports 2, 3, 4, 5, 6, 8, 9, A, B, C, G, H, I, J, K, M, N, O, P and AN (A/D input) : MB91F355A/F356B/F357B/355A/354A • Use within recommended operating conditions. • Use at DC voltage (current). • + B signals are input signals that exceed the VCC voltage. • A limiting resistance should always be applied to +B signals by connecting the resistance between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in low power consumption mode, the + B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. • Note that if a + B input is applied when the microcontroller is off (not fixed at 0 V), power is supplied through the pin, possibly causing the microcontroller to partially operate. • Note that if a + B input is applied when the power supply is turned on, power is supplied through the pin, possibly resulting in a power-supply voltage at which power-on reset does not work. • Ensure that a + B input pin does not form an open circuit. • Note that analog I/O pins other than the A/D input pins (such as the LCD drive and comparator input pins) cannot input + B. • Sample recommended circuits : • Input/output equivalent circuits Protective diode
Vcc
Limiting resistance + B input (0 V to 16 V)
P-ch
N-ch
R
*8 : VI must not exceed the rated voltage. However, If the maximum current to/from an input is limited by some means using external components, the ICLAMP rating supersedes the VI rating. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
93
MB91350A Series
2. Recommended Operating Conditions
( Other than MB91F356B/F357B) (VSS = DAVS = AVSS = 0 V) Parameter Power supply voltage Analog power supply voltage Analog reference voltage Operating temperature Symbol VCC VCC DAVC AVCC AVRH Ta Value Min 3.0 3.0 VSS − 0.3 VSS − 0.3 AVSS − 40 Max 3.6 3.6 VSS + 3.6 VSS + 3.6 AVCC + 85 Unit V V V V °C Remarks During normal operation Hold RAM status at stop
(MB91F356B/F357B only) (VSS = DAVS = AVSS = 0 V) Parameter Symbol VCC Power supply voltage VCC VCC Analog power supply voltage Analog reference voltage Operating temperature * : Including the F355A/F353A WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. DAVC AVCC AVRH Ta Value Min 2.7 2.7 3.0 VSS − 0.3 VSS − 0.3 AVSS − 40 0 Max 3.6 3.6 3.6 VSS + 3.6 VSS + 3.6 AVCC + 85 +70 Unit V V V V V °C °C When writing or erasing Flash memory* Remarks During normal operation Hold RAM status at stop When writing or erasing Flash memory
94
MB91350A Series
3. DC Characteristics
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) , VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C) Parameter
Symbol
Pin name Port 2, 3, 4, 5, 6, 9, A Port 2, 3, 4, 5, 6, 9, A, B, C Port 8, H, I, M, N, O, MD0, MD1, MD2, INIT, NMI Port 8, G, H, I, M, N, O, P, MD0, MD1, MD2, INIT, NMI Port K, L
Conditions
Value Min VCC × 0.65 Typ Max
Unit
Remarks
MB91F353A/353A/ 352A/351A MB91F355A/F356B/ F357B/355A/354A
VIH
VCC + 0.3
Hysteresis input MB91F353A/353A/ 352A/351A Hysteresis input MB91F355A/F356B/ F357B/355A/354A Hysteresis input withstand voltage of 5 V MB91F353A/353A/ 352A/351A Hysteresis input withstand voltage of 5 V MB91F355A/F356B/ F357B/355A/354A MB91F353A/353A/ 352A/351A MB91F355A/F356B/ F357B/355A/354A Hysteresis input MB91F353A/353A/ 352A/351A Hysteresis input MB91F355A/F356B/ F357B/355A/354A Hysteresis input withstand voltage of 5 V MB91F353A/353A/ 352A/351A Hysteresis input withstand voltage of 5 V MB91F355A/F356B/ F357B/355A/354A
VIHS “H” level input voltage
⎯ VCC × 0.8
⎯
V
VIHST Port J, K, L Port 2, 3, 4, 5, 6, 9, A Port 2, 3, 4, 5, 6, 9, A, B, C Port 8, H, I, M, N, O, MD0, MD1, MD2, INIT, NMI Port 8, G, H, I, M, N, O, P, MD0, MD1, MD2, INIT, NMI Port K, L VILST Port J, K, L ⎯ VSS ⎯
5.25
VIL
VCC × 0.25
VILS “L” level input voltage
V VCC × 0.2
(Continued)
95
MB91350A Series
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) , VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C) Parameter
Symbol
Pin name Port 2, 3, 4, 5, 6, 8, 9, A, H, I, J, K, M, N, O
Conditions
Value Min Typ Max
Unit
Remarks
MB91F353A/ 353A/352A/351A VCC − 0.5 ⎯ VCC V MB91F355A/ F356B/F357B/ 355A/354A
“H” level output voltage
VOH
VCC = 3.0 V, Port 2, 3, 4, IOH = −4.0 mA 5, 6, 8, 9, A, B, C, G, H, I, J, K, M, N, O, P
Port 2, 3, 4, 5, 6, 8, 9, A, H, I, K, M, N, O “L” level output voltage VOL1
MB91F353A/ 353A/352A/351A
VCC = 3.0 V, Port 2, 3, 4, IOL = 4.0 mA 5, 6, 8, 9, A, B, C, G, H, I, J, K, M, N, O, P Port L VCC = 3.0 V, IOL = 15.0 mA
VSS
⎯
0.4
V
MB91F355A/ F356B/F357B/ 355A/354A N-ch open-drain
VOL2 Input leak current (High-Z Output Leakage Current) Pull-up resistance
ILI
All input pin
VCC = 3.6 V, 0
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