MB96V300BRB-ES

厂商：
FUJITSU(富士通)
封装：
描述：
MB96V300BRB-ES - 16-bit Proprietary Microcontroller - Fujitsu Component Limited.

数据手册：

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数据手册
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MB96V300BRB-ES 数据手册

FUJITSU SEMICONDUCTOR DATA SHEET FME-MB96390 rev 3 16-bit Proprietary Microcontroller CMOS F2MC-16FX MB96390 Series MB96F395*1 ■ DESCRIPTION MB96390 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include signiﬁcantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 40MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 25ns going together with excellent EMI behavior. An on-chip clock modulation circuit signiﬁcantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A ﬂexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed. *1: These devices are under development and speciﬁcation is preliminary. These products under development may change its speciﬁcation without notice. Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. PR Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.6 EL http://edevice.fujitsu.com/micom/en-support/ IM IN AR Y MB96390 Series ■ FEATURES Feature Technology • 0.18µm CMOS • F2MC-16FX CPU • Up to 40 MHz internal, 25 ns instruction cycle time CPU • Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) • 8-byte instruction execution queue • Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available • On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop) • 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on Q-factor). • Up to 40 MHz external clock • 32-100 kHz subsystem quartz clock System clock Description • Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals. • Clock modulator On-chip voltage regula- • Internal voltage regulator supports reduced internal MCU voltage, offering low EMI tor and low power consumption figures Low voltage reset Code Security Memory Patch Function • Reset is generated when supply voltage is below minimum. • Protects ROM content from unintended read-out • Replaces ROM content • Can also be used to implement embedded debug support Interrupts Timers 2 PR • Fast Interrupt processing • 8 programmable priority levels • Non-Maskable Interrupt (NMI) • Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) • Watchdog Timer EL IM • Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode) IN • 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog AR Y FME-MB96390 rev 3 MB96390 Series Feature • ISO16845 certified • Bit rates up to 1 Mbit/s • 32 message objects CAN • Each message object has its own identifier mask • Programmable FIFO mode (concatenation of message objects) • Maskable interrupt • Disabled Automatic Retransmission mode for Time Triggered CAN applications • Full duplex USARTs (SCI/LIN) USART Description • Supports CAN protocol version 2.0 part A and B • Wide range of baud rate settings using a dedicated reload timer • Special synchronous options for adapting to different synchronous serial protocols • LIN functionality working either as master or slave LIN device • Master and Slave functionality, 7-bit and 10-bit addressing • SAR-type • 10-bit resolution • Up to 400 kbps A/D converter • 16-bit wide Reload Timers • Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency • Event count function • Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency • 16-bit wide • Signals an interrupt upon external event • Rising edge, falling edge or rising & falling edge sensitive • 16-bit wide • A pair of compare registers can be used to generate an output signal. • 16-bit down counter, cycle and duty setting registers • Interrupt at trigger, counter borrow and/or duty match • PWM operation and one-shot operation • Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer underflow as clock input • Can be triggered by software or reload timer Free Running Timers Input Capture Units Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs Programmable Pulse Generator FME-MB96390 rev 3 PR EL IM • Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer IN I2C AR • Programmable loop-back mode for self-test operation Y 3 MB96390 Series Feature Description • Stepper Motor Controller with integrated high current output drivers • Four high current outputs for each channel Stepper Motor Control- • Two synchronized 8/10-bit PWMs per channel ler • Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock • Separate power supply for high current output drivers • Internal or external voltage generation • Fixed 1/3 bias • Programmable frame period • LCD controller with up to 4 COM × SEG • Duty cycle: Selectable from options: 1/2, 1/3 and 1/4 • Clock source selectable from three options (peripheral clock, subclock or RC oscillator clock) LCD Controller • On-chip drivers for internal divider resistors or external divider resistors • LCD display can be operated in Timer Mode • Blank display: selectable • All SEG, COM and V pins can be switched between general and specialized purposes • External divided resistors can be also used to shut off the current when LCD is deactivated Sound Generator • 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter • Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the RC oscillator Real Time Clock • Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) • PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock • On-chip data memory for display External Interrupts Non Maskable Interrupt 4 PR • Read/write accessible second/minute/hour registers • Can signal interrupts every half second/second/minute/hour/day • Internal clock divider and prescaler provide exact 1s clock • Edge sensitive or level sensitive • Interrupt mask and pending bit per channel • Each available CAN channel RX has an external interrupt for wake-up • Selected USART channels SIN have an external interrupt for wake-up • Disabled after reset • Once enabled, can not be disabled other than by reset. • Level high or level low sensitive • Pin shared with external interrupt 0. EL IM IN AR Y FME-MB96390 rev 3 MB96390 Series Feature Description • Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds Alarm comparator • Threshold voltages defined externally or generated internally • Status is readable, interrupts can be masked separately • Virtually all external pins can be used as general purpose I/O • All push-pull outputs (except when used as I2C SDA/SCL line) I/O Ports • Bit-wise programmable input enable • Bit-wise programmable pull-up resistor Packages • 100-pin plastic LQFP • Bit-wise programmable as input/output or peripheral signal • Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL • Bit-wise programmable output driving strength for EMI optimization • Supports automatic programming, Embedded Algorithm • Write/Erase/Erase-Suspend/Resume commands • A flag indicating completion of the algorithm • Number of erase cycles: 10,000 times Flash Memory • Data retention time: 20 years • Sector protection • Erase can be performed on each sector individually • Flash Security feature to protect the content of the Flash • Low voltage detection during Flash erase FME-MB96390 rev 3 PR EL IM IN AR Y 5 MB96390 Series ■ PRODUCT LINEUP Features Product type Product options MB96V300B Evaluation sample MB96(F)39x Flash product: MB96F39x Mask ROM product: MB9639x RS NA YW RW Flash/ROM RAM ROM/Flash memory emulation by external RAM, 92KB internal RAM BGA416 16 channels 10 channels 2 channels 40 channels yes Low voltage reset can be disabled / Single clock devices Low voltage reset can be disabled / Dual clock devices 160KB 5KB Package DMA USART I2C A/D Converter A/D Converter Reference Voltage switch 16-bit Reload Timer 16-bit Free-Running Timer 16-bit Output Compare 16-bit Input Capture IN 1 IM 1 channel 6 channels + 1 channel (for PPG) 4 channels EL 12 channels PR 12 channels 20 channels 5 channels 6 channels 16 channels 2 channels 4 COM x 72 SEG 16-bit Programmable Pulse Generator CAN Interface Stepping Motor Controller External Interrupts Non-Maskable Interrupt Sound generator LCD Controller Real Time Clock 6 AR No Low voltage reset persistently on / Dual clock devices MB96F395Y*1, MB96F395R*1, FPT-100P-M20 0 channels 3 channels 1 channel 11 channels 4 channels + 1 channel (for PPG) 2 channels 4 channels 4 channels 4 channels 1 channels 4 channels 8 channels 4 COM x 49 SEG Y 1 channels YS Low voltage reset persistently on / Single clock devices FME-MB96390 rev 3 MB96390 Series Features I/O Ports Alarm comparator External bus interface Clock output function Low voltage reset On-chip RC-oscillator MB96V300B 136 2 channels Yes 2 channels Yes MB96(F)39x 74 for part number with sufﬁx "W", 76 for part number with sufﬁx "S" 1 channels No FME-MB96390 rev 3 PR EL IM IN AR *1: These devices are under development and speciﬁcation is preliminary. These products under development may change its speciﬁcation without notice. Y Yes 7 MB96390 Series ■ BLOCK DIAGRAMS Block diagram of MB96F39x CKOT0_R, CKOT1, CKOT1_R CKOTX0, CKOTX1, CKOTX1_R X0, X1 X0A, X1A *1 RSTX MD0...MD2 NMI Y Memory Patch Unit 16FX CPU Interrupt Controller Flash Memory A Clock & Mode Controller 16FX Core Bus (CLKB) AR RAM Watchdog Peripheral Bus Bridge Peripheral Bus Bridge Boot ROM Voltage Regulator SDA0 SCL0 I2C 1 ch. Peripheral Bus 2 (CLKP2) IN IM USART 3 ch. Alarm Comparator 1 ch. 16-bit PPG 4 ch. RLT6 Stepper Motor Controller 4 ch. Real Time Clock Peripheral Bus 1 (CLKP1) VCC VSS C TX0 RX0 SGO0 SGA0 AVCC AVSS AVRH AVRL AN2,3,4,6,7,8,10 AN11,12,14,15 ADTG 10-bit ADC 11 ch. CAN Interface 1 ch. Sound Generator 1 ch. FRCK1 IN6,IN7 IN7_R INT0 ... INT7 INT1_R ... INT7_R V0 ... V3 COM0 ... COM3 SEG0 ... SEG64 (Except 5,6,8,9,10, 29,31,32,34,35,48 49,50,54,58,62) I/O Timer 1 ICU 6/7 PR External Interrupt LCD controller/ driver FRCK0 FRCK0_R IN0 IN0_R,IN1_R OUT0 ... OUT3 OUT0_R,OUT2_R EL TIN0, TIN1 TIN2, TIN3 TOT0, TOT1 TOT2, TOT3 16-bit Reload Timer 4 ch. SIN0...SIN2 SOT0...SOT2 SCK0...SCK2 I/O Timer 0 ICU 0/1 OCU 0/1/2/3 ALARM0 TTG0,TTG2,TTG3 PPG0,PPG1,PPG3 PPG0_R ... PPG3_R PWM1M0 ... PWM1M2,PWM1M4 PWM1P0 ... PWM1P2,PWM1P4 PWM2M0 ... PWM2M2,PWM2M4 PWM2P0 ... PWM2P2,PWM2P4 DVCC DVSS WOT *1: X0A, X1A only available on devices with sufﬁx “W” 8 FME-MB96390 rev 3 MB96390 Series ■ PIN ASSIGNMENTS Pin assignment of MB96F39x Vss P00_3/INT6_R/SEG15 P00_4/INT7_R/SEG16 P00_5/TTG2/IN6/SEG17 P00_6/TTG3/IN7/SEG18 P00_7/SGO0/SEG19 P01_0/SGA0/SEG20 P01_1/OUT0/CKOT1/SEG21 P01_2/OUT1/CKOTX1/SEG22 P01_3/SEG23 P01_4/SEG24 P01_5/SEG25 P01_6/SEG26 P01_7/CKOTX1_R/SEG27 P02_0/CKOT1_R/SEG28 P02_2/CKOT0_R/IN7_R/SEG30 P02_5/OUT0_R/SEG33 P03_0/V0/SEG36 P03_1/V1/SEG37 P03_2/V2/SEG38 P03_3/V3/SEG39 P03_4/INT4/RX0 P03_5/TX0 P03_6/NMI/INT0 Vcc 76 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AR 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P00_1/INT4_R/SEG13 P00_0/INT3_R/SEG12 P12_7/INT1_R/SEG11 P12_3/OUT2_R/SEG7 P12_0/IN1_R/SEG4 P11_7/IN0_R/SEG3 P11_6/FRCK0_R/SEG2 P11_5/SEG1 P11_4/PPG3_R/SEG0 P11_3/PPG2_R/COM3 P11_2/PPG1_R/COM2 P11_1/PPG0_R/COM1 P11_0/COM0 RSTX X1A/P04_1 *1 X0A/P04_0 *1 Vss X1 X0 MD2 MD1 MD0 Vss Vcc P00_2/INT5_R/SEG14 77 IN AVRL AVss P05_0/AN8/ALARM0/SEG57 LQFP - 100 Package code (mold) FPT-100P-M20 IM 1 EL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Vss C P03_7/INT1/SIN1/SEG40 P13_0/INT2/SOT1/SEG41 P13_1/INT3/SCK1/SEG42 P13_2/PPG0/TIN0/FRCK1/SEG43 P13_3/PPG1/TOT0/WOT/SEG44 P13_4/SIN0/INT6/SEG45 P13_5/SOT0/ADTG/INT7/SEG46 P13_6/SCK0/CKOTX0/SEG47 P04_4/PPG3/SDA0 P04_5/SCL0 P06_2/AN2/INT5/SEG51 P06_3/AN3/FRCK0/SEG52 *1: Devices with sufﬁx W: X0A, X1A Devices with sufﬁx S: P04_0, P04_1 PR (FPT-100P-M20) FME-MB96390 rev 3 P06_4/AN4/IN0/TTG0/SEG53 P06_6/AN6/TIN1/SEG55 P06_7/AN7/TOT1/SEG56 AVcc AVRH P05_2/AN10/OUT2/SEG59 P05_3/AN11/OUT3/SEG60 Vcc Y Vcc P10_3/PWM2M4 P10_2/PWM2P4/SCK2 P10_1/PWM1M4/SOT2/TOT3 P10_0/PWM1P4/SIN2/TIN3 DVss DVcc P09_3/PWM2M2 P09_2/PWM2P2 P09_1/PWM1M2 P09_0/PWM1P2 P08_7/PWM2M1 P08_6/PWM2P1 P08_5/PWM1M1 DVss DVcc P08_4/PWM1P1 P08_3/PWM2M0 P08_2/PWM2P0 P08_1/PWM1M0 P08_0/PWM1P0 P05_7/AN15/TOT2/SEG64 P05_6/AN14/TIN2/SEG63 P05_4/AN12/INT2_R/SEG61 Vss 9 MB96390 Series ■ PIN FUNCTION DESCRIPTION Pin Function description (1 of 2) Pin name ADTG ALARMn ANn AVCC AVRH AVRL AVSS C CKOTn CKOTn_R CKOTXn CKOTXn_R COMn DVCC FRCKn FRCKn_R INn INn_R INTn INTn_R MDn NMI OUTn OUTn_R Pxx_n PPGn PPGn_R PWMn RSTX Feature ADC Alarm comparator ADC Supply ADC ADC Supply Voltage regulator Clock output function Clock output function Clock output function Clock output function LCD Supply Free Running Timer Free Running Timer ICU ICU Description A/D converter trigger input Alarm Comparator n input A/D converter channel n input Analog circuits power supply A/D converter high reference voltage input A/D converter low reference voltage input Analog circuits power supply Internally regulated power supply stabilization capacitor pin Clock Output function n output Relocated Clock Output function n inverted output IM EL External Interrupt External Interrupt Core PR OCU OCU GPIO PPG PPG SMC Core External Interrupt Relocated Output Compare Unit n waveform output General purpose IO Programmable Pulse Generator n output Relocated Programmable Pulse Generator n output SMC PWM high current Reset input 10 IN Relocated Clock Output function n output Clock Output function n inverted output Relocated Free Running Timer n input Input Capture Unit n input Relocated Input Capture Unit n input External Interrupt n input Relocated External Interrupt n input Input pins for specifying the operating mode. Non-Maskable Interrupt input Output Compare Unit n waveform output AR LCD COM pins SMC pins power supply Free Running Timer n input Y FME-MB96390 rev 3 MB96390 Series Pin Function description (2 of 2) Pin name RXn SCKn SCLn SDAn SEGn SGA SGO SINn SOTn TINn TOTn TTGn TXn Vn VCC VSS WOT X0 X0A X1 X1A Feature CAN USART I2C I2C LCD Sound Generator Sound Generator USART USART Reload Timer Reload Timer PPG CAN LCD Supply Supply RTC Clock Description CAN interface n RX input USART n serial clock input/output I2C interface n clock I/O input/output I2C interface n serial data I/O input/output IN IM Programmable Pulse Generator n trigger input CAN interface n TX output LCD voltage references Power supply Power supply Real Timer clock output Oscillator input Clock Clock EL Subclock Oscillator input (only for devices with sufﬁx "W") Oscillator output Subclock Oscillator output (only for devices with sufﬁx "W") Clock FME-MB96390 rev 3 PR AR SG sound/tone output USART n serial data input USART n serial data output Reload Timer n event input Reload Timer n output Y LCD segment n SG amplitude output 11 MB96390 Series ■ PIN CIRCUIT TYPE Pin circuit types (1 of 2) FPT-100P-M20 Pin no. 1 2 3 to 10 11,12 13 to 17 18 19 to 20 21 22 to 24 25,26 27 to 29 30 to 34 35,36 37 to 43 44,45 46 to 49 50, 51 52 to 54 55, 56 57 58,59 58,59 60 61 to 74 75 to 76 77 to 92 93 to 96 Circuit type *1 Supply F J N K Supply G Supply K Supply K M Supply M Supply M Supply C A Supply B *2) H *3 E J Supply J L 12 PR EL FME-MB96390 rev 3 IM IN AR Y MB96390 Series Pin circuit types (2 of 2) FPT-100P-M20 Pin no. 97 to 99 100 Circuit type *1 H Supply *1: Please refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types *2: Devices with sufﬁx ”W” *3: Devices without sufﬁx ”W” FME-MB96390 rev 3 PR EL IM IN AR 13 Y MB96390 Series ■ I/O CIRCUIT TYPE Type A X1 R Circuit Remarks High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Programmable feedback resistor = approx. 2 * 0.5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode 0 MRFBE 1 Xout R FCI X0 FCI or osc disable B X1A R Xout SRFBE R X0A osc disable C R EL Hysteresis inputs Hysteresis inputs IM PR Pull-up Resistor R E 14 IN AR Low-speed oscillation circuit: • Programmable feedback resistor = approx. 2 * 5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled • Mask ROM and EVA device: CMOS Hysteresis input pin • Flash device: CMOS input pin • CMOS Hysteresis input pin • Pull-up resistor value: approx. 50 kΩ Y FME-MB96390 rev 3 MB96390 Series Type F Circuit Remarks • Power supply input protection circuit G ANE AVR ANE H pull-up control Pout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown FME-MB96390 rev 3 PR EL IM Nout TTL input Hysteresis input Hysteresis input Automotive input IN AR • A/D converter ref+ (AVRH/AVRH2) power supply input pin with protection circuit • Flash devices do not have a protection circuit against VCC for pins AVRH/AVRH2 • Devices without AVRH reference switch do not have an analog switch for the AVRL pin • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. Y 15 MB96390 Series Type J pull-up control Circuit Remarks • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. • SEG or COM output Pout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input Hysteresis input Automotive input TTL input SEG, COM output pull-up control Pout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown PR 16 EL Nout TTL input Analog input SEG output IM Hysteresis input Hysteresis input Automotive input K IN AR • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function. • Programmable pull-up resistor: 50kΩ approx. • Analog input • SEG output FME-MB96390 rev 3 Y Nout MB96390 Series Type L pull-up control Circuit Remarks • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. • Analog input • Vx input • SEG output Pout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input Hysteresis input Automotive input TTL input Analog input SEG output Vx input IM pull-up control R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown M PR FME-MB96390 rev 3 EL Nout Pout Hysteresis input Hysteresis input Automotive input TTL input IN • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, IOL = 30mA, IOH = -30mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. AR 17 Y Nout MB96390 Series Type N pull-up control Circuit Remarks • CMOS level output (IOL = 3mA, IOH = -3mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. *1: N-channel transistor has slew rate control according to I2C spec, irrespective of usage Hysteresis input Pout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input Automotive input TTL input 18 PR EL FME-MB96390 rev 3 IM IN AR Y Nout *1 MB96390 Series ■ MEMORY MAP MB96V300B FF:FFFFH MB96F39x Emulation ROM DE:0000H USER ROM / Reserved*4 External Bus Reserved 10:0000H 0F:E000H Boot-ROM Reserved 0E:0000H IN IM RAMSTART0 *2 External RAM 02:0000H Internal RAM bank 1 01:0000H ROM/RAM MIRROR 00:8000H EL GPR*1 DMA Internal RAM bank 0 RAMSTART0*3 00:0C00H External Bus Peripherals 00:0380H 00:0180H 00:0100H 00:00F0H 00:0000H PR External Bus Peripheral *1: Unused GPR banks can be used as RAM area *2: For RAMSTART0 addresses, please refer to the table on the next page. *3: For EVA device, RAMSTART0 depends on the conﬁguration of the emulated device. *4: For details about USER ROM area, see the ■ USER ROM MEMORY MAP FOR FLASH DEVICES on the following pages. The DMA area is only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. FME-MB96390 rev 3 AR Boot-ROM Reserved ROM/RAM MIRROR Internal RAM bank 0 Reserved Peripherals GPR*1 Reserved Reserved Peripheral Y 19 MB96390 Series ■ RAMSTART/END AND EXTERNAL BUS END ADDRESSES Devices MB96F395 Bank 0 RAM size 5KByte RAMSTART0 00:6E40H 20 PR EL FME-MB96390 rev 3 IM IN AR Y MB96390 Series ■ USER ROM MEMORY MAP FOR FLASH DEVICES MB96F395R MB96F395Y Alternative mode CPU address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH Flash memory mode address 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H Flash size 160kByte S39 - 64K S38 - 64K Reserved E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH DE:0000H *1: Sector SA0 contains the ROM Conﬁguration Block RCBA at CPU address DF:0000H - DF:007FH FME-MB96390 rev 3 PR EL 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H IM SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 Reserved IN AR 21 Y MB96390 Series ■ SERIAL PROGRAMMING COMMUNICATION INTERFACE USART pins for Flash serial programming (MD[2:0] = 010, Serial Communication mode) MB96F39x Pin number USART Number LQFP-100 8 9 10 3 4 5 46 47 48 USART2 USART1 USART0 Normal function SOT0 SCK0 SIN1 SOT1 SCK1 SIN2 SOT2 SCK2 22 PR EL FME-MB96390 rev 3 IM Note: If a Flash programmer and its software needs to use a handshaking pin, Fujitsu suggests to the tool vendor to support at least port P00_1 on pin 88. If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins. IN AR Y SIN0 MB96390 Series ■ I/O MAP I/O map MB96F39x (1 of 22) Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 000020H 000021H 000022H 000023H Register I/O Port P00 - Port Data Register I/O Port P01 - Port Data Register I/O Port P02 - Port Data Register I/O Port P03 - Port Data Register I/O Port P04 - Port Data Register I/O Port P05 - Port Data Register I/O Port P06 - Port Data Register Reserved I/O Port P08 - Port Data Register I/O Port P09 - Port Data Register I/O Port P10 - Port Data Register I/O Port P11 - Port Data Register I/O Port P12 - Port Data Register I/O Port P13 - Port Data Register Reserved Abbreviation 8-bit access PDR00 PDR01 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ADCSL ADCSH ADCRL ADCRH ADSR ADCR ADCS R/W R/W R R R/W R/W ADECR R/W TCDT0 R/W R/W TCCSL0 TCCSH0 TCCS0 R/W R/W IN IM ADC0 - Control Status register Low ADC0 - Control Status register High ADC0 - Data Register Low ADC0 - Data Register High ADC0 - Setting Register ADC0 - Setting Register ADC0 - Extended Conﬁguration Register Reserved FRT0 - Data register of free-running timer FRT0 - Data register of free-running timer FRT0 - Control status register of free-running timer Low FRT0 - Control status register of free-running timer High FME-MB96390 rev 3 PR EL AR Y PDR03 PDR04 PDR05 PDR06 PDR08 PDR09 PDR10 PDR11 PDR12 PDR13 PDR02 23 MB96390 Series I/O map MB96F39x (2 of 22) Address 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H000051H 000052H 000053H 000054H Register FRT1 - Data register of free-running timer FRT1 - Data register of free-running timer FRT1 - Control status register of free-running timer Low FRT1 - Control status register of free-running timer High OCU0 - Output Compare Control Status OCU1 - Output Compare Control Status OCU0 - Compare Register OCU0 - Compare Register OCU1 - Compare Register OCU1 - Compare Register OCU2 - Output Compare Control Status OCU3 - Output Compare Control Status OCU2 - Compare Register OCU2 - Compare Register OCU3 - Compare Register OCU3 - Compare Register Reserved TCCSL1 TCCSH1 OCS0 OCS1 TCCS1 Abbreviation 8-bit access Abbreviation 16-bit access TCDT1 Access R/W R/W R/W R/W R/W R/W OCCP0 R/W R/W OCCP1 R/W R/W R/W R/W OCCP2 R/W R/W OCCP3 R/W R/W ICS01 ICE01 IPCPL0 IPCPH0 IPCPL1 IPCPH1 IPCP1 IPCP0 R/W R/W R R R R ICS67 ICE67 IPCPL6 IPCP6 R/W R/W R ICU0/ICU1 - Control Status Register ICU0/ICU1 - Edge register ICU0 - Capture Register Low ICU0 - Capture Register High ICU1 - Capture Register Low ICU1 - Capture Register High Reserved ICU6/ICU7 - Control Status Register ICU6/ICU7 - Edge register ICU6 - Capture Register Low 24 PR EL IM IN AR OCS2 OCS3 Y FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (3 of 22) Address 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH00005FH 000060H 000061H 000062H 000062H 000063H 000063H 000064H 000065H 000066H 000066H 000067H 000067H 000068H 000069H 00006AH 00006AH 00006BH 00006BH 00006CH 00006DH 00006EH Register ICU6 - Capture Register High ICU7 - Capture Register Low ICU7 - Capture Register High EXTINT0 - External Interrupt Enable Register EXTINT0 - External Interrupt Interrupt request Register EXTINT0 - External Interrupt Level Select Low Abbreviation 8-bit access IPCPH6 IPCPL7 IPCPH7 ENIR0 IPCP7 Abbreviation 16-bit access Access R R R R/W R/W ELVR0 R/W R/W TMCSR0 R/W R/W TMRLR0 TMR0 W R W R TMCSRL1 TMCSRH1 TMRLR1 TMR1 TMCSR1 R/W R/W W R W R TMCSRL2 TMCSRH2 TMRLR2 TMR2 TMCSR2 R/W R/W W R W R TMCSRL3 TMCSRH3 TMRLR3 TMCSR3 R/W R/W W EXTINT0 - External Interrupt Level Select High Reserved RLT0 - Timer Control Status Register Low RLT0 - Timer Control Status Register High RLT0 - Reload Register - for writing IN RLT0 - Reload Register - for reading RLT0 - Reload Register - for writing RLT0 - Reload Register - for reading RLT1 - Timer Control Status Register Low RLT1 - Reload Register - for writing RLT1 - Reload Register - for reading RLT1 - Reload Register - for writing RLT2 - Timer Control Status Register Low RLT2 - Timer Control Status Register High RLT2 - Reload Register - for writing RLT2 - Reload Register - for reading RLT2 - Reload Register - for writing RLT2 - Reload Register - for reading RLT3 - Timer Control Status Register Low RLT3 - Timer Control Status Register High RLT3 - Reload Register - for writing FME-MB96390 rev 3 PR RLT1 - Reload Register - for reading EL RLT1 - Timer Control Status Register High IM AR Y EIRR0 ELVRL0 ELVRH0 TMCSRL0 TMCSRH0 25 MB96390 Series I/O map MB96F39x (4 of 22) Address 00006EH 00006FH 00006FH 000070H 000071H 000072H 000072H 000073H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H Register RLT3 - Reload Register - for reading RLT3 - Reload Register - for writing RLT3 - Reload Register - for reading Abbreviation 8-bit access Abbreviation 16-bit access TMR3 Access R W R RLT6 - Reload Register (dedic. RLT for PPG) - for writing RLT6 - Reload Register (dedic. RLT for PPG) - for reading RLT6 - Reload Register (dedic. RLT for PPG) - for writing RLT6 - Reload Register (dedic. RLT for PPG) - for reading PPG3-PPG0 - General Control register 1 Low AR GCN1L0 GCN1H0 GCN2L0 GCN2H0 PCNL0 PCNH0 RLT6 - Timer Control Status Register High (dedic. RLT for PPG) TMCSRH6 Y RLT6 - Timer Control Status Register Low (dedic. RLT for PPG) TMCSRL6 TMCSR6 R/W R/W W R W R TMRLR6 TMR6 IN GCN10 R/W R/W PPG3-PPG0 - General Control register 1 High PPG3-PPG0 - General Control register 2 Low IM GCN20 R/W R/W PPG3-PPG0 - General Control register 2 High PPG0 - Timer register EL PPG0 - Timer register PTMR0 R R PPG0 - Period setting register PPG0 - Period setting register PPG0 - Duty cycle register PPG0 - Duty cycle register PCSR0 W W PR PDUT0 W W PPG0 - Control status register Low PPG0 - Control status register High PPG1 - Timer register PPG1 - Timer register PPG1 - Period setting register PPG1 - Period setting register PPG1 - Duty cycle register PCN0 R/W R/W PTMR1 R R PCSR1 W W PDUT1 W 26 FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (5 of 22) Address 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 000090H 000091H 000092H 000093H 000094H 000095H 000096H 000097H 000098H0000ABH 0000ACH 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H Register PPG1 - Duty cycle register PPG1 - Control status register Low PPG1 - Control status register High PPG2 - Timer register PPG2 - Timer register PPG2 - Period setting register PPG2 - Period setting register PPG2 - Duty cycle register PPG2 - Duty cycle register PPG2 - Control status register Low PPG2 - Control status register High PPG3 - Timer register PPG3 - Timer register PPG3 - Period setting register PPG3 - Period setting register PPG3 - Duty cycle register PPG3 - Duty cycle register PCNL1 PCNH1 PTMR2 PCN1 Abbreviation 8-bit access Abbreviation 16-bit access Access W R/W R/W R R PCSR2 W W PDUT2 W W PCN2 R/W R/W PTMR3 R R PCSR3 W W PDUT3 W W PCNL3 PCNH3 PCN3 R/W R/W IBSR0 IBCR0 ITBAL0 ITBAH0 ITMKL0 ITMKH0 ISBA0 ISMK0 IDAR0 ITMK0 ITBA0 R R/W R/W R/W R/W R/W R/W R/W R/W PPG3 - Control status register Low PPG3 - Control status register High Reserved I2C0 - Bus Control Register I2C0 - Ten bit Slave address Register Low I2C0 - Ten bit Slave address Register High I2C0 - Ten bit Address mask Register Low I2C0 - Ten bit Address mask Register High I2C0 - Seven bit Slave address Register I2C0 - Seven bit Address mask Register I2C0 - Data Register FME-MB96390 rev 3 PR I2C0 - Bus Status Register EL IM IN AR Y PCNL2 PCNH2 27 MB96390 Series I/O map MB96F39x (6 of 22) Address 0000B5H 0000B6H0000BFH 0000C0H 0000C1H 0000C2H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D6H 0000D7H Register I2C0 - Clock Control Register Reserved USART0 - Serial Mode Register USART0 - Serial Control Register USART0 - TX Register USART0 - RX Register USART0 - Serial Status USART0 - Control/Com. Register USART0 - Ext. Status Register USART0 - Baud Rate Generator Register Low USART0 - Baud Rate Generator Register High USART0 - Extended Serial Interrupt Register Reserved USART1 - Serial Mode Register SMR0 SCR0 TDR0 Abbreviation 8-bit access ICCR0 Abbreviation 16-bit access Access R/W R/W R/W W R R/W R/W R/W BGR0 R/W R/W R/W R/W R/W W R R/W R/W R/W BGR1 R/W R/W R/W SMR2 SCR2 TDR2 RDR2 SSR2 R/W R/W W R R/W IM USART1 - Serial Control Register USART1 - TX Register USART1 - RX Register USART1 - Serial Status EL USART1 - Control/Com. Register USART1 - Ext. Status Register USART1 - Baud Rate Generator Register High USART1 - Extended Serial Interrupt Register Reserved PR USART1 - Baud Rate Generator Register Low USART2 - Serial Mode Register USART2 - Serial Control Register USART2 - TX Register USART2 - RX Register USART2 - Serial Status 28 IN AR RDR0 SSR0 ECCR0 ESCR0 BGRL0 BGRH0 ESIR0 SMR1 SCR1 TDR1 RDR1 SSR1 ECCR1 ESCR1 BGRL1 BGRH1 ESIR1 Y FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (7 of 22) Address 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH00017FH 000180H00037FH 000380H00039FH 0003A0H 0003A1H 0003A2H 0003A3H 0003A4H 0003A5H 0003A6H0003ABH 0003ACH 0003ADH 0003AEH 0003AFH 0003B0H 0003B1H 0003B2H 0003B3H 0003B4H 0003B5H 0003B6H 0003B7H Register USART2 - Control/Com. Register USART2 - Ext. Status Register USART2 - Baud Rate Generator Register Low USART2 - Baud Rate Generator Register High USART2 - Extended Serial Interrupt Register Reserved Abbreviation 8-bit access ECCR2 ESCR2 BGRL2 BGRH2 BGR2 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W ICR R/W R/W TBR R/W R/W R/W R/W EDSU2L EDSU2H ROMM EDSU PFCS0 EDSU2 R/W R/W R/W R/W R/W R/W PFCS1 R/W R/W PFCS2 R/W R/W PFCS3 R/W R/W CPU - General Purpose registers (RAM access) Reserved Interrupt level register Interrupt index register IN Interrupt vector table base register Low Delayed Interrupt register IM Interrupt vector table base register High Non Maskable Interrupt register Reserved EDSU communication interrupt selection Low EDSU communication interrupt selection High ROM mirror control register Memory patch control/status register ch 0/1 Memory patch control/status register ch 0/1 Memory patch control/status register ch 2/3 Memory patch control/status register ch 2/3 Memory patch control/status register ch 4/5 Memory patch control/status register ch 4/5 Memory patch control/status register ch 6/7 Memory patch control/status register ch 6/7 FME-MB96390 rev 3 PR EDSU conﬁguration register EL AR ILR IDX TBRL TBRH DIRR NMI Y ESIR2 GPR_RAM 29 MB96390 Series I/O map MB96F39x (8 of 22) Address 0003B8H 0003B9H 0003BAH 0003BBH 0003BCH 0003BDH 0003BEH 0003BFH 0003C0H 0003C1H 0003C2H 0003C3H 0003C4H 0003C5H 0003C6H 0003C7H 0003C8H 0003C9H 0003CAH 0003CBH 0003CCH 0003CDH 0003CEH 0003CFH 0003D0H 0003D1H 0003D2H 0003D3H 0003D4H 0003D5H Register Memory Patch function - Patch address 0 low Memory Patch function - Patch address 0 middle Memory Patch function - Patch address 0 high Memory Patch function - Patch address 1 low Memory Patch function - Patch address 1 middle Memory Patch function - Patch address 1 high Memory Patch function - Patch address 2 low Memory Patch function - Patch address 2 middle Memory Patch function - Patch address 2 high Memory Patch function - Patch address 3 low Memory Patch function - Patch address 3 middle Memory Patch function - Patch address 3 high Memory Patch function - Patch address 4 low Abbreviation 8-bit access PFAL0 PFAM0 PFAH0 PFAL1 PFAM1 PFAH1 PFAL2 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PFD0 R/W R/W PFD1 R/W R/W PFD2 R/W R/W Memory Patch function - Patch address 4 high Memory Patch function - Patch address 5 low IM Memory Patch function - Patch address 4 middle Memory Patch function - Patch address 5 middle Memory Patch function - Patch address 5 high Memory Patch function - Patch address 6 low Memory Patch function - Patch address 6 middle Memory Patch function - Patch address 6 high Memory Patch function - Patch address 7 low Memory Patch function - Patch address 7 middle Memory Patch function - Patch address 7 high Memory Patch function - Patch data 0 Low Memory Patch function - Patch data 0 High Memory Patch function - Patch data 1 Low Memory Patch function - Patch data 1 High Memory Patch function - Patch data 2 Low Memory Patch function - Patch data 2 High EL PR 30 IN AR PFAM2 PFAH2 PFAL3 PFAM3 PFAH3 PFAL4 PFAM4 PFAH4 PFAL5 PFAM5 PFAH5 PFAL6 PFAM6 PFAH6 PFAL7 PFAM7 PFAH7 PFDL0 PFDH0 PFDL1 PFDH1 PFDL2 PFDH2 Y FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (9 of 22) Address 0003D6H 0003D7H 0003D8H 0003D9H 0003DAH 0003DBH 0003DCH 0003DDH 0003DEH 0003DFH 0003E0H0003F0H 0003F1H 0003F2H 0003F3H 0003F4H0003F7H 0003F8H 0003F9H 0003FAH 0003FBH 0003FCH 0003FDH 0003FEH0003FFH 000400H 000401H 000402H 000403H 000404H 000405H Register Memory Patch function - Patch data 3 Low Memory Patch function - Patch data 3 High Memory Patch function - Patch data 4 Low Memory Patch function - Patch data 4 High Memory Patch function - Patch data 5 Low Memory Patch function - Patch data 5 High Memory Patch function - Patch data 6 Low Abbreviation 8-bit access PFDL3 PFDH3 PFDL4 PFDH4 PFD4 Abbreviation 16-bit access PFD3 Access R/W R/W R/W R/W PFD5 R/W R/W PFD6 R/W R/W PFD7 R/W R/W MCSRA MTCRAL MTCRAH MTCRA R/W R/W R/W FMWC0 FMWC1 FMWC2 FMWC3 FMWC4 FMWC5 R/W R/W R/W R/W R/W R/W SMCR CKSR CKSSR CKMR CKFCRL CKFCRH CKFCR R/W R/W R/W R R/W R/W Memory Patch function - Patch data 6 High Memory Patch function - Patch data 7 Low Memory Patch function - Patch data 7 High Reserved Memory Control Status Register A Memory Timing Conﬁguration Register A Low Memory Timing Conﬁguration Register A High Reserved Flash Memory Write Control register 1 Flash Memory Write Control register 2 Flash Memory Write Control register 3 Flash Memory Write Control register 5 Reserved Standby Mode control register Clock select register Clock Stabilization select register Clock monitor register Clock Frequency control register Low Clock Frequency control register High FME-MB96390 rev 3 PR Flash Memory Write Control register 4 EL Flash Memory Write Control register 0 IM IN AR Y PFDL5 PFDH5 PFDL6 PFDH6 PFDL7 PFDH7 31 MB96390 Series I/O map MB96F39x (10 of 22) Address 000406H 000407H 000408H 000409H 00040AH 00040BH 00040CH 00040DH 00040EH 00040FH 000410H000414H 000415H 000416H 000417H 000418H 000419H 00041AH 00041BH 00041CH00042BH 00042CH 00042DH 00042EH00042FH 000430H 000431H 000432H 000433H 000434H Register PLL Control register Low PLL Control register High RC clock timer control register Main clock timer control register Sub clock timer control register Reset cause and clock status register with clear function Reset conﬁguration register Reset cause and clock status register Watch dog timer conﬁguration register Watch dog timer clear pattern register Reserved Clock output activation register Clock output conﬁguration register 0 Clock output conﬁguration register 1 Clock Modulator control register Reserved Abbreviation 8-bit access PLLCRL PLLCRH RCTCR MCTCR SCTCR Abbreviation 16-bit access PLLCR Access R/W R/W R/W R/W R/W R R/W R R/W W R/W R/W R/W R/W CMPRL CMPRH CMPR R/W R/W VRCR CILCR R/W R/W DDR00 DDR01 DDR02 DDR03 DDR04 R/W R/W R/W R/W R/W IM Clock Modulator Parameter register Low Clock Modulator Parameter register High Reserved Voltage Regulator Control register Clock Input and LVD Control Register Reserved I/O Port P00 - Data Direction Register I/O Port P01 - Data Direction Register I/O Port P02 - Data Direction Register I/O Port P03 - Data Direction Register I/O Port P04 - Data Direction Register 32 PR EL IN AR RCR RCCSR WDTC WDTCP COAR COCR0 COCR1 CMCR RCCSRC Y FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (11 of 22) Address 000435H 000436H 000437H 000438H 000439H 00043AH 00043BH 00043CH 00043DH 00043EH000443H 000444H 000445H 000446H 000447H 000448H 000449H 00044AH 00044BH 00044CH 00044DH 00044EH 00044FH 000450H 000451H 000452H000457H 000458H 000459H 00045AH 00045BH Register I/O Port P05 - Data Direction Register I/O Port P06 - Data Direction Register Reserved I/O Port P08 - Data Direction Register I/O Port P09 - Data Direction Register I/O Port P10 - Data Direction Register I/O Port P11 - Data Direction Register I/O Port P12 - Data Direction Register I/O Port P13 - Data Direction Register Reserved I/O Port P00 - Port Input Enable Register I/O Port P01 - Port Input Enable Register I/O Port P02 - Port Input Enable Register I/O Port P03 - Port Input Enable Register I/O Port P04 - Port Input Enable Register I/O Port P05 - Port Input Enable Register DDR08 Abbreviation 8-bit access DDR05 DDR06 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PIER08 PIER09 PIER10 PIER11 PIER12 PIER13 R/W R/W R/W R/W R/W R/W PILR00 PILR01 PILR02 PILR03 R/W R/W R/W R/W IN IM Reserved I/O Port P08 - Port Input Enable Register I/O Port P09 - Port Input Enable Register I/O Port P11 - Port Input Enable Register I/O Port P12 - Port Input Enable Register I/O Port P13 - Port Input Enable Register Reserved I/O Port P00 - Port Input Level Register I/O Port P01 - Port Input Level Register I/O Port P02 - Port Input Level Register I/O Port P03 - Port Input Level Register FME-MB96390 rev 3 PR I/O Port P10 - Port Input Enable Register EL I/O Port P06 - Port Input Enable Register AR Y DDR09 DDR10 DDR11 DDR12 DDR13 PIER00 PIER01 PIER02 PIER03 PIER04 PIER05 PIER06 33 MB96390 Series I/O map MB96F39x (12 of 22) Address 00045CH 00045DH 00045EH 00045FH 000460H 000461H 000462H 000463H 000464H 000465H 000466H00046BH 00046CH 00046DH 00046EH 00046FH 000470H 000471H 000472H 000473H 000474H 000475H 000476H 000477H 000478H 000479H 00047AH00047FH 000480H 000481H 000482H Register I/O Port P04 - Port Input Level Register I/O Port P05 - Port Input Level Register I/O Port P06 - Port Input Level Register Reserved I/O Port P08 - Port Input Level Register I/O Port P09 - Port Input Level Register I/O Port P10 - Port Input Level Register I/O Port P11 - Port Input Level Register I/O Port P12 - Port Input Level Register I/O Port P13 - Port Input Level Register Reserved PILR08 PILR09 PILR10 PILR11 PILR12 PILR13 Abbreviation 8-bit access PILR04 PILR05 PILR06 Abbreviation 16-bit access Access R/W R/W R/W - Y R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - I/O Port P00 - Extended Port Input Level Register I/O Port P01 - Extended Port Input Level Register I/O Port P02 - Extended Port Input Level Register I/O Port P03 - Extended Port Input Level Register I/O Port P04 - Extended Port Input Level Register IM I/O Port P06 - Extended Port Input Level Register Reserved EL I/O Port P05 - Extended Port Input Level Register I/O Port P08 - Extended Port Input Level Register IN AR EPILR00 EPILR01 EPILR02 EPILR03 EPILR04 EPILR05 EPILR06 EPILR08 EPILR09 EPILR10 EPILR11 EPILR12 EPILR13 PODR00 PODR01 PODR02 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Port P10 - Extended Port Input Level Register I/O Port P11 - Extended Port Input Level Register I/O Port P12 - Extended Port Input Level Register I/O Port P13 - Extended Port Input Level Register Reserved I/O Port P00 - Port Output Drive Register I/O Port P01 - Port Output Drive Register I/O Port P02 - Port Output Drive Register 34 PR I/O Port P09 - Extended Port Input Level Register FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (13 of 22) Address 000483H 000484H 000485H 000486H 000487H 000488H 000489H 00048AH 00048BH 00048CH 00048DH 00048EH00049BH 00049CH 00049DH 00049EH 00049FH0004A7H 0004A8H 0004A9H 0004AAH 0004ABH 0004ACH 0004ADH 0004AEH 0004AFH 0004B0H 0004B1H 0004B2H 0004B3H 0004B4H Register I/O Port P03 - Port Output Drive Register I/O Port P04 - Port Output Drive Register I/O Port P05 - Port Output Drive Register I/O Port P06 - Port Output Drive Register Reserved I/O Port P08 - Port Output Drive Register I/O Port P09 - Port Output Drive Register I/O Port P10 - Port Output Drive Register I/O Port P11 - Port Output Drive Register I/O Port P12 - Port Output Drive Register I/O Port P13 - Port Output Drive Register Reserved Abbreviation 8-bit access PODR03 PODR04 PODR05 PODR06 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PHDR08 PHDR09 PHDR10 R/W R/W R/W PUCR00 PUCR01 PUCR02 PUCR03 PUCR04 PUCR05 PUCR06 R/W R/W R/W R/W R/W R/W R/W PUCR08 PUCR09 PUCR10 PUCR11 PUCR12 R/W R/W R/W R/W R/W I/O Port P08 - Port High Drive Register I/O Port P09 - Port High Drive Register I/O Port P10 - Port High Drive Register Reserved I/O Port P00 - Pull-Up resistor Control Register I/O Port P01 - Pull-Up resistor Control Register I/O Port P02 - Pull-Up resistor Control Register I/O Port P04 - Pull-Up resistor Control Register I/O Port P05 - Pull-Up resistor Control Register I/O Port P06 - Pull-Up resistor Control Register Reserved I/O Port P08 - Pull-Up resistor Control Register I/O Port P09 - Pull-Up resistor Control Register I/O Port P10 - Pull-Up resistor Control Register I/O Port P11 - Pull-Up resistor Control Register I/O Port P12 - Pull-Up resistor Control Register FME-MB96390 rev 3 PR I/O Port P03 - Pull-Up resistor Control Register EL IM IN AR Y PODR08 PODR09 PODR10 PODR11 PODR12 PODR13 35 MB96390 Series I/O map MB96F39x (14 of 22) Address 0004B5H 0004B6H0004BBH 0004BCH 0004BDH 0004BEH 0004BFH 0004C0H 0004C1H 0004C2H 0004C3H 0004C4H 0004C5H 0004C6H 0004C7H 0004C8H 0004C9H 0004CAH0004CFH 0004D0H 0004D1H 0004D2H 0004D3H 0004D4H 0004D5H 0004D6H 0004D7H 0004D8H 0004D9H 0004DAH 0004DBH Register I/O Port P13 - Pull-Up resistor Control Register Reserved I/O Port P00 - External Pin State Register I/O Port P01 - External Pin State Register I/O Port P02 - External Pin State Register I/O Port P03 - External Pin State Register I/O Port P04 - External Pin State Register I/O Port P05 - External Pin State Register I/O Port P06 - External Pin State Register Reserved I/O Port P08 - External Pin State Register I/O Port P09 - External Pin State Register I/O Port P10 - External Pin State Register I/O Port P11 - External Pin State Register I/O Port P12 - External Pin State Register I/O Port P13 - External Pin State Register Reserved EPSR00 EPSR01 EPSR02 EPSR03 EPSR04 EPSR05 EPSR06 Abbreviation 8-bit access PUCR13 Abbreviation 16-bit access Access R/W R R R R R R R R R R R R R ADER0 ADER1 ADER2 ADER3 ADER4 R/W R/W R/W R/W R/W PRRR0 PRRR1 PRRR2 PRRR3 PRRR4 PRRR5 R/W R/W R/W R/W R/W R/W IM ADC analog input enable register 0 ADC analog input enable register 1 ADC analog input enable register 3 ADC analog input enable register 4 Reserved Peripheral Resource Relocation Register 0 Peripheral Resource Relocation Register 1 Peripheral Resource Relocation Register 2 Peripheral Resource Relocation Register 3 Peripheral Resource Relocation Register 4 Peripheral Resource Relocation Register 5 36 PR ADC analog input enable register 2 EL IN AR EPSR08 EPSR09 EPSR10 EPSR11 EPSR12 EPSR13 Y FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (15 of 22) Address 0004DCH 0004DDH 0004DEH 0004DFH 0004E0H 0004E1H 0004E2H 0004E3H 0004E4H 0004E5H 0004E6H 0004E7H 0004E8H 0004E9H 0004EAH 0004EBH 0004ECH 0004EDH 0004EEH 0004EFH 0004F0H 0004F1H 0004F2H0004F9H 0004FAH 0004FBH00055FH 000560H 000561H 000562H0005DFH Register Peripheral Resource Relocation Register 6 Peripheral Resource Relocation Register 7 Peripheral Resource Relocation Register 8 Peripheral Resource Relocation Register 9 RTC - Sub Second Register L RTC - Sub Second Register M RTC - Sub-Second Register H RTC - Second Register RTC - Minutes RTC - Hour RTC - Timer Control Extended Register RTC - Clock select register RTC - Timer Control Register Low Abbreviation 8-bit access PRRR6 PRRR7 PRRR8 PRRR9 Abbreviation 16-bit access Access R/W R/W R/W R/W WTBR0 R/W R/W R/W R/W R/W R/W R/W R/W WTCR R/W R/W R/W CUTDL CUTDH CUTR2L CUTR2H CUTR1L CUTR1H CUTR1 CUTR2 CUTD R/W R/W R R R R TMISR R/W ACSR0 AECSR0 R/W R/W - IN CAL - Calibration unit Control register Reserved IM RTC - Timer Control Register High CAL - Duration Timer Data Register Low CAL - Duration Timer Data Register High CAL - Calibration Timer Register 2 Low CAL - Calibration Timer Register 2 High CAL - Calibration Timer Register 1 Low CAL - Calibration Timer Register 1 High Reserved RLT - Timer input select (for Cascading) Reserved ALARM0 - Control Status Register ALARM0 - Extended Control Status Register Reserved FME-MB96390 rev 3 PR EL AR Y WTBRL0 WTBRH0 WTBR1 WTSR WTMR WTHR WTCER WTCKSR WTCRL WTCRH CUCR 37 MB96390 Series I/O map MB96F39x (16 of 22) Address 0005E0H 0005E1H 0005E2H 0005E3H 0005E4H 0005E5H 0005E6H 0005E7H 0005E8H0005E9H 0005EAH 0005EBH 0005ECH 0005EDH 0005EEH 0005EFH 0005F0H 0005F1H 0005F2H0005F3H 0005F4H 0005F5H 0005F6H 0005F7H 0005F8H 0005F9H 0005FAH 0005FBH 0005FCH000607H 000608H Register SMC0 - PWM control register SMC0 - Extended control register (Output enable) SMC0 - PWM compare register PWM 1 SMC0 - PWM compare register PWM 1 SMC0 - PWM compare register PWM 2 SMC0 - PWM compare register PWM 2 SMC0 - PWM Select register SMC0 - PWM Select register Reserved SMC1 - PWM control register Abbreviation 8-bit access PWC0 PWEC0 PWC10 Abbreviation 16-bit access Access R/W R/W R/W R/W Y AR PWS10 PWS20 PWC1 PWC20 R/W R/W R/W R/W R/W R/W SMC1 - Extended control register (Output enable) SMC1 - PWM compare register PWM 1 SMC1 - PWM compare register PWM 1 SMC1 - PWM compare register PWM 2 SMC1 - PWM compare register PWM 2 SMC1 - PWM Select register SMC1 - PWM Select register Reserved IN PWEC1 PWC11 R/W R/W IM PWC21 R/W R/W PWS11 PWS21 R/W R/W - SMC2 - PWM control register EL PWC2 PWEC2 PWC12 R/W R/W R/W R/W PWC22 R/W R/W SMC2 - PWM compare register PWM 1 SMC2 - PWM compare register PWM 1 SMC2 - PWM compare register PWM 2 SMC2 - PWM compare register PWM 2 SMC2 - PWM Select register SMC2 - PWM Select register Reserved SMC4 - PWM control register PWC4 PWS12 PWS22 PR SMC2 - Extended control register (Output enable) R/W R/W R/W 38 FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (17 of 22) Address 000609H 00060AH 00060BH 00060CH 00060DH 00060EH 00060FH 000610H00061BH 00061CH 00061DH 00061EH 00061FH 000620H 000621H 000622H 000623H 000624H 000625H 000626H 000627H 000628H 000629H 00062AH 00062BH 00062CH 00062DH 00062EH 00062FH 000630H Register SMC4 - Extended control register (Output enable) SMC4 - PWM compare register PWM 1 SMC4 - PWM compare register PWM 1 SMC4 - PWM compare register PWM 2 SMC4 - PWM compare register PWM 2 SMC4 - PWM Select register SMC4 - PWM Select register Reserved LCD - Output Enable Register 0 (Seg 7-0) PWC24 Abbreviation 8-bit access PWEC4 PWC14 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LCDVER LECR LCDCMR LCR VRAM0 VRAM1 VRAM2 VRAM3 VRAM4 VRAM5 VRAM6 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LCD - Output Enable Register 1 (Seg 15-8) LCD - Output Enable Register 2 (Seg 23-16) LCD - Output Enable Register 3 (Seg 31-24) LCD - Output Enable Register 4 (Seg 39-32) LCD - Output Enable Register 5 (Seg 47-40) LCD - Output Enable Register 6 (Seg 55-48) LCD - Output Enable Register 7 (Seg 63-56) IN IM Reserved LCD - Output Enable Register V (Vx) LCD - Extended Control Register LCD - Control Register LCD - Data register for Segment 1-0 LCD - Data register for Segment 3-2 LCD - Data register for Segment 5-4 LCD - Data register for Segment 7-6 LCD - Data register for Segment 9-8 LCD - Data register for Segment 11-10 LCD - Data register for Segment 13-12 FME-MB96390 rev 3 PR LCD - Common pin switching register EL LCD - Output Enable Register 8 (Seg 71-64) AR Y PWS14 PWS24 LCDER0 LCDER1 LCDER2 LCDER3 LCDER4 LCDER5 LCDER6 LCDER7 LCDER8 39 MB96390 Series I/O map MB96F39x (18 of 22) Address 000631H 000632H 000633H 000634H 000635H 000636H 000637H 000638H 000639H 00063AH 00063BH 00063CH 00063DH 00063EH 00063FH 000640H 000641H 000642H 000643H 000644H 000645H 000646H 000647H 000648H 000649H 00064AH 00064BH00065FH 000660H 000661H Register LCD - Data register for Segment 15-14 LCD - Data register for Segment 17-16 LCD - Data register for Segment 19-18 LCD - Data register for Segment 21-20 LCD - Data register for Segment 23-22 LCD - Data register for Segment 25-24 LCD - Data register for Segment 27-26 LCD - Data register for Segment 29-28 LCD - Data register for Segment 31-30 LCD - Data register for Segment 33-32 LCD - Data register for Segment 35-34 LCD - Data register for Segment 37-36 LCD - Data register for Segment 39-38 LCD - Data register for Segment 41-40 LCD - Data register for Segment 43-42 LCD - Data register for Segment 45-44 LCD - Data register for Segment 47-46 LCD - Data register for Segment 49-48 LCD - Data register for Segment 51-50 LCD - Data register for Segment 53-52 LCD - Data register for Segment 55-54 LCD - Data register for Segment 57-56 LCD - Data register for Segment 59-58 LCD - Data register for Segment 61-60 LCD - Data register for Segment 63-62 LCD - Data register for Segment 65-64 Reserved Peripheral Resource Relocation Register 10 Peripheral Resource Relocation Register 11 PRRR10 PRRR11 Abbreviation 8-bit access VRAM7 VRAM8 VRAM9 VRAM10 VRAM11 VRAM12 VRAM13 VRAM14 VRAM15 VRAM16 VRAM17 VRAM18 VRAM19 VRAM20 VRAM21 VRAM22 VRAM23 VRAM24 VRAM25 VRAM26 VRAM27 VRAM28 VRAM29 VRAM30 VRAM31 VRAM32 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 40 PR EL IM IN AR Y FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (19 of 22) Address 000662H 000663H 000664H0006FFH 000700H 000701H 000702H 000703H 000704H 000705H 000706H 000707H 000708H 000709H 00070AH 00070BH 00070CH 00070DH 00070EH00070FH 000710H 000711H 000712H 000713H 000714H 000715H 000716H 000717H 000718H 000719H Register Peripheral Resource Relocation Register 12 Peripheral Resource Relocation Register 13 Reserved CAN0 - Control register Low CAN0 - Control register High (reserved) CAN0 - Status register Low CAN0 - Status register High (reserved) CAN0 - Error Counter Low (Transmit) CAN0 - Error Counter High (Receive) CAN0 - Bit Timing Register Low CAN0 - Bit Timing Register High CAN0 - Interrupt Register Low CAN0 - Interrupt Register High CAN0 - Test Register Low Abbreviation 8-bit access PRRR12 PRRR13 Abbreviation 16-bit access Access R/W W - Y CTRLRL0 CTRLRH0 STATRL0 CTRLR0 R/W R AR STATR0 R/W R STATRH0 ERRCNT0 ERRCNTL0 R R ERRCNTH0 BTRL0 BTR0 R/W R/W IN BTRH0 INTRL0 INTRH0 TESTRL0 TESTRH0 BRPERL0 BRPERH0 BRPER0 TESTR0 INTR0 R R R/W R R/W R - CAN0 - Test Register High (reserved) CAN0 - BRP Extension register Low Reserved CAN0 - IF1 Command request register Low EL CAN0 - BRP Extension register High (reserved) IM IF1CREQL0 IF1CREQH0 IF1CMSKL0 IF1CMSKH0 IF1MSK1L0 IF1MSK1H0 IF1MSK2L0 IF1MSK2H0 IF1ARB1L0 IF1ARB1H0 IF1CREQ0 R/W R/W CAN0 - IF1 Command Mask register Low CAN0 - IF1 Command Mask register High (reserved) CAN0 - IF1 Mask 1 Register Low CAN0 - IF1 Mask 1 Register High CAN0 - IF1 Mask 2 Register Low CAN0 - IF1 Mask 2 Register High CAN0 - IF1 Arbitration 1 Register Low CAN0 - IF1 Arbitration 1 Register High PR CAN0 - IF1 Command request register High IF1CMSK0 R/W R IF1MSK10 R/W R/W IF1MSK20 R/W R/W IF1ARB10 R/W R/W FME-MB96390 rev 3 41 MB96390 Series I/O map MB96F39x (20 of 22) Address 00071AH 00071BH 00071CH 00071DH 00071EH 00071FH 000720H 000721H 000722H 000723H 000724H 000725H 000726H00073FH 000740H 000741H 000742H 000743H 000744H 000745H 000746H 000747H 000748H 000749H 00074AH 00074BH 00074CH 00074DH 00074EH 00074FH Register CAN0 - IF1 Arbitration 2 Register Low CAN0 - IF1 Arbitration 2 Register High CAN0 - IF1 Message Control Register Low CAN0 - IF1 Message Control Register High CAN0 - IF1 Data A1 Low CAN0 - IF1 Data A1 High CAN0 - IF1 Data A2 Low CAN0 - IF1 Data A2 High CAN0 - IF1 Data B1 Low CAN0 - IF1 Data B1 High CAN0 - IF1 Data B2 Low CAN0 - IF1 Data B2 High Reserved Abbreviation 8-bit access IF1ARB2L0 IF1ARB2H0 IF1MCTRL0 IF1MCTRH0 IF1DTA1L0 IF1MCTR0 Abbreviation 16-bit access IF1ARB20 Access R/W R/W R/W R/W IF1DTA10 R/W R/W R/W R/W IF1DTB10 R/W R/W IF1DTB20 R/W R/W IF2CREQ0 R/W R/W IF2CMSK0 R/W R IF2MSK10 R/W R/W IF2MSK20 R/W R/W IF2ARB10 R/W R/W IF2ARB20 R/W R/W IF2MCTR0 R/W R/W IF2DTA10 R/W R/W IF1DTA1H0 IF1DTA2L0 AR IF1DTA2H0 IF1DTB1L0 IF1DTB1H0 IF1DTB2L0 CAN0 - IF2 Command request register Low IM CAN0 - IF2 Command request register High CAN0 - IF2 Command Mask register Low EL CAN0 - IF2 Command Mask register High (reserved) CAN0 - IF2 Mask 1 Register Low CAN0 - IF2 Mask 1 Register High CAN0 - IF2 Mask 2 Register High CAN0 - IF2 Arbitration 1 Register Low CAN0 - IF2 Arbitration 1 Register High CAN0 - IF2 Arbitration 2 Register Low CAN0 - IF2 Arbitration 2 Register High CAN0 - IF2 Message Control Register Low CAN0 - IF2 Message Control Register High CAN0 - IF2 Data A1 Low CAN0 - IF2 Data A1 High PR CAN0 - IF2 Mask 2 Register Low 42 IN IF1DTB2H0 IF2CREQL0 IF2CREQH0 IF2CMSKL0 IF2CMSKH0 IF2MSK1L0 IF2MSK1H0 IF2MSK2L0 IF2MSK2H0 IF2ARB1L0 IF2ARB1H0 IF2ARB2L0 IF2ARB2H0 IF2MCTRL0 IF2MCTRH0 IF2DTA1L0 IF2DTA1H0 Y IF1DTA20 FME-MB96390 rev 3 MB96390 Series I/O map MB96F39x (21 of 22) Address 000750H 000751H 000752H 000753H 000754H 000755H 000756H00077FH 000780H 000781H 000782H 000783H 000784H00078FH 000790H 000791H 000792H 000793H 000794H00079FH 0007A0H 0007A1H 0007A2H 0007A3H 0007A4H0007AFH 0007B0H 0007B1H 0007B2H 0007B3H 0007B4H0007CDH Register CAN0 - IF2 Data A2 Low CAN0 - IF2 Data A2 High CAN0 - IF2 Data B1 Low CAN0 - IF2 Data B1 High CAN0 - IF2 Data B2 Low CAN0 - IF2 Data B2 High Reserved Abbreviation 8-bit access IF2DTA2L0 IF2DTA2H0 IF2DTB1L0 IF2DTB1H0 IF2DTB10 Abbreviation 16-bit access IF2DTA20 Access R/W R/W R/W R/W IF2DTB20 R/W R/W TREQR10 R R TREQR20 R R NEWDT1L0 NEWDT1H0 NEWDT2L0 NEWDT2H0 NEWDT20 NEWDT10 R R R R INTPND1L0 INTPND1H0 INTPND2L0 INTPND2H0 INTPND20 INTPND10 R R R R MSGVAL1L0 MSGVAL1H0 MSGVAL2L0 MSGVAL2H0 MSGVAL20 MSGVAL10 R R R R - IF2DTB2H0 CAN0 - Transmission Request 1 Register Low CAN0 - Transmission Request 1 Register High CAN0 - Transmission Request 2 Register Low CAN0 - Transmission Request 2 Register High Reserved CAN0 - New Data 1 Register Low IN CAN0 - New Data 1 Register High CAN0 - New Data 2 Register Low Reserved CAN0 - Interrupt Pending 1 Register Low CAN0 - Interrupt Pending 1 Register High CAN0 - Interrupt Pending 2 Register Low CAN0 - Interrupt Pending 2 Register High Reserved CAN0 - Message Valid 1 Register Low CAN0 - Message Valid 1 Register High CAN0 - Message Valid 2 Register Low CAN0 - Message Valid 2 Register High Reserved FME-MB96390 rev 3 PR EL CAN0 - New Data 2 Register High IM AR TREQR1H0 TREQR2L0 TREQR2H0 Y IF2DTB2L0 TREQR1L0 43 MB96390 Series I/O map MB96F39x (22 of 22) Address 0007CEH 0007CFH 0007D0H 0007D1H 0007D2H 0007D3H 0007D4H 0007D5H 0007D6H000BFFH Register CAN0 - Output enable register Reserved SG0 - Sound Generator Control Register Low SG0 - Sound Generator Control Register High SG0 - Sound Generator Frequency Register SG0 - Sound Generator Amplitude Register SG0 - Sound Generator Decrement Register SG0 - Sound Generator Tone Register Reserved SGCRL0 SGCRH0 SGFR0 SGCR0 Abbreviation 8-bit access COER0 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W - SGAR0 44 PR EL FME-MB96390 rev 3 IM IN Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results in reading ‘X’. Registers of resources which are described in this table, but which are not supported by the device, should also be handled as “Reserved”. AR SGDR0 SGTR0 Y MB96390 Series ■ INTERRUPT VECTOR TABLE Interrupt vector table MB96(F)39x (1 of 3) Offset in Index in Vector vector taVector name ICR to pronumber ble gram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 398H 394H 390H 388H 384H 380H 37CH EXTINT0 EXTINT1 EXTINT2 EXTINT3 EXTINT4 EXTINT5 EXTINT6 EXTINT7 CAN0 CALLV0 CALLV1 CALLV2 CALLV3 CALLV4 CALLV5 CALLV6 CALLV7 RESET INT9 EXCEPTION NMI DLY RC_TIMER MC_TIMER SC_TIMER - Description IM 14 15 17 18 19 20 21 22 23 24 25 27 28 29 30 EL PPG0 PPG1 PPG2 PPG3 PR 39CH 38CH FME-MB96390 rev 3 IN 12 13 AR Non-Maskable Interrupt Delayed Interrupt RC Timer Main Clock Timer Sub Clock Timer Reserved External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 CAN Controller 0 Reserved Programmable Pulse Generator 0 Programmable Pulse Generator 1 Programmable Pulse Generator 2 Programmable Pulse Generator 3 Reserved Reserved 45 Y MB96390 Series Interrupt vector table MB96(F)39x (2 of 3) Offset in Index in Vector vector taVector name ICR to pronumber ble gram 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H 2F0H ICU6 ICU7 OCU0 OCU1 OCU2 OCU3 FRT0 FRT1 RTC0 CAL0 SG0 IIC0 46 47 48 49 50 51 RLT0 RLT1 RLT2 RLT3 PPGRLT ICU0 ICU1 35 36 37 38 39 40 41 Reserved Reserved Reload Timer 0 Reload Timer 1 Reload Timer 3 Reload Timer 2 Description Input Capture Unit 0 Input Capture Unit 1 Reserved Reserved Reserved Reserved EL 53 54 55 56 58 59 60 62 63 64 65 66 67 PR ADC0 ALARM0 LINR0 LINT0 LINR1 LINT1 LINR2 LINT2 46 IM 52 IN Reserved I2C interface A/D Converter Reserved Input Capture Unit 6 Input Capture Unit 7 Output Compare Unit 0 Output Compare Unit 1 Output Compare Unit 2 Output Compare Unit 3 Free Running Timer 0 Free Running Timer 1 Real Timer Clock Clock Calibration Unit Sound Generator 0 Alarm Comparator 0 LIN USART 0 RX LIN USART 0 TX LIN USART 1 RX LIN USART 1 TX LIN USART 2 RX LIN USART 2 TX AR Reload Timer 6 - dedicated for PPG Y FME-MB96390 rev 3 MB96390 Series Interrupt vector table MB96(F)39x (3 of 3) Offset in Index in Vector vector taVector name ICR to pronumber ble gram 68 69 70 71 72 73 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H FLASH_A 72 Reserved Reserved Reserved Reserved Reserved Flash memory A (only Flash devices) Description FME-MB96390 rev 3 PR EL IM IN AR 47 Y MB96390 Series ■ HANDLING DEVICES Special care is required for the following when handling the device: • • • • • • • • • • • • • Latch-up prevention Unused pins handling External clock usage Unused sub clock signal Notes on PLL clock mode operation Power supply pins (VCC/VSS) Crystal oscillator circuit Turn on sequence of power supply to A/D converter and analog inputs Pin handling when not using the A/D converter Notes on energization Stabilization of power supply voltage SMC power supply pins Serial communication 1. Latch-up prevention Latch-up may increase the power supply current dramatically, causing thermal damages to the device. For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 2. Unused pins handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. External clock usage 1. Single phase external clock • When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open. PR The permitted frequency range of an external clock depends on the oscillator type and conﬁguration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: EL Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 kΩ. IM 48 IN CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC pins and VSS pins. • The AVCC power supply is applied before the VCC voltage. AR X0 X1 Y FME-MB96390 rev 3 MB96390 Series 2. Opposite phase external clock • When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. X0 X1 4. Unused sub clock signal 5. Notes on PLL clock mode operation If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between VCC and VSS as close as possible to VCC and VSS pins. 7. Crystal oscillator and ceramic resonator circuit It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 8. Turn on sequence of power supply to A/D converter and analog inputs It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. Pin handling when not using the A/D converter It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS. 10. Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage proﬁle while turning the power supply on should be slower than 50µs from 0.2 V to 2.7 V. FME-MB96390 rev 3 PR EL Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. IM VCC and VSS must be connected to the device from the power supply with lowest possible impedance. IN 6. Power supply pins (VCC/VSS) AR If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin must be left open. Y 49 MB96390 Series 11. Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple ﬂuctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the transient ﬂuctuation rate becomes 0.1V/µs or less in instantaneous ﬂuctuation for power supply switching. 12. SMC power supply pins All DVSS pins must be set to the same level as the VSS pins. The DVCC power supply level can be set independently of the VCC power supply level. However note that the SMC I/O pin state is undeﬁned if DVCC is powered on and VCC is below 3V. To avoid this, we recommend to always power VCC before DVCC. There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. 50 PR EL FME-MB96390 rev 3 IM IN AR 13. Serial communication Y MB96390 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage AD Converter voltage references SMC Power supply LCD power supply voltage Input voltage Output voltage Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current Symbol VCC AVCC AVRH, AVRL DVCC VI VO ICLAMP Σ|ICLAMP| IOL1 Rating Min Max VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 -4.0 +4.0 40 15 40 5 30 100 330 50 250 -15 -40 -5 -30 -100 -330 -50 -250 Unit V V V V V V V VCC = AVCC *1 AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH > AVRL, AVRL ≥ AVSS See *7 V0 to V3 must not exceed VCC VI ≤ (D)VCC + 0.3V *2 Remarks V0 to V3 VSS - 0.3 VSS + 6.0 AR mA mA mA IN IOLSMC “L” level average output current IOLAV1 IM IOLAVSMC ΣIOL1 ΣIOLSMC ΣIOLAV1 IOH1 ΣIOLAVSMC IOHSMC IOHAV1 IOHAVSMC ΣIOH1 ΣIOHSMC ΣIOHAV1 ΣIOHASMC “L” level maximum overall output current “L” level average overall output current ”H” level maximum output current EL PR ”H” level average output current ”H” level maximum overall output current ”H” level average overall output current FME-MB96390 rev 3 Y VO ≤ (D)VCC + 0.3V *2 Applicable to general purpose I/O pins *3 Applicable to general purpose I/O pins *3 mA Normal outputs with driving strength set to 5mA mA High current outputs with driving strength set to 30mA mA Normal outputs with driving strength set to 5mA mA High current outputs with driving strength set to 30mA mA Normal outputs mA High current outputs mA Normal outputs mA High current outputs Normal outputs with driving strength set to 5mA mA High current outputs with driving strength set to 30mA mA Normal outputs with driving strength set to 5mA mA High current outputs with driving strength set to 30mA mA Normal outputs mA High current outputs mA Normal outputs mA High current outputs 51 MB96390 Series Rating Min Permitted Power dissipation (MB96F395) *4 PD 0 Operating ambient temperature TA -40 -40 Storage temperature TSTG -55 320*5 575*5 +70 +105 +125 +150 mW mW Max 255*5 510*5 830*5 Parameter Symbol Unit mW TA=105oC mW TA=85oC mW TA=60oC Remarks TA=125oC, no Flash program/ erase *6 TA=105oC, no Flash program/ erase *6 MB96V300B *6 *2: VI and VO should not exceed (D)VCC + 0.3 V. VI should also not exceed the speciﬁed ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of high current ports depend on DVCC. Input/output voltages of standard ports depend on VCC. *3: • Applicable to all general purpose I/O pins (Pnn_m) except I/O pins with SEG or COM functionality. • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not ﬁxed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufﬁcient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). • No +B signal must be applied to any LCD I/O pin (including unused SEG/COM pins). 52 PR EL IM IN *1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC neither when the power is switched on. AR o o Y C C FME-MB96390 rev 3 MB96390 Series • Sample recommended circuits: Protective Diode VCC Limiting resistance +B input (0V to 16V) P-ch N-ch R *5: Worst case value for a package mounted on single layer PCB at speciﬁed TA without air ﬂow. *6: Please contact Fujitsu for reliability limitations when using under these conditions. *7: If DVCC is powered before VCC, then SMC I/O pins state is undeﬁned. To avoid this, we recommend to always power VCC before DVCC. It is not necessary to set VCC and DVCC to the same value. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. FME-MB96390 rev 3 PR EL IM IN *4: The maximum permitted power dissipation depends on the ambient temperature, the air ﬂow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports) PINT = VCC * (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator. IA is the analog current consumption into AVCC. AR Y 53 MB96390 Series 2. Recommended Operating Conditions Value Min 3.0 3.5 Typ 4.7 Max 5.5 15 Parameter Power supply voltage Smoothing capacitor at C pin Symbol VCC, DVCC CS Unit V µF Remarks 54 PR EL FME-MB96390 rev 3 IM IN AR WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Y Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics MB96390 Series 3. DC characteristics (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Input H voltage Symbol Pin Condition CMOS Hysteresis 0.8/0.2 input selected CMOS Hysteresis Port inputs 0.7/0.3 input selected Pnn_m AUTOMOTIVE Hysteresis input selected TTL input selected VIHX0F VIHX0S VIHR VIHM Input L voltage X0 X0,X1, X0A,X1A RSTX Value Min 0.8 VCC 0.7 VCC 0.74 VCC 0.8 VCC 2.0 Typ - Max (D)VCC + 0.3 (D)VCC + 0.3 (D)VCC + 0.3 (D)VCC + 0.3 (D)VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.2 (D)VCC 0.3 (D)VCC 0.5 (D)VCC 0.46 (D)VCC 0.8 Unit Remarks V V V V V V V V V V CMOS Hysteresis input (D)VCC ≥ 4.5V (D)VCC < 4.5V VIH External clock in “oscillation mode” - IN - External clock in “Fast Clock Input mode” IM MD2-MD0 EL Pnn_m CMOS Hysteresis 0.8/0.2 input selected VIL CMOS Hysteresis 0.7/0.3 input sePort inputs lected AUTOMOTIVE Hysteresis input selected TTL input selected External clock in “Fast Clock Input mode” External clock in “oscillation mode” AR 0.8 VCC 2.5 0.8 VCC VCC 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 - Y 0.4 V V (D)VCC ≥ 4.5V (D)VCC < 4.5V V V V V V CMOS Hysteresis input PR VILX0F X0 VILX0S VILR VILM FME-MB96390 rev 3 0.2 VCC X0,X1, X0A,X1A RSTX 0.2 VCC VSS + 0.3 MD2-MD0 55 MB96390 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Output H voltage VOH2 Normal and High Current outputs Symbol Pin Condition 4.5V ≤ (D)VCC ≤ 5.5V IOH = -2mA 3.0V ≤ (D)VCC < 4.5V IOH = -1.6mA 4.5V ≤ (D)VCC ≤ 5.5V IOH = -5mA 3.0V ≤ (D)VCC < 4.5V IOH = -3mA 4.5V ≤ DVCC ≤ 5.5V (D)VCC - 0.5 (D)VCC - 0.5 - Value Min Typ Max Unit Remarks V Driving strength set to 2mA (PODR:OD=1, PHDR:HD=0) VOH5 AR 0.4 0.4 0.5 0.4 -1 +1 Normal and High Current outputs Y V V V V V V V Driving strength set to 5mA (PODR:OD=0, PHDR:HD=0) VOH30 IOH = -20mA 4.5V ≤ VCC ≤ 5.5V VOH3 3mA outputs IOH = -3mA IN VCC 0.5 High current outputs DVCC 0.5 3.0V ≤ DVCC < 4.5V IOH = -30mA Driving strength set to 30mA (PHDR:HD=1) Output L voltage VOL2 Normal and High Current outputs 4.5V ≤ (D)VCC ≤ 5.5V IOL = +2mA 3.0V ≤ (D)VCC < 4.5V IOL = +1.6mA 4.5V ≤ (D)VCC ≤ 5.5V IOL = +5mA 3.0V ≤ (D)VCC < 4.5V IOL = +3mA IM IOH = -2mA IOL = +30mA IOL = +20mA IOL = +3mA 3.0V ≤ VCC < 4.5V I/O circuit type “N” VOL5 PR Normal and High Current outputs EL Driving strength set to 2mA (PODR:OD=1, PHDR:HD=0) Driving strength set to 5mA (PODR:OD=0, PHDR:HD=0) 4.5V ≤ DVCC ≤ 5.5V 3.0V ≤ DVCC < 4.5V 3.0V ≤ VCC ≤ 5.5V VOL30 High current outputs Driving strength set to 30mA (PHDR:HD=1) VOL3 3mA outputs Pnn_m I/O circuit type “N” VSS < VI < VCC Input leak current IIL AVSS, AVRL < VI < AVCC, AVRH µA Single port pin 56 FME-MB96390 rev 3 MB96390 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Total LCD leak current Internal LCD divide resistance Pull-up resistance Symbol Σ|IILCD| RLCD RUP Pin all SEG/ COM pins Between V3 and VSS Pnn_m, RSTX Condition Value Min 25 40 25 Typ 0.5 40 100 50 Max 10 65 160 100 Unit Remarks VCC = 5.0V VCC = 5.0V VCC = 3.3V ± 10% VCC = 5.0V ± 10% Maximum leakage µA current of all LCD pins kΩ kΩ kΩ FME-MB96390 rev 3 PR EL IM IN AR Note: Input/output voltages of high current ports depend on DVCC, of other ports on VCC. Y 57 MB96390 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) PLL Run mode with CLKS1/2 = CLKB = CLKP1 = 16MHz, CLKP2 = 8MHz 1 Flash/ROM wait state (CLKRC and CLKSC stopped) PLL Run mode with CLKS1/2 = CLKB = CLKP1 = 32MHz, CLKP2 = 16MHz 2 Flash/ROM wait states (CLKRC and CLKSC stopped) ICCPLL PLL Run mode with CLKS1/2 = 48MHz, CLKB = CLKP1/2 = 24MHz +25˚C 23 +25˚C Value Typ 15 Max 20 Unit Remarks mA AR 24.5 31.5 27 39 28.5 41.5 38 51 39.5 53.5 4.2 5.2 4.7 7 2.7 3.7 3.2 5.4 +125˚C IN +125˚C +25˚C +125˚C +25˚C +125˚C +25˚C +125˚C +25˚C 0 Flash/ROM wait states Power supply current in Run modes* (CLKRC and CLKSC stopped) PLL Run mode with CLKS1/2 = 80MHz, CLKB = CLKP1 = 40MHz, CLKP2 = 20MHz EL 1 Flash wait state IM (CLKRC and CLKSC stopped. Core voltage at 1.9V) Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz PR ICCMAIN 1 Flash/ROM wait state (CLKPLL, CLKSC and CLKRC stopped) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 2MHz ICCRCH 1 Flash/ROM wait state (CLKMC, CLKPLL and CLKSC stopped) 58 Y 29 mA mA mA mA mA FME-MB96390 rev 3 +125˚C 16 22.5 MB96390 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 0 1 Flash/ROM wait state (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) ICCRCL RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 1 1 Flash/ROM wait state +25˚C Value Typ 0.4 Max 0.6 Unit Remarks mA Power supply current in Run modes* AR +25˚C 0.15 0.55 +25˚C 0.1 0.5 Y 0.25 mA 1.75 0.2 mA 1.7 59 +125˚C 0.9 2.1 ICCSUB 1 Flash/ROM wait state FME-MB96390 rev 3 PR EL (CLKMC, CLKPLL and +125˚C CLKRC stopped, no Flash programming/erasing allowed) IM Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz IN (CLKMC, CLKPLL and +125˚C CLKSC stopped. Voltage regulator in low power mode, no Flash programming/erasing allowed) MB96390 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) PLL Sleep mode with CLKS1/2 = CLKP1 = 16MHz, CLKP2 = 8MHz (CLKRC and CLKSC stopped) PLL Sleep mode with CLKS1/2 = CLKP1 = 32MHz, CLKP2 = 16MHz (CLKRC and CLKSC stopped) PLL Sleep mode with CLKS1/2 = 48MHz, CLKP1/2 = 24MHz Power supply current in Sleep modes* (CLKRC and CLKSC stopped) +25˚C Value Typ 4 Max 6 mA +125˚C 4.6 8 Unit Remarks +25˚C 7 AR 7.6 11.5 7 9 7.6 11 11 13 11.6 15 1.3 1.8 0.8 1.3 1.8 3.3 1.4 2.9 +125˚C ICCSPLL +25˚C (CLKRC and CLKSC stopped. Core voltage at 1.9V) Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz (CLKPLL, CLKSC and CLKRC stopped) EL IM PLL Sleep mode with CLKS1/2 = 80MHz, CLKP1 = 40MHz, CLKP2 = 20MHz IN +25˚C +125˚C +25˚C +125˚C +25˚C +125˚C +125˚C ICCSMAIN 60 PR ICCSRCH RC Sleep mode with CLKS1/2 = CLKP1/2 = 2MHz (CLKMC, CLKPLL and CLKSC stopped) Y 9.5 mA mA mA mA mA FME-MB96390 rev 3 MB96390 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 1 +25˚C Value Typ 0.3 Max 0.5 Unit Remarks mA +125˚C 0.7 2 ICCSRCL Power supply current in Sleep modes* AR +125˚C 0.44 +25˚C 0.04 0.43 1.5 +125˚C +25˚C +125˚C 2 +25˚C 0.35 +125˚C 0.75 +25˚C 0.1 +125˚C 0.5 +25˚C Y 0.05 0.15 mA 1.6 0.12 mA 1.55 2 mA 3.6 0.55 mA 2 0.18 1.6 61 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz ICCSSUB (CLKMC, CLKPLL and CLKRC stopped) ICCTPLL PLL Timer mode with CLKMC = 4MHz, CLKPLL = 48MHz (CLKRC and CLKSC stopped. Core voltage at 1.9V) Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 Power supply current in Timer modes* ICCTMAIN FME-MB96390 rev 3 PR EL (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in high power mode) Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 1 (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in low power mode) IM IN MB96390 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 1 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) Power supply current in Timer modes* RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 0 +25˚C Value Typ 0.35 Max 0.5 mA +125˚C 0.75 2 Unit Remarks ICCTRCH +25˚C 0.07 AR 0.46 1.6 0.3 0.45 0.65 1.9 0.03 0.1 0.41 1.55 0.035 0.42 0.02 0.4 0.015 0.3 90 100 3 0.1 1.55 0.08 1.5 0.06 1.2 140 150 4.5 +125˚C +25˚C IN +125˚C +25˚C +125˚C +25˚C +125˚C +25˚C +125˚C +25˚C +125˚C +25˚C +125˚C - RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 1 IM ICCTRCL (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) ICCTSUB Sub Timer mode with CLKSC = 32kHz EL (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) (CLKMC, CLKPLL and CLKRC stopped) VRCR:LPMB[2:0] = 110B (Core voltage at 1.8V) PR Power supply current in Stop Mode ICCH VRCR:LPMB[2:0] = 000B (Core voltage at 1.2V) Power supply current for active Low Voltage detector Power supply current for active Clock modulator Y 0.15 mA mA mA mA mA mA µA This current must be added to all Power supply currents above Must be added to all current above mA FME-MB96390 rev 3 ICCLVD Low voltage detector enabled (RCR:LVDE = 1) Clock modulator enabled (CMCR:PDX = 1) ICCCLOMO 62 MB96390 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Flash Write/Erase current Input capacitance Symbol ICCFLASH CIN Condition (at TA) Current for one Flash module Value Typ 15 15 Max 40 30 Unit mA pF Remarks Must be added to all current above High current outputs Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS, High current outputs FME-MB96390 rev 3 PR EL IM IN AR * The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. Y Input capacitance CIN - - 5 15 pF 63 MB96390 Series 4. AC Characteristics Source Clock timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Value Min 3 Clock frequency fC X0, X1 0 3.5 0 Clock frequency fFCI X0 3.5 32 X0A, X1A Clock frequency fCL X0A 0 0 50 Clock frequency fCR 1 RC clock stabilization time PLL Clock frequency PLL Phase Jitter Input clock pulse width Input clock pulse width tRCSTAB fCLKVCO TPSKEW PWH, PWL 64 32.768 Typ Max 16 16 16 56 56 Unit Remarks MHz When using a crystal oscillator, PLL off MHz MHz MHz 100 100 50 IN kHz 200 4 kHz MHz 200 ±5 MHz ns ns µs IM 2 - 100 64 RC clock cycles EL 8 5 PWHL, PWLL X0A,X1A 64 PR X0,X1 AR MHz kHz When using a crystal oscillator or opposite phase external clock, PLL on When using a single phase external clock in “Fast Clock Input mode” , PLL off When using a single phase external clock in “Fast Clock Input mode” , PLL on When using an opposite phase external clock When using a single phase external clock kHz When using an oscillation circuit When using slow frequency of RC oscillator When using fast frequency of RC oscillator Applied after any reset and when activating the RC oscillator. Permitted VCO output frequency of PLL (CLKVCO) For CLKMC (PLL input clock) ≥ 4MHz, jitter coming from external oscillator, crystal or resonator is not covered Duty ratio is about 30% to 70% Y When using an opposite phase external clock, PLL off FME-MB96390 rev 3 MB96390 Series tCYL VIH X0 PWH PWL VIL tCYLL X0A PWHL Y VIH VIL FME-MB96390 rev 3 PR EL IM IN AR PWLL 65 MB96390 Series Internal Clock timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Core Voltage Settings Parameter Internal System clock frequency (CLKS1 and CLKS2) Internal CPU clock frequency (CLKB), internal peripheral clock frequency (CLKP1) Internal peripheral clock frequency (CLKP2) Symbol Min fCLKS1, fCLKS2 0 0 fCLKB, fCLKP1 0 0 fCLKP2 0 1.8V Max 92 72 52 36 28 Min 0 0 0 0 0 1.9V Max 96 80 56 40 32 MHz MHz MHz MHz MHz Others than below MB96F395 Others than below MB96F395 Unit Remarks 66 PR EL FME-MB96390 rev 3 IM IN AR Y MB96390 Series External Reset timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Reset input time Symbol tRSTL Pin RSTX Value Min 500 Typ Max Unit ns Remarks tRSTL RSTX 0.2 VCC FME-MB96390 rev 3 PR EL IM IN AR 0.2 VCC Y 67 MB96390 Series Power On Reset timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Power on rise time Power off time Symbol tR tOFF Pin Vcc Vcc Value Min 0.05 1 Typ Max 30 Unit ms ms Remarks tR VCC 0.2 V 2.7V 0.2 V If the power supply is changed too rapidly, a power-on reset may occur. We recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the ﬁgure below. VCC 3V IM PR EL 68 IN AR 0.2 V tOFF Rising edge of 50 mV/ms maximum is allowed Y FME-MB96390 rev 3 MB96390 Series External Input timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin INTn(_R) NMI(_R) Pnn_m Input pulse width tINH tINL TINn(_R) TTGn(_R) ADTG(_R) FRCKn(_R) INn(_R) ⎯ Condition Value Min 200 Max ⎯ Unit ns Used Pin input function External Interrupt NMI General Purpose IO Reload Timer PPG Trigger input AD Converter Trigger Free Running Timer external clock Input Capture 2*tCLKP1 + 200 (tCLKP1=1/ fCLKP1) Note : Relocated Resource Inputs have same characteristics External Pin input VIH IN VIH tINH AR VIL Y ⎯ tINL ns VIL FME-MB96390 rev 3 PR EL IM 69 MB96390 Series Slew Rate High Current Outputs (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Condition Output driving strength set to “30mA” Value Min Max Unit Remarks Note : Relocated Resource Inputs have same characteristics • Slew rate output timing VH VL VH tR30 70 PR EL FME-MB96390 rev 3 IM IN AR VL tF30 Y VH = VOL30 + 0.9 × (VOH30 - VOL30) VL = VOL30 + 0.1 × (VOH30 - VOL30) Output rise/fall time tR30 tF30 I/O circuit type M 15 ⎯ ns MB96390 Series USART timing WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. (TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF) VCC = AVCC= 4.5V VCC = AVCC= 3.0V to 5.5V to 4.5V Unit Min Max Min Max Parameter Serial clock cycle time SCK ↓ → SOT delay time SOT → SCK ↑ delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time SCK fall time SCK rise time Symbol tSCYCI tSLOVI tOVSHI tIVSHI tSHIXI tSLSHE tSHSLE tSLOVE tIVSHE tSHIXE tFE Pin SCKn SCKn, SOTn SCKn, SOTn SCKn, SINn SCKn, SINn SCKn SCKn SCKn, SOTn SCKn, SINn SCKn, SINn SCKn SCKn Condition Y ⎯ -20 +20 ⎯ ⎯ ⎯ ⎯ ⎯ 0 ⎯ ⎯ ⎯ 20 20 ⎯ ⎯ 4 tCLKP1 4 tCLKP1 -30 N*tCLKP1 30 *1 tCLKP1 + 55 0 tCLKP1 + 10 tCLKP1 + 10 ⎯ tCLKP1/2 + 10 tCLKP1 + 10 ⎯ ⎯ ⎯ +30 ⎯ ⎯ ⎯ ⎯ ⎯ 2 tCLKP1 + 55 ⎯ ⎯ 20 20 ns ns ns ns ns ns ns ns ns ns ns ns Internal Shift Clock Mode IN External Shift Clock Mode 2 3 4 ... ... IM 4*tCLKP1 tRE *1: Parameter N depends on tSCYCI and can be calculated as follows: • if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2 • if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1 Examples: tSCYCI N 5*tCLKP1, 6*tCLKP1 7*tCLKP1, 8*tCLKP1 FME-MB96390 rev 3 PR Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL” • tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns EL AR N*tCLKP1 - 20 *1 tCLKP1 + 45 tCLKP1 + 10 tCLKP1 + 10 tCLKP1/2 + 10 tCLKP1 + 10 2 tCLKP1 + 45 71 MB96390 Series tSCYCI SCK for ESCR:SCES = 0 0.8*VCC 0.2*VCC 0.2*VCC 0.2*VCC tSLOVI tOVSHI 0.8*VCC 0.2*VCC tIVSHI VIH VIL SOT SIN VIH VIL Internal Shift Clock Mode IM tSLSHE VIL VIH tRE 0.8*VCC 0.2*VCC tIVSHE VIH VIL SCK for ESCR:SCES = 0 IN tSHSLE VIH VIH VIL VIL tSHIXE VIH VIL VIH VIL SCK for ESCR:SCES = 1 SOT SIN 72 PR EL VIH VIL tFE tSLOVE External Shift Clock Mode AR tSHIXI Y FME-MB96390 rev 3 SCK for ESCR:SCES = 1 0.8*VCC 0.8*VCC MB96390 Series I2C Timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter SCL clock frequency Hold time (repeated) START condition SDA↓→SCL↓ “L” width of the SCL clock “H” width of the SCL clock Set-up time for a repeated START condition SCL↑→SDA↓ Data hold time SCL↓→SDA↓↑ Data set-up time SDA↓↑→SCL↑ Set-up time for STOP condition SCL↑→SDA↑ Bus free time between a STOP and START condition Output fall time from 0.7*Vcc to 0.3*Vcc with a bus capacitance from 10 pF to 400 pF Capacitive load for each bus line Pulse width of spikes which will be suppressed by input noise filter Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS tof Standard-mode Min 0 4.0 4.7 4.0 4.7 0 Max 100 ⎯ Fast-mode*1 Min 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 20 + 0.1*Cb *2 ⎯ 0 Max 400 ⎯ ⎯ ⎯ ⎯ 0.9 ⎯ ⎯ ⎯ 250 400 1*tCLKP1*3 Unit kHz µs µs µs µs µs ns µs µs ns pF ns IN 4.7 ⎯ n/a tSUSTA IM Cb tSP 20 + 0.1*Cb *2 *2 : Cb = capacitance of one bus line in pF. *3 : tCLKP1 is the cycle time of the periperal clock CLKP1. SDA PR EL *1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz. AR ⎯ 3.45 ⎯ ⎯ ⎯ 250 400 n/a 250 4.0 tHDSTA Y ⎯ ⎯ tLOW SCL tSUDAT tBUS tHDSTA tHDDAT tHIGH tSUSTO • VOH = 0.7 * VCC • VOL = 0.3 * VCC • CMOS Hysteresis 0.7/0.3 input selected FME-MB96390 rev 3 73 MB96390 Series 5. Analog Digital Converter (TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero transition voltage Full scale transition voltage Compare time Sampling time Symbol VOT VFST Pin ANn ANn Value Min Typ Max 10 ±3 ± 2.5 ± 1.9 Unit bit LSB LSB Remarks AVRL - AVRL+ AVRL + 1.5 LSB 0.5 LSB 2.5 LSB AVRH - AVRH - AVRH + 3.5 LSB 1.5 LSB 0.5 LSB 1.0 2.0 0.5 1.2 -1 16,500 - IN 2.5 0.7 5 5 1 5 4 IAIN ANn IM -1.2 AVRL 0.75 AVcc AVSS - Analog input leakage current (during conversion) EL AVRH AVRL AVcc AVcc AVRH/ AVRL AVRH/ AVRL ANn Analog input voltage range Reference voltage range VAIN AVRH AVRL IA ANn Power supply current PR IAH IR IRH - Reference voltage current Offset between input channels Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller. 74 AR V V µs µs µs µs +1 +1.2 AVRH AVcc 0.25 AVCC V V V µA µA LSB Y LSB 4.5V ≤ ΑVCC ≤ 5.5V 3.0V ≤ ΑVCC < 4.5V 4.5V ≤ ΑVCC ≤ 5.5V 3.0V ≤ ΑVCC < 4.5V TA ≤ 105 ˚C, µA AVSS, AVRL < VI < AVCC, AVRH 105 ˚C < TA ≤ 125 ˚C, µA AVSS, AVRL < VI < AVCC, AVRH mA A/D Converter active A/D Converter not operated mA A/D Converter active A/D Converter not operated FME-MB96390 rev 3 MB96390 Series Definition of A/D Converter Terms Resolution: Analog variation that is recognized by an A/D converter. Total error : Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” “00 0000 0001”) and full-scale transition line (“11 1111 1110” “11 1111 1111”) and actual conversion characteristics. Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Zero reading voltage: Input voltage which results in the minimum conversion value. Full scale reading voltage: Input voltage which results in the maximum conversion value. Total error 3FF 3FE 3FD Digital output Actual conversion characteristics 004 003 002 001 AVRL 0.5 LSB EL IM Analog input Actual conversion characteristics Ideal characteristics Total error of digital output “N” = N: A/D converter digital output value VOT (Ideal value) = AVRL + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N − 1) to N. FME-MB96390 rev 3 PR VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVRL 1 LSB = (Ideal value) [V] 1024 IN {1 LSB × (N − 1) + 0.5 LSB} AR 1.5 LSB VNT (Actually-measured value) AVRH Y [LSB] 75 MB96390 Series Nonlinearity error 3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Differential nonlinearity error Ideal characteristics Actual conversion characteristics Digital output N 004 003 002 N−1 Ideal characteristics 001 VOT (actual measurement value) AVRL Analog input AVRH N−2 AVRL AR [V] Y Analog input V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVRH Nonlinearity error of digital output N = Differential nonlinearity error of digital output N = 1 LSB = IN V (N+1) T − VNT 1 LSB VFST − VOT 1022 VNT − {1 LSB × (N − 1) + VOT} 1 LSB −1 LSB [LSB] [LSB] 76 PR EL N : A/D converter digital output value VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” IM FME-MB96390 rev 3 MB96390 Series Accuracy and setting of the A/D Converter sampling time If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufﬁcient, adversely affecting the A/D conversion precision. To satisfy the A/D conversion precision, a sufﬁcient sampling time must be selected. The required sampling time depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVcc voltage level. The following replacement model can be used for the calculation: MCU Rext Source Cext CIN RADC Sampling switch The sampling time should be set to minimum “7τ“. The following approximation formula for the replacement model above can be used: Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC) × CADC) • Do not select a sampling time below the absolute minimum permitted value (0.5µs for 4.5V ≤ AVcc ≤ 5.5V; 1.2 µs for 3.0V ≤ AVcc < 4.5V). • If the sampling time cannot be sufﬁcient, connect a capacitor of about 0.1 µF to the analog input pin. In this case the internal sampling capacitance CADC will be charged out of this external capacitance. • The accuracy gets worse as |AVRH - AVRL| becomes smaller. FME-MB96390 rev 3 PR • A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor. EL IM IN Rext: external driving impedance Cext: capacitance of PCB at A/D converter input CIN: capacitance of MCU input pin: 15pF (max) RADC: resistance within MCU: 2.6kΩ (max) for 4.5V ≤ AVcc ≤ 5.5V 12kΩ (max) for 3.0V ≤ AVcc < 4.5V CADC: sampling capacitance within MCU: 10pF (max) AR 77 Y CADC Analog input Comparator MB96390 Series 6. Alarm Comparator (TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Value Min AVCC Typ 25 Max 45 Unit µA Remarks Alarm comparator enabled in fast mode (one channel) Alarm comparator enabled in slow mode (one channel) Alarm comparator disabled IA5ALMF Power supply current IA5ALMS IA5ALMH -1 -3 0 7 - AR 5 +1 +3 AVCC 1.1 1.3 2.4 2.6 0.1 1 1 100 1.55 2.85 300 1 10 10 500 ALARM pin input current ALARM pin input voltage range External low threshold high->low transition External low threshold low->high transition External high threshold high->low transition External high threshold low->high transition Internal low threshold high->low transition Internal low threshold low->high transition Internal high threshold high->low transition Internal high threshold low->high transition Switching hysteresis Comparison time Power-up stabilization time after enabling alarm comparator Slow/Fast mode transition time IALIN VALIN VEVTL(H->L) VEVTL(L->H) VEVTH(H->L) VEVTH(L->H) VIVTL(H->L) VIVTL(L->H) VIVTH(H->L) VIVTH(L->H) VHYS IN 0.36 * AVCC 0.36 * AVCC -0.25 -0.1 - 0.36 * AVCC 0.36 * AVCC +0.1 +0.25 Y 13 µA µA V V V V V V V V V mV µs µs ms µs µA TA = 25 ˚C µA TA = 125 ˚C EL 2.2 50 - ALARM0, ALARM1 IM 0.9 0.78 * AVCC 0.78 * AVCC -0.25 -0.1 INTREF = 0 0.78 * AVCC 0.78 * AVCC +0.1 +0.25 INTREF = 1 PR tCOMPF CMD = 1 (fast) CMD = 0 (slow) Threshold levels speciﬁed above are not guaranteed within this time tCOMPS tPD tCMD 78 FME-MB96390 rev 3 MB96390 Series Comparator Output H L VxVTx(H->L) VxVTx(L->H) FME-MB96390 rev 3 PR EL IM IN AR VHYS Y VALIN 79 MB96390 Series 7. Low Voltage Detector characteristics (TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V) Parameter Stabilization time Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 Level 9 Level 10 Level 11 Level 12 Level 13 Level 14 Level 15 Symbol TLVDSTAB VDL0 VDL1 VDL2 VDL3 VDL4 VDL5 VDL6 VDL7 VDL8 VDL9 VDL10 VDL11 VDL12 VDL13 VDL14 VDL15 Value Min 2.7 2.9 3.1 3.5 3.6 3.7 3.8 3.9 4.0 4.1 Max 75 2.9 3.1 3.3 3.75 3.85 3.95 4.05 4.15 4.25 4.35 Unit µs V V V V V V V V V V Remarks After power-up or change of detection level CILCR:LVL[3:0]=”0000” CILCR:LVL[3:0]=”0001” CILCR:LVL[3:0]=”0010” CILCR:LVL[3:0]=”0011” CILCR:LVL[3:0]=”0100” CILCR:LVL[3:0]=”0101” CILCR:LVL[3:0]=”0110” CILCR:LVL[3:0]=”0111” CILCR:LVL[3:0]=”1000” not used not used not used not used not used not used CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register. V For correct detection, the slope of the voltage level must satisfy dV ≤ 0.004 ----- . EL IM dt µs Faster variations are regarded as noise and may not be detected. 80 PR The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of “Level 0” (VDL0_MIN). The electrical characteristics however are only valid in the speciﬁed range (usually down to 3.0V). IN CILCR:LVL[3:0]=”1001” AR FME-MB96390 rev 3 Y MB96390 Series Low Voltage Detector Operation In the following ﬁgure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. Voltage [V] VCC VDLx, Min AR Y dV dt Time [s] Power Reset Extension Time Low Voltage Reset Assertion VDLx, Max Normal Operation FME-MB96390 rev 3 PR EL IM IN 81 MB96390 Series 8. FLASH memory program/erase characteristics (TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Sector erase time Chip erase time Word (16-bit width) programming time Program/Erase cycle Flash data retention time Value Min 10 000 20 Typ 0.9 n*0.9 23 Max 3.6 n*3.6 370 Unit s s us Remarks Without erasure pre-programming time Without erasure pre-programming time (n is the number of Flash sector of the device) - AR cycle year Y Without overhead time for submitting write command *1 *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) 82 PR EL FME-MB96390 rev 3 IM IN MB96390 Series FME-MB96390 rev 3 PR EL IM IN AR 83 Y MB96390 Series ■ EXAMPLE CHARACTERISTICS 1. Temperature dependency of power supply currents The following diagrams show the current consumption of samples with typical wafer process parameters in different operation modes. Common condition for all operation modes: • VCC = AVCC = 5.0V • Main clock = 4MHz external clock • Sub clock = 32kHz external clock Operation mode details: Mode name PLL Run 40 Details Main Run RC Run 2M RC Run mode current ICCRCH with the following settings: • RC oscillator set to 2MHz (CKFCR:RCFS = 1) • fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 2MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • 1 Flash/ROM wait states (MTCRA=0239H) • PLL, Main oscillator and Sub oscillator stopped 84 PR Main Run mode current ICCMAIN with the following settings: • fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 4MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • 1 Flash/ROM wait states (MTCRA=0239H) • PLL, RC oscillator and Sub oscillator stopped EL IM PLL Run 24 PLL Run mode current ICCPLL with the following settings: • fCLKS1 = fCLKS2 = 48MHz • fCLKB = fCLKP1 = fCLKP2 = 24MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • 0 Flash/ROM wait states (MTCRA=2208H) • RC oscillator and Sub oscillator stopped IN PLL Run mode current ICCPLL with the following settings: • fCLKS1 = fCLKS2 = 80MHz • fCLKB = fCLKP1 = 40MHz • fCLKP2 = 20MHz • Regulator in High Power Mode • Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) • 1 Flash/ROM wait states (MTCRA=6B09H) • RC oscillator and Sub oscillator stopped AR FME-MB96390 rev 3 Y MB96390 Series Mode name RC Run 100k Details RC Run mode current ICCRCL with the following settings: • RC oscillator set to 100kHz (CKFCR:RCFS = 0) • fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 100kHz • Regulator in Low Power Mode A (SMCR:LPMS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • 1 Flash/ROM wait states (MTCRA=0239H) • PLL, Main oscillator and Sub oscillator stopped Sub Run mode current ICCSUB with the following settings: • fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 32kHz • Regulator in Low Power Mode A (by hardware) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • 1 Flash/ROM wait states (MTCRA=0239H) • PLL, RC oscillator and Main oscillator stopped PLL Sleep 40 PLL Sleep 24 Main Sleep Main Sleep mode current ICCSMAIN with the following settings: • fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 4MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • PLL, RC oscillator and Sub oscillator stopped RC Sleep 100k RC Sleep mode current ICCSRCL with the following settings: • RC oscillator set to 100kHz (CKFCR:RCFS = 0) • fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 100kHz • Regulator in Low Power Mode A (SMCR:LPMSS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, Main oscillator and Sub oscillator stopped FME-MB96390 rev 3 PR RC Sleep 2M RC Sleep mode current ICCSRCH with the following settings: • RC oscillator set to 2MHz (CKFCR:RCFS = 1) • fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 2MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • PLL, Main oscillator and Sub oscillator stopped EL IM PLL Sleep mode current ICCSPLL with the following settings: • fCLKS1 = fCLKS2 = 48MHz • fCLKP1 = fCLKP2 = 24MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • RC oscillator and Sub oscillator stopped IN PLL Sleep mode current ICCSPLL with the following settings: • fCLKS1 = fCLKS2 = 80MHz • fCLKP1 = 40MHz • fCLKP2 = 20MHz • Regulator in High Power Mode • Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) • RC oscillator and Sub oscillator stopped AR 85 Y Sub Run MB96390 Series Mode name Sub Sleep Details Sub Sleep mode current ICCSSUB with the following settings: • fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 32kHz • Regulator in Low Power Mode A (by hardware) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, RC oscillator and Main oscillator stopped PLL Timer mode current ICCTPLL with the following settings: • fCLKS1 = fCLKS2 = 48MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • RC oscillator and Sub oscillator stopped PLL Timer 48 Main Timer Main Timer mode current ICCTMAIN with the following settings: • fCLKS1 = fCLKS2 = 4MHz • Regulator in Low Power Mode A (SMCR:LPMSS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, RC oscillator and Sub oscillator stopped RC Timer mode current ICCTRCH with the following settings: • RC oscillator set to 2MHz (CKFCR:RCFS = 1) • fCLKS1 = fCLKS2 = 2MHz • Regulator in Low Power Mode A (SMCR:LPMSS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, Main oscillator and Sub oscillator stopped RC Timer mode current ICCTRCL with the following settings: • RC oscillator set to 100kHz (CKFCR:RCFS = 0) • fCLKS1 = fCLKS2 = 100kHz • Regulator in Low Power Mode A (SMCR:LPMSS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, Main oscillator and Sub oscillator stopped Sub Timer mode current ICCTSUB with the following settings: • fCLKS1 = fCLKS2 = 32kHz • Regulator in Low Power Mode A (by hardware) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, RC oscillator and Main oscillator stopped Stop mode current ICCH with the following settings: • Regulator in Low Power Mode B (by hardware) • Core voltage at 1.8V (VRCR:LPMB[2:0] = 110B) Stop mode current ICCH with the following settings: • Regulator in Low Power Mode B (by hardware) • Core voltage at 1.2V (VRCR:LPMB[2:0] = 000B) RC Timer 2M RC Timer 100k Sub Timer Stop 1.8V Stop 1.2V 86 PR EL IM IN AR FME-MB96390 rev 3 Y MB96390 Series MB96F395 PLL Run and Sleep mode currents 40 PLL Run 40 30 PLL Run 24 20 Icc[mA] 10 PLL Sleep 40 PLL Sleep 24 0 -60 -40 -20 0 IN 20 40 AR 60 80 100 120 Ta [˚C] 5 Main Run 4 3 2 PLL Timer 48 Main Sleep 1 RC Sleep 2M 0 -60 -40 -20 0 20 40 60 80 100 120 PR Ta [˚C] RC Run 2M FME-MB96390 rev 3 EL Icc[mA] IM MB96F395 operation modes with medium currents Y 87 MB96390 Series MB96F395 Low power mode currents 1 RC Run 100k 0.1 Main Timer Sub Timer 0.01 RC Timer 100k Stop 1.8V Stop 1.2V 0.001 -60 -40 -20 0 20 IN 40 60 AR 80 100 120 RC Sleep 100k Sub Sleep Ta [˚C] 88 PR EL FME-MB96390 rev 3 IM Y Sub RC Timer 2M Icc[mA] MB96390 Series 2. Frequency dependency of power supply currents in PLL Run mode The following diagrams show the current consumption of samples with typical wafer process parameters in PLL Run mode at different frequencies and Flash timing settings. Measurement conditions: • VCC = AVCC = 5.0V • Ta = 25˚C • fCLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram • fCLKS2 = fCLKS1 • fCLKP1 = fCLKB • fCLKP2 = fCLKB/2 • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram • Main clock = 4MHz external clock • Flash memory timing settings: • MTCRA=2128H/2208H (0 Flash wait states, fCLKS1 = 2*fCLKB) • MTCRA=0239H/2129H (1 Flash wait state, fCLKS1 = fCLKB) • MTCRA=4C09H/6B09H (1 Flash wait state, fCLKS1 = 2*fCLKB) • MTCRA=233AH (2 Flash wait states, fCLKS1 = fCLKB) • Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit): • 0 Flash wait states: 0.5 • 1 Flash wait states: 0.33 • 2 Flash wait states: 0.25 MB96F395 PLL Run mode currents 40 IM EL 0 Flash wait states (CLKS1=2*CLKB, 1.8V) IN 20 CLKB/CLKP1 (MHz) AR 24 28 35 30 25 ICCPLL (mA) Y 2 Flash wait states (CLKS1=CLKB, 1.8V) 1 Flash wait state (CLKS1=2*CLKB, 1.9V) 1 Flash wait state (CLKS1=2*CLKB, 1.8V) 2 Flash wait states (CLKS1=CLKB, 1.9V) 15 10 PR 0 4 8 12 20 1 Flash wait state (CLKS1=CLKB, 1.8V) : Specified in "DC characteristics" 5 0 16 32 36 40 FME-MB96390 rev 3 89 MB96390 Series ■ PACKAGE DIMENSION MB96F39x LQFP 100P 100-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 mm × 14.0 mm Gullwing Plastic mold AR Code (Reference) 51 Y Details of "A" part 1.50 –0.10 .059 –.004 (Mounting height) +0.20 +.008 1.70 mm Max 0.65 g (FPT-100P-M20) P-LFQFP100-14×14-0.50 100-pin plastic LQFP (FPT-100P-M20) 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 76 EL INDEX IM 50 PR IN 26 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 0.08(.003) 100 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0˚~8˚ "A" (0.50(.020)) 0.60±0.15 (.024±.006) 1 25 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M 0.145±0.055 (.0057±.0022) ©2005-2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-2-2 C 2005 FUJITSU LIMITED F100031S-c-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 90 FME-MB96390 rev 3 MB96390 Series ■ ORDERING INFORMATION Persistent Low Voltage Reset Yes No Yes No 100 pin Plastic LQFP (FPT-100P-M20) Part number MB96F395YSB PMC-GSE2 *1 MB96F395RSB PMC-GSE2 *1 *1 Flash/ROM Subclock Package No Flash A (160KB) Yes Emulated by ext. RAM Yes MB96F395YWB PMC-GSE2 MB96V300BRB-ES (for evaluation) MB96F395RWB PMC-GSE2 *1 *1: These devices are under development and speciﬁcation is preliminary. These products under development may change its speciﬁcation without notice. This datasheet is also valid for the following outdated devices: MB96F395YSA, MB96F395RSA, MB96F395YWA, MB96F395RWA. FME-MB96390 rev 3 PR EL IM IN AR Y No 416 pin Plastic BGA (BGA-416P-M02) 91 MB96390 Series ■ REVISION HISTORY Revision Prelim 1 Prelim 2 Date 2008-04-18 2009-01-09 Initial Draft Modiﬁcation 92 PR EL FME-MB96390 rev 3 IM • Format adjusted to ofﬁcial Fujitsu Microelectronics datasheet standard (mainly style changes and ofﬁcial notes and disclaimer added) • speciﬁed AD converter channel offset to 4LSB • package code of MB96V300 corrected in ordering information • Internal LCD divider resistance value corrected: Typ 35kOhm -> 40kOhm, Max 50kOhm -> 65kOhm • Added voltage condition to pull-up resistance and LCD divide resistance spec • Ordering information: column “Flash/ROM” added, column “Remarks” removed • Ofﬁcial package dimension drawing with additional notes added • Empty pages removed • Alarm comparator: Power supply current max values increased, comparison time reduced, mode transition time and power-up stabilization time newly added • Handling devices: Notes added about Serial communication and about using ceramic resonators. • Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators. For resonators, maximum frequency depends on Q-factor • AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz • VOL3 spec improved: spec valid for 3mA load for full Vcc range • All ICC (Run/Sleep/Timer/Stop mode) currents adjusted to evaluation results • IO map cleaned up (removed not available resources) • Absolute maximum ratings: Pd spec corrected • C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted IN AR Y MB96390 Series Revision Prelim 3 Date 2010-06-25 Modiﬁcation • AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA above 105deg • Note added that PLL phase jitter spec does not include jitter coming from Main clock • Alarm comparator: Maximum power-up stabilization time increased to 10ms • Note added in DC characteristics how to select driving strength of ports • I2C AC spec updated: tof, Cb and tSP spec added, wrong footnotes and Condition removed • I/O Circuit type: Note added for type “N” (slew rate control according to I2C spec) • Updated Power Supply current spec in Run/Sleep/Timer/Stop modes (new spec items in PLL Run/Sleep mode, small adjustment of most other values) • Prepared Example characteristics • Package dimension: Added the following sentence under the ﬁgure: “Please conﬁrm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/” • AD converter: Impact of input pin capacitance and external capacitance added to formula for calculation of the sampling time • Added speciﬁcation of RC clock stabilization time • Feature description I2C: ‘8-bit addressing’ corrected to ‘7-bit addressing’ • Feature description PPG: ‘Reload timer overﬂow as clock input’ corrected to ‘Reload timer underﬂow as clock input’ • Company name updated on the cover page: Fujitsu Microelectronics Limited -> Fujitsu Semiconductor Limited • Ordering information: MB96F395**A -> MB96F395**B FME-MB96390 rev 3 PR EL IM IN AR Y 93 MB96390 Series FME-MB96390 rev 3 PR EL IM IN AR Y MB96390 Series FME-MB96390 rev 3 PR EL IM IN AR 95 Y MB96390 Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Paciﬁc FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department 96 PR EL IM IN AR Y FME-MB96390 rev 3

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