ACS8530T

ACS8530 SETS Synchronous Equipment Timing Source for Stratum 2/3E Systems ADVANCED COMMUNICATIONS Description FINAL Features The ACS8530 is a highly integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) function in a SONET or SDH Network Element. The device generates SONET or SDH Equipment Clocks (SEC) and Frame Synchronization clocks. The ACS8530 is fully compliant with the required international specifications and standards. The device supports Free-run, Locked and Holdover modes. It also supports all three types of reference clock source: recovered line clock, PDH network, and node synchronization. The ACS8530 generates independent SEC and BITS clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. Two ACS8530 devices can be used together in a Master/ Slave configuration mode allowing system protection against a single ACS8530 failure. A microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring. The ACS8530 supports IEEE 1149.1[5] JTAG boundary scan. Block Diagram DATASHEET ‹ Suitable for Stratum 2, 3E, 3, 4E and 4 and SONET Minimum Clock (SMC) or SONET/SDH Equipment Clock (SEC) applications (to Telcordia 1244-CORE[19] Stratum 3E, and GR-253[17], and ITU-T G.812[10] Type III and G.813[11] specifications) ‹ Accepts 14 individual input reference clocks, all with robust input clock source quality monitoring ‹ Simultaneously generates nine output clocks, plus two sync pulse outputs ‹ Absolute Holdover accuracy better than 3 x 10-10 (manual), 7.5 x 10-14 (instantaneous); Holdover stability defined by choice of external XO ‹ Programmable PLL bandwidth, for wander and jitter tracking/attenuation, 0.5 mHz to 70 Hz in 18 steps ‹ Automatic hit-less source switchover on loss of input ‹ Phase Transient Protection and Phase Build-out on locked to reference and on reference switching ‹ Microprocessor interface - Intel, Motorola, Serial, Multiplexed, or boot from EPROM ‹ Output phase adjustment in 6 ps steps up to ±200 ns ‹ IEEE 1149.1 JTAG[5] Boundary Scan ‹ Single 3.3 V operation. 5 V tolerant ‹ Available in LQFP 100 package ‹ Lead (Pb) - free version available (ACS8530T), RoHS and WEEE compliant. Figure 1 Block Diagram of the ACS8530 SETS T4 DPLL/Freq. Synthesis 2 x AMI 10 x TTL 2 x PECL/LVDS Programmable; 64/8 kHz (AMI) 2 kHz 4 kHz N x 8 kHz 1.544/2.048 MHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz TCK TDI TMS TRST TDO T4 Selector Optional Divider, 1/n n = 1 to 214 PFD Digital Loop Filter T4 APLL DTO Frequency Dividers Input Port Monitors and Selection Control T0 DPLL/Freq. Synthesis T0 APLL (output) 14 x SEC T0 Selector IEEE 1149.1 JTAG Chip Clock Generator Optional Divider, 1/n n = 1 to 214 PFD Priority Register Set Table Digital Loop Filter Microprocessor Port OCXO Frequency Dividers DTO Output Ports TO1 to TO7 Outputs T01-TO7: E1/DS1 (2.048/ 1.544 MHz) and frequency multiples: 1.5 x, 2 x, 3 x 4 x, 6 x, 12 x 16 x and 24 x E3/DS3 2 kHz 8 kHz and OC-N* rates TO8 & TO9 T08: AMI TO9: E1/DS1 TO10 & TO11 TO10: 8 kHz (FrSync) TO11: 2 kHz (MFrSync) TO APLL (feedback) OC-N* rates = OC-1 51.84 MHz OC-3 155.52 MHz and derivatives: 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz 311.04 MHz F8530D_001BLOCKDIA_09 Revision 3.02/November 2005 © Semtech Corp. Page 1 www.semtech.com Table of Contents ADVANCED COMMUNICATIONS Table of Contents FINAL Section ACS8530 SETS DATASHEET Page Description ................................................................................................................................................................................................. 1 Block Diagram............................................................................................................................................................................................ 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 4 Pin Description........................................................................................................................................................................................... 5 Introduction................................................................................................................................................................................................ 8 General Description................................................................................................................................................................................... 8 Overview .............................................................................................................................................................................................8 Input Reference Clock Ports .......................................................................................................................................................... 10 Locking Frequency Modes .................................................................................................................................................... 10 PECL/LVDS/AMI Input Port Selection .................................................................................................................................. 11 Clock Quality Monitoring................................................................................................................................................................. 12 Activity Monitoring ................................................................................................................................................................. 12 Frequency Monitoring ........................................................................................................................................................... 14 Selection of Input Reference Clock Source................................................................................................................................... 14 Forced Control Selection....................................................................................................................................................... 15 Automatic Control Selection ................................................................................................................................................. 15 Ultra Fast Switching .............................................................................................................................................................. 15 Fast External Switching Mode-SCRSW Pin .......................................................................................................................... 16 Output Clock Phase Continuity on Source Switchover ....................................................................................................... 16 Modes of Operation ........................................................................................................................................................................ 16 Free-run Mode ....................................................................................................................................................................... 16 Pre-locked Mode ................................................................................................................................................................... 16 Locked Mode ......................................................................................................................................................................... 17 Lost-phase Mode................................................................................................................................................................... 17 Holdover Mode ...................................................................................................................................................................... 17 Pre-locked2 Mode ................................................................................................................................................................. 19 DPLL Architecture and Configuration ............................................................................................................................................ 20 TO DPLL Main Features ........................................................................................................................................................ 20 T4 DPLL Main Features ........................................................................................................................................................ 20 TO DPLL Automatic Bandwidth Controls.............................................................................................................................. 21 Phase Detectors .................................................................................................................................................................... 21 Phase Lock/Loss Detection.................................................................................................................................................. 21 Damping Factor Programmability......................................................................................................................................... 22 Local Oscillator Clock ............................................................................................................................................................ 22 Output Wander ...................................................................................................................................................................... 23 Jitter and Wander Transfer ................................................................................................................................................... 25 Phase Build-out ..................................................................................................................................................................... 25 Input to Output Phase Adjustment....................................................................................................................................... 26 Input Wander and Jitter Tolerance....................................................................................................................................... 26 Using the DPLLs for Accurate Frequency and Phase Reporting ........................................................................................ 28 Configuration for Redundancy Protection ..................................................................................................................................... 29 Alignment of Priority Tables in Master and Slave ACS8530 .............................................................................................. 30 T4 Generation in Master and Slave ACS8530 .................................................................................................................... 30 Alignment of the Output Clock Phases in Master and Slave ACS8530............................................................................. 30 MFrSync and FrSync Alignment-SYNC2K............................................................................................................................. 31 Output Clock Ports .......................................................................................................................................................................... 32 PECL/LVDS/AMI Output Port Selection ............................................................................................................................... 32 Output Frequency Selection and Configuration .................................................................................................................. 32 Revision 3.02/November 2005 © Semtech Corp. Page 2 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Section Page Microprocessor Interface ....................................................................................................................................................................... 43 Introduction to Microprocessor Modes ......................................................................................................................................... 43 Motorola Mode ...................................................................................................................................................................... 44 Intel Mode.............................................................................................................................................................................. 46 Multiplexed Mode.................................................................................................................................................................. 48 Serial Mode............................................................................................................................................................................ 50 EPROM Mode......................................................................................................................................................................... 52 Power-On Reset............................................................................................................................................................................... 52 Register Map........................................................................................................................................................................................... 53 Register Organization ..................................................................................................................................................................... 53 Multi-word Registers ............................................................................................................................................................. 53 Register Access ..................................................................................................................................................................... 53 Interrupt Enable and Clear ................................................................................................................................................... 53 Defaults.................................................................................................................................................................................. 53 Register Descriptions ............................................................................................................................................................................. 57 Electrical Specifications ....................................................................................................................................................................... 134 JTAG ............................................................................................................................................................................................... 134 Over-voltage Protection ................................................................................................................................................................ 134 ESD Protection .............................................................................................................................................................................. 134 Latchup Protection........................................................................................................................................................................ 134 Maximum Ratings ......................................................................................................................................................................... 135 Operating Conditions .................................................................................................................................................................... 135 DC Characteristics ........................................................................................................................................................................ 135 DC Characteristics: AMI Input/Output Port ....................................................................................................................... 139 Jitter Performance ........................................................................................................................................................................ 141 Input/Output Timing ..................................................................................................................................................................... 144 Package Information ............................................................................................................................................................................ 145 Thermal Conditions....................................................................................................................................................................... 146 Application Information ........................................................................................................................................................................ 147 References ............................................................................................................................................................................................ 148 Abbreviations ........................................................................................................................................................................................ 148 Trademark Acknowledgements ........................................................................................................................................................... 149 Revision Status/History ....................................................................................................................................................................... 150 Notes ..................................................................................................................................................................................................... 151 Ordering Information ............................................................................................................................................................................ 152 Disclaimers.................................................................................................................................................................................... 152 Contacts......................................................................................................................................................................................... 152 Revision 3.02/November 2005 © Semtech Corp. Page 3 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS Pin Diagram FINAL DATASHEET 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SONSDHB MSTSLVB IC7 IC6 IC5 TO9 TO5 TO4 AGND3 VA3+ TO3 TO2 TO1 DGNDb VDDb VDDc DGNDc AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Figure 2 ACS8530 Pin Diagram Synchronous Equipment Timing Source for Stratum 2/3E Systems AGND TRST IC1 IC2 AGND1 VA1+ TMS INTREQ TCK REFCLK DGND1 VD1+ VD3+ DGND3 DGND2 VD2+ IC3 SRCSW VA2+ AGND2 TDO IC4 TDI I1 I2 ACS8530 SONET/SDH SETS 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RDY PORB ALE RDB WRB CSB A0 A1 A2 A3 A4 A5 A6 DGNDd VDDd UPSEL0 UPSEL1 UPSEL2 I14 I13 I12 I11 I10 I9 I8 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VAMI+ TO8NEG TO8POS GND_AMI FrSync MFrSync GND_DIFFa VDD_DIFFa TO6POS TO6NEG TO7POS TO7NEG GND_DIFFb VDD_DIFFb I5POS I5NEG I6POS I6NEG VDD5 SYNC2K I3 I4 I7 DGNDa VDDa 1 2 3 4 5 6 7 8 9 10 11 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Revision 3.02/November 2005 © Semtech Corp. Page 4 F8530D_002PINDIAG_04 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS Pin Description FINAL DATASHEET Table 1 Power Pins Pin Number Symbol I/O Type Description 12, 13, 16 VD1+, VD3+, VD2+ P - Supply Voltage: Digital supply to gates in analog section, +3.3 Volts ±10%. 26 VAMI+ P - Supply Voltage: Digital supply to AMI output, +3.3 Volts ±10%. 33, 39 VDD_DIFFa, VDD_DIFFb P - Supply Voltage: Digital supply for differential ports, +3.3 Volts ±10%. 44 VDD5 P - Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts (±10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts. 50, 61, 85, 86 VDDa, VDDd, VDDc, VDDb P - Supply Voltage: Digital supply to logic, +3.3 Volts ±10%. 6 VA1+ P - Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts ±10%. 19, 91 VA2+, VA3+ P - Supply Voltage: Analog supply to output PLLs, +3.3 Volts ±10%. 11, 14, 15, DGND1, DGND3, DGND2, P - Supply Ground: Digital ground for components in PLLs. 49, 62, 84, 87 DGNDa, DGNDd, DGNDc, DGNDb P - Supply Ground: Digital ground for logic. 29 GND_AMI P - Supply Ground: Digital ground for AMI output. 32, 38 GND_DIFFa, GND_DIFFb P - Supply Ground: Digital ground for differential ports. 1, 5, 20, 92 AGND, AGND1, AGND2, AGND3 P - Supply Ground: Analog grounds. Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor. Table 2 Internally Connected Pin Number 3, 4, 17, 22, 96, 97, 98 Symbol I/O Type IC1, IC2, IC3, IC4, IC5, IC6, IC7 - - Revision 3.02/November 2005 © Semtech Corp. Description Internally Connected: Leave to Float. Page 5 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 3 Other Pins Pin Number Symbol I/O Type Description 2 TRST I TTLD JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for Boundary Scan stand-by mode, still allowing correct device operation. If not used connect to GND or leave floating. 7 TMS I TTLU JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. If not used connect to VDD or leave floating. 8 INTREQ O TTL/CMOS 9 TCK I TTLD JTAG Clock: Boundary Scan clock input. If not used connect to GND or leave floating. 10 REFCLK I TTL Reference Clock: 12.800 MHz (refer to section headed Local Oscillator Clock). 18 SRCSW I TTLD Source Switching: Force Fast Source Switching. See “Fast External Switching Mode-SCRSW Pin” on page 16. 21 TDO O TTL/CMOS JTAG Output: Serial test data output. Updated on falling edge of TCK. If not used leave floating. 23 TDI I TTLU JTAG Input: Serial test data Input. Sampled on rising edge of TCK. If not used connect to VDD or leave floating. 24 I1 I AMI Input Reference 1: Composite clock 64 kHz + 8 kHz. 25 I2 I AMI Input Reference 2: Composite clock 64 kHz + 8 kHz. 27 TO8NEG O AMI Output Reference 8: Composite clock, 64 kHz + 8 kHz negative pulse. 28 TO8POS O AMI Output Reference 8: Composite clock, 64 kHz + 8 kHz positive pulse. 30 FrSync O TTL/CMOS Output Reference 10: 8 kHz Frame Sync output. 31 MFrSync O TTL/CMOS Output Reference 11: 2 kHz Multi-Frame Sync output. 34, 35 TO6POS, TO6NEG O LVDS/PECL Output Reference 6: Programmable, default 38.88 MHz, default type LVDS. 36, 37 TO7POS, TO7NEG O PECL/LVDS Output Reference 7: Programmable, default 19.44 MHz, default type PECL. 40, 41 I5POS, I5NEG I LVDS/PECL Input Reference 5: Programmable, default 19.44 MHz, default type LVDS. 42, 43 I6POS, I6NEG I PECL/LVDS Input Reference 6: Programmable, default 19.44 MHz, default type PECL. 45 SYNC2K I TTLD External Sync input: 2 kHz, 4 kHz or 8 kHz for frame alignment. 46 I3 I TTLD Input Reference 3: Programmable, default 8 kHz. 47 I4 I TTLD Input Reference 4: Programmable, default 8 kHz. 48 I7 I TTLD Input Reference 7: Programmable, default 19.44 MHz. 51 I8 I TTLD Input Reference 8: Programmable, default 19.44 MHz. 52 I9 I TTLD Input Reference 9: Programmable, default 19.44 MHz. 53 I10 I TTLD Input Reference 10: Programmable, default 19.44 MHz. Revision 3.02/November 2005 © Semtech Corp. Interrupt Request: Active High/Low software Interrupt output. Page 6 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 3 Other Pins (cont...) Pin Number Symbol I/O Type Description 54 I11 I TTLD Input Reference 11: Programmable, default (Master mode) 1.544/2.048 MHz, default (Slave mode) 6.48 MHz. 55 I12 I TTLD Input Reference 12: Programmable, default 1.544/2.048 MHz. 56 I13 I TTLD Input Reference 13: Programmable, default 1.544/2.048 MHz. 57 I14 I TTLD Input Reference 14: Programmable, default 1.544/2.048 MHz. 58 - 60 UPSEL(2:0) I TTLD Microprocessor select: Configures the interface for a particular microprocessor type at reset. 63 - 69 A(6:0) I TTLD Microprocessor Interface Address: Address bus for the microprocessor interface registers. A(0) is SDI in Serial mode - output in EPROM mode only. A(1) is CLKE in serial mode. 70 CSB I TTLU Chip Select (Active Low): This pin is asserted Low by the microprocessor to enable the microprocessor interface - output in EPROM mode only. 71 WRB I TTLU Write (Active Low): This pin is asserted Low by the microprocessor to initiate a write cycle. In Motorola mode, WRB = 1 for Read. 72 RDB I TTLU Read (Active Low): This pin is asserted Low by the microprocessor to initiate a read cycle. 73 ALE I TTLD Address Latch Enable: This pin becomes the address latch enable from the microprocessor. When this pin transitions from High to Low, the address bus inputs are latched into the internal registers. ALE = SCLK in Serial mode. 74 PORB I TTLU Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. 75 RDY O TTL/CMOS 76 - 83 AD(7:0) IO TTLD 88 TO1 O TTL/CMOS Output Reference 1: Programmable, default 6.48 MHz. 89 TO2 O TTL/CMOS Output Reference 2: Programmable, default 38.88 MHz. 90 TO3 O TTL/CMOS Output Reference 3: Programmable, default 19.44 MHz. 93 TO4 O TTL/CMOS Output Reference 4: Programmable, default 38.88 MHz. 94 TO5 O TTL/CMOS Output Reference 5: Programmable, default 77.76 MHz. 95 TO9 O TTL/CMOS Output Reference 9: 1.544/2.048 MHz, as per ITU G.783 BITS requirements. 99 MSTSLVB I TTLU Master/Slave Select: sets the state of the Master/Slave selection register, Reg. 34, Bit 1. 100 SONSDHB I TTLD SONET or SDH Frequency Select: sets the initial power up state (or state after a PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. When set Low, SDH rates are selected (2.048 MHz etc.) and when set High, SONET rates are selected (1.544 MHz etc.) The register states can be changed after power-up by software. Revision 3.02/November 2005 © Semtech Corp. Ready/Data Acknowledge: This pin is asserted High to indicate the device has completed a read or write operation. Address/Data: Multiplexed data/address bus depending on the microprocessor mode selection. AD(0) is SDO in Serial mode. Page 7 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS Introduction FINAL The ACS8530 is a highly integrated, single-chip solution for the SETS function in a SONET/SDH Network Element, for the generation of SEC and Frame/MultiFrame Synchronization pulses. Digital Phase Locked Loop (DPLL) and direct digital synthesis methods are used in the device so that the overall PLL characteristics are very stable and consistent compared to traditional analog PLLs. In Free-run mode, the ACS8530 generates a stable, lownoise clock signal at a frequency to the same accuracy as the external oscillator, or it can be made more accurate via software calibration to within ±0.02 ppm. In Locked mode, the ACS8530 selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. In Holdover mode, the ACS8530 generates a stable, low-noise clock signal, adjusted to match the last known good frequency of the last selected reference source. A high level of phase and frequency accuracy is made possible by an internal resolution of up to 54 bits and internal Holdover accuracy of up to 7.5 x 10-14 (instantaneous). In all modes, the frequency accuracy, jitter and drift performance of the clock meet the requirements of ITU G.736[7], G.742[8], G783[9], G.812[10], G.813[11], G.823[13], G.824[14] and Telcordia GR-253-CORE[17] and GR-1244-CORE[19]. The ACS8530 supports all three types of reference clock source: recovered line clock, PDH network synchronization timing and node synchronization. The ACS8530 generates independent T0 and T4 clocks, an 8 kHz Frame Synchronization clock and a 2 kHz MultiFrame Synchronization clock. One key architectural advantage that the ACS8530 has over traditional solutions is in the use of DPLL technology for precise and repeatable performance over temperature or voltage variations and between parts. The overall PLL bandwidth, loop damping, pull-in range and frequency accuracy are all determined by digital parameters that provide a consistent level of performance. An Analog PLL (APLL) takes the signal from the DPLL output and provides a lower jitter output. The APLL bandwidth is set four orders of magnitude higher than the DPLL bandwidth. This ensures that the overall system performance still maintains the advantage of consistent behavior provided by the digital approach. The DPLLs are clocked by the external Oscillator module (OCXO) so that the Free-run or Holdover frequency stability is only determined by the stability of the external Revision 3.02/November 2005 © Semtech Corp. DATASHEET oscillator module. This second key advantage confines all temperature critical components to one well defined and pre-calibrated module, whose performance can be chosen to match the application; for example an OCXO for Stratum 3E applications. All performance parameters of the DPLLs are programmable without the need to understand detailed PLL equations. Bandwidth, damping factor and lock range can all be set directly, for example. The PLL bandwidth can be set over a wide range, 0.5 mHz to 70 Hz in 18 steps, to cover all SONET/SDH clock synchronization applications. The ACS8530 supports protection. Two ACS8530 devices can be configured to provide protection against a single ACS8530 failure. The protection maintains alignment of the two ACS8530 devices (Master and Slave) and ensures that both ACS8530 devices maintain the same priority table, choose the same reference input and generate the T0 clock, the 8 kHz Frame Synchronization clock and the 2 kHz Multi-Frame Synchronization clock with the same phase. The ACS8530 includes a multistandard microprocessor port, providing access to the configuration and status registers for device setup and monitoring. General Description Overview The following description refers to the Block Diagram (Figure 1 on page 1). The ACS8530 SETS device has 14 input clocks, generates 11 output clocks, and has a total of 55 possible output frequencies. There are two main paths through the device: T0 and T4. Each path has an independent DPLL and APLL pair. The T0 path is a high quality, highly configurable path designed to provide features necessary for node timing synchronization within a SONET/SDH network. The T4 path is a simpler and less configurable path designed to give a totally independent path for internal equipment synchronization. The device supports use of either or both paths, either locked together or independent. Of the 14 input references, two are AMI composite clock, two are LVDS/PECL and the remaining ten are TTL/CMOS compatible inputs. All the TTL/CMOS are 3 V and 5 V compatible (with clamping if required by connecting the Page 8 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL VDD5 pin). The AMI inputs are ±1 V typically A.C. coupled. Refer to the electrical characteristics section for more information on the electrical compatibility and details. Input frequencies supported range from 2 kHz to 155.52 MHz. Common E1, DS1, OC-3 and sub-divisions are supported as spot frequencies that the DPLLs will directly lock to. Any input frequency, up to 100 MHz, that is a multiple of 8 kHz can also be locked to via an inbuilt programmable divider. An input reference monitor is assigned to each of the 14 inputs. The monitors operate continuously such that at all times the status of all of the inputs to the device are known. Each input can be monitored for both frequency and activity, activity alone, or the monitors can be disabled. The frequency monitors have a “hard” (rejection) alarm limit and a “soft” (flag only) alarm limit for monitoring frequency, whilst the reference is still within its allowed frequency band. Each input reference can be programmed with a priority number allowing references to be chosen according to the highest priority valid input. The two paths (T0 and T4) have independent priorities to allow completely independent operation of the two paths. Both paths operate either automatic or external source selection. For automatic input reference selection, the T0 path has a more complex state machine than the T4 path. The T0 and T4 PLL paths support the following common features: z z z z z z z z Automatic source selection according to input priorities and quality level Different quality levels (activity alarm thresholds) for each input Variable bandwidth, lock range and damping factor. Direct PLL locking to common SONET/SDH input frequencies or any multiple of 8 kHz Automatic mode switching between Free-run, Locked and Holdover states Fast detection on input failure and entry into Holdover mode (holds at the last good frequency value) Frequency translation between input and output rates via direct digital synthesis High accuracy digital architecture for stable PLL dynamics combined with an APLL for low jitter final output clocks. Revision 3.02/November 2005 © Semtech Corp. DATASHEET There are a number of features supported by the T0 path that are not supported by the T4 path, although these can also all be externally controlled by software. The additional T0 features supported are: z z z z z z z z z Non-revertive mode Phase Build-out on source switch (hit-less source switching) Phase Build-out following phase hit on locked-to source I/O phase offset control Greater programmable bandwidth from 0.5 mHz to 70 Hz in 18 steps (T4 path programmable bandwidth in 3 steps, 18, 35 and 70 Hz) Noise rejection on low frequency input Manual Holdover frequency control Controllable automatic Holdover frequency filtering Frame Sync pulse alignment. Either the software or an internal state machine controls the operation of the DPLL in the T0 path. The state machine for the T4 path is very simple and cannot be manually/externally controlled, however the overall operation can be controlled by manual reference source selection. One additional feature of the T4 path is the ability to measure a phase difference between two inputs. The T0 path DPLL always produces an output at 77.76 MHz to feed the APLL, regardless of the frequency selected at the output pins. The T4 path can be operated at a number of frequencies. This is to enable the generation of extra output frequencies, which cannot be easily related to 77.76 MHz. When the T4 path is selected to lock to the T0 path, the T4 DPLL locks to the 8 kHz from the T0 DPLL. This is because all of the frequencies of operation of the T4 path can be divided to 8 kHz and this will ensure synchronization of all the frequencies within the two paths. Both of the DPLLs’ outputs are connected to multiplying and filtering APLLs. The outputs of these APLLs are divided making a number of frequencies simultaneously available for selection at the output clock ports. The various combinations of DPLL, APLL and divider configurations allow for generation of a comprehensive set of frequencies, as listed in Table 13. To synchronize the lower output frequencies when the T0 PLL is locked to a high frequency reference input, an additional input is provided. The SYNC2K pin (pin 45) is used to reset the dividers that generate the 2kHz and Page 9 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL 8 kHz outputs such that the output 2/8 kHz clocks are lined up with the input 2 kHz. This synchronization method allows for example, a master and a slave device to be in precise alignment. The ACS8530 also supports Sync pulse references of 4 kHz or 8 kHz although in these cases frequencies lower than the Sync pulse reference may not necessarily be in phase. Input Reference Clock Ports Table 4 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. Note that SDH and SONET networks use different default frequencies; the network type is pinselectable (using either the SONSDHB pin or via software). Specific frequencies and priorities are set by configuration. SDH and SONET networks use different default frequencies; the network type is selectable using the cnfg_input_mode Reg. 34 Bit 2, ip_sonsdhb. z For SONET, ip_sonsdhb = 1 z For SDH, ip_sonsdhb = 0. DATASHEET Lock8k Mode Lock8k mode automatically sets the divider parameters to divide the input frequency down to 8 kHz. Lock8k can only be used on the supported spot frequencies (see Table 4 Note(i)). Lock8k mode is enabled by setting the lock8k bit (Bit 6) in the appropriate cnfg_ref_source_frequency register location. Using lower frequencies for phase comparisons in the DPLL results in a greater tolerance to input jitter. It is possible to choose which edge of the input reference clock to lock to, by setting 8K edge polarity (Bit 2 of Reg. 03, test_register1). DivN Mode In DivN mode, the divider parameters are set manually by configuration (Bit 7 of the cnfg_ref_source_frequency register), but must be set so that the frequency after division is 8 kHz. The DivN function is defined as: DivN = “Divide by N+1”, i.e. it is the dividing factor used for the division of the input frequency, and has a value of (N+1) where N is an integer from 1 to 12499 inclusive. Therefore, in DivN mode the input frequency can be divided by any integer value between 2 to 12500. Consequently, any input frequency which is a multiple of 8 kHz, between 8 kHz to 100 MHz, can be supported by using DivN mode. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 100). Specific frequencies and priorities are set by configuration. The frequency selection is programmed via the cnfg_ref_source_frequency register (Reg. 20 - Reg. 2D). Note...Any reference input can be set to use DivN independently of the frequencies and configurations of the other inputs. However only one value of N is allowed, so all inputs with DivN selected must be running at the same frequency. DivN Examples (a) To lock to 2.000 MHz: Locking Frequency Modes (i) There are three locking frequency modes that can be configured: Direct Lock, Lock8k and DivN. Direct Lock Mode (ii) To achieve 8 kHz, the 2 MHz input must be divided by 250. So, if DivN = 250 = (N + 1) then N must be set to 249. This is done by writing F9 hex (249 dec) to the DivN register pair Reg. 46/47. In Direct Lock Mode, the internal DPLL can lock to the selected input at the spot frequency of the input, for example 19.44 MHz performs the DPLL phase comparisons at 19.44 MHz. In Lock8k and DivN modes (and for special case of 155 MHz), an internal divider is used prior to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. Revision 3.02/November 2005 © Semtech Corp. Set the cnfg_ref_source_frequency register to 10XX0000 (binary) to enable DivN, and set the frequency to 8 kHz - the frequency required after division. (XX = “Leaky Bucket” ID for this input). (b) To lock to 10.000 MHz: Page 10 (i) The cnfg_ref_source_frequency register is set to 10XX0000 (binary) to set the DivN and the www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL frequency to 8 kHz, the post-division frequency. (XX = “Leaky Bucket” ID for this input). (ii) To achieve 8 kHz, the 10 MHz input must be divided by 1,250. So, if DivN, = 250 = (N+1) then N must be set to 1,249. This is done by writing 4E1 hex (1,249 dec to the DivN register pair Reg. 46/47. Direct Lock Mode 155 MHz. The max frequency allowed for phase comparison is 77.76 MHz, so for the special case of a 155 MHz input set to Direct Lock Mode, there is a divide-by-two function automatically selected to bring the frequency down to within the limits of operation. DATASHEET PECL/LVDS/AMI Input Port Selection The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register, Reg. 36. Unused PECL differential inputs should be fixed with one input High (VDD) and the other input Low (GND), or set in LVDS mode and left floating, in which case one input is internally pulled High and the other Low. An AMI port supports a composite clock, consisting of a 64 kHz AMI clock with 8 kHz boundaries marked by deliberate violations of the AMI coding rules, as specified in ITU recommendation G.703[6]. Departures from the nominal pattern are detected within the ACS8530, and may cause reference-switching if too frequent. See section DC Characteristics: AMI Input/Output Port, for more details. If the AMI port is unused, the pins (I1 and I2) should be tied to GND. Table 4 Input Reference Source Selection and Priority Table Port Number Channel Number (Bin) Input Port Technology Frequencies Supported Default Priority I1 0001 AMI 64/8 kHz (composite clock, 64 kHz + 8 kHz) Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz 2 I2 0010 AMI 64/8 kHz (composite clock, 64 kHz + 8 kHz) Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz 3 I3 0011 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz 4 I4 0100 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz 5 I5 0101 LVDS/PECL LVDS Up to 155.52 MHz (see Note (ii)) default Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 6 I6 0110 PECL/LVDS PECL Up to 155.52 MHz (see Note (ii)) default Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 7 I7 0111 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 8 I8 1000 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 9 I9 1001 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 10 I10 1010 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 11 I11 1011 TTL/CMOS Up to 100 MHz (see Note (i)) Default (Master) (SONET): 1.544 MHz Default (Master) (SDH): 2.048 MHz Default (Slave) 6.48 MHz 12/1 (Note (iii)) I12 1100 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz 13 Revision 3.02/November 2005 © Semtech Corp. Page 11 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 4 Input Reference Source Selection and Priority Table (cont...) Port Number Channel Number (Bin) Input Port Technology Frequencies Supported Default Priority I13 1101 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz 14 I14 1110 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz 15 Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 Bit 2, ip_sonsdhb). (ii) PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz (and 311.04 MHz for TO6 only). (iii) Input port I11 is set at priority 12 on the Master SETS IC and priority 1 on the Slave SETS IC, as default on power up (or PORB). The default setup of Master or Slave I11 priority is determined by the MSTSLVB pin. Clock Quality Monitoring Clock quality is monitored and used to modify the priority tables of the local and remote ACS8530 devices. For each input, the following parameters are monitored: 1. Activity (toggling). 2. Frequency (this monitoring is only performed when there is no irregular operation of the clock or loss of clock condition). In addition, input ports I1 and I2 carry AMI-encoded composite clocks which are monitored by the AMIdecoder blocks. Loss of signal is declared by the decoders when either the signal amplitude falls below +0.3 V or there is no activity for 1 ms. Any reference source that suffers a loss-of-activity or clock-out-of-band condition will be declared as unavailable. Clock quality monitoring is a continuous process which is used to identify clock problems. There is a difference in dynamics between the selected clock and the other reference clocks. Anomalies occurring on non-selected reference sources affect only that source's suitability for selection, whereas anomalies occurring on the selected clock could have a detrimental impact on the accuracy of the output clock. Anomalies detected by the activity detector are integrated in a Leaky Bucket Accumulator (one per input channel). Occasional anomalies do not cause the Accumulator to cross the alarm setting threshold, so the selected reference source is retained. Persistent anomalies cause the alarm setting threshold to be crossed and result in the selected reference source being rejected. Revision 3.02/November 2005 © Semtech Corp. Anomalies on the currently locked-to input reference clock, whether affecting signal purity or signal frequency, could induce jitter or frequency offsets in the output clock, leading to anomalous behavior. Anomalies on the selected clock, therefore, have to be detected as they occur and the phase locked loop must be temporarily isolated until the clock is once again pure. The clock monitoring process cannot be used for this because the high degree of accuracy required dictates that the process be slow. To achieve the immediacy required by the phase locked loop requires an alternative mechanism. The phase locked loop itself contains a fast activity detector such that within approximately two missing input clock cycles, a no-activity flag is raised and the DPLL is frozen in Holdover mode. This flag can also be read as the main_ref_failed bit (from Reg. 06, Bit 6) and can be set to indicate a phase lost state by enabling Reg. 73, Bit 6. With the DPLL in Holdover mode it is isolated from further disturbances. If the input becomes available again before the activity or frequency monitor rejection alarms have been raised, then the DPLL will continue to lock to the input, with little disturbance. In this scenario, with the DPLL in the “locked” state, the DPLL uses “nearest edge locking” mode (±180° capture) avoiding cycle slips or glitches caused by trying to lock to an edge 360° away, as would happen with traditional PLLs. Activity Monitoring The ACS8530 has a combined inactivity and irregularity monitor. The ACS8530 uses a Leaky Bucket Accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. Such integrators Page 12 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. Events which are sufficiently spread out should not trigger the alarm. By adjusting the alarm setting threshold, the point at which the alarm is triggered can be controlled. The point at which the alarm is cleared depends upon the decay rate and the alarm clearing threshold. On the alarm setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur a little more spread out, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. On the alarm clearing side, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarm clearing threshold. The ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. This means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). See Figure 3. DATASHEET There is one Leaky Bucket Accumulator per input channel. Each Leaky Bucket can select from four configurations (Leaky Bucket Configuration 0 to 3). Each Leaky Bucket Configuration is programmable for size, alarm set and reset thresholds, and decay rate. Each source is monitored over a 128 ms period. If, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the Accumulator is incremented. The Accumulator will continue to increment up to the point that it reaches the programmed Bucket size. The “fill rate” of the Leaky Bucket is, therefore, 8 units/second. The “leak rate” of the Leaky Bucket is programmable to be in multiples of the fill rate (x 1, x 0.5, x 0.25 and x 0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. A conflict between trying to “leak” at the same time as a “fill” is avoided by preventing a leak when a fill event occurs. Disqualification of a non-selected reference source is based on inactivity, or on an out-of-band result from the frequency monitors. The currently selected reference source can be disqualified for phase, frequency, inactivity or if the source is outside the DPLL lock range. If the currently selected reference source is disqualified, the next highest priority, qualified reference source is selected. Figure 3 Inactivity and Irregularity Monitoring Inactivities/Irregularities Reference Source bucket_size Leaky Bucket Response upper_threshold lower_threshold Programmable Fall Slopes (all programmable) Alarm F8530D_026Inact_Irreg_Mon_02 Revision 3.02/November 2005 © Semtech Corp. Page 13 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL Interrupts for Activity Monitors DATASHEET Leaky Bucket Timing The loss of the currently selected reference source will eventually cause the input to be considered invalid, triggering an interrupt, if not masked. The time taken to raise this interrupt is dependant on the Leaky Bucket Configuration of the activity monitors. The fastest Leaky Bucket setting will still take up to 128 ms to trigger the interrupt. The interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source failure detection if desired. It is triggered after missing just a couple of cycles of the reference source. Some applications require the facility to switch downstream devices based on the status of the reference sources. In order to provide extra flexibility, it is possible to flag the main_ref_failed interrupt (Reg. 06 Bit 6) on the pin TDO. This is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. The bit is reset by writing to the interrupt status register in the normal way. This feature can be enabled and disabled by writing to Reg. 48 Bit 6. The time taken (in seconds) to raise an inactivity alarm on a reference source that has previously been fully active (Leaky Bucket empty) will be: (cnfg_upper_threshold_n) / 8 where n is the number (0 to 3) of the Leaky Bucket Configuration. If an input is intermittently inactive then this time can be longer. The default setting of cnfg_upper_threshold_n is 6, therefore the default time is 0.75 s. The time taken (in seconds) to cancel the activity alarm on a previously completely inactive reference source is calculated, for a particular Leaky Bucket, as: [2 (a) x (b - c)]/ 8 where: a = cnfg_decay_rate_n b = cnfg_bucket_size_n c = cnfg_lower_threshold_n (where n = the number (0 to 3) of the relevant Leaky Bucket Configuration in each case). The default setting is shown in the following: [21 x (8 - 4)] /8 = 1.0 secs Frequency Monitoring The ACS8530 performs frequency monitoring to identify reference sources which have drifted outside the acceptable frequency range measured with respect either to the output clock or to the XO clock. The sts_reference_sources out-of-band alarm for a particular reference source is raised when the reference source is outside the acceptable frequency range. With the default register settings a soft alarm is raised if the drift is outside ±11.43 ppm and a hard alarm is raised if the drift is outside ±15.24 ppm. Both of these limits are programmable from 3.8 ppm up to 61 ppm. The ACS8530 DPLL has a programmable lock and capture range frequency limit up to ±80 ppm (default is ±9.2 ppm). Selection of Input Reference Clock Source Under normal operation, the input reference sources are selected automatically by an order of priority. But, for special circumstances, such as chip or board testing, the selection may be forced by configuration. Revision 3.02/November 2005 © Semtech Corp. Automatic operation selects a reference source based on its pre-defined priority and its current availability. A table is maintained which lists all reference sources in the order of priority. This is initially defined by the default configuration and can be changed via the microprocessor interface by the Network Manager. In this way, when all the defined sources are active and valid, the source with the highest programmed priority is selected but, if this source fails, the next-highest source is selected, and so on. Restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. For this, the ACS8530 has two modes of operation; Revertive and Non-revertive. In Revertive mode, if a re-validated (or newly validated) source has a higher priority than the reference source which is currently selected, a switch over will take place. Many applications prefer to minimize the clock switching events and choose Non-revertive mode. In Non-revertive mode, when a re-validated (or newly validated) source has a higher priority then the selected source will be maintained. The re-validation of the reference source will be flagged in the sts_sources_valid register and, if not masked, will generate an interrupt. Page 14 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL Selection of the re-validated source can take place under software control or if the currently selected source fails. To enable software control, the software should briefly enable Revertive mode to effect a switch-over to the higher priority source. When there is a reference available with higher priority than the selected reference, there will be NO change of reference source as long as the Non-revertive mode remains on, and the currently selected source is valid. A failure of the selected reference will always trigger a switch-over regardless of whether Revertive or Non-revertive mode has been chosen. Also, in a Master/Slave redundancy-protection scheme, the Slave device(s) must follow the Master device. The alignment of the Master and Slave devices is part of the protection mechanism. The availability of each source is determined by a combination of local and remote monitoring of each source. Each input reference source supplied to each ACS8530 device is monitored locally and the results are made available to other devices. DATASHEET are 1 to 15 (dec). A value of 0 disables the reference source. However if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. If the first of two same priority number sources goes invalid the second will be switched in. If the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. If a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. There is no implied priority based on the channel numbers. Revertive/Non-revertive mode has no effect on sources with the same priority value. The input port I11 is also for the connection of the synchronous clock of the T0 output of the Master device (or the active-Slave device), to be used to align the T0 output with the Master (or active-Slave) device if this device is acting in a subordinate-Slave or subordinateMaster role. Forced Control Selection Ultra Fast Switching A configuration register, force_select_reference_source Reg. 33, controls both the choice of automatic or forced selection and the selection itself (when forced selection is required). For Automatic choice of source selection, the 4 LSB bit value is set to all zeros or all ones (default). To force a particular input (In), the Bit value is set to n (bin). Forced selection is not the normal mode of operation, and the force_select_reference_source variable is defaulted to the all-one value on reset, thereby adopting the automatic selection of the reference source. A reference source is normally disqualified after the Leaky Bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented, whereby if Reg. 48 Bit 5 (ultra_fast_switch) is set, then a loss of activity of just a few reference clock cycles will set the main_ref_failed alarm and cause a reference switch. This can be configured (see Reg. 06, Bit 6) to cause an interrupt to occur instead of, or as well as, causing the reference switch. Automatic Control Selection When an automatic selection is required, the force_select_reference_source register LSB 4 bits must be set to all zeros or all ones. The configuration registers, cnfg_ref_selection_priority, held in the µP port block, consist of seven, 8-bit registers organized as one 4-bit register per input reference port. Each register holds a 4-bit value which represents the desired priority of that particular port. Unused ports should be given the value, 0000, in the relevant register to indicate they are not to be included in the priority table. On power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined by Table 4. The selection priority values are all relative to each other, with lowervalued numbers taking higher priorities. Each reference source should be given a unique number; the valid values Revision 3.02/November 2005 © Semtech Corp. The sts_interrupts register Reg. 06 Bit 6 (main_ref_failed) is used to flag inactivity on the reference that the device is locked to much faster than the activity monitors can support. If Reg. 48 Bit 6 of the cnfg_monitors register (los_flag_on_TDO) is set, then the state of this bit is driven onto the TDO pin of the device. Note...The flagging of the loss of the main reference failure on TDO is simply allowing the status of the sts_interrupts bit main_ref_failed Reg. 06 Bit 6, to be reflected in the state of the TDO output pin. The pin will, therefore, remain High until the interrupt is cleared. This functionality is not enabled by default so the usual JTAG functions can be used. When the TDO output from the ACS8530 is connected to the TDI pin of the next device in the JTAG scan chain, the implementation should be such that a logic change caused by the action of the interrupt on the TDI input should not effect the operation when JTAG is not active. Page 15 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL Fast External Switching Mode-SCRSW Pin Fast external switching mode, for fast switching between inputs I3 or I5 and I4 or I6, can also be triggered directly from a dedicated pin SRCSW (Figure 4), once the mode has been initialized. The mode is initialized by either holding SRCSW pin High during reset (SRCSW must remain High for at least a further 251 ms after PORB has gone High - see following Note), or by writing to Reg. 48 Bit 4. After External Protection Switching mode has been initialized, the value on this pin directly selects either I3/I5 (SRCSW High) or I4/I6 (SRCSW Low). If this mode is initialized at reset by pulling the SRCSW pin High, then it configures the default frequency tolerance of I3/I5 and I4/I6 to ±80 ppm (Reg. 41 and Reg. 42) as opposed to the normal frequency tolerance of ±9.2 ppm. Any of these registers can be subsequently set by external software, if required. Note...The 251 ms comprises 250 ms allowance for the internal reset to be removed plus 1 ms allowance for APLLs to start-up and become stable. Selection of either input I3 or I5 is determined by the Priority value of I3; if the programmed priority of I3 is 0, then I5 is selected. Similarly, I6 is selected if the programmed priority of I4 is 0. Figure 4 I3/I5 and I4/I6 Switching I3 Priority >0 SRCSW I3 1 I5 0 1 T0 DPLL I4 1 0 I6 0 I4 Priority >0 F8530D_006IPSWI3I4I5I6_01 When external protection switching is enabled, the device will operate as a simple switch. All clock monitoring is disabled and the DPLL will simply be forced to try to lock on to the indicated reference source. Consequently the device will always indicate “locked” state in the sts_operating register (Reg. 09, Bits 2:0). Revision 3.02/November 2005 © Semtech Corp. DATASHEET Output Clock Phase Continuity on Source Switchover If either PBO is selected on (default), or, if DPLL frequency limit is set to less than ±30 ppm or (±9.2 ppm default), the device will always comply with GR-1244-CORE[19] specification for Stratum 3 (maximum rate of phase change of 81 ns/1.326 ms), for all input frequencies. Modes of Operation The ACS8530 has three primary modes of operation (Free-run, Locked and Holdover) supported by three secondary, temporary modes (Pre-Locked, Lost-Phase and Pre-Locked2). These are shown in the State Transition Diagram for the T0 DPLL, Figure 5. The ACS8530 can operate in Forced or Automatic control. On reset, the ACS8530 reverts to Automatic Control, where transitions between states are controlled completely automatically. Forced Control can be invoked by configuration, allowing transitions to be performed under external control. This is not the normal mode of operation, but is provided for special occasions such as testing, or where a high degree of hands-on control is required. Free-run Mode The Free-run mode is typically used following a power-on reset or a device reset before network synchronization has been achieved. In the Free-run mode, the timing and synchronization signals generated from the ACS8530 are based on the 12.800 MHz clock frequency provided from the external oscillator and are not synchronized to an input reference source. By default, the frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the oscillator. However the external oscillator frequency can be calibrated to improve its accuracy by a software calibration routine using register cnfg_nominal_frequency (Reg. 3C and 3D). For example a 500 ppm offset crystal could be made to look like one accurate to within ±0.02 ppm. The transition from Free-run to Pre-locked occurs when the ACS8530 selects a reference source. Pre-locked Mode The ACS8530 will spend a maximum of 100 seconds in the Pre-locked mode. If the device is required to spend up to 700 seconds acquiring lock (e.g. in a Stratum3E Page 16 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL application) external software will be required to force the device into Locked mode until phase lock has been achieved. Without software control, if the device cannot achieve lock within 100 seconds, the reference is disqualified and a phase alarm is raised on it. The device will then revert to Free-run mode and another reference source, if available, will be selected. Holdover can be configured to operate in either: z Automatic Mode (Reg. 34 Bit 4, cnfg_input_mode: man_holdover set Low), or z Manual Mode (Reg. 34 Bit 4, cnfg_input_mode: man_holdover set High). Locked Mode The Locked mode is entered from Pre-locked, Pre-locked2 or Phase-lost mode when an input reference source has been selected and the DPLL has locked. The DPLL is considered to be locked when the phase loss/lock detectors (See“Phase Lock/Loss Detection” on page 21) indicate that the DPLL has remained in phase lock continuously for at least one second. When the ACS8530 is in Locked mode, the output frequency and phase tracks that of the selected input reference source. Automatic Mode In Automatic mode, the device can be configured to operate using either: z Averaged (Reg. 40 Bit 7, cnfg_holdover_modes, auto_averaging: set High) or z Instantaneous (Reg. 40 Bit 7, cnfg_holdover_modes, auto_averaging: set Low). Lost-phase Mode Lost-phase mode is used whenever the phase loss/lock detectors (See“Phase Lock/Loss Detection” on page 21) indicate that the DPLL has lost phase lock. The DPLL will still be trying to lock to the input clock reference, if it exists. If the Leaky Bucket Accumulator calculates that the anomaly is serious, the device disqualifies the reference source. If the device spends more than 100 seconds in Lost-phase mode, the reference is disqualified and a phase alarm is raised on it. If the reference is disqualified, one of the following transitions takes place: 1. Go to Pre-locked2; - If a known good stand-by source is available. Averaged In the Averaged mode, the frequency (as reported by sts_current_DPLL_frequency, see Reg. 0C, Reg. 0D and Reg. 07) is filtered internally using an Infinite Impulse Response filter, which can be set to either: z Fast (Reg. 40 Bit 6, cnfg_holdover_modes, fast_averaging: set High), giving a -3 dB filter response point corresponding to a period of approx. eight minutes, or z Slow (Reg. 40 Bit 6, cnfg_holdover_modes, fast_averaging: set Low) giving a -3 dB filter response point corresponding to a period of approx. 110 minutes. 2. Go to Holdover; - If no stand-by sources are available. Holdover Mode Holdover mode is the operating condition the device enters when its currently selected input source becomes invalid, and no other valid replacement source is available. In this mode, the device resorts to using stored frequency data, acquired when the input reference source was still valid, to control its output frequency. In Holdover mode, the ACS8530 provides the timing and synchronization signals to maintain the Network Element but is not phase locked to any input reference source. Its output frequency is determined by an averaged version of the DPLL frequency when last in the Locked Mode. Revision 3.02/November 2005 © Semtech Corp. DATASHEET Instantaneous In Instantaneous mode, the DPLL freezes at the frequency it was operating at the time of entering Holdover mode. It does this by using only its internal DPLL integral path value (as reported in Reg. 0C, 0D, and 07) to determine output frequency. The DPLL proportional path is not used so that any recent phase disturbances have a minimal effect on the Holdover frequency. The integral value used can be viewed as a filtered version of the locked output frequency over a short period of time. The period being in inverse proportion to the DPLL bandwidth setting. Page 17 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 5 Automatic Mode Control State Diagram (T0 DPLL) (1) Reset Free-run select ref (state 001) (2) all refs evaluated & at least one ref valid (3) no valid standby ref & (main ref invalid or out of lock > 100s Reference sources are flagged as valid when active, in-band and have no phase alarm set. (4) valid standby ref & [main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock > 100s] All sources are continuously checked for activity and frequency Pre-locked wait for up to 100s (state 110) Only the main source is checked for phase. A phase lock alarm is only raised on a reference when that reference has lost phase whilst being used as the main reference. The micro-processor can reset the phase lock alarm. (5) selected ref phase locked A source is considered to have phase locked when it has been continuously in phase lock for between 1 and 2 seconds. Locked keep ref (state 100) (6) no valid standby ref & main ref invalid (10) selected source phase locked (9) valid standby ref & [main ref invalid or (higher priority ref valid & in revertive mode)] Pre-locked2 wait for up to 100s (state 101) (12) valid standby ref & (main ref invalid or out of lock >100s) (15) valid standby ref & [main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] (8) phase regained within 100s (7) phase lost on main ref (11) no valid standby ref & Lost-phase (main ref invalid wait for up to 100s or out of lock >100s) (state 111) Holdover select ref (state 010) (13) no valid standby ref & (main ref invalid or out of lock >100s) (14) all refs evaluated & at least one ref valid F8530D_018AutoModeContStateDia_02 Note...The state diagram above is for T0 DPLL only, and the 3-bit state value refers to the register sts_operating Reg. 09 Bits [2:0] T0_DPLL_operating _mode. By contrast, the T4 DPLL has only automatic operation and can be in one of only two possible states: “Instantaneous Automatic Holdover” with zero frequency offset (its start-up state), or “Locked”. The T4 DPLL states are not configurable by the User and there is no “Free-run” state. Revision 3.02/November 2005 © Semtech Corp. Page 18 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL Manual Mode (Reg. 34 Bit 4, cnfg_input_mode, man_holdover set High.) The Holdover frequency is determined by the value in register cnfg_holdover_frequency (Reg. 3E, Reg. 3F, and part of Reg. 40). This is a 19-bit signed number, with a LSB resolution of 0.0003068 ppm, which gives an adjustment range of ±80 ppm. This value can be derived from a reading of the register sts_current_DPLL_frequency (Reg. 0D, Reg. 0C and Reg. 07), which gives, in the same format, an indication of the current output frequency deviation, which would be read when the device is locked. If required, this value could be read by external software and averaged over time. The averaged value could then be fed to the cnfg_holdover_frequency register, ready for setting the averaged frequency value when the device enters Holdover mode. The sts_current_DPLL_frequency value is internally derived from the Digital Phase Locked Loop (DPLL) integral path, which represents a short-term average measure of the current frequency, depending on the locked loop bandwidth (Reg. 67) selected. It is also possible to combine the internal averaging filters with some additional software filtering. For example the internal fast filter could be used as an anti-aliasing filter and the software could further filter this before determining the actual Holdover frequency. To support this feature, a facility to read out the internally averaged frequency has been provided. By setting Reg. 40, Bit 5, cnfg_holdover_modes, read_average, the value read back from the cnfg_holdover_frequency register will be the filtered value. The filtered value is available regardless of what actual Holdover mode is selected. Clearly this results in the register not reading back the data that was written to it. Example: Software averaging to eliminate temperature drift. Select Manual Holdover mode by setting Reg. 34 Bit 4, cnfg_input_mode, man_holdover High. Select Fast Holdover Averaging mode by setting Reg. 40 Bit 6, cnfg_holdover_modes, auto_averaging High and Reg. 40 Bit 7 High. Select to be able to read back filtered output by setting Reg. 40 Bit 5, cnfg_holdover_modes, read_average High. Software periodically reads averaged value from the cnfg_holdover_frequency register and the temperature (not supplied from ACS8530). Software processes frequency and temperature and places data in software look-up table or other algorithm. Software writes back Revision 3.02/November 2005 © Semtech Corp. DATASHEET appropriate averaged value into the cnfg_holdover_frequency register. Once Holdover mode is entered, software periodically updates the cnfg_holdover_frequency register using the temperature information (not supplied from ACS8530). Mini-holdover Mode Holdover mode so far described refers to a state to which the internal state machine switches as a result of activity or frequency alarms, and this state is reported in Reg. 09. To avoid the DPLL’s frequency being pulled off as a result of a failed input, then the DPLL has a fast mechanism to freeze its current frequency within one or two cycles of the input clock source stopping. Under these circumstances the DPLL enters Mini-holdover mode; the Mini-holdover frequency used being determined by Reg. 40, Bits [4:3], cnfg_holdover_modes, mini_holdover_mode. Mini-holdover mode only lasts until one of the following happens: z z z A new source has been selected, or The state machine enters Holdover mode, or The original fault on the input recovers. External Factors Affecting Holdover Mode If the external OCXO frequency is varying due to temperature fluctuations in the room, then the instantaneous value can be different from the average value, and then it may be possible to exceed the 0.05 ppm limit (depending on how extreme the temperature fluctuations are). It is advantageous to shield the OCXO to slow down frequency changes due to drift and external temperature fluctuations. The frequency accuracy of Holdover mode has to meet the ITU-T, ETSI and Telcordia performance requirements. The performance of the external oscillator clock is critical in this mode, although only the frequency stability is important - the stability of the output clock in Holdover is directly related to the stability of the external oscillator. Pre-locked2 Mode This state is very similar to the Pre-Locked state. It is entered from the Holdover state when a reference source has been selected and applied to the phase locked loop. It is also entered if the device is operating in Revertive mode and a higher-priority reference source is restored. The ACS8530 will spend a maximum of 100 seconds in the Pre-locked2 mode. If the device is required to spend Page 19 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET up to 700 seconds acquiring lock (e.g. in a Stratum3E application) external software will be required to force the device into Locked mode until phase lock has been achieved. Without software control, if the device cannot achieve lock within 100 seconds, the reference is disqualified and a phase alarm is raised on it. It will then revert to Holdover mode and another reference source, if available, will be selected. TO DPLL Main Features DPLL Architecture and Configuration z A Digital PLL gives a stable and consistent level of performance that can be easily programmed for different dynamic behavior or operating range. It is not affected by operating conditions or silicon process variations. Digital synthesis is used to generate all required SONET/SDH output frequencies. The digital logic operates at 204.8 MHz that is multiplied up from the external 12.800 MHz oscillator module. Hence the best resolution of the output signals from the DPLL is one 204.8 MHz cycle or 4.9 ns. z Additional resolution and lower final output jitter is provided by a de-jittering Analog PLL that reduces the 4.9 ns p-p jitter from the digital down to 500 ps p-p and 60 ps RMS as typical final outputs measured broadband (from 10 Hz to 1 GHz). This arrangement combines the advantages of the flexibility and repeatability of a DPLL with the low jitter of an APLL. The DPLLs in the ACS8530 are uniquely very programmable for all PLL parameters of bandwidth (from 0.5 mHz up to 70 Hz), damping factor (from 1.2 to 20), frequency acceptance and output range (from 0 to 80 ppm, typically 9.2 ppm), input frequency (12 common SONET/SDH spot frequencies) and input-to-output phase offset (in 6 ps steps up to 200 ns). There is no requirement to understand the loop filter equations or detailed gain parameters since all high level factors such as overall bandwidth can be set directly via registers in the microprocessor interface. No external critical components are required for either the internal DPLLs or APLLs, providing another key advantage over traditional discrete designs. The T4 DPLL is similar in structure to the T0 DPLL, but since the T4 is only providing a clock synthesis and input to output frequency translation function, with no defined requirement for jitter attenuation or input phase jump absorption, then its bandwidth is limited to the high end and the T4 does not incorporate many of the Phase Buildout and adjustment facilities of the T0 DPLL. Revision 3.02/November 2005 © Semtech Corp. z z z z z z z z z z Two programmable DPLL bandwidth controls (Locked and Acquisition bandwidth), each with 18 steps from 0.5 mHz to 70 Hz Programmable damping factor for optional faster locking and peaking control. Factors = 1.2, 2.5, 5, 10 or 20 Multiple phase lock detectors Input to output phase offset adjustment (Master/Slave), ±200 ns, 6 ps resolution step size PBO phase offset on source switching - disturbance down to ±5 ns Detection of phase jump on the current source: programmable limit from 1 - 3.5 us in 100 ms Optional automatic Phase Build-out event on a detected input phase jump Multi-cycle phase detection and locking, programmable up to ±8192 UI - improves jitter tolerance in direct lock mode Holdover frequency averaging with a choice of averaging times: 8 minutes or 110 minutes and value can be read out Multiple E1 and DS1 outputs supported Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs 2 kHz and 8 kHz on TO1 to TO7 with programmable pulse width and polarity. T4 DPLL Main Features z z z z z z z z z z Page 20 A single programmable DPLL bandwidth control: 18 Hz, 35 Hz, or 70 Hz Programmable damping factor for optional faster locking and peaking control. Factors = 1.2, 2.5, 5, 10 or 20 Multiple phase lock detectors Multi-cycle phase detection and locking, programmable up to ±8192 UI - improves jitter tolerance in direct lock mode DS3/E3 support (44.736 MHz / 34.368 MHz) at same time as OC-N rates from T0 Low jitter E1/DS1 options at same time as OC-N rates from T0 Frequencies of n x E1/DS1 including 16 and 12 x E1, and 16 and 24 x DS1 supported Low jitter 2 kHz and 8 kHz outputs on TO1 to TO7 Can use the T4 DPLL as an Independent FrSync DPLL Can use the phase detector in T4 DPLL to measure the input phase difference between two inputs. www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL The structure of the T0 and T4 PLLs are shown later in Figure 11 in the section on output clock ports. That section also details how the DPLLs and particular output frequencies are configured. The following sections detail some component parts of the DPLL. TO DPLL Automatic Bandwidth Controls In Automatic Bandwidth Selection mode (Reg. 3B Bit 7), the T0 DPLL bandwidth setting is selected automatically from the Acquisition Bandwidth or Locked Bandwidth configurations programmed in cnfg_T0_DPLL_acq_bw Reg. 69 and cnfg_T0_DPLL_locked_bw Reg. 67 respectively. If this mode is not selected, the DPLL acquires and locks using only the bandwidth set by Reg. 67. Phase Detectors A Phase and Frequency detector is used to compare input and feedback clocks. This operates at input frequencies up to 77.76 MHz. The whole DPLL can operate at spot frequencies from 2 kHz up to 77.76 MHz (155.52 MHz is internally divided down to 77.76 MHz). A common arrangement however is to use Lock8k mode (See Reg. 22 to 2D, Bit 6) where all input frequencies are divided down to 8 kHz internally. Marginally better MTIE figures may be possible in direct lock mode due to more regular phase updates. This direct locking capability is one of the unique features of the ACS8530. A patented multi-phase detector is used in order to give an infinitesimally small input phase resolution combined with large jitter tolerance. The following phase detectors are used: z z z The balance between the first two types of phase detector employed can be adjusted via registers 6A to 6D. The default settings should be sufficient for all modes. Adjustment of these settings affects only small signal overshoot and bandwidth. The multi-cycle phase detector is enabled via Reg. 74, Bit 6 set to 1 and the range is set in exponentially increasing steps from ±1 UI, 3 UI, 7 UI, 15 UI … up to 8191 UI via Reg. 74, Bits [3:0]. When this detector is enabled it keeps a track of the correct phase position over many cycles of phase difference to give excellent jitter tolerance. This provides an alternative to switching to Lock8k mode as a method of achieving high jitter tolerance. An additional control (Reg. 74 Bit 5) enables the multiphase detector value to be used in the final phase value as part of the DPLL loop. When enabled by setting High, the multi cycle phase value will be used in the loop and gives faster pull in (but more overshoot). The characteristics of the loop will be similar to Lock8k mode where again large input phase differences contribute to the loop dynamics. Setting the bit Low only uses a max figure of 360 degrees in the loop and will give slower pullin but gives less overshoot. The final phase position that the loop has to pull in to is still tracked and remembered by the multi-cycle phase detector in either case. Phase Lock/Loss Detection Phase lock/loss detection is handled in several ways. Phase loss can be triggered from: z z z The phase detectors can be configured to be immune to occasional missing input clock pulses by using nearest edge detection (±180 deg capture) or the normal ± 360 deg phase capture range which gives frequency locking. The device will automatically switch to nearest edge locking when the multi-UI phase detector is not enabled, and the other phase detectors have detected that phase lock has been achieved. It is possible to disable the selection of nearest edge locking via Reg. 03 Revision 3.02/November 2005 © Semtech Corp. Bit 6 set to 1. In this setting, frequency locking will always be enabled. z Phase and frequency detector (±360 deg or ± 180 deg range) An Early/ Late Phase detector for fine resolution A multi-cycle phase detector for large input jitter tolerance (up to 8191 UI), which captures and remembers phase differences of many cycles between input and feedback clocks. DATASHEET The fine phase lock detector, which measures the phase between input and feedback clock The coarse phase lock detector, which monitors whole cycle slips Detection that the DPLL is at min or max frequency Detection of no activity on the input. Each of these sources of phase loss indication is individually enabled via register bits (see Reg. 73, 74 and 4D). Phase lock or lost is used to determine whether to switch to nearest edge locking and whether to use Acquisition or Locked bandwidth settings for the DPLL. Acquisition bandwidth is used for faster pull in from an unlocked state. The coarse phase lock detector detects phase differences of n cycles between input and feedback clocks, where n is set by Reg. 74, Bits 3:0; the same register that is used for Page 21 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL the coarse phase detector range, since these functions go hand in hand. This detector may be used in the case where it is required that a phase loss indication is not given for reasonable amounts of input jitter and so the fine phase loss detector is disabled and the coarse detector is used instead. Damping Factor Programmability The DPLL damping factor is set by default to provide a maximum wander gain peak of around 0.1 dB. Many of the specifications (e.g. GR-1244-CORE[19], G.812[10] and G.813[11]) specify a wander transfer gain of less than 0.2 dB. GR-253[17] specifies jitter (not wander) transfer of less than 0.1 dB. To accommodate the required levels of transfer gain, the ACS8530 provides a choice of damping factors, with more choice given as the bandwidth setting increases into the frequency regions classified as jitter. Table 5 shows which damping factors are available for selection at the different bandwidth settings, and what the corresponding jitter transfer approximate gain peak will be. Table 5 Available Damping Factors for different DPLL Bandwidths, and associated Jitter Peak Values DATASHEET Local Oscillator Clock The Master system clock on the ACS8530 should be provided by an external clock oscillator of frequency 12.800 MHz. The clock specification is important for meeting the AT&T, ITU/ETSI and Telcordia performance requirements for Holdover mode. Telcordia specifications require a non-temperature-related drift of less than 1 ppb per day and a drift of 10 ppb over the temperature range 0 to +50°C. Telcordia GR-1244 Specification Table 6 Stratum 3E Specification Parameter Value Initial Offset ±1 x 10-9 Offset Over Temperature (Note i) ±10 x 10-9 (Note ii) Drift Rate Due to Ageing ±1.16 x 10-14/second (Note ii) (= 1 x 10-9/day) Notes: (i) Figure quoted is for long-term drift over the range 0°C to +40°C, but for short-term ( 1 to 3.5 µs could be absorbed automatically or just flagged by the device with an interrupt raised, the external processor can then decide when and whether to perform a PBO event to absorb the phase disturbance. The monitoring block for detecting Figure 8 TO DPLL Wander and Jitter Measured Transfer Characteristics (Jitter = 0.2 UI p-p) Revision 3.02/November 2005 © Semtech Corp. Page 25 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET phase shifts within the 0.1 second period operates in the following manner: When the input phase changes by more than 156 ns with respect to an internal version of the DPLL output then the internal 0.1 second interval counter is started. This internal DPLL output can be considered as representing the previous phase of the input. If the phase change is greater than the preset threshold (programmable from 1 to 3.5 µs) during any time up to the 0.1 second limit, then a PBO event will be triggered automatically (with Reg. 76, Bits 5 and 4 = 1), hence absorbing the phase disturbance. The disturbance to the DPLL is minimal with low DPLL bandwidth and when the input phase change occurs within a small time interval. be used to compensate for circuit and board wiring delays. The output phase can be adjusted in 6 ps steps up to 200 ns in a positive or negative direction. The phase adjustment actually changes the phase position of the feedback clock so that the DPLL adjusts the output clock phases to compensate. The rate of change of phase is therefore related to the DPLL bandwidth. For the DPLL to track large instant changes in phase, either Lock8k mode should be on, or the coarse phase detector should be enabled. Register cnfg_phase_offset at Reg. 70 and 71 controls the output phase, which is only used when PBO is off (Reg. 48, Bit 2 = 0 and Reg. 76, Bit 4 = 0). When a PBO event is triggered, the device enters a temporary Holdover state. When in this temporary state, the phase of the input reference is measured, relative to the output. The device then automatically accounts for any measured phase difference and adds the appropriate phase offset into the DPLL to compensate. Following a PBO event, whatever the phase difference on change of input, the output phase transient is minimized to be no greater than 5 ns. Input Wander and Jitter Tolerance On the ACS8530, PBO can be enabled, disabled or frozen using the microprocessor interface. By default, it is enabled. When PBO is enabled, PBO can also be frozen (at the current offset setting). The device will then ignore any further PBO events occurring on any subsequent reference switch, and maintain the current phase offset. If PBO is disabled while the device is in the Locked mode, there may be a phase shift on the output SEC clocks as the DPLL locks back to 0 degrees phase error. The rate of phase shift will depend on the programmed bandwidth. Enabling PBO whilst in the Locked stated will also trigger a PBO event. PBO Phase Offset In order to minimize the systematic (average) phase error for PBO, a PBO Phase Offset can be programmed in 0.101 ns steps in the cnfg_PBO_phase_offset register, Reg.72. The range of the programmable PBO phase offset is restricted to ±1.4 ns. This can be used to eliminate an accumulation of phase shifts in one direction. Input to Output Phase Adjustment When PBO is off (including Auto-PBO on phase transients), such that the system always tries to align the outputs to the inputs at the 0° position, there is a mechanism provided in the ACS8530 for precise fine tuning of the output phase position with respect to the input. This can Revision 3.02/November 2005 © Semtech Corp. The ACS8530 is compliant to the requirements of all relevant standards, principally ITU Recommendation G.825[15], ANSI DS1.101-1999[1], Telcordia GR1244[19], GR253[17], G812[10], G813[11] and ETS 300 462-5 (1996)[4]. All reference clock inputs have a tight frequency tolerance but a generous jitter tolerance. Pull-in, hold-in and pull-out ranges are specified in Table 7. Minimum jitter tolerance masks are specified in Figures 9 and 10, and Tables 7 and 9, respectively. The ACS8530 will tolerate wander and jitter components greater than those shown in Figure 9 and Figure 10, up to a limit determined by a combination of the apparent long-term frequency offset caused by wander and the eye-closure caused by jitter (the input source will be rejected if the offset pushes the frequency outside the hold-in range for long enough to be detected, whilst the signal will also be rejected if the eye closes sufficiently to affect the signal purity). Either the Lock8k mode, or one of the extended phase capture ranges should be engaged for high jitter tolerance according to these masks. All reference clock ports are monitored for quality, including frequency offset and general activity. Single short-term interruptions in selected reference clocks may not cause re- arrangements, whilst longer interruptions, or multiple, short-term interruptions, will cause rearrangements, as will frequency offsets which are sufficiently large or sufficiently long to cause loss-of-lock in the phase-locked loop. The failed reference source will be removed from the priority table and declared as unserviceable, until its perceived quality has been restored to an acceptable level. Page 26 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 7 Input Reference Source Jitter Tolerance Jitter Tolerance Frequency Monitor Acceptance Range Frequency Acceptance Range (Pull-in) Frequency Acceptance Range (Hold-in) Frequency Acceptance Range (Pull-out) ±4.6 ppm (see Note (i)) ±9.2 ppm (see Note (ii)) ±4.6 ppm (see Note (i)) ±9.2 ppm (see Note (ii)) ±4.6 ppm (see Note (i)) ±9.2 ppm (see Note (ii)) G.703[6] G.783[9] ±16.6 ppm G.823[13] GR-1244-CORE[19] Notes: (i) The frequency acceptance and generation range will be ±4.6 ppm around the required frequency when the external crystal frequency accuracy is within a tolerance of ±4.6 ppm. (ii) The fundamental acceptance range and generation range is ±9.2 ppm with an exact external crystal frequency of 12.800 MHz. This is the default DPLL range, the range is also programmable from 0 to 80 ppm in 0.08 ppm steps. Figure 9 Minimum Input Jitter Tolerance (OC-3/STM-1) A0 A1 A2 A3 A4 Jitter and Wander Frequency (log scale) f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 F8530_003MINIPJITTOLOC3STM1_02 Note...For inputs supporting G.783[9] compliant sources.) Table 8 Amplitude and Frequency Values for Jitter Tolerance (OC-3/STM-1) STM level Peak to peak amplitude (unit Interval) A0 STM-1 2800 A1 A2 A3 A4 311 39 1.5 0.15 Revision 3.02/November 2005 © Semtech Corp. Frequency (Hz) F0 F1 F2 F3 F4 12 u 178 u 1.6 m 15.6 m 0.125 Page 27 F5 19.3 F6 F7 F8 F9 500 6.5 k 65 k 1.3 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 10 Minimum Input Jitter Tolerance (DS1/E1) Peak-to-peak Jitter and Wander Amplitude (log scale) A1 A2 Jitter and Wander Frequency (log scale) f1 f2 f3 F8530D_004MINIPJITTOLDS1E1_02 f4 Table 9 Amplitude and Frequency Values for Jitter Tolerance (DS1/E1) Type Spec. Amplitude (UI p-p) A1 Frequency (Hz) A2 F1 F2 F3 F4 DS1 GR-1244-CORE[19] 5 0.1 10 500 8k 40 k E1 ITU G.823[13] 1.5 0.2 20 2.4 k 18 k 100 Using the DPLLs for Accurate Frequency and Phase Reporting The frequency monitors in the ACS8530 perform frequency monitoring with a programmable acceptable limit of up to ±60.96 ppm. The resolution of the measurement is 3.8 ppm and the measured frequency can be read back from Reg. 4C, with channel selection at Reg. 4B. For more accurate measurement of both frequency and phase, the T0 and T4 DPLLs and their phase detectors, can be used to monitor both input frequency and phase. The T0 DPLL is always monitoring the currently locked to source, but if the T4 path is not used then the T4 DPLL can be used as a roving phase and frequency meter. Via software control it could be switched to monitor each input in turn and both the phase and frequency can be reported with a very fine resolution. The registers sts_current_DPLL_frequency (Reg. 0C, Reg. 0D and Reg. 07) report the frequency of either the T0 or T4 DPLL with respect to the external crystal XO frequency (after calibration via Reg. 3C, 3D if used). The selection of T4 or T0 DPLL reporting is made via Reg. 4B, Bit 4. The value is a 19-bit signed number with one LSB representing 0.0003068 ppm (range of ±80 ppm). This value is actually the integral path value in the DPLL, and as such corresponds to an averaged measurement of the Revision 3.02/November 2005 © Semtech Corp. input frequency, with an averaging time inversely proportional to the DPLL bandwidth setting. Reading this regularly can show how the currently locked source is varying in value e.g. due to frequency wander on its input. The input phase, as seen at the DPLL phase detector, can be read back from register sts_current_phase, Reg. 77 and 78. T0 or T4 DPLL phase detector reporting is again controlled by Reg. 4B, Bit 4. One LSB corresponds to approximately 0.7 degrees phase difference. For the T0 DPLL this will be reporting the phase difference between the input and the internal feedback clock. The phase result is internally averaged or filtered with a -3 dB attenuation point at approximately 100 Hz. For low DPLL bandwidths, 1 mHz for example, this measured phase information from the T0 DPLL gives input phase wander in the frequency band from for example 1 mHz to 100 Hz. This could be used to give a crude input MTIE measurement up to an observation period of approximately 1000 seconds using external software. In addition, the T4 DPLL phase detector can be used to make a phase measurement between two inputs. Reg. 65, Bit 7 is used to switch one input to the T4 phase detector over to the current T0 input. The other phase detector input remains connected to the selected T4 input source, the selected source can be forced via Reg. 35, Page 28 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL Bits [3:0], or changed via the T4 priority (Reg. 18 to 1E, when Reg. 4B, Bit 4 = 1). Consequently the phase detector from the T4 DPLL could be used to measure the phase difference between the currently selected source and the stand-by source, or it could be used to measure the phase wander of all standby sources with respect to the current source by selecting each input in sequence. An MTIE and TDEV calculation could be made for each input via external processing. Configuration for Redundancy Protection When two ACS8530 devices are to be used in a redundancy-protection scheme within a Network Element (NE), one will be designated as Master, one as Slave. Table 10 How to Align the Outputs of Two ACS8530s Action Result If possible, one device (the nominated Slave) should lock to the other device (the nominated Master). With the Slave locked to the Master, their output frequencies will be guaranteed to be the same. All programmed priorities within the two devices should be the same, except for the fact that: (1) the Master output is designated the highest priority input on the Slave, (2) the Slave output is designated zero priority (disabled) on the Master (Reg. 18 to 1E). These two actions ensure that if the Master device fails, the Slave device will switch to lock to the same source that the Master was locked to before it failed. It is expected that an NE will use the T0 output for its internal operations. The phase of the outputs from the T4 path (TO8 & TO9) will not be aligned, unless the T4 outputs are locked to the T0 outputs. In many applications, the clocks supplied into the system are required to be aligned not only in frequency, but also in phase between the Master and Slave devices. This ensures minimal disturbance when any clock sink switches between Master and Slave. In order to ensure that the outputs of the two ACS8530s are always aligned in frequency and phase, the procedures in Table 10 should be followed. In order to maintain the conditions outlined in Table 10 it is necessary for software systems to maintain monitoring and control functions. These monitoring functions should either poll the device or respond to interrupts in order to maintain the correct settings within the two devices. Please refer to the descriptions or registers mentioned in Table 10 and also Regs 34, 3B, 48, 67 and 69, for more details on these associated settings. See also Application Note AN-SETS-7. Table 11 MSTSLVB Pin Operation MSTSLVB 1= Master Any input detected as invalid in one device should be disabled within the other device (Reg. 0E/0F & 30/31). Phase Build-out should be disabled on the Slave whilst it is locked to the Master. This will ensure that the phase of the Slave is locked to the phase of the Master. It also enables the use of the Phase offset control register to compensate for delays between the Master and Slave. Revertive mode should be enabled. This will ensure that the Slave locks to the Master although it may have been locked to another source previously. The bandwidth of the Slave should be set higher than that of the Master (it is recommended to configure the slave with the highest supported bandwidth). This ensures that any transient occurring on the output of the Master is followed as closely as possible on the Slave. Revision 3.02/November 2005 © Semtech Corp. DATASHEET Page 29 Feature Setting Reason Priority of input I11 As programmed (program 0 to ensure it gets disabled) Make sure that the designated Master device cannot lock to the output of the Slave device. Phase Build-out As programmed in register If the system requires PBO, then this being enabled on the Master will give the overall system performance with PBO. The slave only needs to track the Master (no PBO). Revertive mode As programmed in register Revertive behavior of the Master in a Master/Slave system will define the overall Revertive behavior of the system. T0 DPLL bandwidth As programmed in register (automatic or manual) Device selects locked or acquisition bandwidth. www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL Table 11 MSTSLVB Pin Operation (cont...) MSTSLVB 0= Slave Feature Setting Reason Priority of input I11 1 (highest priority) When a Slave, this input is designated as that connected to the output of the Master. Phase Build-out Disabled This ensures that the Slave locks to the Master with the minimum phase offset possible. Revertive mode Enabled This ensures that the Slave always locks to the Master when it is available. T0 DPLL bandwidth Forced to the acquisition bandwidth setting A higher bandwidth on the Slave ensures closer phase tracking. For direct hardware control of Master or Slave operation the Master/Slave control pin (MSTSLVB) can be used to externally control some of these functions according to Table 11. These functions can also be controlled via software. Whilst the Master and Slave outputs could be crossconnected and connected to any input on the alternative device, input I11 has been chosen as the input controlled by the MSTSLVB pin. Alignment of Priority Tables in Master and Slave ACS8530 In a redundant system where the Slave is normally locked to the Master device, if the Master device fails the Slave device must revert to locking to the same external reference that the Master was locked to. This will ensure that minimum disturbance, both in frequency and phase, is created on the output of the Slave device due to the failure of the Master device. As stated previously (Table 10), it is recommended that the programmed priorities of the reference sources are the same in both devices, apart from the Master/Slave cross-connect inputs. Both devices can also monitor all their reference sources and determine the validity of each source. It is recommended that the availability of valid sources are also aligned between the two devices. This is achieved by writing the value, as reported by sts_sources_valid Revision 3.02/November 2005 © Semtech Corp. DATASHEET Reg. 0E & 0F), from one device into the cnfg_sts_remote_sources_valid register (Reg. 30 & 31) of the other. This will ensure that any source considered invalid by one device is also considered invalid by the other. If a failure of the Master does occur, this will ensure that the Slave will always select the reference that the Master was locked to. T4 Generation in Master and Slave ACS8530 As specified by the I.T.U., there is no need to align the phases of the T4 outputs in Master and Slave devices. For a fully redundant system, there is a need, however, to ensure that all devices select the same reference source. As there is no need to guarantee the alignment of phase of the T4 outputs, the Slave devices T4 input does not need to lock to the Masters T4 output, but only needs to ensure that it locks to the same external reference source. The actions of aligning the priority tables and available reference sources performed for the T0 outputs will be equally valid for the T4 outputs. The only difference being that the input connected to the Master's output is disabled for the T4 path (allowing it only to lock to external references). This can be easily achieved as the T4 and T0 paths have separate programmed priorities. There is no defined Holdover requirement for the T4 path. Alignment of the Output Clock Phases in Master and Slave ACS8530 When the ACS8530 is locked to a reference source of frequency f, the output clocks of frequency f will be inphase with the reference source (with Phase Build-out disabled). As all T0 output clocks from the ACS8530 are derived from the same T0 frequency, any frequency greater than f at the output will be “falling edge aligned” with the output at frequency f. Any frequency less than f will be effectively a division of f, if possible. Similarly for T4, all T4 output clocks will be phase-related to the T4 input. The effect of this relationship is that if the Master and Slave devices are cross-connected with 19.44 MHz clocks, their output clocks at 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz & 311.04 MHz will be aligned between the two devices. However, their outputs of 6.48 MHZ, 1.544 MHz, 2.048 MHz, 2 kHz and 8 kHz etc. would not necessarily be aligned. Whilst most applications would not be affected by the non-alignment of most of these clocks, the non-alignment of the 2 kHz and/or the 8 kHz may cause framing errors. Page 30 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL There are two ways to align the 2 kHz and/or 8 kHz outputs: 1. the use of the External syncing function, or 2. directly locking the Slave to 2 kHz or 8 kHz from the Master. By directly locking the Slave to the 2 kHz (MFrSync) output of the Master, all frequencies output from the Slave will be in phase alignment with the same frequency generated from the Master. If the Slave is directly locked to the 8 kHz (FrSync) output from the Master, then all frequencies except for 2 kHz MFrSync outputs will be in alignment. If using the external syncing function then the clock and sync signals need to be interconnected between the Master and Slave. This requires some configuration enhancements. The Sync signal is not locked to, it is sampled using the reference clock and used to realign the generated outputs. The generated outputs are still always locked to the reference clock and related to each other. Details on the Master and Slave interconnection wiring and software configuration can be found in refer to the application note AN-SETS-2. The following section describes the resynchronization operation of the MFrSync via the SYNC2K input. MFrSync and FrSync Alignment-SYNC2K The SYNC2K input (pin 45) is monitored by the ACS8530 for consistent phase and correct frequency and if it does not pass these quality checks, an alarm flag is raised (Reg. 08, Bit 7 and Reg. 09, Bit 7). The check for consistent phase involves checking that each input edge is within an expected timing window. The window size is set by Reg. 7C, Bits [6:4]. An internal detector senses that a correct SYNC2K signal is present and only then allows the signal to resynchronize the internal dividers that generate the 8 kHz FrSync and 2 kHz MFrSync outputs. This sequence avoids spurious resynchronizations that may otherwise occur with connections and disconnections of the SYNC2K input. The SYNC2K input will normally be a 2 kHz frequency, only its falling edge is used. It can however be at a frequencies of 4 kHz or 8 kHz without any change to the register setups. Only alignment of the 8 kHz will be achieved in this case. Safe sampling of the SYNC2K input is achieved by using the currently selected clock reference source to do the Revision 3.02/November 2005 © Semtech Corp. DATASHEET input sampling. This is based on the principle that FrSync alignment is being used on a Slave device that is locked to the clock reference of a Master device that is also providing the 2 kHz SYNC2K input. Phase Build-out mode should be off (Reg. 48, Bit 2 = 0). The 2 kHz MFrSync output from the Master device has its falling edge aligned with the falling edge of the other output clocks, hence the SYNC2K input is normally sampled on the rising edge of the current input reference clock, in order to provide the most margin. Some modification of the expected timing of the SYNC2K with respect to the reference clock can be achieved via Reg. 7B, Bits [1:0]. This allows for the SYNC2K input to arrive either half a reference clock cycle early or up to one and a half cycle late, hence allowing a safe sampling margin to be maintained. A different sampling resolution is used depending on the input reference frequency and the setting of Reg. 7B Bit 6, cnfg_sync_phase. With this bit Low, the SYNC2K input sampling has a 6.48 MHz resolution, this being the preferred reference frequency to lock to from the Master, in conjunction with the SYNC2K 2 kHz, since it gives the most timing margin on the sampling and aligns all of the higher rate OC-3 derived clocks. When Bit 6 is High the SYNC2K can have a sampling resolution of either 19.44 MHz (when the current locked to reference is 19.44 MHz) or 38.88 MHz (all other frequencies). This would allow for instance a 19.44 MHz and 2 kHz pair to be used for Slave synchronization or for Line Card synchronization. Reg. 7B Bit 7, indep_Fr/MFrSync controls whether the 2 kHz MFrSync and 8 kHz FrSync outputs keep their precise alignment with the other output clocks. When indep_FrSync/MFrSync Reg. 7B Bit 7 is Low the FrSyncs and the other higher rate clocks are not independent and their alignment on the falling 8kHz edge is maintained. This means that when bit Sync_OC-N_rates is High, the OC-N rate dividers and clocks are also synchronized by the SYNC2K input. On a change of phase position of the SYNC2K, this could result in a shift in phase of the 6.48 MHz output clock when a 19.44 MHz precision is used for the SYNC2K input. To avoid disturbing any of the output clocks and only align the MFrSync and FrSync outputs, at the chosen level of precision, then independent Frame Sync mode can be used (Reg. 7B, Bit 7 = 1). Edge alignment of the FrSync output with other clocks outputs may then change depending on the SYNC2K sampling precision used. For example, with a 19.44 MHz reference input clock and Reg. 7B, Bits 6 & 7 both High (Independent mode and Page 31 www.semtech.com ACS8530 SETS ADVANCED COMMUNICATIONS FINAL Sync OC-N rates), then the FrSync output will still align with the 19.44 MHz output but not with the 6.48 MHz output clock. The FrSync and MFrSync outputs always come from the T0 DPLL path. 2kHz and 8kHz outputs can also be produced at the TO1 to TO7 outputs. These can come from either the T0 DPLL or from the T4 DPLL, controlled by Reg. 7A, Bit 7. If required, this allows the T4 DPLL to be used as a separate PLL for the FrSync and MFrSync path with a 2 kHz input and 2 kHz and 8 kHz Frame Sync outputs. Output Clock Ports The device supports a set of main output clocks, T0 and T4, and a pair of secondary Sync outputs, FrSync and MFrSync. The two main output clocks, T0 and T4, are independent of each other and are individually selectable. The two secondary output clocks, FrSync and MFrSync, are derived from either T0 or T4. The frequencies of the main output clocks are selectable from a range of predefined spot frequencies and a variety of output technologies are supported, as defined in Table 12. PECL/LVDS/AMI Output Port Selection The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_outputs register, Reg. 3A. AMI port, TO8, supports a composite clock, consisting of a 64 kHz AMI clock with 8 kHz boundaries marked by deliberate violations of the AMI coding rules, as specified in ITU recommendation G.703[6]. Departures from the nominal pattern are detected within the ACS8530, and may cause reference-switching if too frequent. See “DC Characteristics: AMI Input/Output Port” on page 139., for more details. Output Frequency Selection and Configuration The output frequency at many of the outputs is controlled by a number of inter-dependent parameters. These parameters control the selections within the various blocks shown in Figure 11. The ACS8530 contains two main DPLL/APLL paths. Whilst they are largely independent, there are a number of ways in which these two structures can interact. Figure 11 shows an expansion of the original Block Diagram (Figure 1) for the PLL paths. Revision 3.02/November 2005 © Semtech Corp. DATASHEET T0 DPLL and APLLs The T0 DPLL always produces 77.76 MHz regardless of either the reference frequency (frequency at the input pin of the device) or the locking frequency (frequency at the input of the DPLL Phase and Frequency Detector (PFD)). The input reference is either passed directly to the PFD or via a pre-divider (not shown) to produce the reference input. The feedback 77.76 MHz is either divided or synthesized to generate the locking frequency. Digital Frequency Synthesis (DFS) is a technique for generating an output frequency using a higher frequency system clock (204.8 MHz in the case of the 77.76 MHz synthesis). However, the edges of the output clock are not ideally placed in time, since all edges of the output clock will be aligned to the active edge of the system clock. This will mean that the generated clock will inherently have jitter on it equivalent to one period of the system clock. The T0 77M forward DFS block uses DFS clocked by the 204.8 MHz system clock to synthesize the 77.76 MHz and, therefore, has an inherent 4.9 ns of p-p jitter. There is an option to use an APLL, the T0 feedback APLL, to filter out this jitter before the 77.76 MHz is used to generate the feedback locking frequency in the T0 feedback DFS block. This analog feedback option allows a lower jitter (