GS1535-CFUE3-LOS

GS1535 HD-LINX II™ Multi-Rate SDI Automatic Reclocker GS1535 Data Sheet Key Features Description • SMPTE 292M, 259M and 344M compliant • Supports data rates of 143, 177, 270, 360, 540, 1483.5, 1485 Mb/s • Supports DVB-ASI at 270Mb/s • Auto and Manual Modes for rate selection The GS1535 Multi-Rate Serial Digital Reclocker is designed to automatically recover the embedded clock signal and re-time the data from a SMPTE 292M, SMPTE 259M or SMPTE 344M compliant digital video signal. • Standards indication in Auto Mode • 4:1 input multiplexor • Lock Detect Output • On-chip Input and Output Termination • Differential inputs and outputs • Configuarble automatic Mute or Bypass when not locked • Manual Bypass function • SD/HD indication output to control GS1528 Dual Slew-Rate Cable Driver • Pb-free and Green • Single 3.3V power supply • Operating temperature range: 0°C to 70°C The device removes the high frequency jitter components from the bit-serial stream. Input termination is on-chip for seamless matching to 50Ω transmission lines. An LVPECL compliant output interfaces seamlessly to the GS1528 Cable Driver The GS1535 can operate in either auto or manual rate selection mode. In Auto mode the GS1535 automatically detects and locks onto an incoming SMPTE SDI data signal from 143 Mb/s to 1.485 Gb/s. For single rate data systems, the GS1535 can be configured to operate in manual mode. In both modes, the GS1535 requires only one external crystal to set the VCO frequency when not locked and provides adjustment free operation. In systems which require passing non-SMPTE data rates, the GS1535 will automatically or manually enter a bypass mode in order to pass the signal without reclocking. Applications • SMPTE 292M, SMPTE 259M and SMPTE 344M Serial Digital Interfaces XTAL+ XTAL- XTAL XTAL OUT+ OUT- XTAL OSC LF+ LF- The ASI/177 input pin allows for manual selection of support of either 177Mb/s or DVB-ASI inputs. KBB BUFFER RE-TIMER M U X DATA BUFFER DDO/DDO DDO_MUTE DDI 0 DDI 1 DDI 2 DDI 3 PHASE FREQUENCY DETECTOR D A T A M U X CHARGE PUMP VCO PHASE DETECTOR M U X DIVIDE BY 2,4,6,8,12,16 DIVIDE BY 152, 160, 208 BYPASS LOGIC CONTROL LOGIC DDI_SEL[1:0] SS[2:0] ASI/177 AUTO/MAN LD AUTOBYPASS BYPASS GS1535 Functional Block Diagram 18557 - 8 February 2005 1 of 22 www.gennum.com GS1535 Data Sheet Contents Key Features .................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................3 1.1 Pin Assignment ...............................................................................................3 1.2 Pin Descriptions ..............................................................................................4 2. Electrical Characteristics ...........................................................................................7 2.1 Absolute Maximum Ratings ............................................................................7 2.2 DC Electrical Characteristics ..........................................................................7 2.3 AC Electrical Characteristics ...........................................................................8 2.4 Input/Output Circuits .....................................................................................10 3. Detailed Description ................................................................................................13 3.1 Slew Rate Phase Lock Loop (S-PLL) ...........................................................13 3.2 VCO ..............................................................................................................14 3.3 Charge Pump ................................................................................................14 3.4 Frequency Acquisition Loop —The Phase-Frequency Detector ...................14 3.5 Phase Acquisition Loop — The Phase Detector ...........................................15 3.6 4:1 Input Mux ................................................................................................15 3.7 Automatic And Manual Data Rate Selection .................................................16 3.8 Bypass Mode ................................................................................................17 3.9 DVB/ASI Operation .......................................................................................17 3.10 LOCK ..........................................................................................................17 3.11 Output Drivers .............................................................................................18 3.12 Output Mute ................................................................................................18 4. Application Reference Design .................................................................................19 4.1 Typical Application Circuit .............................................................................19 5. References ..............................................................................................................20 6. Package & Ordering Information .............................................................................20 6.1 Package Dimensions ....................................................................................20 6.2 Packaging Data .............................................................................................21 6.3 Ordering Information .....................................................................................21 7. Revision History ......................................................................................................22 18557 - 8 February 2005 2 of 22 GS1535 Data Sheet 1. Pin Out GND LF- LF+ VCC_CP VEE_CP RSVD RSVD VCC RSVD VCC GND XTAL- XTAL+ XTAL_OUT- XTAL_OUT+ GND 1.1 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DDI0 1 48 VEE_DDO DDI0_VTT 2 47 VCC_DDO DDI0 3 46 DDO GND 4 45 DDO_VTT DDI1 5 44 DDO DDI1_VTT 6 43 GND DDI1 7 42 VEE_INT GND 8 41 VCC_INT DDI2 9 40 RSVD GS1535 64 PIN LQFP TOP VIEW DDI2_VTT 10 39 RSVD DDI2 11 38 RSVD GND 12 37 GND P 17 18 19 20 21 18557 - 8 22 23 24 25 26 27 28 29 30 31 32 GND SD/HD VEE_DIG 33 VCC_DIG 16 RSVD GND LD KBB ASI/177 34 SS2 15 SS1 DDI3 SS0 GND VEE_VCO 35 VCC_VCO 14 AUTO/MAN DDI3_VTT AUTOBYPASS DDO_MUTE BYPASS 36 DDI_SEL1 13 DDI_SEL0 DDI3 February 2005 3 of 22 GS1535 Data Sheet 1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number Name Type Description 1, 3 DDI0, DDI0 INPUT Serial digital differential input 0. 2 DDI0_VTT PASSIVE 5, 7 DDI1,DDI1 INPUT 6 DDI1_VTT PASSIVE 9, 11 DDI2, DDI2 INPUT 10 DDI2_VTT PASSIVE 13, 15 DDI3, DDI3 INPUT 14 DDI3_VTT PASSIVE 17, 18 DDI_SEL[1:0] LOGIC INPUT Center tap of two 50Ω on-chip termination resistors between DDI0 and DDI0. Serial digital differential input 1. Center tap of two 50Ω on-chip termination resistors between DDI1 and DDI1. Serial digital differential input 2. Center tap of two 50Ω on-chip termination resistors between DDI2 and DDI2. Serial digital differential input 3 . Center tap of two 50Ω on-chip termination resistors between DDI3 and DDI3. Serial digital input select. DDI_SEL1 DDI_SEL0 INPUT SELECTED 0 0 DDI0 0 1 DDI1 1 0 DDI2 1 1 DDI3 19 BYPASS LOGIC INPUT Bypasses the reclocker stage (Active HIGH). When BYPASS is HIGH, it overwrites the AUTOBYPASS setting. 20 AUTOBYPASS LOGIC INPUT Automatically bypasses the reclocker stage when the PLL is not locked (Active HIGH). 21 AUTO/MAN LOGIC INPUT 18557 - 8 When active, the standard is automatically detected from the input data rate. February 2005 4 of 22 GS1535 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number Name Type Description 24, 25, 26 SS[2:0] BIDIRECTIONAL When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to which the PLL has locked. When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a selected data rate. SS2 SS1 SS0 DATA RATE SELECTED/FORCED (Mb/s) 0 0 0 143 0 0 1 177 0 1 0 270 0 1 1 360 1 0 0 540 1 0 1 1483.5/1485 27 ASI/177 LOGIC INPUT 28 LD OUTPUT 29 RSVD RESERVED 33 SD/HD OUTPUT This signal is LOW when the reclocker has locked to 1.485Gbps or 1.485/1.001Gbps, and HIGH when the reclocker has locked to 143Mbps, 177Mbps, 270Mbps, 360Mbps, or 540Mbps. 34 KBB ANALOG INPUT Controls the loop bandwidth of the PLL. Leave this pin floating for serial reclocking applications. 36 DDO_MUTE LOGIC INPUT 44, 46 DDO, DDO OUTPUT Differential Serial Digital Outputs. 45 DDO_VTT PASSIVE Center tap of two 50Ω on-chip termination resistors between DDO and DDO.. 50, 51 XTAL_OUT+, XTAL_OUT- OUTPUT Differential buffered outputs of the reference oscillator. 52, 53 XTAL+, XTAL- INPUT 62, 63 LF+, LF- PASSIVE Loop filter capacitor connection. (CLF = 47nF). 4, 8, 12,16, 32, 35, 37, 43, 49, 54, 64 GND PASSIVE Recommended connect to GND. 43 GND_DRV PASSIVE Recommended connect to GND. 18557 - 8 Disables 177Mbps data rate in the AUTO data rate detection circuit. This prevents a FALSE LOCK to 177Mbps when using DVB/ASI. LOCK DETECT. HIGH when the PLL is locked. DO NOT CONNECT. Mutes the DDO/DDO outputs, when not in bypass mode. Reference crystal input. Connect to the GO1535. February 2005 5 of 22 GS1535 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number Name Type 55, 57 VCC PASSIVE Recommend connect to 3.3V. 22 VCC_VCO POWER Most positive power supply connection for the internal VCO section. Connect to 3.3V. 30 VCC_DIG POWER Most positive power supply connection for the internal glue logic. Connect to 3.3V. 41 VCC_INT POWER Most positive power supply connection. Connect to 3.3V. 47 VCC_DDO POWER Most positive power supply connection for the DDO/DDO output driver. Connect to 3.3V. 61 VCC_CP POWER Most positive power supply connection for the internal charge pump. Connect to 3.3V. 23 VEE_VCO POWER Most negative power supply connection for the internal VCO section. Connect to ground. 31 VEE_DIG POWER Most negative power supply connection for the internal glue logic. Connect to ground. 42 VEE_INT POWER Most negative power supply connection. Connect to ground. 48 VEE_DDO POWER Most negative power supply connection for the DDO/DDO output driver. Connect to ground. 60 VEE_CP POWER Most negative power supply connection for the internal charge pump. Connect to ground. 38, 39, 40, 56, 58, 59 RSVD RESERVED 18557 - 8 Description Do not Connect. February 2005 6 of 22 GS1535 Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Value Supply Voltage +3.6 VDC Input ESD Voltage 500V Storage Temperature Range -50°C< Ts < 125°C Inputs VCC + 0.5V 2.2 DC Electrical Characteristics Table 2-2: DC Electrical Characteristics Vcc = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Conditions Symbol Min Typ Max Units Test Levels Supply Voltage Operating Range VCC 3.135 3.3 3.465 V 3 Power Consumption TA=25°C 408 600 849 mW 5 Supply Current TA=25°C ICC 130 182 245 mA 1 Logic Inputs High VIH 2.0 - - V 3 Low VIL - - 0.8 V 3 250µA Load VOH 3.2 - - V 3 VOL - - 0.6 V 3 DDI_SEL[1:0], BYPASS, AUTOBYPASS, AUTO/MAN, ASI/177, SDO_MUTE Logic Outputs SD/HD and LD Bi-Directional Pins High VIH 2.0 - - V 3 SS[2:0], AUTO/MAN = 0 (Manual Mode) Low VIL - - 0.8 V 3 Bi-Directional Pins High VOH 2.6 - V 1 SS[2:0], AUTO/MAN = 1 (AUTO Mode) Low VOL - - V 1 18557 - 8 February 2005 0.6 7 of 22 GS1535 Data Sheet Table 2-2: DC Electrical Characteristics Vcc = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Conditions Symbol Min Typ Max Units Test Levels XTAL_OUT+, XTAL_OUT- High VOH - VCC - V 7 Low VOL - VCC - 0.285 - V 7 Serial Input Voltage Common mode 1.65 + (VSID/2) - VCC - (VSID/2) V 1 Output Voltage Common mode - VCC - VOD/2 - V 1 SDO, SDO Test Levels 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. 2.3 AC Electrical Characteristics Table 2-3: AC Electrical Characteristics Vcc = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Test Levels 143 - 1485 Mb/s 3 0.8 - - UI 1 - 5 10 ms 6,7 SD/HD=0 0.29 - - µs 6,7 SD/HD=1 0.16 - - µs 6,7 - 114 - ps 6,7 - 106 - ps Serial Input Data Rate Serial Input Jitter Tolerance Worst case modulation Eg. Square wave modulation 143, 270, 360, 1485 Mb/s PLL Lock Time Asynchronous t ALOCK PLL Lock Time - Synchronous t SLOCK Serial Output Rise/Fall Time (20% - 80%) trSDO CLF=47nF 50Ω load (on chip) tfSDO Serial Input - Signal Swing VSID 50Ω load (on chip) 100 - 800 mVp-p Serial Output - Signal Swing VOD Differential (across 100Ω). 1400 - 2000 mVp-p 18557 - 8 February 2005 6,7 8 of 22 GS1535 Data Sheet Table 2-3: AC Electrical Characteristics Vcc = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Symbol Conditions Serial Output Jitter tIJ KBB=Float, (additive) Loop Bandwidth Min Typ Max Units Test Levels 143Mb/s - 0.02 - UI 1 177Mbs - 0.02 - UI 1 270Mb/s - 0.02 0.09 UI 1 360Mbs - 0.03 - UI 1 540Mbs - 0.03 0.09 UI 1 1485Mb/s - 0.06 0.13 UI 1 BYPASS - 0.06 0.13 UI 1 - 1.5 - MHz 6,7 - 3.5 - MHz 6,7 270 Mb/s KBB = FLOAT - 520 - KHz 6,7 270 Mb/s KBB = GND - 1000 - KHz 6,7 PRN, BWLOOP 223 -1 1.485 Gb/s KBB = FLOAT 1.485 Gb/s KBB = GND 0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra phase correction signals will be generated which instructs the charge pump to create larger frequency corrections for the VCO. i-PHASE ALIGNMENT EDGE DATA RE-TIMING EDGE I-clk q-clk q-PHASE ALIGNMENT EDGE INPUT DATA WITH JITTER 0.25UI 0.8UI RE-TIMED OUTPUT DATA Figure 3-2: Phase Detector Characteristics. When the PA loop is active, the crystal frequency and the incomming data rate are compared. If the resultant is more that 2%, the PLL is considered to be unlocked and the system jumps to the FA loop. 3.6 4:1 Input Mux The 4:1 input mux allows the connection of four independent streams of video/data. These are differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be selected via the DDI_SEL[1:0] pins. Table 3-1 shows the input selected for a given state at DDI_SEL[1:0]. Table 3-1: Bit Pattern for Input Select 18557 - 8 DDI_SEL1:0] Selected Input 00 DDI0 01 DDI1 10 DDI2 11 DDI3 February 2005 15 of 22 GS1535 Data Sheet The DDI inputs are designed to be DC interfaced with the output of the GS1524 Cable Equalizer. There are on chip 50Ω termination resistors which come to a common point at the DDI_VT pins. Connect a 10nF capacitor to this pin and connect the other end of the capacitor to ground. This end-terminates the transmission line at the inputs for optimum performance. If only one input pair is used, connect the unused positive inputs to +3.3V and leave the unused negative inputs floating. This helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 3.7 Automatic And Manual Data Rate Selection The GS1535 can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. The AUTO_MAN pin selects Automatic data rate detection mode (AUTO mode) when HIGH and manual data rate selection mode (MANUAL mode) when LOW. In AUTO mode, the SS[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the PLL is locked to (or previously locked to). The "search algorithm" cycles through the data rates (see Figure 3-3) and starts over if that data rate is not found. POWER-UP 143 Mb\s 177 Mb\s 270Mb\s 360 Mb\s 1.485Mb\s 540 Mb\s Figure 3-3: Data Rate Search Pattern NOTE: When the device is in AUTO mode, the SD/HD output will toggle when the reclocker is not locked, (LD=LOW). The logic level of SD/HD will depend on the current state of the search algorithm. If the device is also in bypass mode, and the SD/HD signal is used to set the slew rate of the GS1528 Cable Driver, that slew rate will change dynamically when the reclocker is not locked. In MANUAL mode, the SS[2:0] pins become inputs and the data rate can be programmed. In this mode, the search algorithm is disabled and the GS1535's PLL will only lock to this data rate. Table 3-2 shows the bit pattern at SS[2:0] for the data rate selected (in MANUAL mode) or the data rate that the PLL has locked to (in AUTO mode). 18557 - 8 February 2005 16 of 22 GS1535 Data Sheet Table 3-2: Data Rate Indication/Selection Bit Pattern SS[2:0] Data Rate (Mb/s) 000 143 001 177 010 270 011 360 100 540 101 1485/1483.5 3.8 Bypass Mode In bypass mode, the GS1535 passes the data at the inputs, directly to the outputs. There are two pins that control the bypass function: BYPASS and AUTOBYPASS. The BYPASS pin is an active high signal which forces the GS1535 into bypass mode for as long as a HIGH is asserted at this pin. The AUTOBYPASS pin is an active high signal which places the GS1535 into bypass mode only when the PLL has not locked to a data rate. Note that if BYPASS is HIGH, this will overwrite the AUTOBYPASS functionallity. When the GS1535’s PLL is not locked and BYPASS = LOW and AUTOBYPASS = LOW, the serial digital output DDO/DDO will produce invalid data. 3.9 DVB/ASI Operation The GS1535 is designed to re-clock DVB/ASI at 270 Mb/s. There is a harmonic present in idle patterns (K28.5) which is very close the 177 Mb/s data rate (EIC 1179). The ASI/177 pin, when HIGH will disable the 177 Mb/s search in AUTO mode. In this mode, the GS1535 will not lock to 177 Mb/s. 3.10 LOCK The LOCK DETECT signal, LD, is an active high output which indicates when the PLL is locked. The lock logic with the GS1535 includes a system which monitors the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a monitor to detect harmonic lock. 18557 - 8 February 2005 17 of 22 GS1535 Data Sheet 3.11 Output Drivers The GS1535’s serial digital data outputs (DDO/DDO) have a nominal voltage of 800mv single ended or 1600mV differential when terminated into 50Ω. The DDO_VTT pin is the common point of two 50Ω termination resistors from the DDO and DDO. This pin can be left open if the termination exists on the receiving device. 3.12 Output Mute The DDO_MUTE pin is provided to allow muting of the retimed output. When the GS1535’s PLL is locked and the device is reclocking, setting DDO_MUTE = LOW will force the serial digital outputs DDO/DDO to mute. However, if the GS1535 is in bypass mode, (AUTOBYPASS = HIGH and/or BYPASS = HIGH), DDO_MUTE will have no effect on the output. 18557 - 8 February 2005 18 of 22 GS1535 Data Sheet 4. Application Reference Design 4.1 Typical Application Circuit GO1535 (14.140MHz) 47n 3.3V 3.3V 56 10n 3 49 50 GND XTAL_OUT+ 52 51 XTAL+ 54 53 XTAL- 55 VCC GND 56 VCC RSVD 57 58 RSVD RSVD 61 60 59 VEE_CP VCC_CP 5 DDI1 DDO 6 DDI1_VT GND 7 DDI1 8 GND 9 DDI2 GND 3.3V 46 45 44 65 Zo = 50 D ATA O U T P U T 10n 43 42 1 0n 3.3V 41 DDI3 DDO_MUTE 39 38 GND DDI3_VT 37 36 SDO_MUTE 35 34 DDI3 KBB GND VEE_DIG SD/HD 10n 3.3V DDI_SEL0 DDI_SEL1 33 32 31 RSVD VCC_DIG 30 29 LD 28 SS2 ASI/177 27 SS1 10n 26 25 SS0 VEE_VC0 24 17 SD/HD VCC_VCO GND DDI_SEL0 16 GND 23 15 RSVD 22 10n RSVD DDI2 AUTO/MAN 14 1 0n 47 40 DDI2_VT AUTOBYPASS 13 VCC_INT 48 RSVD 21 12 GS1535 20 10n VEE_INT BYPASS 10 Zo = 50 62 DDO_VTT 11 D ATA I N P U T 3 63 GND 10n Zo = 50 LF- DDO 19 D ATA I N P U T 2 Zo = 50 VCC_DDO DDI0 4 D ATA I N P U T 1 VEE_DDO DDI0_VT DDI_SEL1 Zo = 50 DDI0 18 D ATA I N P U T 0 2 XTAL_OUT- 1 LF+ GND 64 10n 3.3V ASI_177 LD Note: All resistors in ohms and all capacitors in Farads. Figure 4-1: Typical Application Circuit 18557 - 8 February 2005 19 of 22 GS1535 Data Sheet 5. References Compliant with SMPTE 292M, SMPTE 259M and SMPTE344M. 6. Package & Ordering Information 6.1 Package Dimensions Table X 0 0 0 0 NOTE: Diagram shown is representative only. Table X is fixed for all pin sizes, and Table Y is specific to the 64-pin package. Table Y SYMBOL 64L M I L L I M E TE R b MIN NOM MAX 0.17 0.20 0.27 INCH MIN NOM M AX 0.007 0.008 0.011 e 0.50 BSC D2 7.50 0.295 E2 7.50 0.295 0.020 BSC TOLERANCES OF FORM AND POSITION 18557 - 8 February 2005 aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 20 of 22 GS1535 Data Sheet 6.2 Packaging Data Parameter Value Package Type 10mm x 10mm 64-pin LQFP Package Drawing Reference JEDEC MS026 Moisture Saturation Level 3 Junction to Case Thermal Resistance, θj-c 14.9°C/W Junction to Air Thermal Resistance, θj-a (at zero airflow) 45.4°C/W Psi 0.9°C/W Pb-free and Green Yes 6.3 Ordering Information Part Number Package Temperature Range Pb-Free And Green GS1535-CFU 64 pin LQFP 0°C to 70°C No GS1535-CFUE3 64 pin LQFP 0°C to 70°C Yes 18557 - 8 February 2005 21 of 22 GS1535 Data Sheet 7. Revision History Version ECR Date Changes and / or Modifications 7 134667 November 2004 Corrected TAC pinout for pins 50, 51. Added packaging data section. Updated pins 62 and 63 on the typical application circuit. Converted to new document template. 8 135363 January 2005 Corrected block diagram and pin description table to reflect mute functionality of the device. CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 2002 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 18557 - 8 February 2005 22 of 22 22