GS9062_07

GS9062 HD-LINX® II SD-SDI and DVB-ASI Serializer with ClockCleaner™ GS9062 Data Sheet Key Features • • • • SMPTE 259M-C compliant scrambling and NRZ → NRZI encoding (with bypass) DVB-ASI sync word insertion and 8b/10b encoding adjustable loop bandwidth user selectable additional processing features including: • • • • • • • • • • • • ANC data checksum, and line number calculation and insertion TRS and EDH packet generation and insertion illegal code remapping Description The GS9062 is a dual-standard serializer with an integrated cable driver. When used in conjunction with the GO1555/GO1525* Voltage Controlled Oscillator, a transmit solution can be realized for SD-SDI and DVB-ASI applications. The device features an internal PLL, which can be configured for loop bandwidth as narrow as 100kHz. Thus the GS9062 can tolerate in excess of 300ps jitter on the input PCLK and still provide output jitter well within SMPTE specification. Connect the output clocks from Gennum’s GS4911 clock generator directly to the GS9062’s PCLK input and configure the GS9062’s loop bandwidth accordingly. In addition to serializing the input, the GS9062 performs NRZ-to-NRZI encoding and scrambling as per SMPTE 259M-C when operating in SMPTE mode. When operating in DVB-ASI mode, the device will insert K28.5 sync characters and 8b/10b encode the data prior to serialization. Parallel data inputs are provided for 10-bit multiplexed or 20-bit demultiplexed formats. An appropriate parallel clock input signal is also required. The integrated cable driver features an output mute on loss of parallel clock, high impedance mode and adjustable signal swing. The GS9062 also includes a range of data processing functions including automatic standards detection and EDH support. The device can also insert TRS signals, re-map illegal code words and insert SMPTE 352M payload identifier packets. All processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming. The GS9062 is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS compliant). *For new designs use GO1555 internal flywheel for noise immune TRS generation 20-bit / 10-bit CMOS parallel input data bus 27MHz / 13.5MHz parallel digital input automatic standards detection and indication Pb-free and RoHS compliant 1.8V core power supply and 3.3V charge pump power supply 3.3V digital I/O supply JTAG test interface small footprint compatible with GS1560A, GS1561, GS1532, and GS9060 Applications • • SMPTE 259M-C Serial Digital Interfaces DVB-ASI Serial Digital Interfaces 22209 - 7 February 2007 1 of 46 www.gennum.com GS9062 Data Sheet Functional Block Diagram IOPROC_EN/DIS SMPTE_BYPASS DETECT_TRS VCO_GND dvb-asi bypass DIN[19:0] I/O Buffer & demux 20bit/10bit JTAG/HOST CS_TMS SCLK_TCK VCO_VCC LB_CONT DVB_ASI LOCKED CP_CAP HOST Interface / JTAG test GS9062 Functional Block Diagram 22209 - 7 BLANK SDIN_TDI PCLK VCO VCO LF TRS insertion, data blank, codere-map and flywheel H Reset V RESET_TRST F Phase detector, charge pump, VCO control & power supply ClockCleaner™ SDO_EN/DIS DVB-ASI sync word insert & 8b/10b encode SMPTE 352M generation EDH generation & SMPTE scramble SDO P -> S SDO RSET SDOUT_TDO February 2007 2 of 46 GS9062 Data Sheet Contents Key Features .................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 Functional Block Diagram .............................................................................................2 1. Pin Out .....................................................................................................................5 1.1 Pin Assignment ...............................................................................................5 1.2 Pin Descriptions ..............................................................................................6 2. Electrical Characteristics ........................................................................................12 2.1 Absolute Maximum Ratings ..........................................................................12 2.2 DC Electrical Characteristics ........................................................................12 2.3 AC Electrical Characteristics.........................................................................13 2.4 Solder Reflow Profiles...................................................................................15 2.5 Input/Output Circuits .....................................................................................16 2.6 Host Interface Maps......................................................................................18 2.6.1 Host Interface Map (Read only registers) ...........................................19 2.6.2 Host Interface Map (R/W configurable registers)................................20 3. Detailed Description ...............................................................................................21 3.1 Functional Overview .....................................................................................21 3.2 Parallel Data Inputs.......................................................................................21 3.2.1 Parallel Input in SMPTE Mode............................................................22 3.2.2 Parallel Input in DVB-ASI Mode..........................................................22 3.2.3 Parallel Input in Data-Through Mode ..................................................22 3.2.4 Parallel Input Clock (PCLK) ................................................................23 3.3 SMPTE Mode................................................................................................23 3.3.1 Internal Flywheel.................................................................................23 3.3.2 HVF Timing Signal Extraction .............................................................24 3.4 DVB-ASI Mode..............................................................................................25 3.4.1 Control Signal Inputs ..........................................................................25 3.5 Data-Through Mode ......................................................................................26 3.6 Additional Processing Functions...................................................................26 3.6.1 Input Data Blank .................................................................................26 3.6.2 Automatic Video Standard Detection..................................................26 3.6.3 Packet Generation and Insertion ........................................................28 3.7 Parallel-To-Serial Conversion .......................................................................34 3.8 Serial Digital Data PLL..................................................................................35 3.8.1 External VCO......................................................................................35 3.8.2 Lock Detect Output .............................................................................35 3.8.3 Loop Bandwidth Adjustment ...............................................................36 3.9 Serial Digital Output ......................................................................................36 3.9.1 Output Swing ......................................................................................37 22209 - 7 February 2007 3 of 46 GS9062 Data Sheet 3.9.2 Serial Digital Output Mute...................................................................37 3.10 GSPI Host Interface ....................................................................................37 3.10.1 Command Word Description.............................................................38 3.10.2 Data Read and Write Timing ............................................................39 3.10.3 Configuration and Status Registers ..................................................39 3.11 JTAG...........................................................................................................40 3.12 Device Power Up ........................................................................................41 3.13 Device Reset...............................................................................................41 4. Application Reference Design ................................................................................42 4.1 Typical Application Circuit .............................................................................42 5. References & Relevant Standards.........................................................................43 6. Package & Ordering Information............................................................................44 6.1 Package Dimensions ....................................................................................44 6.2 Packaging Data.............................................................................................45 6.3 Ordering Information .....................................................................................45 7. Revision History .....................................................................................................46 22209 - 7 February 2007 4 of 46 GS9062 Data Sheet 1. Pin Out 1.1 Pin Assignment IO_GND IO_GND IO_VDD DIN16 DIN14 DIN13 DIN15 DIN12 IO_VDD 41 40 39 38 37 36 35 DIN11 DIN17 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 43 DIN2 42 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 IO_VDD DIN18 DIN19 CORE_VDD NC NC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO_GND DIN1 DIN0 CORE_VDD H V F CORE_GND BLANK NC DETECT_TRS CORE_GND PCLK NC NC 9062 34 33 32 31 30 29 28 27 26 25 24 23 22 21 SCLK_TCK SDIN_TDI SDOUT_TDO CS_TMS JTAG/HOST RESET_TRST SDO SDO CD_GND SDO_EN/DIS LOCKED VCO VCO VCO_GND VCO_VCC LF CP_CAP LB_CONT CP_GND NC NC NC NC NC NC NC NC SMPTE_BYPASS PD_GND 20bit/10bit DVB_ASI 22209 - 7 February 2007 IOPROC_EN/DIS CD_VDD NC RSV NC CP_VDD PD_VDD RSET 5 of 46 GS9062 Data Sheet 1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number 1 2 3 4, 6 – 8, 10 – 11, 14 – 17, 31, 70 – 71 5 9 RSV DVB_ASI – Non Synchronous – Input Reserved – connect to analog ground. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH in conjunction with SMPTE_BYPASS = LOW, the device will be configured to operate in DVB-ASI mode. When set LOW, the device will not support the encoding of received DVB-ASI data. 12 20bit/10bit Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select the input data bus width in SMPTE or Data-Through modes. This signal is ignored in DVB-ASI mode. When set HIGH, the parallel input will be 20-bit demultiplexed data. When set LOW, the parallel input will be 10-bit multiplexed data. 13 IOPROC_EN/DIS Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable I/O processing features. When set HIGH, the following I/O processing features of the device are enabled: • EDH Packet Generation and Insertion • SMPTE 352M Packet Generation and Insertion • ANC Data Checksum Calculation and Insertion • TRS Generation and Insertion • Illegal Code Remapping To enable a subset of these features, keep IOPROC_EN/DIS HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accessible via the host interface. When set LOW, the I/O processing features of the device are disabled, regardless of whether the features are enabled in the IOPROC_DISABLE register. Name CP_VDD PD_GND PD_VDD NC Timing – – – – Type Power Power Power – Description Power supply connection for the charge pump. Connect to +3.3V DC analog. Ground connection for the phase detector. Connect to analog GND. Power supply connection for the phase detector. Connect to +1.8V DC analog. No connect. 22209 - 7 February 2007 6 of 46 GS9062 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 18 Name SMPTE_BYPASS Timing Non Synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH in conjunction with DVB_ASI = LOW, the device will be configured to operate in SMPTE mode. All I/O processing features may be enabled in this mode. When set LOW, the device will not support the scrambling or encoding of received SMPTE data. No I/O processing features will be available. 19 RSET Analog Input Used to set the serial digital output signal amplitude. Connect to CD_VDD through 281Ω +/- 1% for 800mVp-p single-ended output swing. Power supply connection for the serial digital cable driver. Connect to +1.8V DC analog. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable the serial digital output stage. When set LOW, the serial digital output signals SDO and SDO are disabled and become high impedance. When set HIGH, the serial digital output signals SDO and SDO are enabled. 20 21 CD_VDD SDO_EN/DIS – Non Synchronous Power Input 22 23, 24 CD_GND SDO, SDO – Analog Power Output Ground connection for the serial digital cable driver. Connect to analog GND. Serial digital output signal operating at 270Mb/s. The slew rate of these outputs is automatically controlled to meet SMPTE 259M specifications. 25 RESET_TRST Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to reset the internal operating conditions to default settings and to reset the JTAG test sequence. Host Mode (JTAG/HOST = LOW) When asserted LOW, all functional blocks will be set to default conditions and all input and output signals become high impedance, including the serial digital outputs SDO and SDO. Must be set HIGH for normal device operation. JTAG Test Mode (JTAG/HOST = HIGH) When asserted LOW, all functional blocks will be set to default and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence resumes. 26 JTAG/HOST Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select JTAG Test Mode or Host Interface Mode. When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured for JTAG boundary scan testing. When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured as GSPI pins for normal host interface operation. 22209 - 7 February 2007 7 of 46 GS9062 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 27 Name CS_TMS Timing Synchronous with SCLK_TCK Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Chip Select / Test Mode Select Host Mode (JTAG/HOST = LOW) CS_TMS operates as the host interface chip select, CS, and is active LOW. JTAG Test Mode (JTAG/HOST = HIGH) CS_TMS operates as the JTAG test mode select, TMS, and is active HIGH. NOTE: If the host interface is not being used, tie this pin HIGH. 28 SDOUT_TDO Synchronous with SCLK_TCK Output CONTROL SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Output / Test Data Output Host Mode (JTAG/HOST = LOW) SDOUT_TDO operates as the host interface serial output, SDOUT, used to read status and configuration information from the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH) SDOUT_TDO operates as the JTAG test data output, TDO. 29 SDIN_TDI Synchronous with SCLK_TCK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data In / Test Data Input Host Mode (JTAG/HOST = LOW) SDIN_TDI operates as the host interface serial input, SDIN, used to write address and configuration information to the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH) SDIN_TDI operates as the JTAG test data input, TDI. NOTE: If the host interface is not being used, tie this pin HIGH. 30 SCLK_TCK Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Clock / Test Clock. Host Mode (JTAG/HOST = LOW) SCLK_TCK operates as the host interface burst clock, SCLK. Command and data read/write words are clocked into the device synchronously with this clock. JTAG Test Mode (JTAG/HOST = HIGH) SCLK_TCK operates as the JTAG test clock, TCK. NOTE: If the host interface is not being used, tie this pin HIGH. 32 BLANK Synchronous with PCLK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable input data blanking. When set LOW, the luma and chroma input data is set to the appropriate blanking levels. Horizontal and vertical ancillary spaces will also be set to blanking levels. When set HIGH, the luma and chroma input data pass through the device unaltered. 22209 - 7 February 2007 8 of 46 GS9062 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 33, 68 34 Name CORE_GND F Timing – Synchronous with PCLK Type Power Input Description Ground connection for the digital core logic. Connect to digital GND. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the ODD / EVEN field of the video signal when DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS signals for the entire period that the F input signal is HIGH (IOPROC_EN/DIS must also be HIGH). The F signal should be set HIGH for the entire period of field 2 and should be set LOW for all lines in field 1 and for all lines in progressive scan systems. The F signal is ignored when DETECT_TRS = HIGH. 35 V Synchronous with PCLK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the portion of the video field / frame that is used for vertical blanking when DETECT_TRS is set LOW. The device will set the V bit in all outgoing TRS signals for the entire period that the V input signal is HIGH (IOPROC_EN/DIS must also be HIGH). The V signal should be set HIGH for the entire vertical blanking period and should be set LOW for all lines outside of the vertical blanking interval. The V signal is ignored when DETECT_TRS = HIGH. 36 H Synchronous with PCLK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the portion of the video line containing active video data when DETECT_TRS is set LOW. The device will set the H bit in all outgoing TRS signals for the entire period that the H input signal is HIGH (IOPROC_EN/DIS must also be HIGH). H signal timing is configurable via the H_CONFIG bit of the IOPROC_DISABLE register, accessible via the host interface. Active Line Blanking (H_CONFIG = 0h) The H signal should be set HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words, and LOW otherwise. This is the default setting. TRS Based Blanking (H_CONFIG = 1h) The H signal should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words, and LOW otherwise. 37, 64 CORE_VDD – Power Power supply connection for the digital core logic. Connect to +1.8V DC digital. 22209 - 7 February 2007 9 of 46 GS9062 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 38, 39, 42– 48, 50 Name DIN[0:9] Timing Synchronous with PCLK Type Input Description PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DIN9 is the MSB and DIN0 is the LSB. 20-bit mode 20bit/10bit = HIGH Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW High impedance in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH 10-bit mode 20bit/10bit = LOW High impedance in all modes. 40, 49, 60 41, 53, 61 51, 52, 54– 59, 62, 63 IO_GND IO_VDD DIN[10:19] – – Synchronous with PCLK Power Power Input Ground connection for digital I/O buffers. Connect to digital GND. Power supply connection for digital I/O buffers. Connect to +3.3V DC digital. PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DIN19 is the MSB and DIN10 is the LSB. 20-bit mode 20bit/10bit = HIGH Luma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data input in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH 10-bit mode 20bit/10bit = LOW Multiplexed Luma and Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in data through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data input in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH 22209 - 7 February 2007 10 of 46 GS9062 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 67 Name DETECT_TRS Timing Non Synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select the timing mode of the device. When set HIGH, the device will lock the internal flywheel to the embedded TRS timing signals in the parallel input data. When set LOW, the device will lock the internal flywheel to the externally supplied H, V, and F input signals. 69 PCLK – Input PARALLEL DATA BUS CLOCK Signal levels are LVCMOS/LVTTL compatible. SD 20-bit mode SD 10-bit mode PCLK = 13.5MHz PCLK = 27MHz 72 LOCKED Synchronous with PCLK Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS / LVTTL compatible. The LOCKED signal will be HIGH whenever the device has correctly received and locked to SMPTE compliant data in SMPTE mode or DVB-ASI compliant data in DVB-ASI mode. It will be LOW otherwise. 73, 74 VCO, VCO Analog Input Differential inputs for the external VCO reference signal. For single ended devices such as the GO1555/GO1525*, VCO should be AC coupled to VCO_GND. *For new designs use GO1555 75 VCO_GND – Output Power Ground reference for the external voltage controlled oscillator. Connect to pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin is an output. Should be isolated from all other grounds. *For new designs use GO1555 76 VCO_VCC – Output Power Power supply for the external voltage controlled oscillator. Connect to pin 5 of the GO1555/GO1525*. This pin is an output. Should be isolated from all other power supplies. *For new designs use GO1555 77 78 79 80 LF CP_CAP LB_CONT CP_GND Analog Analog Analog – Output Input Input Power Control voltage to external voltage controlled oscillator. Nominally +1.25V DC. PLL lock time constant capacitor connection. Normally connected to VCO_GND through 2.2nF. Control voltage to set the loop bandwidth of the integrated reclocker. Ground connection for the charge pump. Connect to analog GND. 22209 - 7 February 2007 11 of 46 GS9062 Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage Core Supply Voltage I/O Input Voltage Range (any input) Ambient Operating Temperature Storage Temperature Solder Reflow Temperature ESD Protection On All Pins Value/Units -0.3V to +2.1V -0.3V to +4.6V -2.0V to + 5.25V -20°C < TA < 85°C -40°C < TSTG < 125°C 230°C 1kV 1. NOTE: See reflow solder profiles (Solder Reflow Profiles on page 15) 2. MIL STD 883 ESD protection applied to all pins on the device. 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Conditions Min Typ Max Units Test Levels Notes System Operation Temperature Range Digital Core Supply Voltage Digital I/O Supply Voltage Charge Pump Supply Voltage Phase Detector Supply Voltage Input Buffer Supply Voltage Cable Driver Supply Voltage External VCO Supply Voltage Output +1.8V Supply Current +3.3V Supply Current Total Device Power TA CORE_VDD IO_VDD CP_VDD PD_VDD BUFF_VDD CD_VDD VCO_VCC I1V8 I3V3 PD – – – – – – – – – – – 0 1.65 3.0 3.0 1.65 1.65 1.71 2.25 – – – – 1.8 3.3 3.3 1.8 1.8 1.8 2.50 – – – 70 1.95 3.6 3.6 1.95 1.95 1.89 2.75 245 45 590 °C V V V V V V V mA mA mW – 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 – 3 – 3 22209 - 7 February 2007 12 of 46 GS9062 Data Sheet Table 2-1: DC Electrical Characteristics (Continued) TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Conditions Min Typ Max Units Test Levels Notes Digital I/O Input Logic LOW Input Logic HIGH Output Logic LOW Output Logic HIGH VIL VIH VOL VOH – – 8mA 8mA – 2.1 – IO_VDD - 0.4 – – 0.2 – 0.8 – 0.4 – V V V V 1 1 1 1 – – – – Input RSET Voltage VRSET RSET=281Ω 0.54 0.6 0.66 V 1 2 Output Output Common Mode Voltage TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. VCMOUT 75Ω load, RSET=281Ω 0.8 NOTES 1. All DC and AC electrical parameters within specification. 2. Set by the value of the RSET resistor. 3. SDO outputs enabled. 1.0 1.2 V 1 – 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics TA = 0°C to 70°C, unless otherwise shown Parameter System Device Latency Symbol Conditions Min Typ Max Units Test Levels Notes SMPTE and Data-Through modes DVB-ASI mode treset – – 1 21 11 – – – – PCLK PCLK ms 6 6 7 – – 3 Reset Pulse Width 22209 - 7 February 2007 13 of 46 GS9062 Data Sheet Table 2-2: AC Electrical Characteristics (Continued) TA = 0°C to 70°C, unless otherwise shown Parameter Parallel Input Parallel Clock Frequency Parallel Clock Duty Cycle Input Data Setup Time Input Data Hold Time Symbol Conditions Min Typ Max Units Test Levels Notes fPCLK DCPCLK tSU tIH – – – – 13.5 40 2 1.5 – 50 – – 27.0 60 – – MHz % ns ns 1 1 1 1 – – 1 1 Serial Digital Output Serial Output Data Rate Serial Output Swing Serial Output Rise Time 20% ~ 80% Serial Output Fall Time 20% ~ 80% Serial Output Intrinsic Jitter Serial Output Duty Cycle Distortion DRSDO ∆VSDD trSDO – RSET = 281Ω Load = 75Ω ORL compensation using recommended circuit ORL compensation using recommended circuit Pseudorandom and pathological signal – – – 400 270 800 550 – – 1500 Mb/s mVp-p ps 1 1 1 – – – tfSDO 400 550 1500 ps 1 – tIJ DCDSDO – – 270 20 350 – ps ps 1 1 – 2 GSPI GSPI Input Clock Frequency GSPI Input Clock Duty Cycle GSPI Input Data Setup Time GSPI Input Data Hold Time GSPI Output Data Hold Time GSPI Output Data Delay Time TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. fSCLK DCSCLK – – – – – – – 40 0 1.43 2.10 – NOTES 1. With 15pF load. 2. Serial Duty Cycle Distortion is defined here to be the difference between the width of a ‘1’ bit, and the width of a ‘0’ bit. 3. See Device Power Up on page 41, Figure 3-13. – 50 – – – – 6.6 60 – – – 7.27 MHz % ns ns ns ns 1 6,7 6,7 6,7 6,7 6,7 – – – – – – 22209 - 7 February 2007 14 of 46 GS9062 Data Sheet 2.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. The recommended standard eutectic reflow profile is shown in Figure 2-1. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-2. Temperature 60-150 sec. 10-20 sec. 2 30˚C 2 20˚C 3 ˚C/sec max 1 83˚C 6˚C/sec max 1 50˚C 1 00˚C 25˚C Tim e 120 sec. max 6 min. max Figure 2-1: Standard Eutectic Solder Reflow Profile Temperature 60-150 sec. 20-40 sec. 2 60˚C 2 50˚C 3 ˚C/sec max 2 17˚C 6˚C/sec max 2 00˚C 1 50˚C 25˚C Tim e 60-180 sec. max 8 min. max Figure 2-2: Maximum Pb-free Solder Reflow Profile (Preferred) 22209 - 7 February 2007 15 of 46 GS9062 Data Sheet 2.5 Input/Output Circuits All resistors in ohms, all capacitors in farads, unless otherwise shown. SDO SDO Figure 2-3: Serial Digital Output LF CP_CAP 300 Figure 2-4: VCO Control Output & PLL Lock Time Capacitor VDD 42K 63K PCLK Figure 2-5: PCLK Input 22209 - 7 February 2007 16 of 46 GS9062 Data Sheet VCO VDD 25 1.5K 5K 25 VCO Figure 2-6: VCO Input LB_CONT 865mV 7.2K Figure 2-7: PLL Loop Bandwidth Control 22209 - 7 February 2007 17 of 46 GS9062 Data Sheet 2.6 Host Interface Maps 15 Not Used Not Used b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b3 b3 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used b11 b11 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used b10 b10 b10 b10 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 14 Not Used Not Used 13 Not Used Not Used 12 Not Used Not Used 11 Not Used Not Used 10 b10 b10 9 b9 b9 8 b8 b8 7 b7 b7 6 b6 b6 5 b5 b5 4 3 2 b2 b2 1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 REGISTER NAME LINE_352M_f2 LINE_352M_f1 FF_LINE_END_F1 FF_LINE_START_F1 FF_LINE_END_F0 FF_LINE_START_F0 AP_LINE_END_F1 AP_LINE_START_F1 AP_LINE_END_F0 AP_LINE_START_F0 RASTER_STRUCTURE4 RASTER_STRUCTURE3 RASTER_STRUCTURE2 RASTER_STRUCTURE1 VIDEO_FORMAT_B VIDEO_FORMAT_A VF4-b7 VF2-b7 VF4-b6 VF2-b6 VF4-b5 VF2-b5 VF4-b4 VF2-b4 VF4-b3 VF2-b3 VF4-b2 VF2-b2 VF4-b1 VF2-b1 VF4-b0 VF2-b0 VF3-b7 VF1-b7 VF3-b6 VF1-b6 VF3-b5 VF1-b5 VF3-b4 VF1-b4 VF3-b3 VF1-b3 VF3-b2 VF1-b2 VF3-b1 VF1-b1 VF3-b0 VF1-b0 VIDEO_STANDARD Not Used Not Used Not Used Not Used Not Used Not Used Not Used ANC-UES ANC-IDA ANC-IDH ANC-EDA ANC-EDH FF-UES Not Used Not Used VDS-b4 VDS-b3 VDS-b2 VDS-b1 VDS-b0 INT_PROG STD_LOCK FF-IDA H_CONFIG Not Used FF-IDH Not Used Not Used FF-EDA 352M_INS Not Used FF-EDH ILLEGAL_ REMAP Not Used AP-UES EDH_CRC_ INS Not Used AP-IDA Not Used AP-IDH ANC_CSUM_ Not Used INS Not Used AP-EDA Not Used Not Used AP-EDH TRS_INS EDH_FLAG IOPROC_DISABLE ADDRESS 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h 22209 - 7 February 2007 18 of 46 GS9062 Data Sheet 2.6.1 Host Interface Map (Read only registers) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REGISTER NAME RASTER_STRUCTURE4 RASTER_STRUCTURE3 RASTER_STRUCTURE2 RASTER_STRUCTURE1 b11 b11 b10 b10 b10 b10 b9 b9 b9 b9 b8 b8 b8 b8 b7 b7 b7 b7 b6 b6 b6 b6 b5 b5 b5 b5 b4 b4 b4 b4 b3 b3 b3 b3 b2 b2 b2 b2 b1 b1 b1 b1 b0 b0 b0 b0 VIDEO_STANDARD ADDRESS 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h VDS-b4 VDS-b3 VDS-b2 VDS-b1 VDS-b0 INT_PROG STD_LOCK 22209 - 7 February 2007 19 of 46 GS9062 Data Sheet 2.6.2 Host Interface Map (R/W configurable registers) 15 14 13 12 11 10 b10 b10 b9 b9 b9 b9 b9 b9 b9 b9 b8 b8 b8 b8 b8 b8 b8 b8 b7 b7 b7 b7 b7 b7 b7 b7 b6 b6 b6 b6 b6 b6 b6 b6 b5 b5 b5 b5 b5 b5 b5 b5 b4 b4 b4 b4 b4 b4 b4 b4 b3 b3 b3 b3 b3 b3 b3 b3 b2 b2 b2 b2 b2 b2 b2 b2 9 b9 b9 8 b8 b8 7 b7 b7 6 b6 b6 5 b5 b5 4 b4 b4 3 b3 b3 2 b2 b2 1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 REGISTER NAME LINE_352M_f2 LINE_352M_f1 FF_LINE_END_F1 FF_LINE_START_F1 FF_LINE_END_F0 FF_LINE_START_F0 AP_LINE_END_F1 AP_LINE_START_F1 AP_LINE_END_F0 AP_LINE_START_F0 VIDEO_FORMAT_B VIDEO_FORMAT_A VF4-b7 VF2-b7 VF4-b6 VF2-b6 VF4-b5 VF2-b5 VF4-b4 VF2-b4 VF4-b3 VF2-b3 VF4-b2 VF2-b2 VF4-b1 VF2-b1 VF4-b0 VF2-b0 VF3-b7 VF1-b7 VF3-b6 VF1-b6 VF3-b5 VF1-b5 VF3-b4 VF1-b4 VF3-b3 VF1-b3 VF3-b2 VF1-b2 VF3-b1 VF1-b1 VF3-b0 VF1-b0 EDH_FLAG ANC-UES ANC-IDA ANC-IDH ANC-EDA ANC-EDH FF-UES FF-IDA H_CONFIG FF-IDH FF-EDA 352M_INS FF-EDH ILLEGAL_ REMAP AP-UES EDH_CRC_ INS AP-IDA ANC_ CSUM_INS AP-IDH AP-EDA AP-EDH TRS_INS IOPROC_DISABLE ADDRESS 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h 22209 - 7 February 2007 20 of 46 GS9062 Data Sheet 3. Detailed Description 3.1 Functional Overview The GS9062 is a dual-standard serializer with an integrated cable driver. When used in conjunction with the external GO1555/GO1525* Voltage Controlled Oscillator, a transmit solution at 270Mb/s is realized. The device has three different modes of operation which must be set by the application layer through external device pins. When SMPTE mode is enabled, the device will accept 10-bit multiplexed or 20-bit demultiplexed SMPTE compliant data. The device’s additional processing features are also enabled in this mode. In DVB-ASI mode, the GS9062 will accept an 8-bit parallel DVB-ASI compliant transport stream on its upper input bus. The serial output data stream will be 8b/10b encoded and stuffed. The GS9062’s third mode allows for the serializing of data not conforming to SMPTE or DVB-ASI streams. The provided serial digital outputs feature a high impedance mode, output mute on loss of parallel clock and adjustable signal swing. In the digital signal processing core, several data processing functions are implemented including SMPTE 352M and EDH data packet generation and insertion, and automatic video standards detection. These features are all enabled by default, but may be individually disabled via internal registers accessible through the GSPI host interface. Finally, the GS9062 contains a JTAG interface for boundary scan test implementations. *For new designs use GO1555 3.2 Parallel Data Inputs Data inputs enter the device on the rising edge of PCLK as shown in Figure 3-1. The input data format is defined by the setting of the external SMPTE_BYPASS and DVB_ASI pins and may be presented in 10-bit or 20-bit format. The input data bus width is controlled independently from the internal data bus width by the 20bit/10bit input pin. 22209 - 7 February 2007 21 of 46 GS9062 Data Sheet PCLK DIN[19:0] DATA Control signal input tIS tIH Figure 3-1: PCLK to Data Timing 3.2.1 Parallel Input in SMPTE Mode When the device is operating in SMPTE mode, SMPTE Mode on page 23, data may be presented to the input bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. In 20-bit mode, (20bit/10bit = HIGH), the input data format should be word aligned, demultiplexed luma and chroma data. Luma words should be presented to DIN[19:10] while chroma words should occupy DIN[9:0]. In 10-bit mode, (20bit/10bit = LOW), the input data format should be word aligned, multiplexed luma and chroma data. The data should be presented to DIN[19:10]. DIN[9:0] will be high impedance in this mode. 3.2.2 Parallel Input in DVB-ASI Mode When operating in DVB-ASI mode, DVB-ASI Mode on page 25, the GS9062 automatically configures the input port for 10-bit operation regardless of the setting of the 20bit/10bit pin. The device will accept 8-bit data words on DIN[17:10] such that DIN17 = HIN is the most significant bit of the encoded transport stream data and DIN10 = AIN is the least significant bit. In addition, DIN19 and DIN18 will be configured as the DVB-ASI control signals INSSYNCIN and KIN respectively. See DVB-ASI Mode on page 25 for a description of these DVB-ASI specific input signals. DIN[9:0] will be high impedance when the GS9062 is operating in DVB-ASI mode. 3.2.3 Parallel Input in Data-Through Mode When operating in Data-Through mode, Data-Through Mode on page 26, the GS9062 passes data presented to the parallel input bus to the serial output without performing any encoding or scrambling. The input data bus width accepted by the device in this mode is controlled by the setting of the 20bit/10bit pin. 22209 - 7 February 2007 22 of 46 GS9062 Data Sheet 3.2.4 Parallel Input Clock (PCLK) The frequency of the PCLK input signal required by the GS9062 is determined by the input data format. Table 3-1 below lists the possible input signal formats and their corresponding parallel clock rates. Note that DVB-ASI input will always be in 10-bit format, regardless of the setting of the 20bit/10bit pin. Table 3-1: Parallel Data Input Format Input Data Format DOUT [19:10] DOUT [9:0] PCLK 20bit/10bit Control Signals SMPTE_BYPASS DVB_ASI SMPTE MODE 20bit DEMULTIPLEXED 10bit MULTIPLEXED LUMA LUMA / CHROMA CHROMA HIGH IMPEDANCE 13.5MHz 27MHz HIGH LOW HIGH HIGH LOW LOW DVB-ASI MODE 10bit DVB-ASI DVB-ASI DATA DVB-ASI DATA HIGH IMPEDANCE HIGH IMPEDANCE 27MHz 27MHz HIGH LOW LOW LOW HIGH HIGH DATA-THROUGH MODE 20bit DEMULTIPLEXED 10bit MULTIPLEXED DATA DATA DATA HIGH IMPEDANCE 13.5MHz 27MHz HIGH LOW LOW LOW LOW LOW 3.3 SMPTE Mode The GS9062 is said to be in SMPTE mode when the SMPTE_BYPASS pin is set HIGH and the DVB_ASI pin is set LOW. In this mode, the parallel data will be scrambled according to SMPTE 259M, and NRZ-to-NRZI encoded prior to serialization. 3.3.1 Internal Flywheel The GS9062 has an internal flywheel which is used in the generation of internal / external timing signals, and in automatic video standards detection. It is operational in SMPTE mode only. The flywheel consists of a number of counters and comparators operating at video pixel and video line rates. These counters maintain information about the total line length, active line length, total number of lines per field / frame and total active lines per field / frame for the received video standard. When DETECT_TRS is LOW, the flywheel will be locked to the externally supplied H, V, and F timing signals. 22209 - 7 February 2007 23 of 46 GS9062 Data Sheet When DETECT_TRS is HIGH, the flywheel will be locked to the embedded TRS signals in the parallel input data. Both 8-bit and 10-bit TRS code words will be identified by the device. The flywheel 'learns' the video standard by timing the horizontal and vertical reference information supplied a the H, V, and F input pins, or contained in the TRS ID words of the received video data. Full synchronization of the flywheel to the received video standard therefore requires one complete video frame. Once synchronization has been achieved, the flywheel will continue to monitor the received TRS timing or the supplied H, V, and F timing information to maintain synchronization. 3.3.2 HVF Timing Signal Extraction As discussed above, the GS9062's internal flywheel may be locked to externally provided H, V, and F signals when DETECT_TRS is set LOW by the application layer. The H signal timing should also be configured via the H_CONFIG bit of the internal IOPROC_DISABLE register as either active line based blanking or TRS based blanking, Packet Generation and Insertion on page 28. Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this mode, the H input should be HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words. This is the default H timing assumed by the device. When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H input should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the associated TRS words. The timing of these signals is shown in Figure 3-2. PCLK CHROMA DATA OUT 3FF 000 3FF 000 LUMA DATA OUT H V F H_CONFIG = HIGH 000 XYZ (eav) 000 XYZ (SAV) H SIGNAL TIMING: H_CONFIG = LOW H:V:F TIMING – 20-BIT INPUT MODE PCLK MULTIPLEXED Y/Cr/Cb DATA OUT H V F 3FF 000 000 XYZ (eav) 3FF 000 000 XYZ (sav) H:V:F TIMING – 10-BIT INPUT MODE Figure 3-2: H, V, F Timing 22209 - 7 February 2007 24 of 46 GS9062 Data Sheet 3.4 DVB-ASI Mode The GS9062 is said to be in DVB-ASI mode when the SMPTE_BYPASS pin is set LOW and the DVB_ASI pin is set HIGH. In this mode, all SMPTE processing functions are disabled, and the 8-bit transport stream data will be 8b/10b encoded prior to serialization. 3.4.1 Control Signal Inputs In DVB-ASI mode, the DIN19 and DIN18 pins will be configured as DVB-ASI control signals INSSYNCIN and KIN respectively. When INSSYNCIN is set HIGH, the device will insert K28.5 sync characters into the data stream. This function is used to assist system implementations where the GS9062 may be preceded by an external data FIFO. Parallel DVB-ASI data may be clocked into the FIFO at some rate less than 27MHz. The INSSYNCIN input may then be connected to the FIFO empty signal, thus providing a means of padding up the data transmission rate to 27MHz. See Figure 3-3. NOTE: 8b/10b encoding will take place after K28.5 sync character insertion. KIN should be set HIGH whenever the parallel data input is to be interpreted as any special character defined by the DVB-ASI standard (including the K28.5 sync character). This pin should be set LOW when the input is to be interpreted as data. NOTE: When operating in DVB-ASI mode, DIN[9:0] become high impedance. AIN ~ HIN TS 8 SDO GS9062 SDO FIFO 8 KIN WRITE_CLK 300ps pclk jitter in Description on page 1. Recommended GO1555 VCO for new designs. Updated Section 4.1 Typical Application Circuit. Added Section 3.8.3 Loop Bandwidth Adjustment. 1 2 132415 133886 – – October 2003 May 2004 3 136147 – February 2005 4 136662 – May 2005 5 6 136982 142405 – 41245 May 2005 October 2006 7 143949 42774 February 2007 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 2002 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 22209 - 7 February 2007 46 46 of 46