SC4524A
28V 2A Step-Down Switching Regulator
POWER MANAGEMENT
Features
Description
Wide input range: 3V to 28V
2A Output Current
200kHz to 2MHz Programmable Frequency
Precision 1V Feedback Voltage
Peak Current-Mode Control
Cycle-by-Cycle Current Limiting
Hiccup Overload Protection with Frequency Foldback
Soft-Start and Enable
Thermal Shutdown
Thermally Enhanced 8-pin SOIC Package
Fully RoHS and WEEE compliant
Applications
XDSL and Cable Modems
Set Top Boxes
Point of Load Applications
CPE Equipment
DSP Power Supplies
LCD and Plasma TVs
The SC4524A is a constant frequency peak current-mode
step-down switching regulator capable of producing 2A
output current from an input ranging from 3V to 28V. The
switching frequency of the SC4524A is programmable
up to 2MHz, allowing the use of small inductors and
ceramic capacitors for miniaturization, and high input/
output conversion ratio. The SC4524A is suitable for
next generation XDSL modems, high-definition TVs and
various point of load applications.
Peak current-mode PWM control employed in the
SC4524A achieves fast transient response with simple loop
compensation. Cycle-by-cycle current limiting and hiccup
overload protection reduces power dissipation during
output overload. Soft-start function reduces input startup current and prevents the output from overshooting
during power-up.
The SC4524A is available in SOIC-8 EDP package.
SS270 REV 4
Typical Application Circuit
Efficiency
IN
90
D1
10V – 28V
C4
2.2mF
BST
IN
SW
8.2mH
SC4524A
SS/EN
85
1N4148
C1
0.1mF
L1
80
OUT
R4
42.2k
5V/2A
FB
COMP
C7
10nF
C8
10pF
ROSC
R7
28.0k
GND
R5
18.2k
D2
20BQ030
R6
10.5k
C2
22mF
Efficiency (%)
V
75
VIN = 12V
VIN = 24V
70
65
60
55
50
45
C5
2.2nF
40
L1: Coiltronics DR73-8R2
C2: Murata GRM31CR60J226K
C4: Murata GRM31CR71H225K
0
0.5
1
1.5
2
Load Current (A)
Figure 1. 1MHz 10V-28V to 5V/2A Step-down Converter
June 26, 2008
Fig.1 Efficiency of the 1MHz 10V-28V to 5V/2A Step-Do
SC4524A
Pin Configuration
Ordering Information
SW
1
8
BST
IN
2
7
FB
ROSC
3
6
COMP
GND
4
5
SS/EN
9
Device
Package
SC4524ASETRT(1)(2)
SOIC-8 EDP
SC4524AEVB
Evaluation Board
Notes:
(1) Available in tape and reel only. A reel contains 2,500 devices.
(2) Available in lead-free package only. Device is fully WEEE and RoHS
compliant.
(8 - Pin SOIC - EDP)
Marking Information
yyww=Date code (Example: 0752)
xxxxx=Semtech Lot No. (Example: E9010)
SC4524A
Absolute Maximum Ratings
Thermal Information
VIN Supply Voltage ……………………………… -0.3 to 32V
Junction to Ambient (1) ……………………………… 36°C/W
BST Voltage ……………………………………………… 42V
Junction to Case (1) …………………………………
BST Voltage above SW …………………………………… 36V
Maximum Junction Temperature……………………… 150°C
5.5°C/W
Storage Temperature ………………………… -65 to +150°C
SS Voltage ……………………………………………-0.3 to 3V
FB Voltage …………………………………………… -0.3 to VIN
SW Voltage ………………………………………… -0.6 to VIN
Lead Temperature (Soldering) 10 sec ………………… 300°C
Recommended Operating Conditions
SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V
Input Voltage Range ……………………………… 3V to 28V
Peak IR Reflow Temperature ………………………….
Maximum Output Current ……………………………… 2A
260°C
ESD Protection Level ………………………………… 2000V
(2)
Operating Ambient Temperature …………… -40 to +105°C
Operating Junction Temperature …………… -40 to +125°C
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not recommended.
NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
(2) Tested according to JEDEC standard JESD22-A114-B.
Electrical Characteristics
Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TJ < 125°C, ROSC = 12.1kΩ.
Parameter
Conditions
Min
Typ
Max
Units
28
V
2.95
V
Input Supply
Input Voltage Range
VIN Start Voltage
3
VIN Rising
2.70
VIN Start Hysteresis
VIN Quiescent Current
VIN Quiescent Current in Shutdown
2.82
225
mV
VCOMP = 0 (Not Switching)
2
2.6
mA
VSS/EN = 0, VIN = 12V
40
50
µA
1.000
1.020
V
Error Amplifier
Feedback Voltage
Feedback Voltage Line Regulation
FB Pin Input Bias Current
0.980
VIN = 3V to 28V
0.005
VFB = 1V, VCOMP = 0.8V
-170
%/V
-340
nA
Error Amplifier Transconductance
280
µΩ-1
Error Amplifier Open-loop Gain
60
dB
COMP Pin to Switch Current Gain
8
A/V
VFB = 0.9V
2.4
V
COMP Source Current
VFB = 0.8V, VCOMP = 0.8V
17
COMP Sink Current
VFB = 1.2V, VCOMP = 0.8V
25
COMP Maximum Voltage
µA
Internal Power Switch
Switch Current Limit
Switch Saturation Voltage
(Note 1)
ISW = -2.6A
2.6
3.3
4.3
A
250
400
mV
SC4524A
Electrical Characteristics (Cont.)
Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TJ < 125°C, ROSC = 12.1kΩ.
Parameter
Conditions
Min
Typ
Max
Units
Minimum Switch On-time
135
ns
Minimum Switch Off-time
100
ns
Switch Leakage Current
10
µA
Minimum Bootstrap Voltage
ISW = -2.6A
1.8
2.3
V
BST Pin Current
ISW = -2.6A
60
95
mA
Oscillator
Switching Frequency
Foldback Frequency
ROSC = 12.1kΩ
1.04
1.3
1.56
MHz
ROSC = 93.1kΩ
230
300
370
kHz
ROSC = 12.1kΩ, VFB = 0
110
230
350
ROSC = 93.1kΩ, VFB = 0
50
100
170
0.2
0.3
0.4
V
1.0
1.13
1.3
V
kHz
Soft Start and Overload Protection
SS/EN Shutdown Threshold
SS/EN Switching Threshold
Soft-start Charging Current
VFB = 0 V
VSS/EN = 0 V
VSS/EN = 1.5 V
1.7
1.2
Soft-start Discharging Current
2.0
2.8
µA
1.5
µA
Hiccup Arming SS/EN Voltage
VSS/EN Rising
2.15
V
Hiccup SS/EN Overload Threshold
VSS/EN Falling
1.9
V
Hiccup Retry SS/EN Voltage
VSS/EN Falling
0.6
1.0
1.2
V
Over Temperature Protection
Thermal Shutdown Temperature
165
°C
Thermal Shutdown Hysteresis
10
°C
Note 1: Switch current limit does not vary with duty cycle.
SC4524A
Pin Descriptions
SO-8
Pin Name
Pin Function
1
SW
Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the
bootstrap capacitor.
2
IN
Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane.
3
ROSC
An external resistor from this pin to ground sets the oscillator frequency.
4
GND
Ground pin
5
SS/EN
Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup
functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off
the regulator to low current state.
6
COMP
The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator.
7
FB
The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to
improve short-circuit robustness (see Applications Information for details).
8
BST
Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive
voltage higher than VIN in order to fully enhance the internal NPN power transistor.
9
Exposed Pad
The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the
PC board.
SC4524A
Block Diagram
Fig.2
IN
SLOPE
COMP
COMP
6
+
2
S
+
+
ISEN
6.1mW
FB
+ EA
+
7
+
ILIM
-
OC
20mV
BST
V1
8
+
PWM
-
S
R
FREQUENCY
FOLDBACK
ROSC
Q
POWER
TRANSISTOR
CLK
OSCILLATOR
3
1
R
R
SW
OVERLOAD
-
PWM
A1
1.23V
+
1
SS/EN
5
1V
1.9V
REFERENCE
& THERMAL
SHUTDOWN
Fig.3
FAULT
SOFT-START
AND
OVERLOAD
HICCUP
CONTROL
GND
4
Figure 2. SC4524A Block Diagram
1.9V
SS/EN
IC
2mA
B4
+
Q
B1
OVERLOAD
R
1V/2.15V
FAULT
S
ID
3.5mA
B2
_
Q
S
OC
R
PWM
B3
Figure 3. Soft-start and Overload Hiccup Control Circuit
Curve 2
Curve 3
Typical Characteristics
SC4524A
Efficiency
80
V O=1.5V
65
60
55
V O=2.5V
70
65
60
55
1MHz, VIN =12V
D2 =20BQ030
1MHz, VIN =24V
D2 =20BQ030
Curve 6
45
Curve 5
45
50
1.01
V O=3.3V
75
Efficiency (%)
70
V O=5V
80
V O=2.5V
75
1.02
VIN =12V
85
V O=3.3V
Feedback Voltage vs Temperature
Efficiency
90
V O=5V
85
Efficiency (%)
SS270 REV 6-7
VFB (V)
SC4524A/B
90
SC4524A
50
40
0.5
1
1.5
2
0.97
0
0.5
Load Current (A)
SS270 REV 6-7
0.99
0.98
40
0
1.00
1
1.5
-50
2
-25
0
25
50
75
100 125
o
Load Current (A)
Temperature ( C)
SS270 REV 6-7
Frequency Setting Resistor
vs Frequency
1.25
VIN =12V
Normalized Frequency
ROSC=93.1k
ROSC (k)
100
10
Curve 8
1
0
0.5
1
1.5
2
1.1
1.0
ROSC=12.1k
0.9
Curve 9
-50
-25
0.5
TA =25oC
0.25
0
25
50
75
0.0
100 125
0.2
0.4
Temperature (o C)
SS270 REV 6-7
SS270 REV 6-7
ROSC=93.1k
0.75
ROSC=12.1k
0.8
2.5
1
0
Frequency (MHz)
Switch Saturation Voltage
vs Switch Current
300
Foldback Frequency vs VFB
Frequency vs Temperature
1.2
Normalized Frequency
1000
0.6
0.8
1.0
VFB (V)
SS270 REV 6-7
Switch Current Limit vs Temperature
BST Pin Current vs Switch Current
100.0
4.5
VIN =12V
-40oC
125oC
150
25oC
100
4.0
BST Pin Current (mA)
200
Current Limit (A)
VCESAT (mV)
250
3.5
3.0
2.5
50
0.0
0.5
1.0
1.5
Switch Current (A)
2.0
2.5
VBST =15V
75.0
50.0
-40oC
125oC
25.0
0.0
-50
-25
0
25
50
75
Temperature (o C)
100 125
0
0.5
1
1.5
2
2.5
3
Switch Current (A)
SC4524A
Curve 12
Curve 11
Typical Characteristics (Cont.)
SS270 REV 6-7
SS270 REV 6-7
SS270 REV 6-7
VIN Supply Current
vs Soft-Start Voltage
VIN Thresholds vs Temperature
2.5
Start
2.8
2.7
2.6
80
-40oC
1.5
1.0
Curve 14
2.5
0.5
2.4
0.0
60
-40oC
-25
0
20
Curve 15
25
50
75
0
100 125
0.5
o
0
1
1.5
5
10
20
25
30
SS270 REV 6-7
Soft-Start Charging Current
vs Soft-Start Voltage
SS Shutdown Threshold
vs Temperature
VIN Quiescent Current vs VIN
0.40
125oC
15
VIN (V)
SS270 REV 6-7
2.5
0
2
VSS (V)
Temperature ( C)
SS270 REV 6-7
125oC
40
UVLO
-50
0.0
-0.5
SS Threshold (V)
-40oC
1.5
1.0
0.5
0.35
Current (uA)
2.0
Current (mA)
VSS = 0
125oC
2.0
Current (mA)
VIN Threshold (V)
2.9
VIN Shutdown Current vs VIN
100
Current (uA)
3.0
0.30
15
VIN (V)
20
25
-2.0
-3.0
0.20
10
-40oC
-1.5
-2.5
0.0
5
125oC
0.25
VCOMP = 0
0
-1.0
30
-50
-25
0
25
50
75
o
Temperature ( C)
100 125
0
0.5
1
1.5
2
VSS (V)
SC4524A
Applications Information
Operation
The SC4524A is a constant-frequency, peak currentmode, step-down switching regulator with an integrated
28V, 2.6A power NPN transistor. Programmable switching
frequency makes the regulator design more flexible. With
the peak current-mode control, the double reactive poles
of the output LC filter are reduced to a single real pole by
the inner current loop. This simplifies loop compensation
and achieves fast transient response with a simple Type-2
compensation network.
As shown in Figure 2, the switch collector current is
sensed with an integrated 6.1mW sense resistor. The
sensed current is summed with a slope-compensating
ramp before it is compared with the transconductance
error amplifier (EA) output. The PWM comparator trip
point determines the switch turn-on pulse width. The
current-limit comparator ILIM turns off the power switch
when the sensed signal exceeds the 20mV current-limit
threshold.
Driving the base of the power transistor above the
input power supply rail minimizes the power transistor
saturation voltage and maximizes efficiency. An external
bootstrap circuit (formed by the capacitor C1 and the
diode D1 in Figure 1) generates such a voltage at the BST
pin for driving the power transistor.
Shutdown and Soft-Start
Table 1
Table 1: SS/EN operation modes
SS/EN
Mode
2.1V
Switching & hiccup armed
The error amplifier EA in Figure 2 has two non-inverting
inputs. The non-inverting input with the lower voltage
predominates. One of the non-inverting inputs is biased
to a precision 1V reference and the other non-inverting
input is tied to the output of the amplifier A1. Amplifier A1
produces an output V1 = 2(VSS/EN -1.23V). V1 is zero and COMP
is forced low when VSS/EN is below 1.23V. During start up,
the effective non-inverting input of EA stays at zero until
the soft-start capacitor is charged above 1.23V. Once VSS/EN
exceeds 1.23V, COMP is released. The regulator starts to
switch when VCOMP rises above 0.4V. If the soft-start interval
is made sufficiently long, then the FB voltage (hence the
output voltage) will track V1 during start up. VSS/EN must be
at least 1.83V for the output to achieve regulation. Proper
soft-start prevents output overshoot. Current drawn from
the input supply is also well controlled.
Overload / Short-Circuit Protection
Table 2 lists various fault conditions and their
corresponding protection schemes in the SC4524A.
Condition
The SS/EN pin is a multiple-function pin. An external
capacitor (4.7nF to 22nF) connected from the SS pin to
ground sets the soft-start and overload shutoff times of
the regulator (Figure 3). The effect of VSS/EN on the SC4524A
is summarized in Table 1.
Table 1
When the SS/EN pin is released, the soft-start capacitor
is charged with an internal 1.6µA current source (not
shown in Figure 3). As the SS/EN voltage exceeds 0.4V,
the internal bias circuit of the SC4524A turns on and the
SC4524A draws 2mA from VIN. The 1.6µA charging current
turns off and the 2µA current source IC in Figure 3 slowly
charges the soft-start capacitor.
Load dependent
Pulling the SS/EN pin below 0.2V shuts off the regulator
and reduces the input supply current to 18µA (VIN = 5V).
Fault
Protective Action
Table 2: Fault conditions and protections
Cycle-by-cycle limit at
IL>ILimit, V FB>0.8V
Condition
Over current
Fault
IL>ILimit,IL>ILimit,
V FB>0.8V
Over current
Over current
V FBILimit, V FB
C
IN V + V − V
IN
4 ⋅ DVDIN ⋅ FCESAT
The peak current limitSWof SC4524A power transistor is at
least 2.6A. The maximum
deliverable
load current for the
D
V
=
D
I
⋅
ESR
+
O
L
SC4524A is 2.6A minus one
half
of the inductor ripple
8
⋅
F
⋅
C
SW
O
( V + VD ) ⋅ ( − D)
current.
DIL = O
FSW ⋅ L
Input Decoupling Capacitor
( V + V ) ⋅ ( − D)
LC => O IOD
IN capacitor
The input
420
⋅ D%
VIN⋅ IO⋅should
F⋅ FSWSW be chosen to handle the RMS
ripple current of a buck converter. This value is given by
IRMS _ CIN = I O ⋅ D ⋅ ( − D)
DV = DI ⋅ ESR +
(5)
DVOcapacitance
= DIL ⋅ ESR must
+
The input
also be high
enough to keep
8 ⋅ FSW ⋅ C O
input ripple voltage within specification. This is important
in reducing the conductive EMI from the regulator. The
input capacitance can be estimated from
Vo
=
Vc
GPWM
R7 =
AC =
VIO
(6)
C5 =
RC4IN=>R 6 O −
4⋅D.V
0INV ⋅ FSW
AC =
inputVripple
DV is the allowable
Awhere
⋅
⋅ FB voltage.
C = − 20 ⋅INlog
C8 =
GOCA+RVSD 2 πFC C O VO
V
D=
Multi-layerVceramic
capacitors, which have very low ESR
IN + VD − VCESAT
handle high RMS ripple current,
.0
(a few mW) and can easily
AC = − 20 ⋅ log
⋅
⋅
=
R=7 5
−3
3
−6
are the ideal choice
3 .3
28 ⋅ 6 . for
⋅ 0input2 πfiltering.
⋅ 80 ⋅ 0 A ⋅ single
22 ⋅ 0 4.7µF
X5R ceramic( Vcapacitor
is adequate for 500kHz or higher
O + VD ) ⋅ ( − D)
DIL =frequency
switching
applications, and 10µF is adequate C 5 =
5 . 9
FSW ⋅ L
for 200kHz
500kHz
switching
For high
0 20 to
=
V frequency.
22 . 3 k
R7 =
Avoltage
−. 28
20applications,
⋅⋅ 0
log−3
⋅ FB (1µF or 2.2µF) can be
a⋅ small ceramic
C =0
C8 =
R 2 πDF)C C O VO
( VO G
+CA
Vwith
D )S⋅ (a−low
placedLin
parallel
ESR
electrolytic
capacitor
to
=
203ESR
% ⋅ IOand
⋅ FSWbulk
Csatisfy
= 0 . 45 nF
5 =
both the
3 capacitance requirements.
2 π ⋅ 6 ⋅ 0
⋅
22
.
⋅
0
.0
AC = − 20 ⋅ log
⋅
⋅
= 5
−3
3
−6
3 . 3 Vo
28
⋅
6
.
⋅
0
2
π
⋅
80
⋅
0
⋅
22
⋅
0
Output
Capacitor
=
C8 = I
= I O3 ⋅⋅ 22D.⋅(⋅ 0
− D3 ) = 2pF
Vc
_ CIN⋅ 0
2 πRMS
⋅ 600
The output5 .9ripple voltage DVO of a buck converter can be
0 20as
Rexpressed
= 22 . 3 k
7 =
− 3 ( + s R
GPWM
Vo 0 . 28 ⋅ 0
ESR C O )
GPWM
=
2
2
D
V
=
D
I
⋅
ESR
+
V
(
+
s
/
ω
)
(
+
s
/
ω
Q
+
s
/
ω
)
(7)
O
c
p L
n
n
8 ⋅3FSW
C5 =
= 0⋅.C
45O nF
3
2 π ⋅ 6 ⋅ 0 ⋅ 22 . ⋅ 0
where CO is the output capacitance.
R7 =
R
V
G
≈ 20 ⋅ log, 3 ⋅ ωp≈ 3 =⋅ 2
,FBpF
ωZ =
,
C
=−
8C =
APWM
⋅ Rinductor
R C OV DI increases
R ESRasC OD
⋅CA
600
⋅ 22 .2 π⋅ F0Ccurrent
S⋅0
Since2 πG
the
C O
O L
G CAIOR S ripple
C IN >(Equation (3)), the output ripple voltage is C 5 =
decreases
AC
4 ⋅ DVIN ⋅ FSW
therefore
0 20 the highest
when VIN is at its maximum.
.0
RA
GPWM
V7oC = − 20 ⋅ log
⋅
( + s R ESR C−O3 ) ⋅
= 5
3
−6
= gm
3 .3
28 ⋅ 6 . ⋅ 0 2 2 π ⋅280 ⋅ 0 ⋅ 22 ⋅ 0
VAc 10µF
( +to
s /47µF
ωp)(X5R
+ s ceramic
/ ωn Q + scapacitor
/ ωn ) is found adequate C 8 =
output filtering in most applications. Ripple current
Cfor
5 =
5R
.9
2 πFoutput
in the
0ZR20 7 capacitor is not
a concern because the
Rinductor
= of
22a. 3 kbuck
G
,
ω
≈
,
ωZ =feeds C ,,
7 = ≈
−
3
current
converter
directly
PWM
p
⋅ 0
0 . 28
GCA
⋅RS
RCO
R ESR C OO
Cresulting
8 =
in
very
low
ripple
current.
Avoid
using
Z5U
2 πFP R 7
Cand
=
=
0
.
45
nF
Y5V
ceramic
capacitors
for
output
filtering
because
A
C
5
3
3
20
2π
⋅ 6 ⋅of
0capacitors
⋅ 22 . ⋅ 0
0
types
have high temperature and high
Rthese
=
7
gm coefficients.
voltage
C8 =
= 2pF
2 π⋅ 600 ⋅ 0 3 ⋅ 22 . ⋅ 0 3
Diode
CFreewheeling
5 =
2 πFZ R 7
G ( + s R diodes
C O ) as freewheeling rectifiers
VUse
of Schottky
o
PWM barrierESR
==
CVreduces
recovery
current spikes,
8
(2 π+Fsdiode
/ ωp )(reverse
+ s / ωn Q
+ s 2 / ωn2input
)
c
P R 7
easing high-side current sensing in the SC4524A. These
GPWM ≈
R
,
GCA ⋅ R S
ωp ≈
,
RCO
ωZ =
11
,
R ESR C O
SC4524A
Fig.5
Applications Information (Cont.)
SS270 REV 6-7
diodes should have an average forward current rating
at least 2A and a reverse blocking voltage of at least a
few volts higher than the input voltage. For switching
regulators operating at low duty cycles (i.e. low output
voltage to input voltage conversion ratios), it is beneficial
to use freewheeling diodes with somewhat higher
average current ratings (thus lower forward voltages). This
is because the diode conduction interval is much longer
than that of the transistor. Converter efficiency will be
improved if the voltage drop across the diode is lower.
Minimum Bootstrap Voltage
vs Temperature
2.2
Voltage (V)
2.1
2.0
1.9
1.8
ISW = -2.6A
1.7
The freewheeling diode should be placed close to the
SW pin of the SC4524A to minimize ringing due to trace
inductance. 20BQ030 (International Rectifier), B230A
(Diodes Inc.), SS13, SS23 (Vishay), CMSH1-40M, CMSH140ML and CMSH2-40M (Central-Semi.) are all suitable.
1.6
Fig.6
The freewheeling diode should be placed close to the SW
pin of the SC4524A on the PCB to minimize ringing due to
trace inductance.
-50
Fig.6
50
75
100 125
D3
D1
BST
C1
VOUT
SW
IN
SC4524A
VIN
D2
GND
(a)
D3
D1
BST
VIN
C1
VOUT
SW
IN
SC4524A
D
GND
(a)
For the bootstrap circuit, a fast switching PN diode (such
as 1N4148 or 1N914) and a small (0.1µF – 0.47µF) ceramic
capacitor is sufficient for most applications. When
bootstrapping from 2.5V to 3.0V output voltages, use a
low forward drop Schottky diode (BAT-54 or similar) for
D1. When bootstrapping from high input voltages (>20V),
reduce the maximum BST voltage by connecting a Zener
diode (D3) in series with D1.
25
Figure 5. Typical Minimum Bootstrap Voltage required
to Saturate Transistor (ISW= -2.6A).
The typical minimum BST-SW voltage required to fully
saturate the power transistor is shown in Figure 5, which
is about 1.96V at room temperature.
The BST-SW voltage is supplied by a bootstrap D1circuit
powered from either the input or the output of the
BST
converter (Figure 6). To maximize efficiency,C1 tie the
bootstrap diode toVINthe converter output
if VO>2.5V. VOUT
SW
IN
Since the bootstrap supply current is proportional to the
SC4524A
D to power
converter load current, using a lower
voltage
2
GND
the bootstrap circuit reduces driving loss and improves
efficiency.
0
Temperature (o C)
VIN
Bootstrapping the Power Transistor
-25
2
(b)
Figure 6. Methods of Bootstrapping the SC4524A
Loop Compensation
The goal of compensation is to shape the frequency
response of the converter so as to achieve high DC
accuracy and fast transient response while maintaining
loop stability.
12
SC4524A
Applications Information (Cont.)
CONTROLLER AND SCHOTTKY DIODE
CA
+
EA
FB
Including the voltage divider (R4 and R6), the control to
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Io
-
Vc
PWM
MODULATOR
SW
Vramp
L1
Vo
COMP
C8
R7
O
R4
Co
C5
Resr
R6
Figure 7. Block diagram of controlFig.8
loops
VFB
⋅
FB
AC =
=diagram
− 20
20 ⋅⋅ log
log
⋅V
The block
in
Figure
7
shows
the
control
loops of a
A
−
⋅
⋅
C
G
G CAR
R S 22 π
πFFC C
CO V
VO
CA
S
C
O
O
buck converter with the SC4524A. The innerloop (current
loop) consists of a current sensing resistor (Rs=6.1mW)
gain⋅ (G =28). The
outer
amplifier
AC =
=−
− 20
20
log (CA) with
CA
VFB and a current
A
⋅⋅ log
⋅
−
3
−6
C
28 ⋅⋅ 66 ..of⋅⋅ 0
0
π amplifier
80 ⋅⋅ 0
0 33 (EA),
22 ⋅⋅ 0
loop (voltage loop) consists
⋅
22 π
⋅⋅ 80
⋅⋅ 22
28
an− 3error
a0 −6
VO
PWM modulator, and a LC filter.
5 . 9
5
20. 9
20
.0
0 loop
0
internally
closed, the remaining
⋅ Since3 the
⋅ −3is=
5
R 7=
=current
22. 93dB
k
V
R
−
6
FB
7 ⋅ 0
3. 3−3 = 22 . 3 k is to design the voltage
2 π⋅ 80task
⋅ 0⋅for
⋅ 22
28
0
⋅ log
⋅ ⋅⋅ 0
the00loop
compensation
..28
R S 2 πFC C O VO
G CAcompensator
(C5, R7, and
C8).
C5 =
=
= 00 ..45
45nF
nF
C
=
3
5
2π
π ⋅⋅ 6
6 ⋅⋅ 0
0 3 ⋅⋅ 22
22 .. ⋅⋅ 0
0 33
2
. 0 F , output
with switching
frequency
⋅ log For a converter
⋅
⋅
= 5SW. 9 dB
−3
3
−6
.2
3 pF
⋅ 6 . ⋅ 0
2, πoutput
⋅ 80 ⋅ 0
⋅ 22 ⋅ 0 C =3and
28 inductance
L
capacitance
loading R, the
C
=
O = 2 pF
C 88 = 1
33 ⋅ 22 . ⋅ 0 33
2
π
⋅
600
⋅
0
2
π
⋅
600
⋅
0
⋅
22
.
⋅
0
control (VC) to output (VO) transfer function in Figure 7 is
= 0 . 45 nF
given by:
5 . 9
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at FZ1, and a high frequency pole
at FP1. The integrator is used to boost the gain at low
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
..0060 = 5 . 9 dB
⋅⋅ 3 . 3 =
5 . 9 dB
3 . 3
30
GAIN (dB)
REF
Rs
Fz1
Fp1
Fp
0
CO
NV
-30
-60
1K
10K
ER
T ER
Fc
LO
CO
MP
OP
G
EN
SA
TO
RG
AIN
AIN
GA
IN
Fz
Fsw/2
100K
FREQUENCY (Hz)
1M
10M
20
= 22 . 3 k V
GPWM (( +
+ ss R
R ESR C
C O ))
−3
G
Voo =
⋅ 0
PWM
ESR O
= 2pF
=
Vc (( +
+ ss // ω
ωp ))(( +
+ ss // ω
ωn Q
Q + s 22 / ωn22 ))
V
c
p
n + s / ωn
= 0 . 45 nF
6 ⋅ 0 3 ⋅This
22 . transfer
⋅ 0 3 function has a finite DC gain
R
GPWM ≈
≈= 2RpF ,,
G
PWM
2
2 3
GCA ⋅⋅ R
RS
00/ ω
⋅ 0
⋅ 22 . ⋅ 0 3 G
CA
S
n)
(8)
ωp ≈
≈ ,,
ω
p
RC
CO
R
O
A
an ESR zero FZ at
AC
0 2020C
0
R7 = )
GPWM ( + s R ESR
R
,
ω7ZC=
=O gm ,
R/CωOp )( + s / ωn Q + sR2gESR
/mωCn2O)
C5 =
= low-frequency
C
a dominant
pole FP at
5
πFFZ R
R
22 π
Z 77
R
,
ωp ≈
ωZ =
,
,
C
=
⋅
R
R
C
R
C 88 = 2 πOF R
A
S
ESR C O
2 πFPP R 77
and double poles at half the switching frequency.
V
R 4 = R 6 O −
.0 V
Figure 8. Bode plots for voltage loop design
Therefore, the procedure of the voltage loop design for
the SC4524A can be summarized as:
ωZ =
= ,,
ω
Z
R ESR C
CO
R
ESR (1)
O Plot the converter gain, i.e. control to feedback transfer
function.
(2) Select the open loop crossover frequency, FC, between
10% and 20% of the switching frequency. At FC, find the
required compensator gain, AC. In typical applications with
ceramic output capacitors, the ESR zero is neglected and
the required compensator gain at FC can be estimated by
V
AC = − 20 ⋅ log
⋅
⋅ FB
G CAR S 2 πFC C O VO
(9)
.0
13
AC = − 20 ⋅ log
⋅
⋅
−3
3
−6
3.
2 π ⋅ 80 ⋅ 0 ⋅ 22 ⋅ 0
28 ⋅ 6 . ⋅ 0
C5 =
C8 =
3
2 π ⋅ 6 ⋅ 0 ⋅ 22 . ⋅ 0 3
= 0 . 45 nF
SC4524A
= 2pF
2 π⋅ 600 ⋅ 0 3 ⋅ 22 . ⋅ 0 3
Applications Information (Cont.)
GPWM ( + s R ESR C O )
Vo
(3) Place =the compensator zero, FZ1,2 between
10% and
Thermal Considerations
Vc ( + s / ωp )( + s / ωn Q + s / ωn2 )
20% of the crossover frequency, FC.
(4) Use the compensator pole, FP1, to cancel the ESR zero,
For the power transistor inside the SC4524A, the
FZ.
R
conduction loss PC, the switching loss PSW, and bootstrap
G
≈
,
ω ≈
,
ωZ =
,
(5) Then,PWM
the parameters
of the pcompensation
network
PBST,
be
Ploss
= Pcan
+ PBST + Pas
GCA ⋅ R S
RCO
R ESR Ccircuit
TOTAL
C +P
SWestimated
Q follows:
O
can be calculated by
AC
0 20
R7 =
gm
PC = D ⋅ VCESAT ⋅ IO
C5 =
2 πFZ R 7
PSW =
C8 =
2 πFP R 7
PBST = D ⋅ VBST ⋅
where gm=0.28mA/V is the EA gain of the SC4524A.
PQ = VIN ⋅ 2mA
⋅ t S ⋅ VIN ⋅ I O ⋅ FSW
2
(10)
IO
40
where PVBST=is(the
voltage and tS is the equivalent
− DBST
) ⋅ Vsupply
D
D ⋅ IO
switching time of the NPN transistor (see Table 3).
Example: Determine the voltage compensator for an
800kHz, 12V to 3.3V/2A converter with 22uF ceramic
output capacitor.
PTable
.Typical
~ .3 )switching
⋅ I2O ⋅ R DC time
IND = (3.
Input Voltage
12V
24V
28V
Choose a loop gain crossover frequency of 80kHz, and
place voltage compensator
zero and pole
VFB at FZ1=16kHz
A
=
−
20
⋅
log
⋅
⋅
C
(20% of FC), and
F =600kHz.
(9), the
G CAR⋅ VSFB 2 πFrom
FC C O Equation
VO
AC = − 20 ⋅ log
⋅ P1
C O Vat
required compensator
O F is
G CAR S 2 πFCgain
C
Load Current
1A
2A
12.5ns
15.3ns
22ns
25ns
25.3ns
28ns
.0
P −6 ⋅= .P0C =+35
PSW
AC = − A
20C ⋅=
log−
. 9 dB+ PBST +
. 9 dBquiescent current loss is
20 ⋅ log − 3 ⋅
In⋅Paddition,
Q = 5 the
3− 3 ⋅ TOTAL
−6
3
.
3
2
π
⋅
80
⋅
0
⋅
22
⋅
0
28 ⋅ 6 . ⋅ 0
3 .3
2 π ⋅ 80 ⋅ 0 ⋅ 22 ⋅ 0
28 ⋅ 6 . ⋅ 0
Then the compensator parameters areP = D ⋅ V
C
CESAT ⋅ IO
0
R7 =
5 . 9
20
PQ = VIN ⋅ 2mA
(11)
= 225. 3.9k
0 20
The total power loss of the SC4524A is therefore
= 22 . 3 k
PSW = ⋅ t S ⋅ VIN ⋅ I O ⋅ FSW
0 . 28
⋅ 0 −3 3 = 0 . 45 nF
C5 =
3
2 π ⋅ 6 ⋅ 0 ⋅ 22 . ⋅ 0
2
PTOTAL = PC + PSW + PBST + PQ
(12)
C
=
=
0
.
45
nF
5
3 = 2pF
3
C8 =
I
3⋅ 6 ⋅ 0 3 ⋅ 22 . ⋅ 0
2
π
2 π⋅ 600 ⋅ 0 ⋅ 22 . ⋅ 0
PBST = D ⋅ VBST ⋅ O
40
The temperature
rise⋅ of
= Vproduct
IN ⋅ 2 mA of the
PC = D ⋅ VCESAT
IO the SC4524A PisQthe
C
=
=
2
pF
total power dissipation (Equation (12)) and qJA (36oC/W),
8 GPWM ( + s R ESR C O )3
Vo
2 π⋅ 600 ⋅ 0 2 ⋅ 22
. ⋅ 0 3
=
2
which is the thermal
impedance from junction to ambient
Vc ( + s / ωp )( + s / ωn Q + s / ωn )
PD = ( − D) ⋅ VD ⋅ IO
P
=
⋅
t
⋅
V
SW
S
IN ⋅ I O ⋅ FSW
Select R7=22.1k, C5=0.47nF, and C8=10pF for the design.
for the SOIC-82 EDP package.
R
GPWM
GPWM ≈ Vo
,
ωp ≈( + ,s R ESR C Oω)Z =
,
I
=
P
= ( . ~ .3 ) ⋅ I2O ⋅ R DCIt is not recommended
G
⋅
R
R
C
R
Compensator
parameters for various typical
ESR2C O applications
PBST = D ⋅ VBST ⋅ O to operate the SC4524A above
VcCA (S + s / ωp )( + Os / ωn Q + s 2 IND
/ω
)
n
o
40
are listed in Table 4. A MathCAD program is also available
125 C junction temperature.
In the applications with high
0
upon
input voltage and high output current, the switching
R 7 = request for detailed calculation of the compensator
gm
parameters.
need
R
frequency
PD =may
( − D
) ⋅ VD to
⋅ IObe reduced to meet the thermal
GPWM
≈
,
ωp ≈
,
ωZ =
,
C5 =
G ⋅R
RC
R Crequirement.
0 . 28 ⋅ 0 −3
R7 =
AC
20
2 πFZ R 7
C8 =
CA
AC
2 πFP R 70 20
R7 =
C5 =
S
O
ESR
O
PIND = ( . ~ .3 ) ⋅ I2O ⋅ R DC
gm
2 πF R
14
SC4524A
PCB Layout Considerations
In a step-down switching regulator, the input bypass
capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
operation, the size of the loop formed by these components
should be minimized. Since the power switch is already
integrated within the SC4524A, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
12
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.
V IN
VOUT
ZL
Figure 9. Heavy lines indicate the critical pulse
current loop. The inductance of this
loop should be minimized.
Vin
Curre nts in Power Section
15
SC4524A
Recommended Component Parameters in Typical Applications
Table 4 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output
voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator
parameters are calculated by assuming a 22mF low ESR ceramic output capacitor and a loop gain crossover frequency
of FSW/10.
SC4524A Compensator Parameters
Table 4. Recommended inductance (L1) and compensator (R7, C5, C8)
Vin(V)
12
24
Typical Applications
Vo(V)
Io(A)
Fsw(kHz)
1
500
1.5
2
500
500
1
1000
2.5
500
2
1000
500
1
1000
3.3
500
2
1000
500
1
1000
5
500
2
1000
500
1
1000
7.5
500
2
1000
500
1
1000
10
500
2
1000
1
1.5
300
2
1
2.5
2
500
1
3.3
2
500
1
1000
5
500
2
1000
500
1
1000
7.5
500
2
1000
500
1
1000
10
500
2
1000
C2(uF)
22
L1(uH)
8.2
4.7
15
6.8
6.8
3.3
15
8.2
8.2
4.7
15
10
8.2
4.7
15
8.2
8.2
4.7
10
4.7
4.7
2.2
15
8.2
15
8.2
22
10
22
15
15
6.8
33
15
15
8.2
33
22
15
10
Recommended Parameters
R7(k)
C5(nF)
C8(pF)
7.15
2.2
7.15
2.2
11.3
1
20
0.68
11.3
1
20
0.47
15
0.82
30.9
0.47
15
0.82
30.9
0.47
23.7
0.68
41.2
0.47
23.7
0.68
45.3
0.47
35.7
0.68
63.4
0.47
35.7
0.68
63.4
0.47
42.2
0.68
84.5
0.47
10
42.2
0.68
84.5
0.47
4.32
2.2
12.4
1.0
15
0.82
20
43.2
20
43.2
35.7
63.4
35.7
63.4
43.2
84.5
43.2
84.5
0.68
0.47
0.68
0.47
0.68
0.47
0.68
0.47
0.68
0.47
0.68
0.47
16
SC4524A
Typical Application Schematics
V IN
D1
D3
24V
18V Zener 1N4148
C4
4.7mF
C1
0.33mF
L1
BST
IN
SW
8.2mH
SC4524A
SS/EN
OUT
R4
33.2k
1.5V/2A
FB
COMP
C7
10nF
ROSC
D2
20BQ030
R5
90.9k
R7
4.32k
C8
22pF
GND
R6
66.5k
C2
22mF
C5
2.2nF
L1: Coiltronics DR73-8R2
C2: Murata GRM31CR60J226K
C4: Murata GRM32ER71H475K
Figure 10. 300kHz 24V to 1.5V/2A Step-down Converter
EVB#d: 300kHz 24V to 1.5V/2A Step-Down Converter
V IN
D1
10V – 26V
Fig.10
C4
4.7mF
1N4148
C1
0.1mF
L1
BST
IN
SW
8.2mH
SC4524A
SS/EN
OUT
R4
3.65k
3.3V/2A
FB
COMP
C7
10nF
C8
22pF
ROSC
R7
13.0k
GND
R5
23.7k
D2
SS23
R6
1.58k
C2
22mF
C5
2.2nF
L1: Coiltronics DR73-8R2
C2: Murata GRM31CR60J226M
C4: Murata GRM32ER71H475K
Figure 11. 800kHz 10V-26V to 3.3V/2A Step-down Converter
800kHz 10V-26V to 3.3V/2A Step-Down Converter
17
TR
SC4524A
Fig.12(b) SS
Typical Performance Characteristics
(For A 24V to 5V/2A Step-down Converter with 1MHz Switching Frequency)
SS270 REV 6-7
Load Characteristic
6
Output Voltage (V)
5
24V Input (10V/DIV)
4
3
5V Output (2V/DIV)
2
1
SS Voltage (1V/DIV)
0
0
0.5
1
1.5
2
2.5
3
Load Current (A)
Fig.12(d) OCP
Figure 12(a). Load Characteristic
10ms/DIV
Figure 12(b). VIN Start up Transient (IO=2A)
5V Output Short (5V/DIV)
5V Output Response (500mV/DIV, AC Coupling)
Inductor Current (1A/DIV)
Retry Inductor Current (2A/DIV)
SS Voltage (2V/DIV)
40us/DIV
Figure 12(c). Load Transient Response
(IO= 0.3A to 2A)
20ms/DIV
Figure 12(d). Output Short Circuit (Hiccup)
18
SC4524A
SO-8 EDP2 Outline
Outline Drawing - SOIC-8 EDP
A
D
e
N
DIM
A
A1
A2
b
c
D
E1
E
e
F
H
h
L
L1
N
01
aaa
bbb
ccc
2X E/2
E1 E
1
2
ccc C
2X N/2 TIPS
e/2
B
D
aaa C
SEATING
PLANE
A2 A
C
bxN
bbb
A1
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.053
.069
.000
.005
.049
.065
.012
.020
.007
.010
.189 .193 .197
.150 .154 .157
.236 BSC
.050 BSC
.116 .120 .130
.085 .095 .099
.010
.020
.016 .028 .041
(.041)
8
0°
8°
.004
.010
.008
C A-B D
1.35
1.75
0.00
0.13
1.25
1.65
0.31
0.51
0.17
0.25
4.80 4.90 5.00
3.80 3.90 4.00
6.00 BSC
1.27 BSC
2.95 3.05 3.30
2.15 2.41 2.51
0.25
0.50
0.40 0.72 1.04
(1.05)
8
0°
8°
0.10
0.25
0.20
h
F
EXPOSED PAD
h
H
H
c
GAGE
PLANE
0.25
L
(L1)
SEE DETAIL
SIDE VIEW
A
DETAIL
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION BA.
Land Pattern - SOIC-8 EDP
SO-8 EDP2 Landing Pattern
E
SOLDER MASK
D
DIM
(C)
F
G
Z
Y
THERMAL VIA
Ø 0.36mm
P
X
C
D
E
F
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.205)
.134
.201
.101
.118
.050
.024
.087
.291
(5.20)
3.40
5.10
2.56
3.00
1.27
0.60
2.20
7.40
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation
Power Mangement Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
19
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