Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
165-Bump BGA Commercial Temp Industrial Temp Features
• Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with present 9Mb, 18Mb, 36Mb and future 144Mb devices • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available
72Mb SigmaCIO DDR-II Burst of 2 SRAM
333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O
Bottom View
165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Common I/O x36 and x18 SigmaCIO DDR-II B2 RAMs always transfer data in two packets. When a new address is loaded, A0 presets an internal 1 bit address counter. The counter increments by 1 (toggles) for each beat of a burst of two data transfer. Common I/O x8 SigmaCIO DDR-II B2 RAMs always transfer data in two packets. When a new address is loaded, the LSB is internally set to 0 for the first read or write transfer, and incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a x8 SigmaCIO DDR-II B4 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 18 has a 2048K addressable index).
SigmaCIO™ Family Overview
The GS8662T08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662T08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662T08/09/18/36E SigmaCIO DDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended
Parameter Synopsis
-333 tKHKH tKHQV 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -267* 3.75 ns 0.45 ns -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns -167 6.0 ns 0.5 ns
* The 267 MHz speed bin is only available on the x18 part.
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2M x 36 SigmaCIO DDR-II SRAM—Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 MCL/SA (144Mb) DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 SA DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to DQ27:DQ35 2. MCL = Must Connect Low
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4M x 18 SigmaCIO DDR-II SRAM—Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 SA DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 SA NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17 2. MCL = Must Connect Low
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
8M x 9 SigmaCIO DDR-II SRAM—Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 SA NC NC NC NC NC NC VREF NC NC DQ7 NC NC NC TCK 3 SA NC NC NC DQ5 NC DQ6 VDDQ NC NC NC NC NC DQ8 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC NC NC NC VREF DQ2 NC NC NC NC NC TMS 11 CQ DQ4 NC NC DQ3 NC NC ZQ NC NC DQ1 NC NC DQ0 TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0. SA0 is set to 0 at the beginning of each access. 2. MCL = Must Connect Low
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8M x 8 SigmaCIO DDR-II SRAM—Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 SA NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 SA NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC NW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC NC TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0. SA0 is set to 0 at the beginning of each access. 2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7 3. MCL = Must Connect Low
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Pin Description Table Symbol
SA NC R W BW0–BW3 NW0–NW1 LD K K C C TMS TDI TCK TDO VREF ZQ MCL DQ Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin
Description
Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Writes Nybble Write Control Pin Synchronous Load Pin Input Clock Input Clock Output Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Must Connect Low Data I/O Disable DLL when low Output Echo Clock Output Echo Clock Power Supply Isolated Output Buffer Supply Power Supply: Ground
Type
Input — Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input — Input/Output Input Output Output Supply Supply Supply
Comments
— — Active High Active Low Active Low x18/x36 only Active Low x8 only Active Low Active High Active Low Active High Active Low — — — — — — — Three State Active Low — — 1.8 V Nominal 1.5 V Nominal —
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated in the timing diagrams. It is not possible to stop a burst once it starts. Two beats of data are always transferred. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer and then execute the deselect command, returning the output drivers to high-Z. A high on the LD# pin prevents the RAM from loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.
SigmaCIO DDR-II B2 SRAM Read Cycles
The SRAM executes pipelined reads. The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. The read command (LD# low and R/W# high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data is transferred on the next rising edge of C, for a total of two transfers per address load.
SigmaCIO DDR-II B2 SRAM Write Cycles
The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command (LD# and R/W# low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures data in on the next rising edge of K#, for a total of two transfers per address load.
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Power-Up Sequence for SigmaQuad-II SRAMs SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations. Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. 1b. 1c. Apply VDD. Apply VDDQ. Apply VREF (may also be applied at the same time as VDDQ).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high. 3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note: If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.
DLL Constraints
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar on page 20). • The DLL cannot operate at a frequency lower than 119 MHz. • If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.
Power-Up Sequence (Doff controlled)
Power UP Interval Unstable Clocking Interval DLL Locking Interval (1024 Cycles) Normal Operation
K
K
VDD
VDDQ
VREF
Doff
Power-Up Sequence (Doff tied High)
Power UP Interval Unstable Clocking Interval Stop Clock Interval 30ns Min DLL Locking Interval (1024 Cycles) Normal Operation
K
K
VDD
VDDQ
VREF
Doff
Note: If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Special Functions
Byte Write and Nybble Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time
Beat 1 Beat 2 Resulting Write Operation
BW0
0 1
BW1
1 0
D0–D8
Data In Don’t Care
D9–D17
Don’t Care Data In
Byte 1 D0–D8
Written Beat 1
Byte 2 D9–D17
Unchanged
Byte 3 D0–D8
Unchanged Beat 2
Byte 4 D9–D17
Written
Output Register Control SigmaCIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.
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Example Four Bank Depth Expansion Schematic
LD3 LD2 LD1 LD0 R/W
A0–An K Bank 0 A LD R/W K C C DQ1– CQ CQ DQ C Bank 1 A LD R/W K CQ DQ Bank 2 A LD R/W K CQ DQ C Bank 3 A LD R/W K C CQ DQ
Note: For simplicity BWn (or NWn), K, and C are not shown.
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Common I/O SigmaCIO DDR-II B2 SRAM Truth Table Kn
↑ ↑ ↑
LD
1 0 0
R/W
X 0 1
DQ A+0
Hi-Z D@Kn+1 Q@Kn+1 or Cn+1
A+1
Hi-Z D@Kn+1 Q@Kn+2 or Cn+2
Operation
Deselect Write Read
Note: Q is controlled by K clocks if C clocks are not used.
B2 Byte Write Clock Truth Table BW K↑ (tn+1)
T T F F
BW K↑ (tn+2)
T F T F
Current Operation K↑ (tn)
Write Dx stored if BWn = 0 in both data transfers Write Dx stored if BWn = 0 in 1st data transfer only Write Dx stored if BWn = 0 in 2nd data transfer only Write Abort No Dx stored in either data transfer
D K↑ (tn+1)
D1 D1 X X
D K↑ (tn+2)
D2 X D2 X
Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.
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B2 Nybble Write Clock Truth Table NW K↑ (tn+1)
T T F F
NW K↑ (tn+2)
T F T F
Current Operation K↑ (tn)
Write Dx stored if NWn = 0 in both data transfers Write Dx stored if NWn = 0 in 1st data transfer only Write Dx stored if NWn = 0 in 2nd data transfer only Write Abort No Dx stored in either data transfer
D K↑ (tn+1)
D1 D1 X X
D K↑ (tn+2)
D2 X D2 X
Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
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x36 Byte Write Enable (BWn) Truth Table BW0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
BW1 BW2 BW3
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
D0–D8
Don’t Care Data In Don’t Care Data In Don’t Care Data In Don’t Care Data In Don’t Care Data In Don’t Care Data In Don’t Care Data In Don’t Care Data In
D9–D17
Don’t Care Don’t Care Data In Data In Don’t Care Don’t Care Data In Data In Don’t Care Don’t Care Data In Data In Don’t Care Don’t Care Data In Data In
D18–D26
Don’t Care Don’t Care Don’t Care Don’t Care Data In Data In Data In Data In Don’t Care Don’t Care Don’t Care Don’t Care Data In Data In Data In Data In
D27–D35
Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Data In Data In Data In Data In Data In Data In Data In Data In
x18 Byte Write Enable (BWn) Truth Table BW0 BW1
1 0 1 0 1 1 0 0
D0–D8
Don’t Care Data In Don’t Care Data In
D9–D17
Don’t Care Don’t Care Data In Data In
x8 Nybble Write Enable (NWn) Truth Table NW0 NW1
1 0 1 0 1 1 0 0
D0–D3
Don’t Care Data In Don’t Care Data In
D4–D7
Don’t Care Don’t Care Data In Data In
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B2 State Diagram
Power-Up
LOAD
NOP
LOAD LOAD Load New Address
LOAD
LOAD
READ
WRITE
LOAD
DDR Read
DDR Write
Notes: 1. The internal address burst counter is a 1 bit counter (i.e., when first address is A0, next internal burst address is A0+1). 2. “READ” refers to read active status with R/W = High, “WRITE” refers to write inactive status with R/W = Low. 3. “LOAD” refers to read new address active status with LD = Low, “LOAD” refers to read new address inactive status with LD = High.
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VREF VI/O VIN IIN IOUT TJ TSTG
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage in VREF Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature
Value
–0.5 to 2.9 –0.5 to VDD –0.5 to VDDQ –0.5 to VDDQ +0.5 (≤ 2.9 V max.) –0.5 to VDDQ +0.5 (≤ 2.9 V max.) +/–100 +/–100 125 –55 to 125
Unit
V V V V V mA dc mA dc
oC o
C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Power Supplies Parameter
Supply Voltage I/O Supply Voltage Reference Voltage
Symbol
VDD VDDQ VREF
Min.
1.7 1.7 0.68
Typ.
1.8 1.8 —
Max.
1.9 1.9 0.95
Unit
V V V
Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ VDDQ ≤ 1.6 V (i.e., 1.5 V I/O) and 1.7 V ≤ VDDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case. 2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD..
Operating Temperature Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
TA TA
Min.
0 –40
Typ.
25 25
Max.
70 85
Unit
°C °C
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HSTL I/O DC Input Characteristics Parameter
DC Input Logic High DC Input Logic Low
Symbol
VIH (dc) VIL (dc)
Min
VREF + 0.10 –0.3 V
Max
VDD + 0.3 V VREF – 0.10
Units
V V
Notes
1 1
Notes: 1. Compatible with both 1.8 V and 1.5 V I/O drivers 2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 3. VIL (Min) DC = –0.3 V, VIL(Min) AC = –1.5 V (pulse width ≤ 3 ns). 4. VIH (Max) DC = VDDQ + 0.3 V, VIH(Max) AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
HSTL I/O AC Input Characteristics Parameter
AC Input Logic High AC Input Logic Low VREF Peak to Peak AC Voltage
Symbol
VIH (ac) VIL (ac) VREF (ac)
Min
VREF + 0.20 — —
Max
— VREF – 0.20 5% VREF (DC)
Units
V V V
Notes
3,4 3,4 1
Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Undershoot Measurement and Timing
VIH
Overshoot Measurement and Timing
20% tKHKH VDD + 1.0 V
VSS 50% VSS – 1.0 V 20% tKHKH
50% VDD
VIL
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Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance Output Capacitance Clock Capacitance Note: This parameter is sample tested.
Symbol
CIN COUT CCLK
Test conditions
VIN = 0 V VOUT = 0 V —
Typ.
4 6 5
Max.
5 7 6
Unit
pF pF pF
AC Test Conditions Parameter
Input high level Input low level Max. input slew rate Input reference level Output reference level Note: Test conditions as specified with output loading as shown unless otherwise noted.
Conditions
VDDQ 0V 2 V/ns VDDQ/2 VDDQ/2
AC Test Load Diagram
DQ 50Ω VT = VDDQ/2 RQ = 250 Ω (HSTL I/O) VREF = 0.75 V
Input and Output Leakage Characteristics Parameter
Input Leakage Current (except mode pins) Doff Output Leakage Current
Symbol
IIL IINDOFF IOL
Test Conditions
VIN = 0 to VDD VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDDQ
Min.
–2 uA –100 uA –2 uA –2 uA
Max
2 uA 2 uA 2 uA 2 uA
Notes
Rev: 1.01 9/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage
Symbol
VOH1 VOL1 VOH2 VOL2
Min.
VDDQ/2 Vss VDDQ – 0.2 Vss
Max.
VDDQ VDDQ/2 VDDQ 0.2
Units
V V V V
Notes
1, 3 2, 3 4, 5 4, 6
Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = –1.0 mA 6. IOL = 1.0 mA
Operating Currents
-333 Parameter Symbol Test Conditions 0 to 70°C TBD TBD TBD TBD –40 to 85°C TBD TBD TBD TBD -300 0 to 70°C TBD TBD TBD TBD –40 to 85°C TBD TBD TBD TBD -267 0 to 70°C TBD TBD TBD TBD –40 to 85°C TBD TBD TBD TBD -250 0 to 70°C TBD TBD TBD TBD –40 to 85°C TBD TBD TBD TBD -200 0 to 70°C TBD TBD TBD TBD –40 to 85°C TBD TBD TBD TBD -167 0 to 70°C TBD TBD TBD TBD –40 to 85°C TBD TBD TBD TBD Notes
Operating Current (x36): DDR Operating Current (x18): DDR Operating Current (x9): DDR Operating Current (x8): DDR Standby Current (NOP): DDR
IDD
VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min Device deselected, IOUT = 0 mA, f = Max, All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V
2, 3
IDD
2, 3
IDD
2, 3
IDD
2, 3
ISB1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2, 4
Notes:
1. 2. 3. 4. Power measured with output pins floating. Minimum cycle, IOUT = 0 mA Operating current is calculated with 50% read cycles and 50% write cycles. Standby Current is only after all pending read and write burst operations are completed.
Rev: 1.01 9/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
AC Electrical Characteristics
Parameter Clock
K, K Clock Cycle Time C, C Clock Cycle Time tTKC Variable K, K Clock High Pulse Width C, C Clock High Pulse Width K, K Clock Low Pulse Width C, C Clock Low Pulse Width K to K High C to C High K, K Clock High to C, C Clock High DLL Lock Time K Static to DLL reset tKHKH tCHCH tKCVar tKHKL tCHCL tKLKH tCLCH tKHKH tKHCH tKCLock tKCReset tKHQV tCHQV tKHQX tCHQX tKHCQV tCHCQV tKHCQX tCHCQX tCQHQV tCQHQX tKHQZ tCHQZ tKHQX1 tCHQX1 tAVKH tIVKH tDVKH 3.0 — 1.2 1.2 1.35 0 1024 30 3.5 0.2 — — — 1.3 — — 3.3 — 1.32 1.32 1.49 0 1024 30 4.2 0.2 — — — 1.45 — — 3.75 — 1.6 1.6 1.8 0 1024 30 5.5 0.2 — — — 1.8 — — 4.0 — 1.6 1.6 1.8 0 1024 30 6.3 0.2 — — — 1.8 — — 5.0 — 2.0 2.0 2.2 0 1024 30 7.88 0.2 — — — 2.3 — — 6.0 — 2.4 2.4 2.7 0 1024 30 8.4 0.2 — — — 2.8 — — ns ns ns ns ns ns cycle ns 6 5
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Output Times
K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold CQ, CQ High Output Valid CQ, CQ High Output Hold K Clock High to Data Output High-Z C Clock High to Data Output High-Z K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z — –0.45 — –0.45 — –0.25 — –0.45 0.45 — 0.45 — 0.25 — 0.45 — — –0.45 — –0.45 — –0.27 — –0.45 0.45 — 0.45 — 0.27 — 0.45 — — –0.45 — –0.45 — –0.30 — –0.45 0.45 — 0.45 — 0.30 — 0.45 — — –0.45 — –0.45 — –0.30 — –0.45 0.45 — 0.45 — 0.30 — 0.45 — — –0.45 — –0.45 — –0.35 — –0.45 0.45 — 0.45 — 0.35 — 0.45 — — –0.5 — –0.5 — –0.40 — –0.5 0.5 — 0.5 — 0.40 — 0.5 — ns ns ns ns ns ns ns ns 7 7 3 3 3 3
Setup Times
Address Input Setup Time Control Input Setup Time Data Input Setup Time 0.4 0.4 0.28 — — — 0.4 0.4 0.3 — — — 0.5 0.5 0.35 — — — 0.5 0.5 0.35 — — — 0.6 0.6 0.4 — — — 0.7 0.7 0.5 — — — ns ns ns 2
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes
-333
-300
-267
-250
-200
-167
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
AC Electrical Characteristics (Continued)
Parameter Hold Times
Address Input Hold Time Control Input Hold Time Data Input Hold Time tKHAX tKHIX tKHDX 0.4 0.4 0.28 — — — 0.4 0.4 0.3 — — — 0.5 0.5 0.35 — — — 0.5 0.5 0.35 — — — 0.6 0.6 0.4 — — — 0.7 0.7 0.5 — — — ns ns ns
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes:
1. 2. 3. 4. All Address inputs must meet the specified setup and hold times for all latching clock edges. Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36). If C, C are tied high, K, K become the references for C, C timing parameters To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations.
5. 6. 7.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes
-333
-300
-267
-250
-200
-167
C and C Controlled Read First Timing Diagram
NOP KHKL KHKH KLKH Read A Read B NOP Write C Read D
Rev: 1.01 9/2005
KHnKH AVKH KHAX A IVKH KHIX B C D IVKH KHIX IVKH KHIX C KHKL KHKH KLKH C+1 KHnKH CHQX CHQV A A+1 CHQX1 B B+1 C DVKH C+1 KHDX CHCQX CHCQV CQHQV CQHQX
K
K
Address
LD
R/W
22/37
BWx
C
C
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DQ
CQ
CQ
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
© 2005, GSI Technology
K and K Controlled Read First Timing Diagram
NOP KHKL KHKH KLKH Read A Read B NOP Write C Read D
Rev: 1.01 9/2005
KHnKH KHAX AVKH A BVKH KHBX B C D BVKH KHBX BVKH KHBX C DVKH KHQX1 A KHCQV KHCQX A+1 B KHQV B+1 KHQX C C+1 KHDX C+1 KHCQX KHCQV CQHQV CQHQX
K
K
Address
LD
R/W
23/37
BWx
DQ1
CQ
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CQ
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
© 2005, GSI Technology
C and C Controlled Write First Timing Diagram
NOP KHKL KHKH KLKH Write A Read B Read C NOP Write D NOP
Rev: 1.01 9/2005
KHnKH AVKH KHAX A IVKH KHIX B C D E IVKH KHIX IVKH KHIX A KHKL KHKH KLKH A+1 D D+1 KHnKH KHDX DVKH A CHCQX CHCQV A+1 B CHQX1 CHQV B+1 C CHQX C+1 D D+1 CHCQX CHCQV CQHQV CQHQX
K
K
Address
LD
R/W
24/37
BWx
C
C
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DQ
CQ
CQ
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
© 2005, GSI Technology
K and K Controlled Write First Timing Diagram
NOP KHKL KHKH KLKH Write A Read B Read C NOP Write D NOP
Rev: 1.01 9/2005
KHnKH AVKH KHAX A BVKH KHBX B C D E BVKH KHBX BVKH KHBX A KHDX DVKH A KHCQV A+1 B KHQX1 KHQV B+1 C KHQX C+1 D D+1 A+1 D D+1 KHCQX KHCQV CQHQV CQHQX
K
K
Address
LD
R/W
25/37
BWx
DQ
KHCQX
CQ
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CQ
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
© 2005, GSI Technology
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
JTAG Port Operation
Overview The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE Standard, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDD. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
I/O
In In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
TDI
Test Data In
In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.
JTAG Port Registers
Overview The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
· · ·
108
·
·
·
·
·
·
· ·
1
Boundary Scan Register
0
Bypass Register
210
0
Instruction Register TDI ID Code Register
31 30 29
TDO
·
···
210
Control Signals TMS TCK Test Access Port (TAP) Controller
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
ID Register Contents
Bit # x36 x18 x9 x8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 0 011011001 0 011011001 0 011011001 0 011011001 0 1 1 1 1
Tap Controller Instruction Set
Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
0
Run Test Idle
Select DR
0 1
Select IR
0 1
Capture DR
0
Capture IR
0
Shift DR
1 1
0 1
Shift IR
1
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
0
Exit2 IR
1
0
Update DR
1 0 1
Update IR
0
Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins.
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Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary Instruction
EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD RFU RFU BYPASS
Code
000 001 010 011 100 101 110 111
Description
Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Do not use this instruction; Reserved for Future Use. Do not use this instruction; Reserved for Future Use. Places Bypass Register between TDI and TDO.
Notes
1 1, 2 1 1 1 1 1 1
Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
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JTAG Port Recommended Operating Conditions and DC Characteristics Parameter
Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage (IOH = –2 mA) Output Low Voltage (IOL = 2 mA)
Symbol
VDDQ VIH VIL VOH VOL
Min.
1.7 1.3 –0.3 1.4 VSS
Typ.
1.8 — — — —
Max.
1.9 VDD + 0.3 0.5 VDD 0.4
Unit
V V V V V
Note: The input level of SRAM pin is to follow the SRAM DC specification.
JTAG Port AC Test Conditions Parameter
Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Notes: 1. Distributed scope and test jig capacitance. 2. Test conditions as shown unless otherwise noted.
Symbol
VIH/VIL TR/TF
Min
1.3/0.5 1.0/1.0 0.9
Unit
V ns V
Rev: 1.01 9/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167 JTAG Port Timing Diagram
tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input
tTKH
tTKL
JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min. 50 20 20 5 5 5 5 5 5 0 Max — — — — — — — — — 10 Unit ns ns ns ns ns ns ns ns ns ns
Rev: 1.01 9/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.60 (165x)
A1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
1.0 10.0 B 0.20(4x) 15±0.05 1.0
17±0.05
14.0
A
Rev: 1.01 9/2005
0.36~0.46 1.50 MAX.
C
SEATING PLANE
0.20 C
33/37
1.0
1.0
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Ordering Information—GSI SigmaCIO DDR-II SRAM Org
8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18
Part Number1
GS8662T08E-333 GS8662T08E-300 GS8662T08E-250 GS8662T08E-200 GS8662T08E-167 GS8662T08E-333I GS8662T08E-300I GS8662T08E-250I GS8662T08E-200I GS8662T08E-167I GS8662T09E-333 GS8662T09E-300 GS8662T09E-250 GS8662T09E-200 GS8662T09E-167 GS8662T09E-333I GS8662T09E-300I GS8662T09E-250I GS8662T09E-200I GS8662T09E-167I GS8662T18E-333 GS8662T18E-300 GS8662T18E-267 GS8662T18E-250 GS8662T18E-200 GS8662T18E-167 GS8662T18E-333I GS8662T18E-300I GS8662T18E-267I GS8662T18E-250I
Type
SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM
Package
165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA
Speed (MHz)
333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 267 250 200 167 333 300 267 250
TA2
C C C C C I I I I I C C C C C I I I I I C C C C C C I I I I
Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.01 9/2005 34/37 © 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Ordering Information—GSI SigmaCIO DDR-II SRAM Org
4M x 18 4M x 18 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9
Part Number1
GS8662T18E-200I GS8662T18E-167I GS8662T36E-333 GS8662T36E-300 GS8662T36E-250 GS8662T36E-200 GS8662T36E-167 GS8662T36E-333I GS8662T36E-300I GS8662T36E-250I GS8662T36E-200I GS8662T36E-167I GS8662T08GE-333 GS8662T08GE-300 GS8662T08GE-250 GS8662T08GE-200 GS8662T08GE-167 GS8662T08GE-333I GS8662T08GE-300I GS8662T08GE-250I GS8662T08GE-200I GS8662T08GE-167I GS8662T09GE-333 GS8662T09GE-300 GS8662T09GE-250 GS8662T09GE-200 GS8662T09GE-167 GS8662T09GE-333I GS8662T09GE-300I GS8662T09GE-250I GS8662T09GE-200I
Type
SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM
Package
165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA
Speed (MHz)
200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200
TA2
I I C C C C C I I I I I C C C C C I I I I I C C C C C I I I I
Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.01 9/2005
35/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Ordering Information—GSI SigmaCIO DDR-II SRAM Org
8M x 9 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36
Part Number1
GS8662T09GE-167I GS8662T18GE-333 GS8662T18GE-300 GS8662T18GE-267 GS8662T18GE-250 GS8662T18GE-200 GS8662T18GE-167 GS8662T18GE-333I GS8662T18GE-300I GS8662T18GE-267I GS8662T18GE-250I GS8662T18GE-200I GS8662T18GE-167I GS8662T36GE-333 GS8662T36GE-300 GS8662T36GE-250 GS8662T36GE-200 GS8662T36GE-167 GS8662T36GE-333I GS8662T36GE-300I GS8662T36GE-250I GS8662T36GE-200I GS8662T36GE-167I
Type
SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM SigmaCIO DDR-II B2 SRAM
Package
RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA
Speed (MHz)
167 333 300 267 250 200 167 333 300 267 250 200 167 333 300 250 200 167 333 300 250 200 167
TA2
I C C C C C C I I I I I I C C C C C I I I I I
Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.01 9/2005
36/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167
Revision History Types of Changes Format or Content
Format Content
Rev. Code: Old; New
Revisions
GS8662Txx_r1 GS8662Txx_r1; GS8662Txx_r1_01
• Creation of new datasheet • Added RoHS-compliant information
Rev: 1.01 9/2005
37/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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