GS880E32T-11

Preliminary GS880E18/32/36T-11/11.5/100/80/66 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipelined operation • Dual Cycle Deselect (DCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock Control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • 100-lead TQFP package -11 -11.5 -100 -80 -66 10 ns 10 ns 12.5 ns 15 ns Pipeline tCycle 10 ns 4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns 3-1-1-1 tKQ 225 mA 225 mA 225 mA 200 mA 185 mA IDD 11 ns 11.5 ns 12 ns 14 ns 18 ns Flow tKQ 15 ns 15 ns 15 ns 20 ns Through tCycle 15 ns 2-1-1-1 IDD 180 mA 180 mA 180 mA 175 mA 165 mA 512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs Flow Through / Pipeline Reads 100 MHz–66 MHz 3.3 V VDD 3.3 V and 2.5 V I/O interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. DCD Pipelined Reads The GS880E18/32/36T is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs. Functional Description Applications The GS880E18/32/36T is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Sleep Mode Low power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS880E18/32/36T operates on a 3.3 V power supply, and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or Rev: 1.11 11/2000 1/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 GS880E18 100-Pin TQFP Pinout NC NC NC VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6 A7 E1 E2 NC NC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9 A18 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC Rev: 1.11 11/2000 LBO A5 A4 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. A3 A2 A1 A0 NC NC V SS VDD NC A17 A10 A11 A12 A13 A14 A15 A16 2/25 © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 GS880E32 100-Pin TQFP Pinout NC DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9 NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC Rev: 1.11 11/2000 LBO A5 A4 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. A3 A2 A1 A0 NC NC VSS V DD NC A17 A10 A11 A12 A13 A14 A15 A16 3/25 © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 GS880E36 100-Pin TQFP Pinout DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9 DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9 Rev: 1.11 11/2000 LBO A5 A4 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. A3 A2 A1 A0 NC NC VSS V DD NC A17 A10 A11 A12 A13 A14 A15 A16 4/25 © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43 80 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 51, 80, 1, 30 51, 80, 1, 30 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 51, 52, 53, 56, 57 75, 78, 79, 1, 2, 3, 6, 7 25, 28, 29, 30 87 93, 94 95, 96 95, 96 89 88 98, 92 97 86 83 84, 85 64 14 31 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 16, 38, 39, 42, 66 Symbol A0, A1 A2–A17 A18 DQA1–DQA8 DQB1–DQB8 DQC1–DQC8 DQD1–DQD8 DQA9, DQB9, DQC9, DQD9 NC DQA1–DQA9 DQB1–DQB9 NC BW BA, BB BC, BD NC CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ NC Typ e I I I I/O Description Address field LSBs and Address Counter preset Inputs Address Inputs Address Inputs Data Input and Output pins (x32, x36 Version) I/O — I/O Data Input and Output pins No Connect (x32 Version) Data Input and Output pins — I I I — I I I I I I I I I I I I I — No Connect Byte Write—Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low (x32, x36 Version) No Connect (x18 Version) Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect. Rev: 1.11 11/2000 5/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 GS880E32 Block Diagram Register A0–An D Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1 LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q D Register 36 4 36 D BB Q Register D BC Q Q Register D Register Q Register D D BD Q Register D Q E1 E2 E3 Register D Q Register D Q FT G Power Down Control 0 ZZ DQx0–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.11 11/2000 6/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Pin Name LBO FT ZZ State L H or NC L H or NC L or NC H Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Note: There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. Burst Counter Sequences Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 1st address 2nd address 3rd address 4th address Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 BPR 1999.05.18 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Byte Write Truth Table Function Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes GW H H H H H H H L BW H L L L L L L X BA X H L H H H L X BB X H H L H H L X BC X H H H L H L X BD X H H H H L L X Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.11 11/2000 7/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Synchronous Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None External External External Next Next Next Next Current Current Current Current State Diagram Key5 X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X H E22 (x36only) ADSP ADSC X L H L H H H X H X H X H X L X L X L L H H H H H H H H ADV X X X X X X L L L L H H H H W3 X X X X F T F F T T F F T T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D D X F F T T T X X X X X X X X Notes: 1. X = Don’t Care, H = High, L = Low. 2. For x36 Version, E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.11 11/2000 8/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.11 11/2000 9/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.11 11/2000 10/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to VDD –0.5 to 6 –0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V V mA mA W o C oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol VDD VDDQ VIH VIL TA TA Min. 3.135 2.375 1.7 –0.3 0 –40 Typ. 3.3 2.5 — — 25 25 Max. 3.6 VDD VDD +0.3 0.8 70 85 Unit V V V V °C °C Notes 1 2 2 3 3 Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V (i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC. Rev: 1.11 11/2000 11/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Undershoot Measurement and Timing VIH VDD + 2.0 V VSS 50% VSS – 2.0 V 20% tKC VIL 50% VDD Overshoot Measurement and Timing 20% tKC Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Input Capacitance Input/Output Capacitance Note: These parameters are sample tested. Symbol CIN CI/O Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF Package Thermal Characteristics Rating Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Layer Board single four — Symbol RΘJA RΘJA RΘJC Max 40 24 9 Unit °C/W °C/W °C/W Notes 1,2 1,2 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1.11 11/2000 12/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions 2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VT = 1.25 V * Distributed Test Jig Capacitance Output Load 2 2.5 V 30pF* DQ 5pF* 225Ω 225Ω DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current Mode Pin Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IINZZ IINM IOL VOH VOH VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –8 mA, VDDQ = 2.375 V IOH = –8 mA, VDDQ = 3.135 V IOL = 8 mA Min –1 uA –1 uA –1 uA –300 uA –1 uA –1 uA 1.7 V 2.4 V — Max 1 uA 1 uA 300 uA 1 uA 1 uA 1 uA — — 0.4 V Rev: 1.11 11/2000 13/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Operating Currents -11 Parameter Test Conditions Symbol IDD Pipeline IDD Flow-Thru ISB Pipeline ISB Flow-Thru IDD Pipeline IDD Flow-Thru 0 to 70°C 225 180 30 30 80 65 –40 to 85°C 235 190 40 40 90 75 -11.5 0 to 70°C 225 180 30 30 80 65 –40 to 85°C 235 190 40 40 90 75 -100 0 to 70°C 225 180 30 30 80 65 –40 to 85°C 235 190 40 40 90 75 0 to 70°C 200 175 30 30 70 55 -80 –40 to 85°C 210 185 40 40 80 65 0 to 70°C 185 165 30 30 60 50 -66 –40 to 85°C 195 175 40 40 70 60 Unit Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open mA mA mA mA mA mA Standby Current ZZ ≥ VDD - 0.2V Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL Rev: 1.11 11/2000 14/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 AC Electrical Characteristics Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time FlowThru Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ 1 -11 Min 10 — 1.5 1.5 15.0 — 3.0 3.0 1.7 2 1.5 — 0 — 1.5 0.5 5 1 20 Max — 4.0 — — — 11.0 — — — — 4.0 4.0 — 4.0 — — — — — 10 — -11.5 Min Max — 4.0 — — — 11.5 — — — — 4.2 4.2 — 4.2 — — — — — 10 — 1.5 1.5 -100 Min Max — 4.0 — — — 12.0 — — — — 4.5 4.5 — 4.5 — — — — — Min 12.5 — 1.5 1.5 15.0 — 3.0 3.0 2 2.2 1.5 — 0 — 2.0 0.5 5 1 20 -80 Max — 4.5 — — — 14.0 — — — — 4.5 4.5 — 4.5 — — — — — Min 15 — 1.5 1.5 20 — 3.0 3.0 2.3 2.5 1.5 — 0 — 2.0 0.5 5 1 20 -66 Max — 5 — — — 18 — — — — 4.8 4.8 — 4.8 — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 1.5 15.0 — 3.0 3.0 1.7 2 1.5 — 0 — 2.0 0.5 5 1 20 tKC tKQ tKQX tLZ1 tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tS tH tZZS2 tZZH2 tZZR 15.0 — 3.0 3.0 2 2.2 1.5 — 0 — 2.0 0.5 5 1 20 Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.11 11/2000 15/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Write Cycle Timing Single Write Burst Write Write Deselected CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH ADV must be inactive for ADSP Write WR2 WR3 A0–An GW WR1 tS tH tS tH BW tS tH BA–BD tS tH WR1 WR1 WR2 WR3 WR3 E1 masks ADSP E1 tS tH Deselected with E2 E2 tS tH E2 and E3 only sampled with ADSP or ADSC E3 G tS tH Write specified byte for 2A and all bytes for 2B, 2c& 2D D2A D2B D2C D2D D3A DQA–DQD Hi-Z D1A Rev: 1.11 11/2000 16/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Flow Through Read-Write Cycle Timing Single Read Single Write Burst Read CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An GW RD1 WR1 RD2 tS tH tS tS tH BW BA–BD tS tH tS WR1 tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 tOHZ E3 tOE G tKQ tS Q1A tH Q2A Q2B Q2c Q2D Q2A DQA–DQD Hi-Z D1A Burst wrap around to it’s initial state Rev: 1.11 11/2000 17/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Flow Through Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0–An GW RD1 tS RD2 RD3 tH tS tH BW BA–BD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2 E2 tS tH E3 tOE tOHZ G tOLZ tKQX Q1A tLZ tKQ tHZ Q2A Q2B Q2C Q2D Q3A tKQX DQA–DQD Hi-Z Rev: 1.11 11/2000 18/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Pipelined DCD Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tS tH ADSC initiated read tKC ADSP is blocked by E1 inactive ADSP ADSC tS tH Suspend Burst ADV tS tH A0–An GW RD1 tS RD2 RD3 tH tS tH BW BA–BD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC E2 tS tH Deselected with E2 E3 tOE G tOHZ Hi-Z tOLZ Q1A tLZ tHZ tKQ tKQX Q2A Q2B Q2c Q2D tKQX Q3A DQA–DQD Rev: 1.11 11/2000 19/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Pipelined DCD Read-Write Cycle Timing Single Write Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An GW RD1 WR1 RD2 tS tH tS tH BW tS tH BA–BD tS tH WR1 E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 tOE tOHZ E3 G DQA–DQD Hi-Z tKQ Q1A tS tH D1A Q2A Q2B Q2c Q2D Rev: 1.11 11/2000 20/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Sleep Mode Timing Diagram CK tS tH tKC tKH tKL ADSP ADSC tZZS ~ ~~~~ ~ ~~~~ ~ tZZH tZZR ZZ Snooze Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 1.11 11/2000 21/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 VD D Q IOut I Out (mA) 0.0 VOut -20.0 VS S -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Down) VDDQ - V Out (Pull Up) 3.6V PD HD 3.3V PD HD 3.1V PD HD 3.1V PU HD 3.3V PU HD 3.6V PU HD Rev: 1.11 11/2000 22/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 TQFP Package Drawing L Symbol A1 A2 b c D D1 E E1 e L L1 Y θ θ c P in 1 Description Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle Min. Nom. Max 0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 — 0.45 — — 0° 0.10 1.40 0.30 — 22.0 20.0 16.0 14.0 0.65 0.60 1.00 — — 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 — 0.75 — 0.10 L1 D D1 e b A1 Y A2 7° E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. BPR 1999.05.18 Rev: 1.11 11/2000 23/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Ordering Information for GSI Synchronous Burst RAMs Org 514K x 18 514K x 18 514K x 18 514K x 18 514K x 18 256K x 32 256K x 32 256K x 32 256K x 32 256K x 32 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 514K x 18 514K x 18 514K x 18 514K x 18 514K x 18 256K x 32 256K x 32 256K x 32 256K x 32 256K x 32 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 Part Number1 GS880E18T-11 GS880E18T-11.5 GS880E18T-100 GS880E18T-80 GS880E18T-66 GS880E32T-11 GS880E32T-11.5 GS880E32T-100 GS880E32T-80 GS880E32T-66 GS880E36T-11 GS880E36T-11.5 GS880E36T-100 GS880E36T-80 GS880E36T-66 GS880E18T-11I GS880E18T-11.5I GS880E18T-100I GS880E18T-80I GS880E18T-66I GS880E32T-11I GS880E32T-11.5I GS880E32T-100I GS880E32T-80I GS880E32T-66I GS880E36T-11I GS880E36T-11.5I GS880E36T-100I GS880E36T-80I GS880E36T-66I Type DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Speed2 (MHz/ns) 100/11 100/11.5 100/12 80/14 66/18 100/11 100/11.5 100/12 80/14 66/18 100/11 100/11.5 100/12 80/14 66/18 100/11 100/11.5 100/12 80/14 66/18 100/11 100/11.5 100/12 80/14 66/18 100/11 100/11.5 100/12 80/14 66/18 TA3 C C C C C C C C C C C C C C C I I I I I I I I I I I I I I I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880E18TT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.11 11/2000 24/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Revision History DS/DateRev. Code: Old; New Types of Changes Page;Revisions;Reason Format or Content • Last Page/Fixed “GSGS..” in Ordering Information Note. • Fromatted Pin Outs and Pin Description to new small caps. • Formatted Block diagrams to new small caps. • Formatted Timing Diagrams to new small caps. • Changed “Flow thru” to “Flow Through” in Timing Diagrams. • Package Diagram/Changed “Dimesion” to “Dimension”. • 5/Fixed pin description table to match pinouts. • Pin Description/Changed chip enables to match pins. • Pin Description/Changed pin 80 from NC to Address Input. • Pin Description/Rearranged Address Inputs to match order of Pinout • Package Diagram/Changed Dimension D Max from 20.1 to 22.1 • Changed Flow Through Read-Write Cycle Timing Diagram for accuracy. • Changed order of TQFP Address Inputs to match pinout. • Changed order of TQFP DATA Input and Output pins to match pinout. • New GSI Logo. • Changed all speed bin information (headings, references, tables, ordering info..) to reflect 150 - 80Mhz Format/Typos GS880E18/32/36TRev1.04h 5/1999; 1.05 9/1999I Content GS880E18/32/36T1.05 11/ 1999K880E18/32/36T1.06 1/ 2000L Content GS880E18/32/36T1.06 1/ 2000L; GS880E18/32/36T1.07 3/ 2000N; GS880E18/32/36T1.07 3/ 2000N; GS880E18/32/36T1.08 3/ 2000O; Content • Corrections to AC Electrical Characteristics Table Content GS880E18/32/36T1.08 3/ 2000O; 880E183236_r1_09 880E18_r1_09; 880E18_r1_10 880E18_r1_10; 880E18_r1_11 Content/Format • Removed 150 MHz speed bin • Changed 133 MHz and 117 MHz speed bins to 11 ns and 11.5 ns (100 MHz) numbers • Updated format to comply with Technical Publications standards • Updated Capitance table—removed Input row and changed Output row to I/O • Corrected typo in AC Electrical Characteristics table Content Content Rev: 1.11 11/2000 25/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.