HMN4M8DV-70

HANBit HMN4M8DV(N) Non-Volatile SRAM MODULE 32Mbit (4,096K x 8-Bit), 40Pin-DIP, 3.3V Part No. HMN4M8DV(N) GENERAL DESCRIPTION The HMN4M8DV Nonvolatile SRAM is a 33,554,432-bit static RAM organized as 4,194,304 bytes by 8 bits. The HMN4M8DV has a self-contained lithium energy source provide reliable non -volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after V CC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain t he memory until after V CC returns valid. The HMN4M8DV uses extremely low standby current CMOS SRAM ’s, coupled with small lithium coin cells to provide non volatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES w Access time : 55, 70ns w High-density design : 32Mbit Design w Battery internally isolated until power is applied w Industry-standard 40-pin 4,096K x 8 pinout w Unlimited write cycles w Data retention in the absence of VCC w 5-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss PIN ASSIGNMENT A21 A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VCC A19 NC A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 NC A21 A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC VCC A19 NC A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 NC 36-pin Encapsulated Package w Package Option - HMN4M8DV - HMN4M8DVN - 36 Pin DIP Package - 40 Pin DIP Package 40-pin Encapsulated Package URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 1 HANBit Electronics Co.,Ltd HANBit FUNCTIONAL DESCRIPTION HMN4M8DV(N) The HMN4M8DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A 0-A19) defines which of the 4,194,304 bytes of data is accessed. Valid data will be a vailable to the eight data output drivers within t ACC (access time) after the last address input signal is stable. When power is valid, the HMN4M8DV operates as a standard CMOS SRAM. During power -down and power-up cycles, the HMN4M8DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents. The HMN4M8DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will d etermine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in t ODW from its falling edge. The HMN4M8DV provides full functional capability for V cc greater than 4.5 V and write protects by 4.37 V nominal. Power-down/power-up control circuitry constantly monitors the V cc supply for a power-fail-detect threshold V PFD. When VCC falls below the V PFD threshold, the SRAM automatically write -protects the data. All inputs to the RAM become “ don’t care” and all outputs are high impedance. As V cc falls below approximately 3 V, the power switching circuit connects the lithium energy soure to RAM to retain d ata. During power-up, when Vcc rises above approximately 3.0 volts, the power switching circuit connects external V cc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 4.5 volts. BLOCK DIAGRAM PIN DESCRIPTION A0-A19 /OE /WE Power /CE A20-A21 Power – Fail Control Lithium Cell (1M x 8) x 4 SRAM Block CE2 /CE1 /CE CON VCC DQ0-DQ7 A0-A21 : Address Input /CE : Chip Enable VSS : Ground DQ0-DQ7 : Data In / Data Out /WE : Write Enable /OE : Output Enable VCC: Power (+5V) NC : No Connection URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 2 HANBit Electronics Co.,Ltd HANBit TRUTH TABLE MODE Not selected Output disable Read W rite /OE X H L X /CE H L L L CE2 X H H H /WE X H H L HMN4M8DV(N) I/O OPERATION High Z High Z DOUT DIN POWER Standby Active Active Active ABSOLUTE MAXIMUM RATINGS PARAMETER DC voltage applied on V CC relative to VSS DC Voltage applied on any pin excluding V CC relative to VSS Operating temperature Storage temperature Temperature under bias Soldering temperature NOTE: SYMBOL VCC VT RATING -0.5V to VCC +0.2V -0.2V to 4.6V 0 to 70°C -40 to 85°C -65°C to 150°C -40°C to 85°C 260°C For 10 second Commercial Industrial CONDITIONS TOPR TSTG TBIAS TSOLDER Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR ) PARAMETER Supply Voltage Ground Input high voltage Input low voltage NOTE: SYMBOL VCC VSS VIH VIL MIN 3.0V 0 2.2 -0.2 2) TYPICAL 3.3V 0 - MAX 3.6V 0 VCC+0.3V 0.6V 1) 1. Overshoot: VCC+2.0V in case of pulse width ≤20ns. 3. Overshoot and undershoot are sampled, not 100% tested. 2. Undershoot: -2.0V in case of pulse width ≤20ns. URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 3 HANBit Electronics Co.,Ltd HANBit CAPACITANCE (TA=25℃ , f=1MHz) DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS Input voltage = 0V Output voltage = 0V SYMBOL CIN CI/O MAX 8 10 HMN4M8DV(N) MIN - UNIT pF pF NOTE: 1. Capacitance is sampled, not 100% tested. DC AND OPERATION CHARACTERISTICS (TA= TOPR, VCCmin £ VCC≤ VCCmax ) PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output low voltage Standby supply current CONDITIONS VIN=VSS to VCC /CE=VIH or /OE=VIH or /WE=VIL IOH=-1.0 mA IOL= 2.1 mA /CE≥ VCC-0.2V Cycle time=Min, 100% duty, II/O=0㎃ , /CE