HM628512LRR-7SL

HM628512 Series 524288-word × 8-bit High Speed CMOS Static RAM ADE-203-236F (Z) Rev. 6.0 Jun. 9, 1995 Description The Hitachi HM628512 is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes igher density, higher performance and low power consumption by employing 0.5 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP, is available for high density mounting. LP-version is suitable for battery backup system. Features • High speed: Fast access time:  55/65/70 ns (max) • Low power  Standby: 10 µW (typ) (L/L-SL version)  Operation: 75 mW (typ) (f = 1 MHz) • Single 5 V supply • Completely static memory No clock or timing strobe required • Equal access and cycle times • Common data input and output: Three state output • Directly TTL compatible: All inputs and outputs • Capability of battery backup operation (L/L-SL version) HM628512 Series Ordering Information Type No. HM628512P-5 HM628512P-7 HM628512LP-5 HM628512LP-7A HM628512LP-7 HM628512LP-5SL HM628512LP-7SL HM628512FP-5 HM628512FP-7 HM628512LFP-5 HM628512LFP-7A HM628512LFP-7 HM628512LFP-5SL HM628512LFP-7SL HM628512LTT-5 HM628512LTT-7A HM628512LTT-7 HM628512LTT-5SL HM628512LTT-7SL HM628512LRR-5 HM628512LRR-7A HM628512LRR-7 HM628512LRR-5SL HM628512LRR-7SL Access Time 55 ns 70 ns 55 ns 65 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 65 ns 70 ns 55 ns 70 ns 55 ns 65 ns 70 ns 55 ns 70 ns 55 ns 65 ns 70 ns 55 ns 70 ns 400-mil 32-pin plastic TSOP II reverse (TTP-32DR) 400-mil 32-pin plastic TSOP II (TTP-32D) 525-mil 32-pin plastic SOP (FP-32D) Package 600-mil 32-pin plastic DIP (DP-32) 2 HM628512 Series Pin Arrangement HM628512P/LP Series HM628512FP/LFP Series A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS HM628512LTT Series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) HM628512LRR Series 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 Pin Description Pin name A0 – A18 I/O0 – I/O7 CS OE WE VCC VSS Function Address Input/output Chip select Output enable Write enable Power supply Ground 3 HM628512 Series Block Diagram V CC V SS • • • • • A5 A6 A0 A1 A2 A3 A4 A7 A12 A14 Row Decoder Memory Matrix 1,024 × 4,096 I/O0 Input Data Control I/O7 • • Column I/O Column Decoder • • A13 A17 A15 A10 A11 A9 A8 A16 A18 • • CS WE OE Timing Pulse Generator Read/Write Control 4 HM628512 Series Function Table WE X H H L L CS H L L L L OE X H L H L Mode Not selected Output disable Read Write Write VCC Current I SB , I SB1 I CC I CC I CC I CC Dout Pin High-Z High-Z Dout Din Din Ref. Cycle — — Read cycle Write cycle (1) Write cycle (2) Note: X: H or L Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias *1 Symbol VT PT Topr Tstg Tbias Value –0.5 to +7.0 1.0 0 to +70 –55 to +125 –10 to +85 *2 Unit V W °C °C °C Notes: 1. Relative to VSS . 2. –3.0 V for pulse half-width ≤ 30 ns Recommended DC Operating Conditions (Ta = 0 to +70 °C) Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 –0.3 *1 Typ 5.0 0 — — Max 5.5 0 6.0 0.8 Unit V V V V 1. –3.0 V for pulse half-width ≤ 30 ns 5 HM628512 Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10% , VSS = 0 V) Parameter Input leakage current Output leakage current Operating power supply current: DC Symbol Min Typ*1 Max |ILI| |ILO | I CC READ I CC WRITE Operating power supply current -5/7A I CC1 -7 Operating power supply current I CC1 I CC2 — — — — — — — — — 15 20 70 60 15 1 1 25 45 100 90 30 Unit µA µA mA mA mA mA mA Test Conditions Vin = VSS to V CC CS = VIH or OE = VIH or WE = VIL, VI/O = VSS to V CC CS = VIL, WE = VIH others = VIH/V IL, I I/O = 0 mA CS = VIL, WE = VIL others = VIH/V IL, I I/O = 0 mA Min cycle, duty = 100% CS = VIL, others = VIH/V IL I I/O = 0 mA Cycle time = 1 µs, duty = 100% I I/O = 0 mA, CS ≤ 0.2 V VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V CS = VIH Vin ≥ 0 V, CS ≥ V CC – 0.2 V Standby power supply current: DC Standby power supply current (1): DC I SB I SB1 — — — — 1 0.02 2 2 — — 3 2 100 50 *3 *2 mA mA µA µA V V Output low voltage Output high voltage VOL VOH — 2.4 0.4 — I OL = 2.1 mA I OH = –1.0 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed. 2. This characteristics is guaranteed only for L version. 3. This characteristics is guaranteed only for L-SL version. Capacitance (Ta = 25°C, f = 1 MHz) Parameter Input capacitance *1 *1 Symbol Cin CI/O Typ — — Max 8 10 Unit pF pF Test Conditions Vin = 0 V VI/O = 0 V Input/output capacitance Note: 1. This parameter is sampled and not 100% tested. 6 HM628512 Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.) Test Conditions • • • • Input pulse levels: 0.8 V to 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate + C L (100 pF) (HM628512-7A/7) 1 TTL Gate + C L (50 pF) (HM628512-5) (Including scope & jig) Read Cycle HM628512 -5 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Chip selection to output in low-Z Output enable to output in low-Z Symbol t RC t AA t CO t OE t LZ t OLZ Min 55 — — — 10 5 0 0 10 Max — 55 55 25 — — 20 20 — -7A Min 65 — — — 10 5 0 0 10 Max — 60 65 30 — — 20 20 — -7 Min 70 — — — 10 5 0 0 10 Max — 70 70 35 — — 25 25 — Unit ns ns ns ns ns ns ns ns ns 2 2 1, 2 1, 2 Notes Chip deselection to output in high-Z t HZ Output disable to output in high-Z Output hold from address change t OHZ t OH Notes: 1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 7 HM628512 Series Read Timing Waveform*1 t RC Address t AA t CO CS t LZ t OE t OLZ OE t OHZ t HZ Dout Valid Data t OH Note: 1. WE is high for read cycle. 8 HM628512 Series Write Cycle HM628512 -5 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time WE to output in high-Z Data to write time overlap Data hold from write time Output active from output in high-Z Output disable to output in high-Z Symbol t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW t OHZ Min 55 50 0 50 40 5 0 25 0 5 0 Max — — — — — — 20 — — — 20 -7A Min 55 50 0 50 40 5 0 25 0 5 0 Max — — — — — — 20 — — — 20 -7 Min 70 60 0 60 50 5 0 30 0 5 0 Max — — — — — — 25 — — — 25 Unit ns ns ns ns ns ns ns ns ns ns ns 6 5, 6 1, 8 4 5, 6, 7 2 3 Notes Notes: 1. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 2. t CW is measured from CS going low to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the earlier of WE or CS going high to the end of write cycle. 5. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 6. This parameter is sampled and not 100% tested. 7. t WHZ is defined as the time at which the outputs acheive the open circuit conditons and is not referred to output voltage levels. 8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP ≥ tDW min + tWHZ max 9 HM628512 Series Write Timing Waveform (1) (OE Clock) t WC Address t AW OE t CW CS *1 t WR t AS t WP WE t OHZ Dout t DW Din Valid Data t DH Note: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output remain in a high impedance state. 10 HM628512 Series Write Timing Waveform (2) (OE Low Fixed) t WC Address t CW t WR CS *1 t AW t WP WE t AS t WHZ t OW t OH *2 *3 Dout t DW Din t DH *4 Valid Data Notes: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output remain in a high impedance state. 2. Dout is the same phase of the write data of this write cycle. 3. Dout is the read data of next address. 4. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 11 HM628512 Series Low VCC Data Retention Characteristics (Ta = 0 to +70 °C) This characteristics is guaranteed only for L/L-SL version. Parameter VCC for data retention Data retention current Symbol VDR I CCDR Min 2 — — Chip deselect to data retention time Operation recovery time t CDR tR 0 5 Typ — 1 1 *4 *4 Max — 50 15 — — *1 *2 Unit V µA µA ns ms Test Conditions*3 CS ≥ V CC – 0.2 V, Vin ≥ 0 V VCC = 3.0 V, Vin ≥ 0 V CS ≥ V CC – 0.2 V See retention waveform — — Notes: 1. For L-version and 20 µA (max.) at Ta = 0 to 40° C. 2. For SL-version and 3 µA (max.) at Ta = 0 to 40° C. 3. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = 25°C and specified loading, and not guaranteed. Low V CC Data Retention Timing Waveform (CS Controlled) t CDR V CC 4.5 V Data retention mode tR 2.4 V V DR CS 0V CS ≥ VCC – 0.2 V 12 HM628512 Series Package Dimensions HM62851P/LP Series (DP-32) Unit: mm 32 41.9 42.5 Max 17 13.4 13.7 Max 1 2.3 Max 5.08 Max 1.2 16 15.24 0.51 Min 2.54 Min 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.11 13 HM628512 Series HM628512FP/LFP Series (FP-32D) Unit: mm 20.45 20.95 Max 32 17 11.7 Max 1 1.0 Max 14.14 ± 0.30 16 3.0 Max + 0.13 – 0.07 1.42 0.22 1.27 0.10 0.40 + 0.05 – 0.10 0.15 M 0.05 Min 0–8° 0.8 HM628512LTT Series (TTP-32D) 20.95 21.35 Max 32 17 Unit: mm 1 1.27 0.21 M 16 10.16 0.40 ± 0.10 1.15 Max 0.17 ± 0.05 11.76 ± 0.2 0 – 5° 1.20 Max 0.10 14 0.08 Min 0.18 Max 0.50 ± 0.10 HM628512 Series HM628512LRR Series (TTP-32DR) 20.95 21.35 Max 1 16 Unit: mm 32 1.27 0.21 M 17 10.16 0.40 ± 0.10 1.15 Max 0.17 ± 0.05 11.76 ± 0.2 0 – 5° 1.20 Max 0.10 0.08 Min 0.18 Max 0.50 ± 0.10 15