2SJ319L

2SJ319(L), 2SJ319(S) Silicon P-Channel MOS FET Application High speed power switching Features • • • • • Low on-resistance High speed switching Low drive current No secondary breakdown Suitable for switching regulator, DC-DC converter Outline DPAK-1 4 4 1 1 D G 1. Gate 2. Drain 3. Source 4. Drain S 2 3 23 2SJ319(L), 2SJ319(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Channel dissipation Channel temperature Storage temperature Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at TC = 25°C Symbol VDSS VGSS ID I D(pulse)* I DR Pch* Tch Tstg 2 1 Ratings –200 ±20 –3 –12 –3 20 150 –55 to +150 Unit V V A A A W °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Symbol Min V(BR)DSS V(BR)GSS I GSS –200 ±20 — — –2.0 — 1.0 — — — — — — — — — Typ — — — — — 1.7 1.7 330 130 25 10 30 40 30 –1.15 180 Max — — ±10 –100 –4.0 2.3 — — — — — — — — — — Unit V V µA µA V Ω S pF pF pF ns ns ns ns V ns I F = –3 A, VGS = 0 I F = –3 A, VGS = 0, diF/dt = 50 A/µs I D = –2 A, VGS = –10 V, RL = 15 Ω Test conditions I D = –10 mA, VGS = 0 I G = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 VDS = –160 V, VGS = 0 I D = –1 mA, VDS = –10 V I D = –2 A, VGS = –10 V*1 I D = –2 A, VDS = –10 V*1 VDS = –10 V, VGS = 0, f = 1 MHz Zero gate voltage drain current I DSS Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body to drain diode forward voltage Body to drain diode reverse recovery time Note: 1. Pulse test VGS(off) RDS(on) |yfs| Ciss Coss Crss t d(on) tr t d(off) tf VDF t rr 2 2SJ319(L), 2SJ319(S) Power vs. Temperature Derating 20 Pch (W) I D (A) –50 –30 –10 –3 –1 –0.3 –0.1 –0.05 0 50 100 150 Tc (°C) 200 –1 Maximum Safe Operation Area 15 Channel Dissipation 10 5 1 10 0 µs 0 µs PW 1 m DC = s 10 O pe m s ra (1 tio sh n (T ot Operation in c ) this area is limited by R DS(on) = 25 °C ) Drain Current Ta = 25 °C –3 –10 –30 –100 –300 –500 Case Temperature Drain to Source Voltage V DS (V) Typical Output Characteristics –5 –10 V I D (A) –4 Pulse Test –8 V –6 V (A) –4 –5 Typical Transfer Characteristics 25 °C Tc = –25 °C –3 ID 75 °C –3 Drain Current –5 V –2 –4 V VGS = –3.5 V 0 –4 –8 –12 Drain to Source Voltage –16 –20 V DS (V) Drain Current –2 –1 –1 V DS = –10 V Pulse Test –2 –4 –6 Gate to Source Voltage –8 –10 V GS (V) 0 3 2SJ319(L), 2SJ319(S) Drain to Source Saturation Voltage vs. Gate to Source Voltage Pulse Test Drain to Source On State Resistance R DS(on) ( Ω ) –20 Drain to Source Saturation Voltage V DS(on) (V) Static Drain to Source on State Resistance vs. Drain Current 10 5 VGS = –10 V Pulse Test –16 2 1 0.5 0.2 0.1 –0.2 –12 I D = –5 A –8 –2 A –1 A 0 –4 –8 12 Gate to Source Voltage –16 –20 V GS (V) –4 –0.5 –1 –2 –5 Drain Current I D (A) –10 Static Drain to Source on State Resistance R DS(on) ( Ω) Forward Transfer Admittance |y fs | (S) Static Drain to Source on State Resistance vs. Temperature 5 Forward Transfer Admittance vs. Drain Current 3 2 Tc = –25 °C 1 25 °C 75 °C 4 –2 A I D = –5 A –1 A 3 0.5 2 1 0 –40 VGS = –10 V Pulse Test 0 40 80 120 160 Case Temperature Tc (°C) 0.2 0.1 V DS = –10 V Pulse Test –0.5 –1 –2 –5 –10 –0.05 –0.1 –0.2 Drain Current I D (A) 4 2SJ319(L), 2SJ319(S) Body–Drain Diode Reverse Recovery Time 500 Reverse Recovery Time trr (ns) Capacitance C (pF) Typical Capacitance vs. Drain to Source Voltage 1000 500 200 100 50 Ciss 200 100 50 20 10 5 –0.5 –1 –2 –5 Coss 20 10 5 –0.05 –0.1 –0.2 VGS = 0 f = 1 MHz Crss di/dt = 50 A/µs, VGS = 0 duty < 1 %, Ta = 25 °C 0 –10 –20 –30 -40 –50 Reverse Drain Current I DR (A) Drain to Source Voltage V DS (V) Dynamic Input Characteristics V DS (V) V GS (V) 0 0 Switching Characteristics 500 200 100 50 20 10 5 –0.05 –0.1 –0.2 –0.5 –1 –2 –5 –10 –100 –4 Drain to Source Voltage –200 V DD = –150 V –100 V –50 V –8 Gate to Source Voltage V DS Switching Time t (ns) V DD = –50 V –100 V –150 V V GS = –10 V, V DD = –30 V duty < 1 %, PW = 2 µs t d(off) tf tr t d(on) –300 –12 –400 –500 V GS –16 –20 0 4 8 12 16 Gate Charge Qg (nc) 20 Drain Current I D (A) 5 2SJ319(L), 2SJ319(S) Reverse Drain Current vs. Source to Drain Voltage –5 Reverse Drain Current I DR (A) Pulse Test –4 –3 –2 –10 V V GS = 0, 5 V –1 0 –0.4 –0.8 –1.2 –1.6 V SD (V) –2 Source to Drain Voltage Normalized Transient Thermal Impedance vs. Pulse Width 3 Normalized Transient Thermal Impedance γ s (t) Tc = 25°C 1 D=1 0.5 0.2 0.1 0.05 0.02 0.0 1 0.3 0.1 θ ch – c(t) = γ s (t) • θ ch – c θ ch – c = 6.25 °C/W, Tc = 25 °C Pu lse PDM PW T 0.03 1s t ho D= PW T 0.01 10 µ 100 µ 1m 10 m Pulse Width 100 m PW (S) 1 10 6 2SJ319(L), 2SJ319(S) Switching Time Test Circuit Vin Monitor D.U.T. RL 90% Vin -10 V 50 Ω V DD . –30 V = . Vout td(on) 90% 10% tr td(off) 90% 10% tf Vout Monitor Vin 10% Waveforms 7 Unit: mm 6.5 ± 0.5 5.4 ± 0.5 1.7 ± 0.5 2.3 ± 0.2 0.55 ± 0.1 5.5 ± 0.5 1.2 ± 0.3 3.1 ± 0.5 1.15 ± 0.1 0.8 ± 0.1 16.2 ± 0.5 2.29 ± 0.5 2.29 ± 0.5 0.55 ± 0.1 Hitachi Code JEDEC EIAJ Weight (reference value) DPAK (L)-(1) — Conforms 0.42 g Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: (2) 2718-3666 Fax: (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: (2) 735 9218 Fax: (2) 730 0281 Telex: 40815 HITEC HX Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.