74HC164

HD74HC164 8-bit Parallel-out Shift Register Description This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flipflop. Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and resets the first flip-vlop to the low level at the next clock pulse. A high level on the input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the clear input. Features • • • • • High Speed Operation: tpd (Clock to Q) = 14.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max Function Table Inputs Clear L H H H H Clock X A X X L X H B X X X L H Outputs QA L QAo L L H QB L QBo QAn QAn QAn ········· ········· ········· ········· ········· ········· QH L QHo QGn QGn QGn QAo to Q Ho = Outputs remain unchanged. QAn to Q Gn = Data shifted from the previous stage on a positive edge at the clock input. HD74HC164 Pin Arrangement Serial Inputs A B QA QB 1 A 2 3 4 5 6 7 (Top view) B QA QB QC QD QH QG QF QE CLR 14 VCC 13 QH 12 QG Outputs 11 QF 10 QE 9 8 Clear Clock Outputs QC QD GND CK Timing Diagram Clock A B Clear QA QB QC QD QE QF QG QH 2 HD74HC164 Logic Diagram Clock A B DQ CLR DQ CLR DQ CLR DQ CLR DQ CLR DQ CLR DQ CLR DQ CLR Clear QA QB QC QD QE QF QG QH 3 HD74HC164 DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = –40 to +85°C Max — — — 0.5 1.35 1.8 — — — — — 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 mA I OL = 5.2 mA Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = –4 mA I OH = –5.2 mA Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = –20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 — 3.15 — 4.2 — — — — — — — — — — 0.5 1.5 3.15 4.2 — VIL 2.0 4.5 6.0 1.35 — 1.8 — 1.9 4.4 5.9 4.13 5.63 — — — Output voltage VOH 2.0 4.5 6.0 4.5 6.0 1.9 2.0 — 4.4 4.5 — 5.9 6.0 — 4.18 — 5.68 — — — — — — — — — — VOL 2.0 4.5 6.0 4.5 6.0 0.0 0.1 0.0 0.1 0.0 0.1 — — — — 0.26 — 0.26 — ±0.1 — 4.0 — Input current Quiescent supply current Iin I CC 6.0 6.0 4 HD74HC164 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = 25°C Item Maximum clock frequency Symbol f max Ta = –40 to +85°C Max 4 20 24 200 40 34 200 40 34 220 44 37 — — — — — — — — — — — — — — — 95 19 16 10 pF ns ns Clear ns Clock ns Clear to Clock ns Clock to A, B ns A, B to Clock ns Clear to Q ns ns Clock to Q Unit MHz Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 — — — — — — — — — — — — — — — — 14 — — 15 — — 17 — 5 25 29 — — — Propagation delay t PHL time 2.0 4.5 6.0 160 — 32 27 — — t PLH 2.0 4.5 6.0 160 — 32 27 — — t PHL 2.0 4.5 6.0 175 — 35 30 — — — — — — — — — — — — — — — 75 15 13 10 — — 125 25 21 5 5 5 5 5 5 100 20 17 100 20 17 — — — — Setup time t su 2.0 4.5 6.0 100 — 20 17 5 5 5 5 5 5 80 16 14 80 16 14 — — — — 1 — — 0 — — 0 — — 8 — — 5 — — 5 — 5 Hold time th 2.0 4.5 6.0 Removal time t rem 2.0 4.5 6.0 Pulse width tw 2.0 4.5 6.0 2.0 4.5 6.0 Output rise/fall time t TLH t THL 2.0 4.5 6.0 Input capacitance Cin — 5 Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8° + 0.20 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.70 ± 0.20 0.15 0.12 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g *Dimension including the plating thickness Base material dimension Unit: mm 8.65 9.05 Max 14 8 3.95 1 1.75 Max 7 *0.20 ± 0.05 6.10 – 0.30 1.08 + 0.10 0.635 Max 0° – 8° 0.67 0.60 + 0.20 – 1.27 *0.40 ± 0.06 0.11 0.14 + 0.04 – 0.15 0.25 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DN Conforms Conforms 0.13 g *Pd plating Cautions 1. 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