ECN2112

P1/12 HIGH-VOLTAGE MONOLITHIC IC ECN2102/2112 ECN2102 / 2112 is a single chip row driver IC for electroluminescent (EL) display panel. Functions * Low-voltage serial to high-voltage parallel converter * 34 outputs of totem pole type Features * Output terminal voltage up to 250V * Source / Sink current 500mA ECN2102 ECN2112 Fig. 1. OUTLINE OF FP-48 PACKAGE Vcc STB Vcc OE Q1 D R1 34 bit static shift register R2 Q2 CLK R34 Q34 D-FF SO Function Block Diagram (Positive Logic) PDE-2102/12-0.1 P2/12 ECN2102/2112 1. GENERAL (1) TYPE (2) APPLICATION (3) STRUCTURE (4) PACKAGE ECN2102/ECN2112 Row line driver for Electroluminecent (EL) Monolithic IC, processed Dielectric Isolation. FP-48 (Fig.1) display panel 2. MAXIMUM ALLOWABLE RATING No ITEMS 1 2 3 4 Supply Voltage (logic) Input Voltage (logic) (Ta=25°C) RATINGS -0.5 ~ +7.0 -0.5 ~ Vcc+0.5 Vcc ±250 UNITS V V V V CONDITIONS to GND terminal to GND terminal to GND terminal Between Vs,Vcc,GND, Input and Q output SYMBOLS Vcc Vin VSG VQ Vs - GND Voltage Output Terminal Voltage 5 6 7 Allowable Power Dissipation Operating Temperature Storage Temperature PT TOP Tstg 800 -40 ~ +85 -55 ~ +150 mW °C °C 3. RECOMMENDED OPERATING CONDITIONS No ITEMS 1 2 3 4 5 6 7 8 Supply Voltage (logic) Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time Output Terminal Voltage Peak Output Source Current Peak Output Sink Current SYMBOLS Min. Vcc fCLK twCLK tsu th VQ HIOH HIOL 5.0 80 80 80 Typ. 5.5 ±230 Max. 6.0 250 -500 +500 UNITS V kHz ns ns ns V mA mA Vcc= 5.5V Note 1 Note 1 Vcc= 5.5V Vin= 0V/5.5V CONDITIONS Note1 : Conduction period £ 5 ms per 1 IC PDE-2102/12-0.1 P3/12 ECN2102/2112 4. ELECTRICAL CHARACTERISTICS No ITEMS 1 Output Voltage (logic) (Unless otherwise specified, Ta= 25°C, Vcc= 5.5V, HVCC=230V) SYMBOLS VOL VOH Min. 5.4 1.0 -1.0 3.5 4.5 - Typ. - Max. UNITS C O N D I T I O N S 0.1 1.0 0.4 10 -10 -100 10 V V mA mA V V V V mA mA mA mA Vin=5.5V all input/1 input Vin=0V D,CLK/1 input Vin=0V STB/1 input No signal all input 5.5V, all output Off IOL= 20mA IOH=-20mA VOL= 0.8V VOLH 4.7V D input 2 Output Current (logic) IOL IOH 3 Input Voltage (logic) VIL VIH VTHL VTLH CLK,STB input 4 Input Current (logic) IIH IIL 5 Dissipation Current(logic) Istb 25 5 3.0 6.0 4.0 8.0 6.0 7.0 mA mA V V V V V/ms V/ms ms ms No signal, 1ch source output On No signal, 1ch sink output On 6 Output Voltage HVOL HIOL=1mA HIOL=200mA HIOH=-1mA HIOH=-200mA Q out-GND Q out-GND Vs-Q out Vs-Q out HVOH 7 Output SCR dv/dt capability dv/dt1 dv/dt2 200 200 - Vs~Q out,+dv/dt apply.Fig.6 Q out~GND,-dv/dt apply.Fig.7 8 Output SCR Off Period toff Source side Sink side Fig.8 5. SWITCHING CHARACTERISTICS (Unless otherwise specified, Ta= 25°C, Vcc= 5.5V, Fig.5) No ITEMS 1 Output Delay Time (logic) SYMBOLS tPLH tPHL 2 Output Delay Time tQLH tQHL Min. Typ. Max. UNITS C O N D I T I O N S 300 300 3 3 ns ns ms ms RLQ=1kW CLQ=2000pF CL=15pF PDE-2102/12-0.1 P4/12 ECN2102/2112 Vcc (*) : Q outputs are "OFF" at "H" level. STB Vcc (*) OE Q1 D R1 34 bit static shift register R2 Q2 CLK R34 Q34 D-FF SO Fig. 2. Function Block Diagram (Positive Logic) 6. FUNCTION TABLE CONTROL INPUT CLK SHIFT OPERATION noD * * * OE(*4) H H STB * * H OUTPUT OPERATION L H L SHIFT REGISTER Rn shift keep H L H L H * H * * R34 H (*2) OFF L (*3) OFF ALL OFF OUTPUT SO(*1) Q (*1) 34th data is pushed out as output at the state of down edge ¯ of clock signal. (*2) When shift register is "H", source SCR of Q output is driven to ON. (*3) When shift register is "H", sink SCR of Q output is driven to ON. (*4) OE must be kept "H". PDE-2102/12-0.1 P5/12 ECN2102/2112 7. INPUT / OUTPUT CIRCUIT Equivalent of each input Typical of serial output Typical of all Q output Pull up Vcc Vcc Vcc Vs source SCR () Input Output Q output sink SCR GND GND GND Fig. 3. Input / Output Circuit PDE-2102/12-0.1 P6/12 ECN2102/2112 8. EXAMPLE OF OPERATING TIMING CHART D ECN2102 CLK ECN2112 CLK H fix. OE STB +HV Vs GND -HV ( means floating condition.) ECN2102 Qn ECN2112 Qn ECN2102 Qn+1 ECN2112 Qn+1 HV : High Voltage Fig. 4. Example of Operating Timing Chart PDE-2102/12-0.1 P7/12 ECN2102/2112 9. MEASUREMENT AND MEASUREMENT CIRCUIT 1/f CLK t WCLK CLK T1 50% Tn : Figure n means n th pulse T2 T34 50% 50% INPUT CONDITION t ILH, t IHL =10ns typ. t ILH t IHL 90% tsu th D 50% t PLH SO 50% t PHL 50% 5.5V 0V 10% (a) Shift function (SW1®OFF, SW2,3®ON) SW1 SW2 D CLK OE STB t QLH H fix. 50% t QHL 90% Q1 10% 90% Q2 Other Q output 10% t QLH t QHL 50% 50% 50% OFF ON OFF ON OFF ON OFF ON OFF OFF (b) Output Function (SW3®OFF) SW1 5.5V Vcc CLK D OE STB GND Q34 SO CL RLQ=1kW CLQ=2000pF CL=15pF Vs Q1 Q2 RLQ CLQ 250V SW3 SW2 Measurement point Fig. 5. Switching Characteristics Measurement Circuit PDE-2102/12-0.1 P8/12 ECN2102/2112 1000pF 5.5V Vcc CLK D OE STB GND Q34 SO Vs Q1 Q2 1kW +dV/dt pulser (to reach 150V) Fig. 6. Output SCR dV/dt capability (dV/dt1) Measurement Circuit 5.5V Vcc CLK D OE STB GND Q34 SO -dV/dt pulser (to reach -150V) Vs Q1 Q2 1000pF 1kW Fig. 7. Output SCR dV/dt capability (dV/dt2) Measurement Circuit PDE-2102/12-0.1 P9/12 ECN2102/2112 Io 5.5V Vcc CLK D OE STB GND SO Qn Vs ¬ 12 CLK D OE STB H fix. H fix. 34 MIN 150V Vs Io 100mA dV/dt @ 100V/ms tOFF SCR OFF SCR ON by mistake (a) Source SCR 5.5V Vcc CLK D Qn OE STB GND SO Vs Io ¬ 12 CLK D OE STB H fix. L fix. 34 MIN 150V Vs Io 100mA dV/dt@100V/ms tOFF SCR OFF SCR ON by mistake (b) Sink SCR Fig. 8. Output SCR tOFF Measurement PDE-2102/12-0.1 P10/12 ECN2102/2112 10. PIN LOCATION Q34 Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 Vs GND Vcc (NC) STB (NC) SO Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Vs GND (NC) OE (NC) CLK D (a) ECN2102 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Vs GND (NC) OE (NC) CLK D Q34 Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 Vs GND Vcc (NC) STB (NC) SO (b) ECN2112 Fig. 9. Pin Location (Top view) PDE-2102/12-0.1 P11/12 ECN2102/2112 11. PACKAGE OUTLINE (1) ECN2102 (Unit : mm) 18.8±0.4 14.0 ±0.2 NOTE 2 3.05 MAX. 9.2± NOTE 1 0.3 20.0 TYP. NOTE 1 0.15 9.2± 1.25 TYP. 0.05 0.15± SURFACE 2.40 TYP. NOTE 5 0 - 10° 1.20±0.20 Notes. 1. THIS DIMENSION IS MEASURED AT ROOT OF LEAD. SPACING AT TIP OF LEAD IS MIN 0.2. 2. THIS DIMENSION INCLUDES A WARPAGE OF PACKAGE. 3. MARKING IS ON THE SURFACE OF PACKAGE, INCLUDING HITACHI MARK, TYPE NAME, LOT NUMBER, AND JAPAN MARK. 4. LEADS ARE SOLDER PLATED. 5. THIS IS THE BENDING ANGLE WITH HORIZONTAL PLANE. Fig. 10. Package outline (ECN2102) 0.8± 0.35± NOTE 3 0.3 0.1 NOTE 1 PDE-2102/12-0.1 P12/12 ECN2102/2112 (Unit : mm) (2) ECN2112 18.8±0.4 14.0 ±0.2 NOTE 2 3.05 MAX. 9.2± NOTE 1 0.3 20.0 TYP. NOTE 1 0.15 9.2± 1.25 TYP. SURFACE 0.05 2.40 TYP. NOTE 5 0 - 10° 1.20±0.20 Notes. 1. THIS DIMENSION IS MEASURED AT ROOT OF LEAD. SPACING AT TIP OF LEAD IS MIN 0.2. 2. THIS DIMENSION INCLUDES A WARPAGE OF PACKAGE. 3. MARKING IS ON THE SURFACE OF PACKAGE, INCLUDING HITACHI MARK, TYPE NAME, LOT NUMBER, AND JAPAN MARK. 4. LEADS ARE SOLDER PLATED. 5. THIS IS THE BENDING ANGLE WITH HORIZONTAL PLANE. 0.15± Fig. 11. Package outline (ECN2112) 0.8± 0.35± NOTE 3 0.3 0.1 NOTE 1 PDE-2102/12-0.1 HITACHI POWER SEMICONDUCTORS Notices 1.The information given herein, including the specifications and dimensions, is subject to change without prior notice to improve product characteristics. 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