HM5118165J-7

HM5118165 Series 16 M EDO DRAM (1-Mword × 16-bit) 1 k Refresh ADE-203-636D (Z) Rev. 4.0 Nov. 1997 Description The Hitachi HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word × 16-bit. It employs the most advanced 0.5 µm CMOS technology for high performance and low power. The HM5118165 offers Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ and 50-pin plastic TSOP II. Features • Single 5 V (±10%) • Access time : 50 ns/60 ns/70 ns (max) • Power dissipation  Active mode : 1045 mW/935 mW/825 mW (max)  Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) • EDO page mode capability • Refresh cycles  1024 refresh cycles : 16 ms : 128 ms (L-version) • 4 variations of refresh  RAS -only refresh  CAS -before-RAS refresh  Hidden refresh  Self refresh (L-version) • 2CAS -byte control • Battery backup operation (L-version) HM5118165 Series Ordering Information Type No. HM5118165J-5 HM5118165J-6 HM5118165J-7 HM5118165LJ-5 HM5118165LJ-6 HM5118165LJ-7 HM5118165TT-5 HM5118165TT-6 HM5118165TT-7 HM5118165LTT-5 HM5118165LTT-6 HM5118165LTT-7 Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 400-mil 50-pin plastic TSOP II (TTP-50/44DC) Package 400-mil 42-pin plastic SOJ (CP-42D) 2 HM5118165 Series Pin Arrangement HM5118165J/LJ Series VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 (Top view) 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS HM5118165TT/LTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 V SS I/O15 I/O14 I/O13 I/O12 V SS I/O11 I/O10 I/O9 I/O8 NC VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 (Top view) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Pin Description Pin name A0 to A9 Function Address input — Row/Refresh address A0 to A9 — Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC 3 HM5118165 Series Block Diagram RAS UCAS LCAS WE OE Timing and control A0 A1 to A9 Row decoder • • • Column address buffers Column decoder 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array • • • I/O buffers Row address buffers I/O0 to I/O15 4 HM5118165 Series Truth Table RAS H L L L L L L L L L L L L L H to L H to L H to L L LCAS D L H L L H L L H L L H L H H L L L UCAS D H L L H L L H L L H L L H L H L L WE D H H H L *2 2 2 2 2 2 OE D L L L D D D H H H L to H L to H L to H D D D D H Output Open Valid Valid Valid Open Open Open Undefined Undefined Undefined Valid Valid Valid Open Open Open Open Open Operation Standby Lower byte Read cycle Upper byte Word Lower byte Early write cycle Upper byte Word Lower byte Delayed write cycle Upper byte Word Lower byte Read-modify-write cycle Upper byte Word Word Word Word Word Read cycle (Output disabled) RAS -only refresh cycle CAS -before-RAS refresh cycle or Self refresh cycle (L-version) L* L* L* L* L* H to L H to L H to L D D D D H Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS ≥ 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS . (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS, LCAS . ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. 5 HM5118165 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value –1.0 to +7.0 –1.0 to +7.0 50 1.0 0 to +70 –55 to +125 Unit V V mA W °C °C Recommended DC Operating Conditions (Ta = 0 to +70 °C) Parameter Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min 4.5 2.4 –1.0 Typ 5.0 — — Max 5.5 6.5 0.8 Unit V V V Notes 1, 2 1 1 Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM5118165 -5 Parameter Operating current* * Standby current 1, 2 -6 -7 Test conditions t RC = min TTL interface RAS , UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS , UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z CMOS interface RAS , UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z Symbol I CC1 I CC2 Min Max Min Max Min Max Unit — — 200 — 2 — 170 — 2 — 150 mA 2 mA — 1 — 1 — 1 mA Standby current (L-version) I CC2 — 150 — 150 — 150 µA 6 HM5118165 Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont.) HM5118165 -5 Parameter RAS -only refresh current* Standby current* 1 2 -6 -7 Test conditions t RC = min RAS = VIH, UCAS, LCAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR refresh: tRC = 125 µs t RAS ≤ 0.3 µs CMOS interface RAS , UCAS, LCAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ 7 V 0 V ≤ Vout ≤ 7 V Dout = disable High Iout = –2 mA Low Iout = 2 mA Symbol I CC3 I CC5 Min Max Min Max Min Max Unit — — 200 — 5 — 170 — 5 — 150 mA 5 mA CAS -before-RAS refresh current I CC6 — — — 190 — 185 — 500 — 170 — 165 — 500 — 150 mA 145 mA 500 µA EDO page mode current*1, * 3 I CC7 Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) 4 I CC10 I CC11 — 300 — 300 — 300 µA Input leakage current Output leakage current Output high voltage Output low voltage I LI I LO VOH VOL –10 10 –10 10 2.4 0 –10 10 –10 10 –10 10 –10 10 VCC 0.4 µA µA V V VCC 2.4 0.4 0 VCC 2.4 0.4 0 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ — — — Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS , UCAS and LCAS = VIH to disable Dout. 7 HM5118165 Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *2, *18, *19, *20 Test Conditions • • • • • Input rise and fall time: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5118165 -5 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT Min 84 30 7 50 7 0 7 0 7 11 9 10 35 5 13 0 0 2 Max — — — -6 Min 104 40 10 Max — — — -7 Min 124 50 13 Max — — — Unit ns ns ns Notes 10000 60 10000 10 — — — — 37 25 — — — — — — 50 0 10 0 10 14 12 13 40 5 15 0 0 2 10000 70 10000 13 — — — — 45 30 — — — — — — 50 0 10 0 13 14 12 13 45 5 18 0 0 2 10000 ns 10000 ns — — — — 52 35 — — — — — — 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 23 22 5 6 6 7 21 21 3 4 8 HM5118165 Series Read Cycle HM5118165 -5 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS next CAS delay time Symbol t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD t RNCD Min — — — — 0 0 50 0 25 15 0 3 3 — — 13 3 — — 13 13 50 Max 50 13 25 13 — — — — — — — — — 13 13 — — 13 13 — — — -6 Min — — — — 0 0 60 0 30 18 0 3 3 — — 15 3 — — 15 15 60 Max 60 15 30 15 — — — — — — — — — 15 15 — — 15 15 — — — -7 Min — — — — 0 0 70 0 35 23 0 3 3 — — 18 3 — — 18 18 70 Max 70 18 35 18 — — — — — — — — — 15 15 — — 15 15 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 27 13 5 27 27 27 12 Notes 8, 9 9, 10, 17 9, 11, 17 9 21 12, 22 9 HM5118165 Series Write Cycle HM5118165 -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 7 7 7 7 0 7 Max — — — — — — — -6 Min 0 10 10 10 10 0 10 Max — — — — — — — -7 Min 0 13 10 13 13 0 13 Max — — — — — — — Unit ns ns ns ns ns ns ns 23 15, 23 15, 23 Notes 14, 21 21 Read-Modify-Write Cycle -5 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol t RWC t RWD t CWD t AWD t OEH Min 111 67 30 42 13 Max — — — — — -6 Min 135 79 34 49 15 Max — — — — — -7 Min 161 92 40 57 18 Max — — — — — Unit ns ns ns ns ns 14 14 14 Notes Refresh Cycle HM5118165 -5 Parameter Symbol Min 5 7 5 Max — — — CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) t CHR RAS precharge to CAS hold time t RPC -6 Min 5 10 5 Max — — — -7 Min 5 10 5 Max — — — Unit ns ns ns Notes 21 22 21 10 HM5118165 Series EDO Page Mode Cycle HM5118165 -5 Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge Symbol t HPC t RASP t CPA Min Max 20 — — 28 3 7 5 28 — -6 Min Max 25 — -7 Min Max 30 — Unit ns Notes 25 16 9, 17, 22 100000 — 28 — — — — — — 35 3 10 5 35 100000 — 35 — — — — — — 40 3 13 5 40 100000 ns 40 — — — — — ns ns ns ns ns ns RAS hold time from CAS precharge t CPRH Output data hold time from CAS low t DOH CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge t COL t COP t RCHC 9 EDO Page Mode Read-Modify-Write Cycle HM5118165 -5 Parameter Symbol Min 57 45 Max — — -6 Min 68 54 Max — — -7 Min 79 62 Max — — Unit ns ns 14, 22 Notes EDO page mode read-modify-write t HPRWC cycle time WE delay time from CAS precharge t CPW Refresh Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 16 128 Unit ms ms Note 1024 cycles 1024 cycles 11 HM5118165 Series Self Refresh Mode (L-version) HM5118165L -5 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol t RASS t RPS t CHS Min 100 90 –50 Max — — — -6 Min 100 110 –50 Max — — — -7 Min 100 130 –50 Max — — — Unit µs ns ns Notes 28, 29, 30, 31 Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS -only refresh or CAS -before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD ≥ tRAD (max) + tAA (max) – tCAC (max), then access time is controlled exclusively by t CAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 12 HM5118165 Series 20 All the V CC and VSS pins shall be supplied with the same voltages. 21. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS . 22. t CRP , t CHR, t RCH, t CPA and tCPW are determined by the later rising edge of UCAS or LCAS . 23. t CWL, t DH, t DS and t CSH should be satisfied by both UCAS and LCAS . 24. t CP is determined by the time that both UCAS and LCAS are high. 25. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH, and between tOFR and t OFF. 28. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS ≥ 100 µs, then RAS precharge time should use tRPS instead of tRP. 29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 32. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 13 HM5118165 Series Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS /LCAS are allowed under the following conditions. 1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following. RAS Delayed write UCAS Early write LCAS WE 3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is satisfied, EDO page mode can be performed. RAS UCAS LCAS t UL 4. Byte control operation by remaining UCAS or LCAS high is guaranteed. 14 HM5118165 Series Timing Waveforms*32 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP UCAS LCAS t ASR t RAD t ASC t RAL t CAL t CAH t RAH Address Row Column t RRH t RCHR t RCS t RCH WE t WED t DZC t CDD t RDD Din High-Z t DZO t OEA t OED OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout t CAC t AA t RAC t CLZ 15 HM5118165 Series Early Write Cycle tRC tRAS tRP RAS tCSH tRCD tT UCAS LCAS tRSH tCAS tCRP tASR tRAH tASC tCAH Address Row Column tWCS tWCH WE tDS tDH Din Din Dout High-Z* * t WCS t WCS (min) 16 HM5118165 Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t RCD tT UCAS LCAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP Address Row Column t CWL t RCS t RWL t WP WE t DZC t DS t DH Din High-Z Din t OEH t OED t DZO  OE t OEZ t CLZ Dout High-Z Invalid Dout 17 HM5118165 Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS tT t RCD t CAS t CRP UCAS LCAS t RAD t ASR t RAH t ASC t CAH Address Row t RCS Column t CWD t AWD t RWD tCWL t RWL t WP WE t DZC t DS Din High-Z Din t DH t DZO t OED t OEA t OEH OE t CAC t AA t RAC t OEZ t OHO High-Z Dout t CLZ Dout 18 HM5118165 Series RAS-Only Refresh Cycle t RC t RAS RAS tT t CRP t RPC t CRP t RP UCAS LCAS t ASR Address t OFR t OFF Dout High-Z Row t RAH 
19 HM5118165 Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP t RAS t RC t RP RAS tT t RPC t CP UCAS LCAS t CSR t CHR t RPC t CP t CRP t CSR t CHR  Address t OFR t OFF Dout High-Z 20 HM5118165 Series Hidden Refresh Cycle t RC t RAS t RC t RAS t RC t RP t RAS t RP t RP RAS tT t RSH t RCD UCAS LCAS t CHR t CRP t RAD t ASR t RAH Address Row t ASC t RAL t CAH Column t RCS WE t RRH t RCH t DZC High-Z Din t WED t CDD t RDD t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t OFR t OHR t OED t OFF t OH t OEZ t WEZ t OHO 21 HM5118165 Series EDO Page Mode Read Cycle t RP t RASP tT UCAS LCAS t RCS WE t RNCD RAS t HPC t HPC tCAS t RCHC t CPRH t CP t t CRP t CSH t CAS t RCHR t CP t HPC t CAS t CP RSH tCAS t RRH t RCH t RCH t RCS tASR Address tRAH tASC Row tCAH t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED Column 1 t CAL tDZC t CAL tRDD tCDD Din High-Z tDZO tCOL tCOP tOED OE tOEA tCAC tAA tRAC tCPA tAA tCAC tWEZ tOEZ tOHO tOEA tCPA tCPA tAA tCAC tDOH tAA tOEZ tCAC tOEA tOFR tOHR tOEZ tOHO tOFF tOH Dout 4 tOHO Dout 3  22 Dout Dout 1 Dout 2 Dout 2 HM5118165 Series EDO Page Mode Read Cycle (2CAS) t RP t RASP t HPC t CAS tHPC t CP t CP t HPC tRSH tCAS t CRP t RNCD RAS tT LCAS t CSH t CAS t CP UCAS t CAS t RCHC t RCS t RRH t RCH WE tASR Address tRAH tASC Row tCAH t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED Column 1 t CAL tDZC t CAL tRDD tCDD Din High-Z tDZO tCOL tCOP tOED  OE tOEA tCPA tCPA tCAC tAA tAA tCAC tOEZ tAA tOHO tOEZ tOFR tOHR tOEZ tOHO tOFF tOH tRAC tDOH tOEA tCAC tOHO L Dout Dout 1 Dout 2 Dout 2 Dout 4 tCPA tAA tCAC tOEA U Dout Dout 1 Dout 3 Dout 4 23 HM5118165 Series EDO Page Mode Early Write Cycle tRASP tRP RAS tT tRCD UCAS LCAS tCSH tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP tASR tRAH tASC tCAH tASC tCAH tASC tCAH Address Row Column 1 Column 2 Column N tWCS tWCH tWCS tWCH tWCS tWCH WE tDS tDH tDS tDH tDS tDH Din Din 1 Din 2 Din N Dout High-Z* * t WCS t WCS (min) 24 HM5118165 Series EDO Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CSH t RCD UCAS LCAS t CP t CAS t HPC t CAS t CP t RSH t CAS t CRP t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL
 t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z Invalid Dout Invalid Dout Invalid Dout 25 HM5118165 Series EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t CP t RCD UCAS LCAS t HPRWC t CP t CAS t CAS t RSH t CAS t CRP t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO t OED t OEH OE Din 1 t DZO t OED t OEH t WP t DZC t DS t DH Din 2 t DZO t OED t OEH t WP t DZC t DS t DH Din N t RCS t CWL t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL Address  t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z Dout Dout 1 Dout 2 Dout N 26 HM5118165 Series EDO Page Mode Mix Cycle (1) t RP RAS t RASP t CRP tCAS tRSH t RCS tCPW tAWD t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL t DS t DH Din 1 High-Z tOED t DS t DH Din 3 tWED tASC t CAH Column 3 tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS t RRH t RCH tT UCAS LCAS t RCD t WCS WE t CP t CAS t CSH t WCH t CAS t CP tCAS t CP tASR Address tASC Column 1 Din  tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH tCAC t DOH tCAC t OHO tOEA Dout OE Dout 2 Dout 3 Dout 4 27 HM5118165 Series EDO Page Mode Mix Cycle (2) t RP t RASP t RNCD RAS tT UCAS LCAS t CSH t CAS t RCD t RCS t RCHR t CP t CAS t CP tCAS t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH t CRP t RCH tWCS t WCH t RCS t RRH t RCH WE tASR Address tRAH Row t ASC tCAH t ASC t CAH Column 2 t ASC t CAH Column 3 t CAL Column 1 t CAL t DS Din t DH Din 2 tRDD tCDD High-Z tOED OE tWED tCOL t OEA tOEZ t OHO tCPA tAA tCAC tOEZ t OHO Dout 3 tAA tOEA tCAC tRAC tCPA tAA tCAC tOEA tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4 Dout Dout 1 28 HM5118165 Series Self Refresh Cycle (L-version)* 28, 29, 30, 31 t RASS t RP t RPS RAS tT t RPC t CP UCAS LCAS t OFR t CRP t CSR t CHS  t OFF Dout High-Z 29 HM5118165 Series Package Dimensions HM5118165J/LJ Series (CP-42D) Unit: mm 27.06 27.43 Max 42 22 10.16 ± 0.13 0.74 3.50 ± 0.26 1 21 11.18 ± 0.13 1.30 Max 0.80 +0.25 –0.17 0.43 ± 0.10 0.41 ± 0.08 1.27 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-42D Conforms — 1.75 g 0.10 Dimension including the plating thickness Base material dimension 30 2.50 ± 0.12 HM5118165 Series HM5118165TT/LTT Series (TTP-50/44DC) Unit: mm 20.95 21.35 Max 40 36 50 26 11 15 1 0.80 25 0.80 0.27 ± 0.07 0.13 M 0.25 ± 0.05 1.15 Max 10.16 11.76 ± 0.20 0.50 ± 0.10 0.68 0° – 5° 0.145 ± 0.05 0.125 ± 0.04 0.10 0.13 ± 0.05 1.20 Max 3.20 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TTP-50/44DC Conforms — 0.50 g 31 HM5118165 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 32 HM5118165 Series Revision Record Rev. 1.0 2.0 Date Sep. 30, 1996 Nov. 26, 1996 Contents of Modification Initial issue Addition of HM5118165-5 Series Power dissipation (active) 1018/907 mW(max) to 1045/935/825 mW (max) DC Characteristics I CC7 max: 185/165 mA to 185/165/145 mA AC Characteristics t RCD min: t RAD min: t RSH min: t RRH min: t RWC min: t RPC min: 20/20 ns to 11/14/14 ns 15/15 ns to 9/12/12 ns 15/18 ns to 10/13/13 ns 0/0 ns to 5/5/5 ns 136/161 ns to 111/135/161 ns 0/0 ns to 5/5/5 ns Drawn by Y. Kasama Y. Kasama Approved by M. Mishima M. Mishima Timing Waveforms Addition of t RNCD timing to EDO page mode mix cycle (2) 3.0 4.0 Feb. 24, 1997 Nov. 1997 AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns Change of Subtitle Y. Kasama Y. Matsuno 33