HM6264ALP-10L

HM6264A Series 8192-word × 8-bit High Speed CMOS Static RAM Features Type No. Access time 100 ns 120 ns 150 ns Package 300-mil, 28-pin plastic DIP (DP-28N) • Low-power standby — 0.1 mW (typ) — 10 µW (typ) L-/LL-version • Low power operation — 15 mW/MHz (typ) • Fast access time — l00/120/150 ns (max) • Single +5 V supply • Completely static memory — No clock or timing strobe required • Equal access and cycle time • Common data input and output, three-state output • Directly TTL compatible — All inputs and outputs • Battery back up operation capability (L-/LL-version) HM6264ASP-10 HM6264ASP-12 HM6264ASP-15 HM6264ALSP-10 100 ns HM6264ALSP-12 120 ns HM6264ALSP-15 150 ns HM6264ALSP-10L 100 ns HM6264ALSP-12L 120 ns HM6264ALSP-15L 150 ns HM6264AFP-10 100 ns 120 ns 150 ns 28-pin plastic SOP *1 (FP-28D/DA) Ordering Information Type No. HM6264AP-10 HM6264AP-12 HM6264AP-15 HM6264ALP-10 HM6264ALP-12 HM6264ALP-15 Access time 100 ns 120 ns 150 ns Package HM6264AFP-12 HM6264AFP-15 HM6264ALFP-10 100 ns 600-mil, 28-pin plastic DIP (DP-28) HM6264ALFP-12 120 ns HM6264ALFP-15 150 ns HM6264ALFP-10L 100 ns 100 ns HM6264ALFP-12L 120 ns 120 ns HM6264ALFP-15L 150 ns 150 ns Note: 1. T is added to the end of the type number for a SOP of 3.00 mm (max) thickness. HM6264ALP-10L 100 ns HM6264ALP-12L 120 ns HM6264ALP-15L 150 ns 1 HM6264A Series Pin Arrangement NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CS2 A8 A9 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 HM6264A Series (Top view) Block Diagram A11 A8 A9 A7 A12 A5 A6 A4 I/O1 Row decoder Memory array 256 × 256 VCC VSS Column I/O Input data control Column decoder I/O8 A1 A2A0A10 A3 CS2 CS1 WE OE Timing pulse generator 2 HM6264A Series Truth Table WE × × H H L L Note: CS1 H × L L L L CS2 × L H H H H OE × × H L H L Output disabled Read Write Write Mode Not selected (power down) I/O pin High Z High Z High Z Dout Din Din HM6264A Series VCC current ISB, ISB1 ISB, ISB1 ICC ICC ICC ICC Read cycle Write cycle 1 Write cycle 2 Note ×: Don’t care. Absolute Maximum Ratings Parameter Terminal voltage *1 Power dissipation Operating temperature Storage temperature Storage temperature (under bias) Symbol VT PT Topr Tstg Tbias Rating –0.5 *2 to +7.0 1.0 0 to +70 –55 to +125 –10 to +85 Unit V W °C °C °C Notes: 1. With respect to VSS. 2. –3.0 V for pulse width ≤ 50 ns Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Symbol VCC VSS Input voltage VIH VIL Note: 1. –3.0 V for pulse width ≤ 50 ns Min 4.5 0 2.2 –0.3 *1 Typ 5.0 0 — — Max 5.5 0 6.0 0.8 Unit V V V V 3 HM6264A Series Parameter Input leakage current Symbol |ILI| Min — — Typ — — Max 2 2 Unit µA µA Test condition Vin = VSS to VCC HM6264A Series DC and Operating Characteristics (VCC = 5 V ± 10%,VSS = 0 V, Ta = 0 to +70°C) Output leakage current |ILO| CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, VI/O = VSS to VCC CS1 = VIL, CS2 = VIH, II/O = 0 mA Operating power supply current Average operating current ICCDC — 7 15 mA ICC1 — — — 30 30 3 45*5 55*6 5 mA Min. cycle, duty = 100%, CS1 = VIL, CS2 = VIH, II/O = 0 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ VCC – 0.2 V, VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V CS1 = VIH or CS2 = VIL ICC2 mA Standby power supply ISB current ISB1 *2 — 1 3 mA — 0.02 2 mA CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or ———————————— — 2*3 100*3 µA 0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin ————————— — 2*4 50*4 — 2.4 — — 0.4 — V V IOL = 2.1 mA IOH = –1.0 mA Output voltage VOL VOH Notes: 1. 2. 3. 4. 5. 6. Typical values are at VCC = 5.0 V, Ta = 25°C and not guaranteed. VIL min = –0.3 V These characteristics are guaranteed only for the L-version. These characteristics are guaranteed only for the LL-version. For 120 ns/150 ns version. For 100 ns version. Capacitance (f = 1 MHz, Ta = 25°C)*1 Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Typ — — Max 5 7 Unit pF pF Test condition Vin = 0 V VI/O = 0 V 1. This parameter is sampled and is not 100% tested. 4 HM6264A Series AC Characteristics (VCC = 5 V ± 10%, Ta = 0 to +70°C) AC Test Conditions: • • • • Input pulse levels: 0.8 V/2.4 V Input rise and fall time: 10 ns Input timing reference level: 1.5 V Output timing reference level — HM6264A-10: 1.5 V — HM6264A-12/15: 0.8 V/2.0 V • Output load: 1 TTL gate and CL (100 pF) (including scope and jig) Read Cycle HM6264A-10 ——————— Min Max 100 — — — — 10 10 5 0 0 0 10 — 100 100 100 50 — — — 35 35 35 — HM6264A-12 ——————— Min Max 120 — — — — 10 10 5 0 0 0 10 — 120 120 120 60 — — — 40 40 40 — HM6264A Series Parameter Read cycle time Address access time Chip selection to output CS1 CS2 Output enable to output valid Chip selection to output in low Z CS1 CS2 Output enable to output in low Z Chip deselection to output in high Z CS1 CS2 Output disable to output in high Z Output hold from address change Notes Symbol tRC tAA tCO1 tCO2 tOE tLZ1 tLZ2 tOLZ tHZ1 tHZ2 t t OHZ OH HM6264A-15 ——————— Min Max 150 — — — — 15 15 5 0 0 0 10 — 150 150 150 70 — — — 50 50 50 — Unit ns ns ns ns ns ns ns ns ns ns ns ns 1. tHZ and tOHZ are defined as the time at which the outputs to achieve the open circuit condition and are not referred to output voltage levels. 2. At any given temperature and voltage condition, tHZ maximum is less than tLZ minimum both for a given device and from device to device. 5 HM6264A Series Read Timing Waveform tRC Address tAA tCO1 CS1 tLZ1 tCO2 CS2 tLZ2 tOE tOLZ OE HM6264A Series tHZ1 tHZ2 tOHZ Dout Valid Data tOH Note: WE is high for read cycle. Write Cycle HM6264A-10 ——————— Min Max 100 80 0 80 60 0 0 40 0 0 5 — — — — — — 35 — — 35 — HM6264A-12 ——————— Min Max 120 85 0 85 70 0 0 40 0 0 5 — — — — — — 40 — — 40 —— HM6264A-15 ——————— Min Max 150 100 0 100 90 0 0 50 0 0 5 — — — — — — 50 — — 50 — Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high Z Data to write time overlap Data hold from write time Output enable to output in high Z Output active from end of write Symbol tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOHZ tOW Unit ns ns ns ns ns ns ns ns ns ns ns 6 HM6264A Series Write Timing Waveform (1) (OE Clock) tWC Address HM6264A Series OE tCW *2 tWR *4 CS1 *6 CS2 tAS *3 tAW tWP *1 WE tOHZ *5 Dout Din tDW tDH Valid Data 7 HM6264A Series Write Timing Waveform (2) (OE Low Fix) tWC Address tAW tCW CS1 *6 *2 HM6264A Series tWR *4 tCW *2 CS2 tWP *1 WE tAS *3 *5 tOH tWHZ tOW *7 *8 Dout tDW tDH *9 Din Valid Data Notes: 1. A write occurs during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the latest transition among CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high. Time tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of the write cycle. 5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If CS1 goes low simultaneously with WE going low or after WE goes low, the outputs remain in high impedance state. 7. Dout is the same phase of the latest written data in this write cycle. 8. Dout is the read data of the next address. 9. If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals of opposite phase to the outputs must not be applied to I/O pins 8 HM6264A Series Low VCC Data Retention In data retention mode, CS2 controls the address, WE, CS1, OE, and the Din buffer. If CS2 controls data retention mode, Vin (for these inputs) can be in the high impedance state. If CS1 controls the data retention mode, CS2 must satisfy either HM6264A Series CS2 ≥ VCC – 0.2 V or CS2 ≤ 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. Low VCC Data Retention Characteristics (Ta = 0 to +70°C) This characteristics is guaranteed only L/LL-version. Parameter VCC for data retention Symbol VDR Min 2.0 Typ — Max — Unit V Test Condition CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC– 0.2 V, or CS2 ≤ 0.2 V VCC = 3.0 V, CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V, or 0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin See retention waveform Data retention current ICCDR — — 1*1 1*2 50*1 25*2 µA Chip deselect to data retention time Operation recovery time t CDR 0 t — — ns tR RC *3 — — ns See retention waveform Notes: 1. VIL min = –0.3 V, 20 µA max at Ta = 0 to 40°C. These characteristics are guaranteed only for the L-version. 2. VIL min = –0.3 V, 10 µA max at Ta = 0 to 40°C. These characteristics are guaranteed only for the LL-version. 3. tRC = Read cycle time. Low VCC Data Retention Waveform (1) (CS1 Controlled) tCDR VCC 4.5 V 2.2 V VDR CS1 0V Data retention mode tR CS1 ≥ VCC – 0.2 V 9 HM6264A Series Low VCC Data Retention Waveform (2) (CS2 Controlled) HM6264A Series VCC 4.5 V CS2 VDR 0.4 V 0V tCDR Data retention mode tR CS2 ≤ 0.2 V 10