HM6264BLSP-8L

HM6264B Series 64 k SRAM (8-kword × 8-bit) ADE-203-454B (Z) Rev. 2.0 Nov. 1997 Description The Hitachi HM6264B is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance and low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil SOP (foot print pitch width), 600 mil plastic DIP, 300 mil plastic DIP, is available for high density mounting. Features • High speed Fast access time: 85/100 ns (max) • Low power Standby: 10 µW (typ) Operation: 15 mW (typ) (f = 1 MHz) • Single 5 V supply • Completely static memory No clock or timing strobe required • Equal access and cycle times • Common data input and output Three state output • Directly TTL compatible All inputs and outputs • Battery backup operation capability HM6264B Series Ordering Information Type No. HM6264BLP-8L HM6264BLP-10L HM6264BLSP-8L HM6264BLSP-10L HM6264BLFP-8LT HM6264BLFP-10LT Access time 85 ns 100 ns 85 ns 100 ns 85 ns 100 ns Package 600-mil, 28-pin plastic DIP (DP-28) 300-mil, 28-pin plastic DIP(DP-28N) 450-mil, 28-pin plastic SOP(FP-28DA) Pin Arrangement HM6264BLP/BLSP/BLFP Series NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CS2 A8 A9 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 (Top view) Pin Description Pin name A0 to A12 I/O1 to I/O8 CS1 CS2 Function Address input Data input/output Chip select 1 Chip select 2 Pin name WE OE NC VCC VSS Function Write enable Output enable No connection Power supply Ground HM6264B Series Block Diagram A11 A8 A9 A7 A12 A5 A6 A4 I/O1 Input data control I/O8 Row decoder Memory array 256 × 256 VCC VSS Column I/O Column decoder A1 A2 A0 A10 A3 CS2 CS1 Timing pulse generator Read, Write control WE OE HM6264B Series Function Table WE × × H H L L CS1 H × L L L L CS2 × L H H H H OE × × H L H L Mode Not selected (power down) Not selected (power down) Output disable Read Write Write VCC current I SB , I SB1 I SB , I SB1 I CC I CC I CC I CC I/O pin High-Z High-Z High-Z Dout Din Din Ref. cycle — — — Read cycle (1)–(3) Write cycle (1) Write cycle (2) Note: ×: H or L Absolute Maximum Ratings Parameter Power supply voltage Terminal voltage *1 *1 Symbol VCC VT PT Topr Tstg Tbias Value –0.5 to +7.0 –0.5 to V CC + 0.3 1.0 0 to + 70 –55 to +125 –10 to +85 *2 *3 Unit V V W °C °C °C Power dissipation Operating temperature Storage temperature Storage temperature under bias Notes: 1. Relative to VSS 2. VT min: –3.0 V for pulse half-width ≤ 50 ns 3. Maximum voltage is 7.0 V Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Note: VIH VIL Min 4.5 0 2.2 –0.3 *1 Typ 5.0 0 — — Max 5.5 0 VCC + 0.3 0.8 Unit V V V V 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns HM6264B Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V) Parameter Input leakage current Output leakage current Operating power supply current Average operating power supply current Symbol Min |ILI| |ILO | I CCDC I CC1 — — — — Typ*1 Max — — 7 30 2 2 15 45 Unit µA µA mA mA Test conditions Vin = VSS to V CC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, VI/O = VSS to V CC CS1 = VIL, CS2 = VIH, I I/O = 0 mA others = VIH/VIL Min cycle, duty = 100%, CS1 = VIL, CS2 = VIH, I I/O = 0 mA others = VIH/VIL Cycle time = 1 µs, duty = 100%, II/O = 0 mA CS1 ≤ 0.2 V, CS2 ≥ VCC – 0.2 V, VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V CS1 = VIH, CS2 = VIL CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin I OL = 2.1 mA I OH = –1.0 mA I CC2 — 3 5 mA Standby power supply current I SB I SB1 — — — 2.4 1 2 — — 3 50 0.4 — mA µA V V Output low voltage Output high voltage VOL VOH Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed. Capacitance (Ta = 25°C, f = 1.0 MHz) Parameter Input capacitance *1 *1 Symbol Cin CI/O Min — — Typ — — Max 5 7 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Input/output capacitance Note: 1. This parameter is sampled and not 100% tested. HM6264B Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.) Test Conditions • • • • Input pulse levels: 0.8 V to 2.4 V Input and output timing reference level: 1.5 V Input rise and fall time: 10 ns Output load: 1 TTL Gate + CL (100 pF) (Including scope & jig) Read Cycle HM6264B-8L Parameter Read cycle time Address access time Chip select access time CS1 CS2 Output enable to output valid Chip selection to output in low-Z CS1 CS2 Output enable to output in low-Z Chip deselection in to output in high-Z CS1 CS2 Output disable to output in high-Z Output hold from address change Symbol t RC t AA t CO1 t CO2 t OE t LZ1 t LZ2 t OLZ t HZ1 t HZ2 t OHZ t OH Min 85 — — — — 10 10 5 0 0 0 10 Max — 85 85 85 45 — — — 30 30 30 — HM6264B-10L Min 100 — — — — 10 10 5 0 0 0 10 Max — 100 100 100 50 — — — 35 35 35 — Unit ns ns ns ns ns ns ns ns ns ns ns ns 2 2 2 1, 2 1, 2 1, 2 Notes Notes: 1. t HZ is defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. At any given temperature and voltage condition, t HZ maximum is less than tLZ minimum both for a given device and from device to device. HM6264B Series Read Timing Waveform (1) (WE = VIH) tRC Address tAA tCO1 CS1 tLZ1 tCO2 CS2 tLZ2 tOE tOLZ OE tOHZ Dout High Impedance Valid data tOH tHZ2 tHZ1 Valid address Read Timing Waveform (2) (WE = VIH, OE = VIL ) Address Valid address t AA t OH t OH Valid data Dout HM6264B Series Read Timing Waveform (3) (WE = VIH, OE = VIL )*1 t CO1 t HZ1 t LZ1 CS2 t CO2 t LZ2 Dout Note: 1. Valid data Address must be valid prior to or simultaneously with CS1 going low or CS2 going high. t HZ2 CS1 HM6264B Series Write Cycle HM6264B-8L Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time WE to output in high-Z Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Symbol t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW t OHZ Min 85 75 0 75 55 0 0 40 0 5 0 Max — — — — — — 30 — — — 30 HM6264B-10L Min 100 80 0 80 60 0 0 40 0 5 0 Max — — — — — — 35 — — — 35 Unit ns ns ns ns ns ns ns ns ns ns ns 5 1, 6 4 5 2 3 Notes Notes: 1. A write occurs during the overlap of a low CS1 , and high CS2, and a high WE. A write begins at the latest transition among CS1 going low,CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high CS2 going low and WE going high. Time tWP is measured from the beginning of write to the end of write. 2. t CW is measured from the later of CS1 going low or CS2 going high to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 5. During this period, I/O pins are in the output state, therefore the input signals of the opposite phase to the outputs must not be applied. 6. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention t WP ≥ tWHZ max + tDW min. HM6264B Series Write Timing Waveform (1) (OE Clock) tWC Address Valid address OE tCW tWR CS1 *1 CS2 tAS WE tAW tWP tOHZ Dout Din High Impedance tDW High Impedance tDH Valid data Note: 1. If CS1 goes low or CS2 goes high simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. HM6264B Series Write Timing Waveform (2) (OE Low Fixed) (OE = VIL ) tWC Address Valid address tAW tCW CS1 *1 tWR CS2 tWP WE tAS tWHZ Dout tOW *2 *3 tOH tDW High Impedance tDH *4 Din Notes: 1. 2. 3. 4. Valid data If CS1 goes low simultaneously with WE going low or after WE goes low, the outputs remain in high impedance state. Dout is the same phase of the written data in this write cycle. Dout is the read data of the next address. If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals of opposite phase to the outputs must not be applied to I/O pins. HM6264B Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) Parameter VCC for data retention Data retention current Symbol VDR I CCDR Min 2.0 — Typ*1 — 1*1 Max — 25*2 Unit V µA Test conditions*4 CS1 ≥ VCC –0.2 V, CS2 ≥ VCC –0.2 V or CS2 ≤ 0.2 V VCC = 3.0 V, 0 V ≤ Vin ≤ VCC CS1 ≥ VCC –0.2 V, CS2 ≥ VCC –0.2 V or 0 V ≤ CS2 ≤ 0.2 V See retention waveform Chip deselect to data retention time Operation recovery time Notes: 1. 2. 3. 4. t CDR tR 0 t RC*3 — — — — ns ns Reference data at Ta = 25°C. 10 µA max at Ta = 0 to + 40°C. t RC = read cycle time. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1 , I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. Low V CC Data Retention Timing Waveform (1) (CS1 Controlled) tCDR VCC 4.5 V 2.2 V VDR CS1 0V CS1 ≥ VCC – 0.2 V tR Data retention mode Low V CC Data Retention Timing Waveform (2) (CS2 Controlled) Data retention mode tCDR tR VCC 4.5 V CS2 VDR 0.4 V 0V CS2 ≤ 0.2 V HM6264B Series Package Dimensions HM6264BLP Series (DP-28) Unit: mm 28 35.6 36.5 Max 15 1 1.2 1.9 Max 14 15.24 2.54 Min 5.7 Max 0.51 Min 13.4 14.6 Max 0.25 – 0.05 0° – 15° + 0.11 2.54 ± 0.25 0.48 ± 0.10 HM6264B Series HM6264BLSP Series (DP-28N) 36.00 37.32 Max 28 15 7.00 Max 6.60 Unit: mm 1 1.30 2.20 Max 14 0.51 Min 2.54 Min 5.08 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.11 HM6264BLTM Series (FP-28DA) 18.3 18.75 Max 28 15 8.4 Unit: mm 3.0 Max 1 0.895 14 + 0.08 – 0.07 11.8 ± 0.3 0.17 0 – 10 ° 1.27 ± 0.10 0.40 – 0.05 + 0.10 0.1 Min 1.0 HM6264B Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071