HM628128ALR-5L

ADE-XXX-XXX HM628128A Series 131,072-word × 8-bit High Speed CMOS Static RAM Rev. X January 1995 The Hitachi HM628128A is a CMOS static RAM organized 128 kword × 8 bit. It realizes higher density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. It offers low power standby power dissipation; therefore, it is suitable for battery back-up systems. The device, packaged in a 525-mil SOP (460-mil body SOP) or a 600-mil plastic DIP, or a 8 × 20 mm TSOP with thickness of 1.2 mm, is available for high density mounting. TSOP package is suitable for cards, and reverse type TSOP is also provided. Features • High speed — Fast access time: 55/70/85/100 ns (max) • Low power — Active: 75 mW (typ) — Standby: 10 µW (typ) • Single 5 V supply • Completely static memory No clock or timing strobe required • Equal access and cycle times • Common data input and output Three state output • Directly TTL compatible All inputs and outputs • Capability of battery back up operation 2 chip selection for battery back up HM628128A Series Ordering Information Type No. HM628128ALP–5 HM628128ALP–7 HM628128ALP–8 HM628128ALP–10 HM628128ALP–5L HM628128ALP–7L HM628128ALP–8L HM628128ALP–10L HM628128ALP–5SL HM628128ALP–7SL HM628128ALP–8SL HM628128ALP–10SL HM628128ALFP–5 HM628128ALFP–7 HM628128ALFP–8 HM628128ALFP–10 HM628128ALFP–5L HM628128ALFP–7L HM628128ALFP–8L HM628128ALFP–10L Access time 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 525-mil 32-pin plastic SOP (FP-32D) Package 600-mil 32-pin plastic DIP (DP-32) Type No. HM628128ALT–5 HM628128ALT–7 HM628128ALT–8 HM628128ALT–10 HM628128ALT–5L HM628128ALT–7L HM628128ALT–8L HM628128ALT–10L HM628128ALT-5SL HM628128ALT-7SL HM628128ALT-8SL HM628128ALT-10SL HM628128ALR–5 HM628128ALR–7 HM628128ALR–8 HM628128ALR–10 HM628128ALR–5L HM628128ALR–7L HM628128ALR–8L HM628128ALR–10L HM628128ALR-5SL HM628128ALR-7SL HM628128ALR-8SL HM628128ALR-10SL Access time 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 55 ns 70 ns 85 ns 100 ns 8 mm × 20 mm 32-pin TSOP (reverse type) (TFP-32DR) Package 8 mm × 20 mm 32-pin TSOP (normal type) (TFP-32D) HM628128ALFP–5SL 55 ns HM628128ALFP–7SL 70 ns HM628128ALFP–8SL 85 ns HM628128ALFP–10SL 100 ns 2 HM628128A Series Pin Arrangement HM628128ALP/ALFP Series NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 HM628128ALR Series A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 HM628128ALT Series A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CS2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Top View) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CS1 A10 OE Pin Description Pin name A0 – A16 I/O0 – I/O7 CS1 CS2 WE Function Address Input/output Chip select 1 Chip select 2 Write enable Pin name OE NC VCC VSS Function Output enable No connection Power supply Ground 3 HM628128A Series Block Diagram (MSB) A13 A15 A6 A7 A12 A14 A16 A5 A4 (LSB) Row Decoder • • • • • V CC V SS Memory Matrix 512 x 2,048 I/O0 Input Data Control I/O7 • • Column I/O Column Decoder • • (LSB) A8 A9 A11 A10 A0 A1 A2 A3 • • (MSB) CS2 CS1 WE OE Timing Pulse Generator Read/Write Control Function Table CS1 H X L L L L Note: CS2 X L H H H H X: H or L OE X X H L H L WE X X H H L L Mode Standby Standby Output disable Read Write Write VCC current ISB, ISB1 ISB, ISB1 ICC ICC ICC ICC I/O pin High-Z High-Z High-Z Dout Din Din Ref. cycle — — — Read cycle Write cycle (1) Write cycle (2) 4 HM628128A Series Absolute Maximum Ratings Parameter Supply voltage relative to VSS Voltage on any pin relative to VSS Power dissipation Operating temperature Storage temperature Storage temperature under bias Note: *1 Symbol VCC VT PT Topr Tstg Tbias Value –0.5 to +7.0 –0.5 1.0 0 to +70 –55 to +125 –10 to +85 *2 Unit V 0.3*3 V W °C °C °C to VCC + 1. With respect to VSS 2. –3.0 V for pulse half-width ≤ 30 ns 3. Maximum voltage is 7.0V. Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Symbol VCC VSS Input voltage (HM628128A-7/8/10) Input voltage (HM628128A-5) Note: VIH VIL VIH VIL Min 4.5 0 2.2 –0.3 *1 2.4 –0.3 *1 Typ 5.0 0 — — — — Max 5.5 0 VCC + 0.3 0.8 VCC + 0.3 0.8 Unit V V V V V V 1. –3.0 V for pulse half-width ≤ 30 ns 5 HM628128A Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) Parameter Input leakage current Output leakage current Symbol |ILI| |ILO| Min — — Typ*1 — — Max 1.0 1.0 Unit µA µA Test conditions Vin = VSS to VCC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, VI/O = VSS to VCC CS1 = VIL, CS2 = VIH, Others = VIH/VIL II/O = 0 mA Min cycle, duty = 100%, CS1 = VIL, CS2 = VIH, Others = VIH/VIL II/O = 0 mA Operating power supply current: DC Operating power supply current ICC — 15 30 mA — ICC1 (HM628128 A-7/8/10) ICC1 — (HM628128 A-5) ICC2 — 45 70 mA 50 80 mA 15 25 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ VCC – 0.2 V VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V (1) CS1 = VIH, CS2 = VIH or (2) CS2 = VIL 0 V ≤ Vin ≤ VCC , (1) CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or (2) 0 V ≤ CS2 ≤ 0.2 V Standby power supply current: DC Standby power supply current (1): DC ISB — 1 2 2 2 100 50 mA µA µA ISB1 — (L version) ISB1 (L-L/L-SL version) — Output voltage VOL VOH — 2.4 — — 0.4 — V V IOL = 2.1 mA IOH = –1.0 mA Note: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading. Capacitance (Ta = 25°C, f = 1.0 MHz)*1 Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min — — Typ — — Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V 1. This parameter is sampled and not 100% tested. 6 HM628128A Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.) Test Conditions • Input pulse levels: 0.8 V to 2.4 V (HM628128A-7/8/10) 0 V to 3 V (HM628128A-5) • Input rise and fall times: 5 ns • Input and output timing reference levels: 1.5 V • Output load: 1 TTL Gate and CL (100 pF) (HM628128A-7/8/10) 1 TTL Gate and CL (30 pF) (HM628128A-5) (Including scope & jig) Read Cycle HM628128A -5 Parameter Read cycle time Address access time Chip selection to output valid Output enable to output valid Chip selection to output in low-Z Output enable to output in low-Z Chip deselection to output in high-Z Output disable to output in high-Z Output hold from address change Symbol tRC tAA tCO1 tCO2 tOE tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ tOH Min 55 — — — — 5 5 5 0 0 0 5 Max — 55 55 55 30 — — — 20 20 20 — -7 Min 70 — — — — 10 10 5 0 0 0 10 Max — 70 70 70 35 — — — 25 25 25 — -8 Min 85 — — — — 10 10 5 0 0 0 10 Max — 85 85 85 45 — — — 30 30 30 — -10 Min 100 — — — — 10 10 5 0 0 0 10 Max — 100 100 100 50 — — — 35 35 35 — Unit ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes 7 HM628128A Series Read Timing Waveform *4 t RC Address Address Valid t AA CS1 t CO1 t LZ1 CS2 t CO2 t LZ2 t HZ2 t HZ1 OE t OE t OLZ Dout High Impedance t OHZ t OH Data Valid Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 3. This parameter is sampled and not 100% tested. 4. WE is high for read cycle. 8 HM628128A Series Write Cycle HM628128A -5 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Data hold from write time Output active from end of write Symbol tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Min 55 50 0 50 40 0 0 25 0 5 Max — — — — — — 20 — — — -7 Min 70 60 0 60 50 0 0 30 0 5 Max — — — — — — 25 — — — -8 Min 85 75 0 75 55 0 0 35 0 5 Max — — — — — — 30 — — — -10 Min 100 80 0 80 60 0 0 40 0 5 Max — — — — — — 35 — — — Unit ns ns ns ns ns ns ns ns ns ns 10 10 Notes 9 HM628128A Series Write Timing Waveform (1) (OE Clock) t WC Address Address Valid t AW OE t CW *2 CS1 *6 t WR*4 CS2 t AS *3 WE t OHZ *5 High Impedance Dout t DW Din t DH t WP *1 Data Valid 10 HM628128A Series Write Timing Waveform (2) (OE low Fixed) t WC Address Address Valid t CW *2 t WR*4 CS1 *6 CS2 t AW t WP *1 WE t AS *3 t WHZ *5 t OW *7 *8 *11 t OH Dout High Impedance t DW t DH *9 Din Data Valid Notes: 1. A write occurs during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 6. If the CS1 goes low simultaneously with WE going low or after the WE going low, the outputs remain in a high impedance state. 7. Dout is the same phase of the latest written data in this write cycle. 8. Dout is the read data of next address. 9. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the input signals of opposite phase to the outputs must not be applied to them. 10. This parameter is sampled and not 100% tested. 11. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of 11 HM628128A Series data bus contention. tWP ≥ tDW min + tWHZ max Low VCC Data Retention Characteristics (Ta = 0 to +70°C) Parameter VCC for data retention Symbol VDR Min 2.0 Typ — Max — Unit V Test conditions*4 CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V Vin>0 V VCC = 3.0 V, Vin ≥ 0 V CS1 ≥ VCC – 0.2V CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V Data retention current — ICCDR (L version) — ICCDR (L-L version) ICCDR (L-SL version) — 1 1 1 50*1 30*2 15*3 µA µA µA Chip deselect to data retention time Operation recovery time tCDR tR 0 5 — — — — ns ms See retention waveform Low VCC Data Retention Timing Waveform (1) (CS1 Controlled) t CDR V CC 4.5 V Data retention mode tR 2.2 V V DR1 CS1 0V CS1 > VCC – 0.2 V Low VCC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR V CC 4.5 V CS2 V DR2 0.4 V 0V 0 V < CS2 < 0.2 V Data retention mode tR 12 HM628128A Series Notes: 1. 2. 3. 4. 20 µA max at Ta = 0 to 40˚C (L-version). 6 µA max at Ta = 0 to 40˚C (L-L-version). 3 µA max at Ta = 0 to 40˚C (L-SL-version). CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 13