REJ03F0041_M61532FP

M61532FP 8ch Electronic Volume with 9 Input Selector REJ03F0041-0100Z Rev.1.0 Sep.19.2003 Feature FUNCTION Electric Volume Twin Input Selector Multi Channel Input Selector Input Gain Control REC Output Output Gain Control Output for ADC Input ATT FEATURE 8channel independent Electric Volume with High Voltage Transistor. (0~-99.0dB/0.5dBstep,-∞dB) Front L/R channel has twin 9 Input Selector.(Main & Sub) Every channel has 2 Input Selector and Input Gain Control Input Gain Control (0/+6/+12/+18dB) 2 Lines REC Output (Both L and R channels) Output Gain Control (0/+6/+12/+18dB) Built-in Single-end output (for ADC) Input ATT (for ADC:0/-6/-12/-18dB) Application Receiver,AV Amp,Mini Stereo etc. Recommended Operating Condition Supply Voltage Range AVCC=7.0V(typ) , AVEE=-7.0V(typ) , DVDD=2.7~5.5V System Block Diagram SUB OUTL 1 2 3 4 Lch 5 6 7 8 9 Output Gain Control Output Gain Control Output Gain Control Output Gain Control REC OUTL Multi FRin Multi FLin AVEE AVCC DGND DVDD CLOCK MCU I/F DATA LATCH Lout Rout SBLout SBRout Cout SRout SLout SWRout GND Multi SBLin 1 2 3 4 Rch 5 6 7 8 9 Multi SBRin Input ATT (for ADC) Multi Cin ADOUTL Input ATT (for ADC) ADOUTR Multi SRin Output Gain Control Output Gain Control Multi SLin Output Gain Control SUB OUTR REC OUTR Multi SWin Output Gain Control Rev.1.0, Sep.19.2003, page 1 of 14 M61532FP Block Diagram and Pin Configuration (Top View) SBRSELOUT SBLSELOUT 26 SWSELOUT SLSELOUT CSELOUT SBROUT SBLOUT SBRVIN SBLVIN SWOUT SWVIN SLOUT SLVIN COUT CVIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 25 GND 24 41 42 43 44 45 MCU I/F SROUT SRVIN SRSELOUT LSELOUT LVIN LOUT ROUT RVIN RSELOUT GND SBRIN1 SBLIN1 SRIN1 SLIN1 CIN1 SWIN1 LIN1 RIN1 GND SUBOUTR SUBOUTL REC R1 REC L1 GND AVEE GND AVCC DVDD CLOCK LATCH DATA DGND SBRIN2 SBLIN2 SRIN2 SLIN2 CIN2 SWIN2 LIN2 RIN2 GND AROUT ALOUT REC R2 REC L2 GND INL1 INR1 23 22 21 20 INR9 INR8 INR7 INR6 INR5 INR4 INR3 INR2 INL9 INL8 INL7 INL6 INL5 INL4 INL3 Rev.1.0, Sep.19.2003, page 2 of 14 INL2 46 47 48 49 R L SR SL C SW SBR SBL 19 18 17 16 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 67 68 69 70 71 72 73 74 75 76 77 78 79 80 M61532FP Pin Description PIN No. 2,80,78,76,74,72,70,68,66, 1,79,77,75,73,71,69,67,65 3,8,23,25,50,59,64 63,4,62,5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 52 53 54 55 56 57 58 60 61 Name INL1,2,3,4,5,6,7,8,9 INR1,2,3,4,5,6,7,8,9 GND1,2,3,4,5,6,7, REC L1/L2/R1/R2 ALOUT AROUT RIN2 LIN2 SWIN2 CIN2 SLIN2 SRIN2 SBLIN2 SBRIN2 DGND DATA LATCH CLOCK DVDD AVCC AVEE SBLSELOUT SBLVIN SBLOUT SBROUT SBRVIN SBRSELOUT SWSELOUT SWVIN SWOUT COUT CVIN CSELOUT SLSELOUT SLVIN SLOUT SROUT SRVIN SRSELOUT LSELOUT LVIN LOUT ROUT RVIN RSELOUT SBRIN1 SBLIN1 SRIN1 SLIN1 CIN1 SWIN1 LIN1 RIN1 SUBOUTR SUBOUTL Function Input pin of L channel (Input Selector) Input pin of R channel (Input Selector) Analog Ground Output pin of REC L/R Output pin of L channel for ADC(Single ended) Output pin of R channel for ADC(Single ended) Input pin of R channel Input pin of L channel Input pin of SW channel Input pin of C channel Input pin of SL channel Input pin of SR channel Input pin of SBL channel Input pin of SBR channel Ground of internal logic circuit Input pin of Control Data Input pin of Control Trigger Input pin of Control Clock Power supply to internal logic circuit Positive power supply to internal analog circuit Negative power supply to internal analog circuit Output pin of SBL channel volume input selector Input pin of SBL channel volume Output pin of SBL channel Output pin of SBR channel Input pin of SBR channel volume Output pin of SBR channel volume input selector Output pin of SW channel volume input selector Input pin of SW channel volume Output pin of SW channel Output pin of C channel Input pin of C channel volume Output pin of C channel volume input selector Output pin of SL channel volume input selector Input pin of SL channel volume Output pin of SL channel Output pin of SR channel Input pin of SR channel volume Output pin of SR channel volume input selector Output pin of L channel volume input selector Input pin of L channel volume Output pin of L channel Output pin of R channel Input pin of R channel volume Output pin of R channel volume input selector Input pin of SBR channel Input pin of SBL channel Input pin of SR channel Input pin of SL channel Input pin of C channel Input pin of SW channel Input pin of L channel Input pin of R channel Sub Output pin of R channel Sub Output pin of L channel Rev.1.0, Sep.19.2003, page 3 of 14 M61532FP Absolute Maximum Ratings Symbol Supply voltage Pd Kθ Topr Tstg Parameter Power supply Power dissipation Thermal derating Operating temperature Storage temperature Condition AVCC-AVEE DVDD-GND Ta≤25°C Ta>25°C Ratings ±8.0 6.0 1250 12.5 -20~+55 -40~+125 mW mW/°C °C °C Unit V THERMAL DERATINGS (MAXIMUM RATING) 1.5 POWER DISSIPATION pd (W) 1.0 0.5 0 0 55 25 50 75 100 125 150 AMBIENT TEMPERATURE Ta ( C) Rev.1.0, Sep.19.2003, page 4 of 14 M61532FP Recommended Operating Conditions (Ta=25°C, unless otherwise noted) Parameter Analog supply voltage (Positive) Analog supply voltage (Negative) Digital supply voltage Logic “H” level input voltage Logic “L” level input voltage Symbol AVCC AVEE DVDD VIH VIL DGND reference DGND reference Condition MIN 4.5 -7.5 2.7 DVDD x 0.7 DGND TYP 7.0 -7.0 3.3   MAX 7.5 -4.5 5.5 DVDD DVDD x 0.2 Unit V V V V V Note:VEE≤DGND≤VDD≤VCC Relationship Between Data and Clock H LATCH SIGNAL D0 D1 D21 D22 D23 D0 DATA L H CLOCK L H LATCH L DATA signal is read at the rising edge of CLOCK. Serial data (D0 – D23) is loaded at the rising edge of the LATCH signal. Rev.1.0, Sep.19.2003, page 5 of 14 M61532FP Clock and Data Timings tcr 75% tSC CLOCK 25% 25% tr tWHC tf tWLC 75% 25% DATA tr tf tSD tHD tSL tr tWHC tf 75% 25% LATCH Timing Definition of Digital Block Limits Symbol tcr tWHC tWLC tr tf tSD tHD tSL tWHL tSC Parameter Clock cycle time Clock pulse width (“H” level) Clock pulse width (“L” level) Rising time of clock,data and latch Falling time of clock,data and latch Data setup time Data hold time Latch setup time Latch pulse width Clock setup time Min 4 1.6 1.6   0.8 0.8 1 1.6 4 typ           Max    0.4 0.4      Unit µsec Rev.1.0, Sep.19.2003, page 6 of 14 M61532FP D0a D14a D19a D15a D16a D20a D17a D21 D18a D22 D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D23 Data Control Specification Rev.1.0, Sep.19.2003, page 7 of 14 Input Selector (Sub) Input ATT 0 0 Input Gain Control Output Gain Control REC Output 1 REC Output 2 Multi Input Selector Multi Input Mute FL/FR VOL Control All ch Output Mute Input Selector (Main) 0 0 D0b D15b D16b D17b D18b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14b D19b D20b D21 D22 D23 FLch Volume FRch Volume 0 0 0 0 0 0 0 1 D0c D15c D16c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14c D17c D18c D19c D20c D21 D22 D23 Cch Volume SWch Volume 0 0 0 0 0 0 1 0 D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14c D15c D16c D17c D18c D19c D20c D21 D22 D23 Initialize all data of the 5 formats when Digital Power supply (DVDD) turn on. SLch Volume SRch Volume 0 0 0 0 0 0 1 1 D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14c D15c D16c D17c D18c D19c D20c D21 D22 D23 SBLch Volume SBRch Volume 0 0 0 0 0 1 0 0 M61532FP Setting Code (1) Input Selector Main Setting Sub ALL OFF IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 (2) Input ATT Setting 0dB -6dB -12dB -18dB (3) REC Output REC Output Setting OFF ON D0a D4a 0 0 0 0 0 0 0 0 1 1 D1a D5a 0 0 0 0 1 1 1 1 0 0 D2a D6a 0 0 1 1 0 0 1 1 0 0 D3a D7a 0 1 0 1 0 1 0 1 0 1 (4) Multi Input Setting Multi In1 Multi In2 D12a 0 1 (5) Multi Input Mute (Except For FL/FR) Setting D13a Mute OFF 0 depend on (4) Multi Input Mute ON 1 (6) FL/FR VOL Input Setting Bypass Multi Input (7) Input Gain Control Setting 0dB +6dB +12dB +18dB (8) Output Gain Control Setting 0dB +6dB +12dB +18dB (9) All Ch Output Mute Setting Mute off Mute on D14a 0 1 D8a 0 0 1 1 D9a 0 1 0 1 D15a D16a 0 0 0 1 1 0 1 1 REC1 REC2 D10a D11a 0 0 1 1 D17a D18a 0 0 0 1 1 0 1 1 D19a 0 1 It's initial setting when power is turned on. Rev.1.0, Sep.19.2003, page 8 of 14 M61532FP (9)6 channel Volume ATT - - - FLch FRch Cch SWch SLch SRch SBLch SBRch 0.0 dB 0.5 dB 1.0 dB 1.5 dB 2.0 dB 2.5 dB 3.0 dB 3.5 dB 4.0 dB 4.5 dB 5.0 dB 5.5 dB 6.0 dB • • 50.0 dB 50.5 dB 51.0 dB 51.5 dB 52.0 dB • • 95.0 dB 95.5 dB 96.0 dB 96.5 dB 97.0 dB 97.5 dB 98.0 dB 98.5 dB 99.0 dB ∞ dB D0b D8b D0c D8c D0d D8d D0e D8e 0 0 0 0 0 0 0 0 0 0 0 0 0 D1b D9b D1c D9c D1d D9d D1e D9e 0 0 0 0 0 0 0 0 0 0 0 0 0 D2b D10b D2c D10c D2d D10d D2e D10e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 D3b D11b D3c D11c D3d D11d D3e D11e 0 0 0 0 0 0 0 0 0 0 0 0 0 • • 0 0 0 0 0 • • 1 1 0 0 0 0 0 0 0 1 D4b D12b D4c D12c D4d D12d D4e D12e 0 0 0 0 0 0 0 0 1 1 1 1 1 D5b D13b D5c D13c D5d D13d D5e D13e 0 0 0 0 1 1 1 1 0 0 0 0 1 D6b D14b D6c D14c D6d D14d D6e D14e 0 0 1 1 0 0 1 1 0 0 1 1 0 D7b D15b D7c D15c D7d D15d D7e D15e 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 It's initial setting when power is turned on. Rev.1.0, Sep.19.2003, page 9 of 14 M61532FP Electrical Characteristics Unless otherwise noted, Ta=25°C,AVCC=7V,AVEE=-7V,DVDD=3.3V,f=1kHz, Volume=0dB, Input Selector=IN1,Input ATT=0dB,Input Gain Control=0dB,Output Gain Control=0dB, L/R Volume Input=Bypass,Multi Input Selector=Multi IN1 setting (1) Power supply characteristics Limits Parameter Analog positive power circuit current Analog negative power Circuit current Digital power circuit current Symbol AIcc Test condition With AVCC=7V and AVEE=-7V Pin22 pin current, when no signal is provided With AVCC=7V and AVEE=-7V Pin24 pin current, when no signal is provided With DVDD=3.3V, Pin21 pin current, when no signal is provided min  typ 50 max 70 Unit mA AIee -70 -50  mA Dldd  3 6 mA (2) Input/Output characteristics (OVER ALL) Limits Parameter Input resistance Maximum output voltage Symbol Rin VOM Test Condition 65-80pin when each selector chooses a terminal concerned (1,2,51,5253,54,55,56) pin input, (47,46,29,28,41,40,35,34) pin output, THD=1%, RL=10kΩ Output Gain Control =+12dB setting (1,2,51,5253,54,55,56) pin input, (47,46,29,28,41,40,35,34) pin output, Vi=0.3Vrms,FLAT (1,2,51,5253,54,55,56) pin input, (47,46,29,28,41,40,35,34) pin output, BW:400Hz~30kHz f=1kHz , Vo=0.3Vrms , RL=10kΩ (1,2,51,5253,54,55,56) pin input, (47,46,29,28,41,40,35,34) pin output, BW:400Hz~30kHz f=1kHz , Vo=2Vrms , RL=10kΩ (1,2)pin input,(47,46)pin output, Vi=0.3Vrms , JIS-A JIS-A , (1,2,51,5253,54,55,56) pin: Output Gain Rg=0Ω, Control=0dB (47,46,29,28,41,40,35,34) pin Output Gain output, Control=+12dB Volume=-∞dB setting JIS-A , (1,2)pin : Output Gain Rg=0Ω, Control=0dB (47,46)pin output, Output Gain Volume=0dB setting Control=+12dB JIS-A , (1,2)pin:Rg=0Ω (5.4)pin output min 35 3.6 typ 47 4.2 max 65  Unit kΩ Vrms Pass gain Gv -2.0  0 2.0 dB Distortion THD1 0.00 5 0.05 % THD2  0.03 0.1 % Channels balance Output noise voltage CBAL Vono (VOL =-∞dB) Vono (VOL=0dB) -0.5      0 1.5 9 2.5 12 3 0.5 6 20 8 25 9 dB µVrms µVrms µVrms µVrms µVrms Vonodac (dac out) Rev.1.0, Sep.19.2003, page 10 of 14 M61532FP Limits Parameter Input/Multi selector channel separation Symbol CS1 Test Condition (47,46)pin output, Vo=1Vrms , Rg=0Ω, RL=10kΩ, JIS-A min  typ -90 max -70 Unit dB CS2 (47,46,29,28,41,40,35,34) pin output, Vo=1Vrms , Rg=0Ω, RL=10kΩ, JIS-A, FL/FR VOL Input=Multi input  -90 -70 dB Cross talk between channels CT1 (L/R) CT2 (Multi Input) (1,2) pin input, (47,46) pin output, Vo=1Vrms , Rg=0Ω, RL=10kΩ, JIS-A (51,52,10,53,54,55,56,57,58) pin input, (29,28,41,40,35,34,47,46) pin output, Vo=1Vrms , Rg=0Ω, RL=10kΩ, JIS-A, L/R VOL Input=Multi input   -90 -90 -70 -70 dB dB (3) 8 channel Volume characteristics Limits Parameter Maximum attenuation Volume gain Between channels Symbol ATTmax Dvol Test condition (47,46,29,28,41,40,35,34) pin output, Vi=2Vrms,JIS-A,VOL=-∞ (47,46,29,28,41,40,35,34) pin output, Volume=0dB setting min  -0.5 typ -100 0 max -95 +0.5 Unit dB dB Rev.1.0, Sep.19.2003, page 11 of 14 57 10 0~-99dB,mute 47k 47k Input Gain Control 0/+6/+12/+18dB M61532FP Input Selector (Sub) 61 4 47k 47k LIN1 LIN2 44 45 Lch VOL Output Gain Control 46 LOUT 63 6 58 9 0~-99dB,mute 47k 47k Input Gain Control 0/+6/+12/+18dB RIN1 RIN2 49 48 Rch VOL 47 ROUT Output Gain Control Internal Block Diagram 2 38 47k Input ATT 0/-6/-12/-18dB 54 13 47k Input Gain Control 0/+6/+12/+18dB SLIN1 SLIN2 47k 39 40 0~-99dB,mute Rev.1.0, Sep.19.2003, page 12 of 14 SLOUT SLch VOL Output Gain Control 80 47k 47k 47k 47k 47k 53 14 47k 47k 47k SRIN1 SRIN2 Input Gain Control 0/+6/+12/+18dB 43 42 41 0~-99dB,mute 78 76 74 72 70 68 47k INL1 INL2 INL3 INL4 INL5 INL6 INL7 INL8 INL9 Input Selector (Main) Input Selector (Sub) 60 5 47k 47k 66 47k SRch VOL SROUT Output Gain Control 62 7 CIN1 CIN2 55 12 Input Gain Control 0/+6/+12/+18dB 37 36 Cch VOL 35 0~-99dB,mute 47k 47k COUT Output Gain Control 56 11 47k SWIN1 SWIN2 47k Input Gain Control 0/+6/+12/+18dB 32 33 SWch VOL 34 0~-99dB,mute SWOUT Output Gain Control 1 47k Input ATT 0/-6/-12/-18dB 52 15 47k 79 47k 47k 47k SBLIN1 SBLIN2 47k Input Gain Control 0/+6/+12/+18dB 26 27 28 SBLch VOL 0~-99dB,mute 47k SBLOUT Output Gain Control 47k 47k 47k 47k INR1 INR2 INR3 INR4 INR5 INR6 INR7 INR8 INR9 DVDD AVCC AVEE -7V DGND +5.0V +7V 34 30 36 64 77 75 73 71 69 67 65 Input Selector (Main) 47k 51 16 SBRIN1 SBRIN2 47k Input Gain Control 0/+6/+12/+18dB 31 30 SBRch VOL 29 0~-99dB,mute SBROUT Output Gain Control M61532FP Application Example SBROUT 4.7u 4.7u SLOUT SLOUT SWOUT SLOUT 4.7u 4.7u SLOUT SBLOUT 4.7u SLSELOUT CSELOUT COUT SWSELOUT SBRSELOUT SLVIN 40 4.7u 39 38 37 36 35 34 SWVIN CVIN 33 32 31 30 SBRVIN + + + + 29 28 SBLVIN + 26 27 25 100u 0.1u AVEE GND 4.7u 4.7u 4.7u 4.7u 4.7u SBLSELOUT 41 24 SROUT 4.7u SRSELOUT LSELOUT 4.7u 4.7u LOUT 4.7u ROUT 4.7u RSELOUT +SRVIN + + 100u CLOCK LATCH DATA 0.1u 42 43 44 23 22 21 GND AVCC DVDD + 45 MCU I/F 20 LVIN M C U 100u + 0.1u 46 47 19 18 + RVIN 48 49 R L SR SL C SW SBR SBL 17 DGND GND 2.2u SBRIN1 2.2u SBLIN1 2.2u SRIN1 2.2u SLIN1 2.2u CIN1 2.2u SWIN1 2.2u LIN1 2.2u RIN1 GND 4.7u SUBOUTR 4.7u SUBOUTL 4.7u REC R1 4.7u REC L1 GND + + + + + + + + 2.2u SBRIN2 2.2u SBLIN2 2.2u 2.2u 2.2u SRIN2 SLIN2 CIN2 16 INR9 INR8 INR7 INR6 INR5 INR4 INR3 INR2 INL9 INL8 INL7 INL6 INL5 INL4 INL3 Rev.1.0, Sep.19.2003, page 13 of 14 INL2 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 2.2u 2.2u 2.2u 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2.2u SWIN2 2.2u 2.2u GND 4.7u AROUT 4.7u ALOUT 4.7u REC R2 4.7u REC L2 GND 2.2u INL1 2.2u INR1 LIN2 RIN2 67 68 69 70 71 72 73 74 75 76 77 78 79 80 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u 2.2u M61532FP 80P6N-A JEDEC Code — MD Weight(g) 1.58 Lead Material Alloy 42 MMP Plastic 80pin 14✕20mm body QFP EIAJ Package Code QFP80-P-1420-0.80 e Package Dimensions HD D 65 64 E 24 41 25 40 HE A2 c x M A1 Rev.1.0, Sep.19.2003, page 14 of 14 1 b2 I2 Recommended Mount Pad Symbol A L1 A A1 A2 b c D E e HD HE L L1 x y L Detail F F e b y b2 I2 MD ME Dimension in Millimeters Min Nom Max — — 3.05 0.1 0.2 0 2.8 — — 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.8 — — 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 — — — — 0.2 0.1 — — 0˚ 10˚ — 0.5 — — 1.3 — — 14.6 — — — — 20.6 ME 80 Sales Strategic Planning Div. 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