HMC708LP5E

HMC708LP5 / 708LP5E v03.0409 0.5 dB LSB 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 1700 - 2200 MHz Typical Applications The HMC708LP5(E) is ideal for: • Cellular Infrastructure • WiBro, WiMAX and LTE/ 4G • Microwave Radio & VSAT • Test Equipment and Sensors Features -2.5 to +29 dB Gain Control in 0.5 dB Steps Power-up State Selection High Output IP3: +37 dBm Low Noise Figure: 1 dB TTL/CMOS Compatible Serial, Parallel, or Latched Parallel Control ±0.25 dB Typical Step Error Single +3V and +5V Supply 32 Lead 5x5mm SMT Package: 25mm2 Functional Diagram 13 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT General Description The HMC708LP5(E) is a digitally controlled variable gain amplifier which operates from 1700 MHz and 2200 GHz, and can be programmed to provide between 2.5 dB attenuation and +29 dB of gain, in 0.5 dB steps. The HMC708LP5(E) delivers noise figure of 1 dB in its maximum gain state, with output IP3 of up to +37 dBm. The dual mode gain control interface accepts either three wire serial input or 6 bit parallel word. The HMC708LP5(E) also features a user selectable power up state and a serial output for cascading other Hittite serially controlled components. For 900 MHz applications please refer to the HMC707LP5(E) data sheet. Electrical Specifi cations, TA = +25° C Rbias = 270 Ohms for Vdd = +5V, Rbias = 10k Ohms for Vdd = +3V, Vdd = Vdd1 = Vdd2 = Vdd3 Min. Parameter Vdd = +3V Frequency Range Gain (Maximum Gain State) Gain Control Range Input Return Loss Output Return Loss Attenuation Accuracy: (Referenced to Maximum Gain State) Output Power for 1 dB Compression Output Third Order Intercept Point (Two-Tone Input Power= -10 dBm Each Tone) Noise Figure Switching Characteristics tRISE, tFALL (50% CTL to 90% RF) Current Amplifier 1 Current Amplifier 2 tRISE tFALL 30 130 23 1.7 - 2.2 27 31.5 16.5 10.5 ±(0.3 + 8%) of Attenuation Setting 13 16 32.5 1.1 47 155 65 190 80 130 25 Vdd = +5V 1.7 - 2.2 30 31.5 20.5 13.5 ±(0.2 + 5%) of Attenuation Setting 18 21.5 37.5 1 140 270 97 155 135 190 GHz dB dB dB dB dB dBm dBm dB ns ns mA mA Typ. Max. Min. Typ. Max. Units [1] Two-tone output power @ -10 dBm [2] Two-tone output power @ -5 dBm 13 - 96 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC708LP5 / 708LP5E v03.0409 0.5 dB LSB 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 1700 - 2200 MHz Maximum Gain vs. Frequency [1] 40 Vdd=5V +25C +85C -40C Normalized Attenuation (Only Major States are Shown) 0 NORMALIZED ATTENUATION (dB) -5 -10 -15 -20 -25 -30 -35 1.5 Vdd=3V Vdd=5V 36 GAIN (dB) 32 28 Vdd=3V 24 20 1.5 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 1.6 1.7 1.8 1.9 2 2.1 2.2 FREQUENCY (GHz) 2.3 2.4 2.5 13 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 13 - 97 Input Return Loss (Only Major States are Shown) 0 Output Return Loss (Only Major States are Shown) 0 RETURN LOSS (dB) -20 RETURN LOSS (dB) -10 Vdd=3V Vdd=5V -5 Vdd=3V Vdd=5V -10 -30 -15 -40 1.5 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 -20 1.5 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 Output IP3 vs. Tone Power [1] 48 44 40 IP3 (dBm) 36 32 Pout=-15dBm Pout=-10dBm Pout= -5dBm Pout= 0dBm Output IP3 vs. Attenuation @ 1900 MHz 40 Power Out = -10dBm Vdd=5V 30 IP3 (dBm) 20 10 28 Vdd=3V Vdd=3V Vdd=5V 24 1.7 0 1.8 1.9 2 FREQUENCY (GHz) 2.1 2.2 0 4 8 12 16 20 24 ATTENUATION STATE (dB) 28 32 [1] Maximum gain state with digital attenuator set to minimum attenuation For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC708LP5 / 708LP5E v03.0409 0.5 dB LSB 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 1700 - 2200 MHz Bit Error vs. Frequency @ +3V (Only Major States are Shown) 3 2 BIT ERROR (dB) BIT ERROR (dB) 1 0 -1 Vdd = 3V Bit Error vs. Frequency @ +5V (Only Major States are Shown) 3 2 1 0 -1 Vdd = 5V -2 -3 1.5 -2 -3 1.5 1.7 1.9 2.1 2.3 2.5 1.7 1.9 2.1 2.3 2.5 13 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 2.5 2 BIT ERROR (dB) 1.5 1 0.5 0 -0.5 0 4 8 FREQUENCY (GHz) FREQUENCY (GHz) Bit Error vs. Attenuation State @ +3V Vdd=3V (1.7, 1.8, 1.9, 2.0, 2.1, 2.2) GHz Bit Error vs. Attenuation State @ +5V 2.5 2 BIT ERROR (dB) Vdd=5V (1.7, 1.8, 1.9, 2.0, 2.1, 2.2) GHz 1.5 1 0.5 0 -0.5 12 16 20 24 ATTENUATION STATE (dB) 28 32 0 4 8 12 16 20 24 ATTENUATION STATE (dB) 28 32 Normal Relative Phase vs. Frequency (Only Major States are Shown) 30 20 10 0 -10 -20 -30 1.5 Vdd=3V Vdd=5V RELATIVE PHASE (deg) 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 13 - 98 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC708LP5 / 708LP5E v03.0409 0.5 dB LSB 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 1700 - 2200 MHz Step Error vs. Frequency @ +3V (Only Major States are Shown) 2 Vdd = 3V Step Error vs. Frequency @ +5V (Only Major States are Shown) 2 Vdd = 5V STEP ERROR (dB) 0 STEP ERROR (dB) 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 1 1 0 -1 -1 -2 1.5 -2 1.5 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 13 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 13 - 99 Noise Figure vs. Frequency 2 Noise Figure vs. Attenuation @ 1900 MHz 20 1.6 NOISE FIGURE (dB) 1.2 NOISE FIGURE (dB) Vdd=3V Vdd=5V 16 Vdd=3V Vdd=5V 12 0.8 8 0.4 4 0 1.5 0 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 0 4 8 12 16 20 24 ATTENUATION (dBm) 28 32 Output IP3 & Supply Current vs. Supply Voltage @ 1900 MHz 44 Idd Output IP3 & Supply Current vs. Rbias @ 1900 MHz 300 45 500 40 IP3 (dBm) 250 IP3 (dBm) 35 400 DC CURRENT (mA) Idd (mA) 36 200 25 Vdd=3V Vdd=5V 300 32 IP3 @1.9GHz 150 15 200 28 2.7 100 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VOLTAGE SUPPLY (V) 5 1 10 100 Rbias (Ohms) 1000 100 10000 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC708LP5 / 708LP5E v03.0409 0.5 dB LSB 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 1700 - 2200 MHz Option 1 [1] : Amp1 + 6-Bit DAT only Gain & Return Loss [1] [2] 30 S21 Noise Figure vs. Frequency [1] [2] 2 20 10 0 -10 S22 Vdd=3V Vdd=5V 1.6 NOISE FIGURE (dB) Vdd=3V Vdd=5V RESPONSE (dB) 1.2 S11 0.8 -20 -30 1.5 0.4 13 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 1.6 1.7 1.8 1.9 2 2.1 2.2 FREQUENCY (GHz) 2.3 2.4 2.5 0 1.5 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 Output IP3 vs. Attenuation @ 1900 MHz [1] 30 Power Out = -20dBm 20 IP3 (dBm) 10 0 Vdd=3V Vdd=5V -10 -20 0 4 8 12 16 20 24 ATTENUATION STATE (dB) 28 32 [1] See Application Circuit [2] Maximum gain state with digital attenuator set to minimum attenuation 13 - 100 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC708LP5 / 708LP5E v03.0409 0.5 dB LSB 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 1700 - 2200 MHz Option 2 [1] : 6 -Bit DAT + Amp2 only Gain & Return Loss [1] [2] 20 15 S21 Output IP3 vs. Attenuation @ 1900 MHz [1] 44 Pout=0dBm 40 36 Setup limit 10 RESPONSE (dB) Vdd=3V Vdd=5V S11 IP3 (dBm) 5 0 -5 -10 32 28 24 Pout=-5dBm Vdd=3V Vdd=5V -15 S22 -20 1.5 20 1.6 1.7 1.8 1.9 2 2.1 2.2 FREQUENCY (GHz) 2.3 2.4 2.5 0 4 8 12 16 20 24 ATTENUATION STATE (dB) 28 32 13 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 13 - 101 Serial Control Interface The HMC708LP5(E) contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. Standard logic families work well. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded asynchronously with parallel digital inputs (D0-D5). When LE is high, 6-bit parallel data is transferred to the attenuator. For all modes of operations, attenuation state will stay constant while LE is kept low. [1] See Application Circuit [2] Maximum gain state with digital attenuator set to minimum attenuation For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC708LP5 / 708LP5E v03.0409 0.5 dB LSB 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 1700 - 2200 MHz Timing Diagram (Latched Parallel Mode) Parameter Min. serial period, tSCK Control set-up time, tCS Control hold-time, tCH LE setup-time, tLN Min. LE pulse width, tLEW Min LE pulse spacing, tLES Serial clock hold-time from LE, tCKN Hold Time, tPH. Latch Enable Minimum Width, tLEN Setup Time, tPS Typ. 100 ns 20 ns 20 ns 10 ns 10 ns 630 ns 10 ns 0 ns 10 ns 2 ns 13 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control the attenuator in this manner. Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. Power-Up States If LE is set to logic LOW at power-up, the logic state of PUP1 and PUP2 determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. The DVGA latches in the desired power-up state approximately 200 ms after power-up. PUP Truth Table LE 0 0 0 0 1 PUP1 0 1 0 1 X PUP2 0 0 1 1 X Gain Relative to Maximum Gain -31.5 -24 -16 Insertion Loss 0 to -31.5 dB Power-On Sequence The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered after Vdd / GND Note: The logic state of D0 - D5 determines the powerup state per truth table shown below when LE is high at power-up. Truth Table Control Voltage Input D5 D4 High High High High High Low High Low D3 High High High High Low High High Low D2 High High High Low High High High Low D1 High High Low High High High High Low D0 High Low High High High High High Low Gain Relative to Maximum Gain 0 dB -0.5 dB -1 dB -2 dB -4 dB -8 dB -16 dB -31.5 dB Control Voltage Table State Low High Vdd = +3V 0 to 0.5V @