HMCAD1050-80

HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter Features • 13-bit resolution • 65/80 MsPs Maximum sampling rate • Ultra-Low Power Dissipation: 85/102 mW • 72 dB snr @ 8 MHz FIn • Internal reference Circuitry • 1.8 v Core supply voltage • 1.7 - 3.6 v I/o supply voltage • Parallel CMos output • 9 x 9 mm 64-Pin QFn (LP9e) Package General Description the HMCAD1050-80 is a high performance low power dual analog-to-digital converter (ADC). the ADC employs internal reference circuitry, a CMos control interface, CMos output data and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. several idle modes with fast startup times exist. each channel can be independently powered down and the entire chip can either be put in standby Mode or Power Down mode. the different modes are optimized to allow the user to select the mode resulting in the lowest possible energy consumption during idle mode and startup. the HMCAD1050-80 has a highly linear tHA optimized for frequencies up to 70 MHz. the differential clock interface is optimized for low jitter clock sources and supports LvDs, LvPeCL, sine wave and CMos clock inputs. Pin compatible with HMCAD1040-40, HMCAD1040-80 and HMCAD1050-40. 0 A / D Converters - sMt • Dual Channel typical applications • Handheld Communication, PMr, sDr • Medical Imaging • Portable test equipment • Digital oscilloscopes • Baseband / IF Communication • video Digitizing • CCD Digitizing Functional Diagram Figure 1. Functional Block Diagram F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 0-1 HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter electrical Specifications DC electrical Specifications AvDD=1.8v, DvDD=1.8v, DvDDCK=1.8v, ovDD=2.5v, 65/80MsPs clock, 50% clock duty cycle, -1dBFs 8MHz input signal, 13 bit output, unless otherwise noted Parameter DC accuracy no missing codes offset error Gain error Gain matching DnL InL vCM Analog Input Input common mode Full scale range, normal Full scale range, option Input capacitance Bandwidth Power Supply Core supply voltage I/o supply voltage supply voltage to all 1.8v domain pins. see Pin Configuration and Description output driver supply voltage (ovDD). should be higher than or equal to Core supply voltage (vovDD ≥ vDvDD) 1.7 1.7 1.8 2.5 2 3.6 v v Analog input common mode voltage Differential input voltage range, Differential input voltage range, 1v (see section reference voltages) Differential input capacitance Input Bandwidth 500 vCM - 0.1 2 1 2 vCM +0.2 v vpp vpp pF MHz Midscale offset Full scale range deviation from typical Gain matching between channels. ± 3 sigma value at worst case conditions Differential nonlinearity (12-bit level) Integral nonlinearity (12-bit level) Common mode voltage output ± 0.5 ± 0.2 ± 0.6 vAvDD/2 Guaranteed 1 ±6 LsB %Fs %Fs LsB LsB v Condition Min Typ Max Unit 0 A / D Converters - sMt 0-2 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter aC electrical Specifications - 65 MSPS AvDD=1.8v, DvDD= 1.8v, DvDDCK= 1.8v, ovDD=2.5v, Fs=65 MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, 13 bit output, unless otherwise noted. Parameter Performance snr signal to noise ratio FIn = 8 MHz FIn = 20 MHz FIn =~ Fs/2 FIn = 40 MHz snDr signal to noise and Distortion ratio FIn = 8 MHz FIn = 20 MHz 70.5 71.7 71.7 71.1 70 75 81 84 79 77 -85 -95 -95 -95 -95 -75 -81 -84 -79 -79 11.4 11.6 11.6 11.5 11.3 -95 32.8 Digital core supply 2.5v output driver supply, sine wave input, FIn = 1 MHz, CK_eXt enabled 2.5v output driver supply, sine wave input, FIn = 1 MHz, CK_eXt disabled ovDD = 2.5v, ~5pF load on output bits, FIn = 1 MHz, CK_eXt disabled ovDD = 2.5v, ~5pF load on output bits, FIn = 1 MHz, CK_eXt disabled Power Dissipation, sleep mode one channel Power Dissipation, sleep mode both channels 65 3 5 8.2 6.6 59 25.5 84.5 9.3 55.3 20.4 dBFs dBFs dBFs dBFs dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dB mA mA mA mA mW mW mW µW mW mW MsPs MsPs 71.6 72.6 71.8 71.5 70.4 dBFs dBFs dBFs dBFs Condition Min Typ Max Unit 0 A / D Converters - sMt FIn =~ Fs/2 FIn = 40 MHz sFDr spurious Free Dynamic range FIn = 8 MHz FIn = 20 MHz FIn =~ Fs/2 FIn = 40 MHz HD2 second order Harmonic Distortion FIn = 8 MHz FIn = 20 MHz FIn =~ Fs/2 FIn = 40 MHz HD3 third order Harmonic Distortion FIn = 8 MHz FIn = 20 MHz FIn =~ Fs/2 FIn = 40 MHz enoB effective number of Bits FIn = 8 MHz FIn = 20 MHz FIn =~ Fs/2 FIn = 40 MHz Crosstalk Power Supply Analog supply current Digital supply current output driver supply output driver supply Analog power Dissipation Digital power Dissipation total power Dissipation Power Down Dissipation sleep Mode 1 sleep Mode 2 Clock Inputs Max. Conversion rate Min. Conversion rate signal crosstalk between channels, FIn1 = 8MHz, FIn0 = 9.9MHz 0-3 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter aC electrical Specifications - 80 MSPS AvDD=1.8v, DvDD=1.8v, DvDDCK=1.8v, ovDD=2.5v, Fs=80MsPs clock, 50% clock duty cycle, -1dBFs 8MHz input signal, 13 bit output, unless otherwise noted. Parameter Performance snr signal to noise ratio FIn = 8 MHz FIn = 20 MHz FIn = 30 MHz FIn =~ Fs/2 snDr signal to noise and Distortion ratio FIn = 8 MHz FIn = 20 MHz FIn = 30 MHz FIn =~ Fs/2 sFDr spurious Free Dynamic range FIn = 8 MHz FIn = 20 MHz FIn = 30 MHz FIn =~ Fs/2 HD2 second order Harmonic Distortion FIn = 8 MHz FIn = 20 MHz FIn = 30 MHz FIn =~ Fs/2 HD3 third order Harmonic Distortion FIn = 8 MHz FIn = 20 MHz FIn = 30 MHz FIn =~ Fs/2 enoB effective number of Bits FIn = 8 MHz FIn = 20 MHz FIn = 30 MHz FIn =~ Fs/2 Crosstalk Power Supply Analog supply current Digital supply current output driver supply output driver supply Analog power Dissipation Digital power Dissipation total power Dissipation Power Down Dissipation sleep Mode 1 sleep Mode 2 Clock Inputs Max. Conversion rate Min. Conversion rate 80 3 MsPs MsPs Power Dissipation, sleep mode one channel Power Dissipation, sleep mode both channels ovDD = 2.5v, 5pF load on output bits, FIn = 1 MHz, CK_eXt disabled ovDD = 2.5v, 5pF load on output bits, FIn = 1 MHz, CK_eXt disabled Digital core supply 2.5v output driver supply, sine wave input, FIn = 1 MHz, CK_eXt enabled 2.5v output driver supply, sine wave input, FIn = 1 MHz, CK_eXt disabled 39.7 6 9.4 7.7 71.5 30 101.5 9.1 66.4 24.1 mA mA mA mA mW mW mW µW mW mW signal crosstalk between channels, FIn1 = 8MHz, FIn0 = 9.9MHz 11.3 11.4 11.4 11.4 11.4 -95 bits bits bits bits dB -74 -77 -78 -78 -78 dBc dBc dBc dBc -80 -95 -90 -90 -85 dBc dBc dBc dBc 74 77 78 78 78 dBc dBc dBc dBc 69.5 70.5 70.5 70.4 70.3 dBFs dBFs dBFs dBFs 70.4 72 71.7 71.2 70.7 dBFs dBFs dBFs dBFs Condition Min Typ Max Unit 0 A / D Converters - sMt 0-4 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter Digital and timing Specifications AvDD= 1.8v, DvDD= 1.8v, DvDDCK= 1.8v, ovDD= 2.5v, Conversion rate: Max specified, 50% clock duty cycle, -1 dBFs input signal, 5 pF capacitive load on data outputs, unless otherwise noted Parameter Clock Inputs Duty Cycle Compliance Input range Input range Input common mode voltage Input capacitance Timing tPD tsLP tovr tAP Єrms tLAt tD tDC Logic Inputs vHI vHI vLI vLI IHI ILI CI Logic Outputs vHo vLo CL CL High Level output voltage Low Level output voltage Max capacitive load. Post-driver supply voltage equal to digital supply voltage vovDD = vDvDD Max capacitive load. Post-driver supply voltage above 2.25v (1) 10 vovDD -0.1 0.1 5 v v pF pF High Level Input voltage. vovDD ≥ 3.0v High Level Input voltage. vovDD = 1.7v – 3.0v Low Level Input voltage. vovDD ≥ 3.0v Low Level Input voltage. vovDD = 1.7v – 3.0v High Level Input leakage Current Low Level Input leakage Current Input Capacitance 3 2 0.8 ·vovDD 0 0 0.8 0.2 ·vovDD ±10 ±10 v v v v µA µA pF Differential input swing Differential input swing, sine wave clock input Keep voltages within ground and voltage of ovDD Differential start up time from Power Down Mode to Active Mode start up time from sleep Mode to Active Mode out of range recovery time Aperture Delay Aperture jitter Pipeline Delay output delay (see timing diagram). 5pF load on output bits output delay relative to CK_eXt (see timing diagram) 3 1 1 0.8 < 0.5 12 10 6 20 0.4 1.6 0.3 2 900 20 vovDD -0.3 80 % high vpp vpp v pF clock cycles clock cycles clock cycles ns ps clock cycles ns ns CMos, LvDs, LvPeCL, sine Wave Condition Min Typ Max Unit 0 A / D Converters - sMt 0-5 (1) the outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter timing Diagram 0 Figure 2: timing Diagram absolute Maximum ratings Absolute maximum ratings are limiting values to be applied for short periods of time. exposure to absolute maximum rating conditions for an extended period of time may reduce device lifetime. table 1: Pin AvDD DvDD Avss, DvssCK, Dvss, ovss ovDD IPx, Inx, analog inputs and outputs Digital outputs CKP, CKn Digital Inputs operating temperature storage temperature soldering Profile Qualification Pin Avss Dvss Dvss ovss Avss ovss DvssCK ovss Rating -0.3v to +2.3v -0.3v to +2.3v -0.3v to +0.3v -0.3v to +3.9v -0.3v to +2.3v -0.3v to +3.9v -0.3v to +3.9v -0.3v to +3.9v -40 to +85 ºC -60 to +150 ºC J-stD-020 eLeCtrostAtIC sensItIve DevICe oBserve HAnDLInG PreCAUtIons stresses above those listed under Absolute Maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 0-6 A / D Converters - sMt HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter Pin Configuration and Description 0 A / D Converters - sMt Figure 3: Package Drawing, 64-pin QFn or tQFP table 2: Pin Function Pin # 1, 18, 23 2 3, 9, 12 4, 5, 8 6, 7 10, 11 13 14 15 16 17, 64 19 20 Name DvDD CM_eXt AvDD Avss IP0, In0 IP1, In1 DvssCK DvDDCK CKP CKn Dvss CK_eXt_en DFrMt Description Digital and I/o-ring pre driver supply voltage, 1.8v Common Mode voltage output Analog supply voltage, 1.8v Analog ground Analog input Channel 0 (non-inverting, inverting) Analog input Channel 1 (non-inverting, inverting) Clock circuitry ground Clock circuitry supply voltage, 1.8v Clock input, non-inverting (Format: LvDs, LvPeCL, CMos/ttL, sine Wave) Clock input, inverting. For CMos input on CKP, connect CKn to ground. Digital circuitry ground CK_eXt signal enabled when low (zero). tristate when high. Data format selection. 0: offset Binary, 1: two’s Complement 0-7 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter table 2: Pin Function Pin # 21 22 24, 41, 58 25, 40, 57 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 59 60, 61 Name PD_n oe_n_1 ovDD ovss D1_0 D1_1 D1_2 D1_3 D1_4 D1_5 D1_6 D1_7 D1_8 D1_9 D1_10 D1_11 D1_12 ornG_1 CK_eXt D0_0 D0_1 D0_2 D0_3 D0_4 D0_5 D0_6 D0_7 D0_8 D0_9 D0_10 D0_11 D0_12 ornG_0 oe_n_0 CM_eXtBC_1, CM_ eXtBC_0 Description Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up always apply Power Down mode before using Active Mode to reset chip. output enable Channel 0. tristate when high I/o ring post-driver supply voltage. voltage range 1.7 to 3.6v Ground for I/o ring output Data Channel 1 (LsB, 13 bit output or 1vpp full scale range ) output Data Channel 1 (LsB, 12 bit output 2vpp full scale range) output Data Channel 1 output Data Channel 1 output Data Channel 1 output Data Channel 1 output Data Channel 1 output Data Channel 1 output Data Channel 1 output Data Channel 1 output Data Channel 1 (MsB for 1vpp full scale range, see reference voltages section) output Data Channel 1 (MsB for 2vpp full scale range) out of range flag Channel 1. High when input signal is out of range output clock signal for data synchronization. CMos levels output Data Channel 0 (LsB, 13 bit output or 1vpp full scale range) output Data Channel 0 (LsB, 12 bit output 2vpp full scale range) output Data Channel 0 output Data Channel 0 output Data Channel 0 output Data Channel 0 output Data Channel 0 output Data Channel 0 output Data Channel 0 output Data Channel 0 output Data Channel 0 output Data Channel 0 (MsB for 1vpp full scale range, see reference voltages section) output Data Channel 0 (MsB for 2vpp full scale range) out of range flag Channel 0. High when input signal is out of range output enable Channel 0. tristate when high Bias control bits for the buffer driving pin CM_eXt 00: oFF 01: 50uA 10: 500uA 11: 1mA sleep Mode 00: sleep Mode 01: Channel 0 active 10: Channel 1 active 11: Both channels active output Data Channel 1 0 A / D Converters - sMt 0-8 62, 63 sLP_n_1, sLP_n_0 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter recommended usage Analog Input the analog inputs to the HMCAD1050-80 is a switched capacitor track-and-hold amplifier optimized for differential operation. operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. the CM_eXt pin provides a voltage suitable as common mode voltage reference. the internal buffer for the CM_eXt voltage can be switched off, and driving capabilities can be changed by using the CM_eXtBC control input. the input amplifier could be inside a companion chip or it could be a dedicated amplifier. several suitable single ended to differential driver amplifiers exist in the market. the system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with the HMCAD1050-80 input specifications. Detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 5 must be varied according to the recommendations for the driver. AC-Coupling A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 6 shows a recommended configuration using a transformer. 0 A / D Converters - sMt Figure 4 shows a simplified drawing of the input network. the signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. A small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. the resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. Figure 6: transformer coupled input Make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. the bandwidth should exceed the sampling rate of the ADC with at least a factor of 10. It is also important to minimize phase mismatch between the differential ADC inputs for good HD2 performance. this type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. Magnetic coupling between the transformers and PCB traces may impact channel crosstalk, and must hence be taken into account during PCB layout. If the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the ADC will also travel along this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. this could reduce the ADC performance. to avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. If this problem could not be avoided, the circuit in figure 8 can be used. Figure 7 shows AC-coupling using capacitors. resistors from the CM_eXt output, rCM, should be used to bias the differential input signals to the correct volt- Figure 4: Input configuration DC-Coupling Figure 5 shows a recommended configuration for DCcoupling. note that the common mode input voltage must be controlled according to specified values. Preferably, the CM_eXt output should be used as reference to set the common mode voltage. Figure 5: DC coupled input with buffer 0-9 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter age. the series capacitor, CI, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. ential clock sources as LvDs, LvPeCL or differential sine wave can be connected directly to the input pins. For CMos inputs, the CKn pin should be connected to ground, and the CMos clock signal should be connected to CKP. For differential sine wave clock, the input amplitude must be at least ± 800 mvpp. the quality of the input clock is extremely important for high-speed, high-resolution ADCs. the contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1, SNRjitter = 20 · log (2 · π · ƒIN · єt) Figure 7: AC coupled input note that startup time from sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. If the input signal has a long traveling distance, and the kick-backs from the ADC not are effectively terminated at the signal source, the input network of figure 8 can be used. the configuration in figure 8 is designed to attenuate the kickback from the ADC and to provide an input impedance that looks as resistive as possible for frequencies below nyquist. values of the series inductor will however depend on board design and conversion rate. In some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pF) may improve ADC performance further. this capacitor attenuate the ADC kick-back even more, and minimize the kicks traveling towards the source. However, the impedance match seen into the transformer becomes worse. (1) where fIn is the signal frequency, and εt is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter performance is obtained with LvDs or LvPeCL clock with fast edges. CMos and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the ADC clock input. Digital Outputs 0 A / D Converters - sMt 0 - 10 Figure 8: Alternative input network Clock Input and Jitter considerations typically high-speed ADCs use both clock edges to generate internal timing signals. In the HMCAD105080 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% are acceptable. the input clock can be supplied in a variety of formats. the clock pins are AC-coupled internally. Hence a wide common mode voltage range is accepted. Differ- Digital output data are presented on parallel CMos form. the voltage on the ovDD pin set the levels of the CMos outputs. the output drivers are dimensioned to drive a wide range of loads for ovDD above 2.25v, but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. In applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the ADC chip. the timing is described in the timing Diagram section. note that the load or equivalent delay on CK_eXt F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter always should be lower than the load on data outputs to ensure sufficient timing margins. the digital outputs can be set in tristate mode by setting the oe_n signal high. the HMCAD1050-80 employs digital offset correction. this means that the output code will be 4096 with shorted inputs. However, small mismatches in parasitics at the input can cause this to alter slightly. the offset correction also results in possible loss of codes at the edges of the full scale range. With no offset correction, the ADC would clip in one end before the other, in practice resulting in code loss at the opposite end. With the output being centered digitally, the output will clip, and the out of range flags will be set, before max code is reached. When out of range flags are set, the code is forced to all ones for overrange and all zeros for underrange. note that the out of range flags (ornG) will behave differently for 12 bit and 13 bit output. For 13 bit output ornG will be set when digital output data are all ones or all zeros. For 12-bit output the ornG flags will be set when all twelve bits are zeros or ones and when the thirteenth bit is equal to the rest of the bits. Data Format Selection the output data are presented on offset binary form when DFrMt is low (connect to ovss). setting DFrMt high (connect to ovDD) results in 2’s complement output format. Details are shown in table 3. 0 A / D Converters - sMt table 3: Data Format Description for 2vpp Full Scale range Differential Input Voltage (IPx - INx) 1.0 v +0.24mv -0.24mv -1.0v Output Data: Dx_12 : Dx_0 (DFrMt = 0, offset Binary) 1 1111 1111 1111 1 0000 0000 0000 0 1111 1111 1111 0 0000 0000 0000 Output Data: Dx_12 : Dx_0 (DFrMt = 1, 2’s Complement) 0 1111 1111 1111 0 0000 0000 0000 1 1111 1111 1111 1 0000 0000 0000 the data outputs can be used in three different configurations. • Normal Mode: All 13 bits are used. MsB is Dx_12 and LsB is Dx_0. this mode gives optimum performance • 12-bit Mode: the LsB is left unconnected such that only 12 bits are used. MsB is Dx_12 and LsB is Dx_1. this mode gives slightly reduced performance due to increased quantization noise. • Reduced Full Scale Range Mode: the full scale range is reduced from 2 vpp to 1 vpp which is equivalent to 6 dB gain in the ADC frontend. note that data are only available in 2’s complement format in this mode. MsB is Dx_11 and LsB is Dx_0. note that the codes will wrap around when exceeding the full scale range, and that out of range bits should be used to clamp output data. see section reference voltages for details. this mode gives slightly reduced performance Reference Voltages the reference voltages are internally generated and buffered based on a bandgap voltage reference. no external decoupling is necessary, and the reference voltages are not available externally. this simplifies usage of the ADC since two extremely sensitive pins, otherwise needed, are removed from the interface. If a lower full scale range is required the 13-bit output word provides sufficient resolution to perform digital scaling with an equivalent impact on noise compared to adjusting the reference voltages. A simple way to obtain 1.0vpp input range with a 12-bit output word is shown in table 4. note that only 2’s complement output data are available in this mode and that out of range conditions must be determined based on a two bit output. the output code will wrap around when the code goes outside the full scale range. the out of range bits should be used to clamp the output data for overrange conditions. 0 - 11 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter table 4: Data Format Description for 1vpp Full Scale range Differential Input Voltage (IPx - Inx) > 0.5v 0.5v +0.24mv -0.24mv -0.5v < -0.5v Output data Dx_11:Dx_0 (DFrMt = 0) (2’s Complement) 0111 1111 1111 0111 1111 1111 0000 0000 0000 1111 1111 1111 1000 0000 0000 1000 0000 0000 Dx_12 = 0 & Dx_11 = 0 Out of Range (Use Logical and Function for &) Dx_12 = 1 & Dx_11 = 1 Output Data Dx_11:Dx_0 (DFrMt = 1) (2’s Complement) 0111 1111 1111 0111 1111 1111 0000 0000 0000 1111 1111 1111 1000 0000 0000 1000 0000 0000 Dx_12 = 1 & Dx_11 = 0 Out of Range (Use Logical and Function for &) D_12 = 0 & D_11 = 1 Operational Modes the operational modes are controlled with the PD_n and sLP_n pins. If PD_n is set low, all other control pins are overridden and the chip is set in Power Down mode. In this mode all circuitry is completely turned off and the internal clock is disabled. Hence, only leakage current contributes to the Power Down Dissipation. the startup time from this mode is longer than for other idle modes as all references need to settle to their final values before normal operation can resume. the sLP_n bus can be used to power down each channel independently, or to set the full chip in sleep Mode. In this mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. However, sleep Mode represents a significant reduction in supply current, and it can be used to save power even for short idle periods. Startup Initialization the HMCAD1050-80 must be reset prior to normal operation. this is required every time the power supply voltage has been switched off. A reset is performed by applying Power Down mode. Wait until a stable supply voltage has been reached, and pull the PD_n pin for the duration of at least one clock cycle. the input clock must be running continuously during this Power Down period and until active operation is reached. Alternatively the PD pin can be kept low during power-up, and then be set high when the power supply voltage is stable. the input clock should be kept running in all idle modes. However, even lower power dissipation is possible in Power Down mode if the input clock is stopped. In this case it is important to start the input clock prior to enabling active mode. 0 A / D Converters - sMt 0 - 12 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter outline Drawing 0 A / D Converters - sMt table 6: 9x9 mm QFn (64 Pin lP9) Dimensions Symbol A A1 A2 A3 b D D1 D2 L e Θ1 F G 0° 1.9 0.24 0.42 0.6 3.79 0.3 0.2 0 0.01 0.65 0.2 reF 0.25 9.00 bsc 8.75 bsc 3.99 0.4 0.50 bsc 12° 0° 0.075 0.010 0.017 0.024 4.19 0.5 0.149 0.012 0.3 0.008 Millimeter Min Typ Max 0.9 0.05 0.7 0 0.000 0.026 0.008 reF 0.01 0.354 bsc 0.344 bsc 0.157 0.016 0.020 bsc 12° 0.165 0.02 0.012 Min Inch Typ Max 0.035 0.002 0.028 0 - 13 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1050-80 v01.0411 Dual 13/12-Bit 65/80 MSPS a/D Converter Package information Part Number HMCAD1050-80 Package Body Material roHs-compliant Low stress Injection Molded Plastic Lead Finish 100% matte sn MSL [1] Level 2A Package Marking [2] AsD0500 XXXX XXXX [1] MsL, Peak temp: the moisture sensitivity level rating classified according to the JeDeC industry standard and to peak solder temperature. [2] Proprietary marking XXXX, 4-Digit lot number XXXX 0 A / D Converters - sMt F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 14