HI-8040QM-01

HI-8040 August 2005 CMOS HIGH VOLTAGE DISPLAY DRIVER APPLICATIONS ! Dichroic Liquid Crystal Displays ! Standard Liquid Crystal Displays ! MEMS Drivers GENERAL DESCRIPTION The HI-8040 is a CMOS integrated circuit designed for high voltage LCD display drive applications. It can drive 85 segments at voltages between +5 and -30 volts. An optional voltage converter can generate the negative display drive voltage. Test inputs facilitate opens and shorts testing. The backplane frequency is checked and, as long as power is available, the segments are shut "Off" if the frequency becomes too low. The HI-8040 is part of a family of display drivers which control segment information in the same way. Data is serially clocked into the device and the data for all segment outputs are latched in parallel when the Load input transitions from high to low. With the Data Out from the shift register available, devices may be cascaded to obtain more segment outputs. The shift register is 85 bits long. The die is metal mask programmable to provide for various package and/or cascade tap options. Consult your Holt Sales representative to explore the possibilities. PIN CONFIGURATION (Top View) S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 PIN QUAD CERPACK FEATURES ! 4 MHz serial input data rate ! 85 segment outputs ! Cascadable ! 5 Volt inputs translated to 35 Volts ! Test pins allow hardware all "ON", all "OFF" or alternating ! Monitors backplane oscillation and forces all segments to "OFF" condition if below 10Hz ! Negative voltage converter available on-chip ! CMOS low power ! Military processing available FUNCTIONAL BLOCK DIAGRAM DIN CL CS LD BPOSC BPIN S80 S81 S82 S83 S84 S85 VSS CS CL LD DIN BPOSC BPIN CONVOT VDD DOUT85 CONVOC VEE T1 T2 BP S1 S2 S3 S4 S5 S6 S7 S8 S9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 See page 5 for magnified view Þ Þ Þ Þ Þ Þ DATA IN 8 5 Sta g e S h i ft R e g i s t e r CLK Þ DOUT 85 LE 85 Bit Latch Oscillator Divider Vo l ta g e Tr a n s l a t o r H i g h Vo l ta g e B u ff e r Vo l ta g e Tr a n s l a t o r s H i g h Vo l ta g e Drivers Þ BP 85 SEGMENTS (DS8040 Rev. B) HOLT INTEGRATED CIRCUITS www.holtic.com 08/05 HI-8040 FUNCTIONAL DESCRIPTION INPUT LOGIC CS must be held low to enter data into the shift register. The data is clocked on the negative edge of CL. LD is normally held low and only pulsed high when new data is ready for display. When LD is high the latch is transparent. All four logic inputs are TTL compatible. A logic "1" at DIN that is eventually latched to the segment drivers will cause the segment to be at the opposite voltage level of the BP pin (out of phase). BPOSC and BPIN The user can either make an oscillator to create the backplane frequency or drive an external clock into BPIN leaving BPOSC open. To make an oscillator, pins BPOSC and BPIN must be connected together and the appropriate R and C combination applied (See Figure 1). If the oscillator is used, the backplane frequency is approximately 1 fBP = 256 RC (for R = 180KW & C = 220pF, fBP » 100Hz). . VEE & NEGATIVE VOLTAGE CONVERTER VEE may be externally driven to a maximum -30V. Alternatively, there is a voltage converter that will provide -21.4 volts (See Figure 2). If the converter pins are left open circuit, an on-chip sense resistor will cause shut down of all current consumption associated with the converter. The converter will survive a shorted segment condition and continue to maintain VEE at -20 volts. The test inputs must be tied to the appropriate logic level for correct circuit operation. DOUT The DOUT pin is available from segment 85 for cascading devices to drive more segments and for verifying the data integrity. This output can drive 2 TTL loads. It changes on the positive edge of CL. AUTOMATIC SEGMENTS OFF The internal backplane signal is tested continuously to be at least 10Hz. If the detector senses f