HI-8583

HI-8582, HI-8583 June 2001 ARINC 429 System on a Chip FEATURES ! ARINC specification 429 compatible ! Dual receiver and transmitter interface ! Analog line driver and receivers connect directly to ARINC bus ! Programmable label recognition ! On-chip 16 label memory for each receiver ! 32 x 32 FIFOs each receiver and transmitter ! Independent data rate selection for transmitter and each receiver ! Status register ! Data scramble control ! 32nd transmit bit can be data or parity ! Self test mode ! Low power ! Industrial & full military temperature ranges GENERAL DESCRIPTION The HI-8582 from Holt Integrated Circuits is a silicon gate CMOS device for interfacing a 16-bit parallel data bus directly to the ARINC 429 serial bus. The HI-8582 design offers many enhancements to the industry standard HI8282 architecture. The device provides two receivers each with label recognition, 32 by 32 FIFO, and analog line receiver. Up to 16 labels may be programmed for each receiver. The independent transmitter has a 32 by 32 FIFO and a built-in line driver. The status of all three FIFOs can be monitored using the external status pins, or by polling the HI-8582’s status register. Other new features include a programmable option of data or parity in the 32nd bit, and the ability to unscramble the 32 bit word. Also, versions are available with different values of input resistance and output resistance to allow users to more easily add external lightning protection circuitry. The device can be used at nonstandard data rates when an option pin, NFD, is invoked. The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The databus, and all control signals are CMOS and TTL compatible. The HI-8582 applies the ARINC protocol to the receivers and transmitter. Timing is based on a 1 Megahertz clock. Although the line driver shares a common substrate with the receivers, the design of the physical isolation does not allow parasitic crosstalk, and thereby achieves the same isolation as common hybrid layouts. PIN CONFIGURATION (Top View) APPLICATIONS ! Avionics data communication ! Serial to parallel conversion ! Parallel to serial conversion FF1 - 1 HF1 - 2 D/R2 - 3 FF2 - 4 HF2 - 5 SEL - 6 EN1 - 7 EN2 - 8 BD15 - 9 BD14 - 10 BD13 - 11 BD12 - 12 BD11 - 13 HI-8582PQI & HI-8582PQT 39 - N/C 38 - CWSTR 37 - ENTX 36 - V+ 35 - TXBOUT 34 - TXAOUT 33 - V32 - FFT 31 - HFT 30 - TX/R 29 - PL2 28 - PL1 27 - BD00 52 - Pin Plastic Quad Flat Pack (PQFP) (See page 14 for additional pin configuration) (DS8582 Rev. H) HOLT INTEGRATED CIRCUITS 1 06/01 HI-8582, HI-8583 PIN DESCRIPTIONS SIGNAL VDD RIN1A RIN1B RIN2A RIN2B D/R1 FF1 HF1 D/R2 FF2 HF2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 GND BD05 BD04 BD03 BD02 BD01 BD00 PL1 PL2 TX/R HFT FFT VTXAOUT TXBOUT V+ ENTX CWSTR RSR NFD CLK TX CLK MR TEST FUNCTION POWER INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O POWER I/O I/O I/O I/O I/O I/O INPUT INPUT OUTPUT OUTPUT OUTPUT POWER OUTPUT OUTPUT POWER INPUT INPUT INPUT INPUT INPUT OUTPUT INPUT INPUT DESCRIPTION +5V ±5% ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag FIFO full Receiver 1 FIFO Half full, Receiver 1 Receiver 2 data ready flag FIFO full Receiver 2 FIFO Half full, Receiver 2 Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2) Data Bus control, enables receiver 1 data to outputs Data Bus control, enables receiver 2 data to outputs if EN1 is high Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus 0V Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1. Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. Transmitter FIFO Half Full Transmitter FIFO Full -9.5V to -12.6V Line driver output - A side Line driver output - B side +9.5V to +12.6V Enable Transmission Clock for control word register Read Status Register if SEL=0, read Control Register if SEL=1 No frequency discrimination if low (pull-up) Master Clock input Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80. Master Reset, active low Disable Transmitter output if high (pull-down) HOLT INTEGRATED CIRCUITS 2 HI-8582, HI-8583 FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-8582 contains a 16-bit control register which is used to configure the device. The control register bits CR0 - CR15 are loaded from BD00 - BD15 when CWSTR is pulsed low. The control register contents are output on the databus when SEL=1 and RSR is pulsed low. Each bit of the control register has the following function: CR STATUS REGISTER The HI-8582 contains a 9-bit status register which can be interrogated to determine the status of the ARINC receivers, data FIFOs and transmitter. The contents of the status register are output on BD00 - BD08 when the RSR pin is taken low and SEL = 0. Unused bits are output as zeros. The following table defines the status register bits. Bit SR0 Bit FUNCTION Receiver 1 Data clock select Label Memory Read / Write STATE 0 1 0 1 DESCRIPTION Data rate = CLK/10 Data rate = CLK/80 Normal operation Load 16 labels using PL1 / PL2 Read 16 labels using EN1 / EN2 Disable label recognition Enable label recognition Disable Label Recognition Enable Label recognition Transmitter 32nd bit is data Transmitter 32nd bit is parity An internal connection is made passing TXAOUT and TXBOUT to the receiver inputs Normal operation Receiver 1 decoder disabled ARINC bits 9 and 10 must match CR7 and CR8 If receiver 1 decoder is enabled, the ARINC bit 9 must match this bit SR FUNCTION Data ready (Receiver 1) STATE 0 1 DESCRIPTION Receiver 1 FIFO empty Receiver 1 FIFO contains valid data Resets to zero when all data has been read. D/R1 pin is the inverse of this bit Receiver 1 FIFO holds less than 16 words Receiver 1 FIFO holds at least 16 words. HF1 pin is the inverse of this bit. Receiver 1 FIFO not full Receiver 1 FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period. FF1 pin is the inverse of this bit Receiver 2 FIFO empty Receiver 2 FIFO contains valid data Resets to zero when all data has been read. D/R2 pin is the inverse of this bit Receiver 2 FIFO holds less than 16 words Receiver 2 FIFO holds at least 16 words. HF2 pin is the inverse of this bit. Receiver 2 FIFO not full Receiver 2 FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period. FF2 pin is the inverse of this bit Transmitter FIFO not empty Transmitter FIFO empty. Transmitter FIFO not full Transmitter FIFO full. FFT pin is the inverse of this bit. Transmitter FIFO contains less than 16 words Transmitter FIFO contains at least 16 words.HFT pin is the inverse of this bit. CR0 CR1 SR1 FIFO half full (Receiver 1) 0 1 CR2 Enable Label Recognition (Receiver 1) Enable Label Recognition (Receiver 2) Enable 32nd bit as parity Self Test 0 1 0 1 0 1 0 CR3 SR2 FIFO full (Receiver 1) 0 1 CR4 CR5 SR3 Data ready (Receiver 2) 0 1 1 CR6 Receiver 1 decoder 0 1 CR7 CR8 CR9 Receiver 2 Decoder 0 1 CR10 CR11 CR12 Invert Transmitter parity Transmitter data clock select Receiver 2 data clock select Data format 0 1 0 1 0 1 0 1 SR4 FIFO half full (Receiver 2) 0 1 SR5 If receiver 1 decoder is enabled, the ARINC bit 10 must match this bit Receiver 2 decoder disabled ARINC bits 9 and 10 must match CR10 and CR11 If receiver 2 decoder is enabled, the ARINC bit 9 must match this bit SR7 If receiver 2 decoder is enabled, the ARINC bit 10 must match this bit Transmitter 32nd bit is Odd parity SR8 Transmitter 32nd bit is Even parity Data rate=CLK/10, O/P slope=1.5us Data rate=CLK/80, O/P slope=10us Data rate=CLK/10 Data rate=CLK/80 Scramble ARINC data Unscramble ARINC data FIFO full (Receiver 2) 0 1 SR6 Transmitter FIFO empty Transmitter FIFO full 0 1 0 1 Transmitter FIFO half full 0 1 CR13 CR14 CR15 HOLT INTEGRATED CIRCUITS 3 HI-8582, HI-8583 FUNCTIONAL DESCRIPTION (cont.) ARINC 429 DATA FORMAT Control register bit CR15 is used to control how individual bits in the received or transmitted ARINC word are mapped to the HI-8582 data bus during data read or write operations. The following table describes this mapping: BYTE 1 DATA BUS ARINC BIT CR15=0 ARINC BIT CR15=1 BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8 The HI-8582 guarantees recognition of these levels with a common mode Voltage with respect to GND less than ±5V for the worst case condition (4.75V supply and 13V signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. RECEIVER LOGIC OPERATION Figure 2 shows a block diagram of the logic section of each receiver. BIT TIMING 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 The ARINC 429 specification contains the following timing specification for the received data: BYTE 2 HIGH SPEED LOW SPEED BIT RATE 100K BPS ± 1% 12K -14.5K BPS PULSE RISE TIME 1.5 ± 0.5 µsec 10 ± 5 µsec PULSE FALL TIME 1.5 ± 0.5 µsec 10 ± 5 µsec PULSE WIDTH 5 µsec ± 5% 34.5 to 41.7 µsec If the NFD pin is high, the HI-8582 accepts signals that meet these specifications and rejects outside the tolerances. The way the logic operation achieves this is described below: DATA BUS ARINC BIT CR15=0 ARINC CR15=1 BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 THE RECEIVERS ARINC BUS INTERFACE Figure 1 shows the input circuit for each receiver. The ARINC 429 specification requires the following detection levels: STATE ONE NULL ZERO DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts 1. Key to the performance of the timing checking logic is an accurate 1MHz clock source. Less than 0.1% error is recommended. 2. The sampling shift registers are 10 bits long and must show three consecutive Ones, Zeros or Nulls to be considered valid data. Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed. 3. Each data bit must follow its predecessor by not less than 8 samples and no more than 12 samples. In this manner the bit rate is checked. With exactly 1MHz input clock frequency, the acceptable data bit rates are as follows: HIGH SPEED DATA BIT RATE MIN DATA BIT RATE MAX 83K BPS 125K BPS LOW SPEED 10.4K BPS 15.6K BPS 4. The Word Gap timer samples the Null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. If the Null is present, the Word Gap counter is incremented. A count of 3 will enable the next reception. If NFD is held low, frequency discrimination is disabled and any data stream totaling 32 bits is accepted even with gaps between bits. The protocol still requires a word gap as defined in 4. above. FIGURE 1. ARINC RECEIVER INPUT HOLT INTEGRATED CIRCUITS 4 HI-8582, HI-8583 FUNCTIONAL DESCRIPTION (cont.) RECEIVER PARITY The receiver parity circuit counts ones received, including the parity bit. If the result is odd, then "0" will appear in the 32nd bit. CR2(3) ARINC word CR6(9) ARINC word matches bits 9,10 label match CR7,8 (10,11) 0 1 1 0 0 1 1 1 1 X No Yes X X Yes No No Yes 0 0 0 1 1 1 1 1 1 X X X No Yes No Yes No Yes FIFO RETRIEVING DATA Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). Depending upon the state of control register bits CR2-CR11, the received ARINC 32-bit word is then checked for correct decoding and label matching before being loaded into the 32 x 32 receive FIFO. ARINC words which do not meet the necessary 9th and 10th ARINC bit or label matching are ignored and are not loaded into the receive FIFO. The following table describes this operation. Load FIFO Ignore data Load FIFO Ignore data Load FIFO Ignore data Ignore data Ignore data Load FIFO TO PINS SEL EN MUX CONTROL 32 TO 16 DRIVER R/W CONTROL CONTROL BITS HF FF D/R FIFO LOAD CONTROL 32 X 32 FIFO CONTROL BIT / 16 x 8 LABEL MEMORY LABEL / DECODE COMPARE CONTROLBITS CR0, CR14 CLOCK OPTION CLOCK BIT COUNTER AND END OF SEQUENCE CLK 32 BIT SHIFT REGISTER DATA BIT CLOCK PARITY CHECK 32ND BIT EOS ONES SHIFT REGISTER WORD GAP WORD GAP TIMER BIT CLOCK START NULL SHIFT REGISTER SEQUENCE CONTROL END ZEROS SHIFT REGISTER ERROR DETECTION ERROR CLOCK FIGURE 2. RECEIVER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 5 HI-8582, HI-8583 Once a valid ARINC word is loaded into the FIFO, then EOS clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The data flag for a receiver will remain low until both ARINC bytes from that receiver are retrieved and the FIFO is empty. This is accomplished by first activating EN with SEL, the byte selector, low to retrieve the first byte and then activating EN with SEL high to retrieve the second byte. EN1 retrieves data from receiver 1 and EN2 retrieves data from receiver 2. Up to 32 ARINC words may be loaded into each receiver’s FIFO. The FF1 (FF2) pin will go low when the receiver 1 (2) FIFO is full. Failure to retrieve data from a full FIFO will cause the next valid ARINC word received to overwrite the existing data in FIFO location 32. A FIFO half full flag HF1 (HF2) goes low if the FIFO contains 16 or more received ARINC words. The HF1 (HF2) pin is intended to act as an interrupt flag to the system’s external microprocessor, allowing a 16 word data retrieval routine to be performed, without the user needing to continually poll the HI8582’s status register bits. READING LABELS After the write that changes CR1 from 0 to 1, the next 16 data reads of the selected receiver (EN taken low) are labels. EN1 is used to read labels for receiver 1, and EN2 to read labels for receiver 2. Label data is presented on DB0-DB7. When writing to, or reading from the label memory, SEL must be a one, all 16 locations should be accessed, and CR1 must be written to zero before returning to normal operation. Label recognition must be disabled (CR2/3=0) during the label read sequence. TRANSMITTER FIFO OPERATION The FIFO is loaded sequentially by first pulsing PL1 to load byte 1 and then PL2 to load byte 2. The control logic automatically loads the 31 bit word (or 32 bit word if CR4=0) in the next available position of the FIFO. If TX/R, the transmitter ready flag is high (FIFO empty), then up to 32 words, each 31 or 32 bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 32 positions are full, the FFT flag is asserted and the FIFO ignores further attempts to load data. A transmitter FIFO half-full flag HFT is provided. When the transmit FIFO contains less than 16 words, HFT is high, indicating to the system microprocessor that a 16 ARINC word block write sequence can be initiated. In normal operation (CR4=1), the 32nd bit transmitted is a parity bit. Odd or even parity is selected by programming control register bit CR12 to a zero or one. If CR4 is programmed to a 0, then all 32-bits of data loaded into the transmitter FIFO are treated as data and are transmitted. LABEL RECOGNITION The chip compares the incoming label to the stored labels if label recognition is enabled. If a match is found, the data is processed. If a match is not found, no indicators of receiving ARINC data are presented. Note that 00(Hex) is treated in the same way as any other label value. Label bit significance is not changed by the status of control register bit CR15. Label bits BD00-BD07 are always compared to received ARINC bits 1-8 respectively. LOADING LABELS After a write that takes CR1 from 0 to 1, the next 16 writes of data (PL pulsed low) load label data into each location of the label memory from the BD0-7 pins. The PL1 pin is used to write label data for receiver 1 and PL2 for receiver 2. Note that ARINC word reception is suspended during the label memory write sequence. HOLT INTEGRATED CIRCUITS 6 HI-8582, HI-8583 DATA TRANSMISSION When ENTX goes high, enabling transmission, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks the first data bit appears at TXAOUT and TXBOUT. The 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the ARINC 429 format with the following timing: HIGH SPEED 10 Clocks 5 Clocks 5 Clocks 40 Clocks LOW SPEED 80 Clocks 40 Clocks 40 Clocks 320 Clocks LINE DRIVER OPERATION The line driver in the HI-8582 is designed to directly drive the ARINC 429 bus. The two ARINC outputs (TXAOUT and TXBOUT) provide a differential voltage to produce a +10 volt One, a -10 volt Zero, and a 0 volt Null. Control register bit CR13 controls both the transmitter data rate, and the slope of the differential output signal. No additional hardware is required to control the slope. Programming CR13 to zero causes a 100 kbits/s data rate and a slope of 1.5 µs on the ARINC outputs; a one on CR13 causes a 12.5 kbit/s data rate and a slope of 10 µs. Timing is set by on-chip resistor and capacitor and tested to be within ARINC requirements. The HI-8582 has 37.5 ohms in series with each line driver output. The 8583 has 10 ohms in series. The HI-8583 is for applications where external series resistance is needed, typically for lightning protection devices. ARINC DATA BIT TIME DATA BIT TIME NULL BIT TIME WORD GAP TIME The word counter detects when all loaded positions have been transmitted and sets the transmitter ready flag, TX/R, high. TRANSMITTER PARITY The parity generator counts the “1”s in the 31-bit word. If control register bit CR12 is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. Setting CR4 to a zero bypasses the parity generator, and allows 32 bits of data to be transmitted. REPEATER OPERATION Repeater mode of operation allows a data word that has been received by the HI-8582 to be placed directly into the transmitter FIFO. Repeater operation is similar to normal receiver operation. In normal operation, either byte of a received data word may be read from the receiver latches first by use of SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read, it is also being loaded into transmitter FIFO which is always loaded with the lower byte of the data word first. Signal flow for repeater operation is shown in the Timing Diagrams section. SELF TEST If control register bit CR5 is set low, the transmitter serial output data are internally connected to each of the two receivers, bypassing the analog interface circuitry. Data is passed unmodified to receiver 1, and inverted to receiver 2. Taking TEST high forces TXAOUT and TXBOUT into the null state regardless of the state of CR5. HI-8582-10 The HI-8582-10 option is similar to the HI-8582 with the exception that it allows an external 10 Kohm resistor to be added in series with each ARINC input without affecting the ARINC input thresholds. This option is especially useful in applications where lightning protection circuitry is also required. Each side of the ARINC bus must be connected through a 10 Kohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that with the external 10 Kohm resistors, they are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5V maximum ARINC null threshold. SYSTEM OPERATION The two receivers are independent of the transmitter. Therefore, control of data exchanges is strictly at the option of the user. The only restrictions are: 1. The received data will be overwritten if the receiver FIFO is full and at least one location is not retrieved before the next complete ARINC word is received. 2. The transmitter FIFO can store 32 words maximum and ignores attempts to load additional data if full. HIGH SPEED OPERATION The HI-8582 may be operated at clock frequencies beyond that required for ARINC compliant operation. For operation at Master Clock (CLK) frequencies up to 5MHz, please contact Holt applications engineering. HOLT INTEGRATED CIRCUITS 7 HI-8582, HI-8583 TXAOUT ARINC BIT TXBOUT DATA NULL DATA NULL DATA NULL BIT 30 BIT 31 BIT 32 WORD GAP BIT 1 NEXT WORD tD/R t END/R tEN t SELEN t D/REN t ENSEL tENEN t DATAEN tSELEN tENSEL tREADEN tDATAEN tENDATA tSELEN DATA BUS t ENDATA t ENDATA DATA BUS BYTE 1 VALID BYTE 2 VALID tDWSET PL1 tDWHLD tDWSET t DWHLD t PL12 tPL PL2 t PL12 TX/R, HFT, FFT tPL t TX/R DATA BUS VALID t CWSET tCWHLD CWSTR tCWSTR HOLT INTEGRATED CIRCUITS 8 HI-8582, HI-8583 tSELEN tENSEL t DATAEN DATA BUS tENDATA tSELEN tENSEL t DATAEN DATA BUS tENDATA tCWSTR tCWSET DATA BUS tCWHLD tDWSET tDWHLD tPL tLABEL tCWSTR t READEN tCWHLD tCWSET DATA BUS Set CR1=1 Label #1 t DATAEN Label #2 Label #16 Set CR1=0 t ENDATA HOLT INTEGRATED CIRCUITS 9 HI-8582, HI-8583 PL2 tDTX/R t PL2EN TXR ENTX tENTX/R ARINC BIT DATA BIT 1 ARINC BIT DATA BIT 2 tENDAT ARINC BIT DATA BIT 32 +5V TXAOUT -5V +5V TXBOUT -5V +5V -5V tfx +10V V DIFF (TXAOUT) - TXBOUT) 90% 10% +10V tfx 10% zero level 90% trx null level trx one level -10V RIN BIT 32 t END/R D/R tD/R EN tD/REN t EN t ENEN t EN t SELEN SEL DON'T CARE tENSEL DON'T CARE tENPL PL1 tPLEN tENPL tSELEN t ENSEL t PLEN PL2 tTX/R TXR tTX/REN ENTX tENTX/R tENDAT TXAOUT TXBOUT BIT 1 t DTX/R BIT 32 t NULL HOLT INTEGRATED CIRCUITS 10 HI-8582, HI-8583 Supply Voltages VDD ........................................... -0.3V to +7V V+ ...................................................... +13.0V V- ...................................................... -13.0V Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ..... -29V to +29V Voltage at any other pin ............................... -0.3V to VDD +0.3V Solder temperature (Leads) .................... 280°C for 10 seconds (Package) .......................................... 220°C Power Dissipation at 25°C Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C Ceramic J-LEAD CERQUAD ...... 1.0 W, derate 7mW/°C DC Current Drain per pin .............................................. ±10mA Storage Temperature Range ........................ -65°C to +150°C Operating Temperature Range (Industrial): .... -40°C to +85°C (Military): ..... -55°C to +125°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HOLT INTEGRATED CIRCUITS 11 HI-8582, HI-8583 VDD = 5V , V+ = 10V, V- = -10V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER ARINC INPUTS Pins RIN1A, RIN1B, RIN2A, RIN2B ONE ZERO NULL Differential To GND To VDD Input Sink Input Source Differential To GND To VDD SYMBOL CONDITIONS LIMITS MIN TYP MAX UNIT Differential Input Voltage: VIH VIL VNUL RI RG RH IIH IIL CI CG CH Pins 2 to 3, 4 to 5: Common mode voltage less than ±5V with respect to GND 6.5 -13.0 -2.5 12 12 12 -450 10.0 -10.0 0 46 38 38 13.0 -6.5 2.5 V V V KW KW KW Input Resistance: Input Current: Input Capacitance: (Guaranteed but not tested) BI-DIRECTIONAL INPUTS - Pins DB0 - DB15 Input Voltage: Input Current: OTHER INPUTS Input Voltage: Input Current: 200 Pins 2 to 3, 4 to 5 20 20 20 µA µA pF pF pF Input Voltage HI Input Voltage LO Input Sink Input Source VIH VIL IIH IIL 2.0 0.8 1.5 -1.5 V V µA µA Input Voltage HI Input Voltage LO Input Sink Input Source Pull-up current (NFD Pin) Pull-down Current (TEST Pin) VIH VIL IIH IIL IPU IPD 2.0 0.8 1.5 -1.5 -150 50 -50 150 V V µA µA µA µA ARINC OUTPUTS - Pins TXAOUT, TXBOUT ARINC output voltage (Ref. To GND) ARINC output voltage (Differential) ARINC output current OTHER OUTPUTS Output Voltage: Output Current: (All Outputs & Bi-directional Pins) Output Capacitance: Operating Voltage Range VDD V+ VOperating Supply Current VDD V+ VIDD1 IDD2 IEE1 4 3.2 3.2 20 16 16 mA mA mA 4.75 9.5 -9.5 5.25 12.6 -12.6 V V V Logic "1" Output Voltage Logic "0" Output Voltage Output Sink Output Source VOH VOL IOL IOH CO IOH = -1.5mA IOL = 1.6mA VOUT = 0.4V VOUT = VDD - 0.4V 2.7 0.4 1.6 -1.0 15 V V mA mA pF One or zero Null One or zero Null VDOUT VNOUT VDDIF VNDIF IOUT No load and magnitude at pin, VDD = 5.0 V No load and magnitude at pin, VDD = 5.0 V 4.50 -0.25 9.0 -0.5 80 5.00 10.0 5.50 0.25 11.0 0.5 V V V V mA HOLT INTEGRATED CIRCUITS 12 HI-8582, HI-8583 VDD = 5V, V+=10V, V-=-10V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz +0.1% with 60/40 duty cycle PARAMETER CONTROL WORD TIMING Pulse Width - CWSTR Setup - DATA BUS Valid to CWSTR HIGH Hold - CWSTR HIGH to DATA BUS Hi-Z RECEIVER FIFO AND LABEL READ TIMING Delay - Start ARINC 32nd Bit to D/R LOW: High Speed Low Speed Delay - D/R LOW to EN L0W Delay - EN LOW to D/R HIGH Setup - SEL to EN L0W Hold - SEL to EN HIGH Delay - EN L0W to DATA BUS Valid Delay - EN HIGH to DATA BUS Hi-Z Pulse Width - EN1 or EN2 Spacing - EN HIGH to next EN L0W (Same ARINC Word) Spacing -EN HIGH to next EN LOW (Next ARINC Word) TRANSMITTER FIFO AND LABEL WRITE TIMING Pulse Width - PL1 or PL2 Setup - DATA BUS Valid to PL HIGH Hold - PL HIGH to DATA BUS Hi-Z Spacing - PL1 or PL2 Spacing between Label Write pulses Delay - PL2 HIGH to TX/R LOW TRANSMISSION TIMING Spacing - PL2 HIGH to ENTX HIGH Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX L0W LINE DRIVER OUTPUT TIMING Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed Line driver transition differential times: (High Speed, control register CR13 = Logic 0) high to low low to high SYMBOL LIMITS MIN TYP MAX UNITS tCWSTR tCWSET tCWHLD 50 50 0 ns ns ns tD/R tD/R tD/REN tEND/R tSELEN tENSEL tENDATA tDATAEN tEN tENEN tREADEN 60 60 200 0 250 0 0 60 50 16 128 350 µs µs ns ns ns ns 100 80 ns ns ns ns ns tPL tDWSET tDWHLD tPL12 tLABEL tTX/R 50 50 0 85 200 300 ns ns ns ns ns ns tPL2EN tDTX/R tENTX/R 0 50 0 µs ns ns tENDAT tENDAT tfx trx 1.0 1.0 1.5 1.5 25 200 2.0 2.0 µs µs µs µs REPEATER OPERATION TIMING Delay - EN LOW to PL LOW Hold - PL HIGH to EN HIGH Delay - TX/R LOW to ENTX HIGH Master Reset Pulse Width ARINC Data Rate and Bit Timing tENPL tPLEN tTX/REN tMR 0 0 0 50 ± 1% ns ns ns ns HOLT INTEGRATED CIRCUITS 13 HI-8582, HI-8583 ADDITIONAL HI-8582 PIN CONFIGURATION FF1 - 8 HF1 - 9 D/R2 - 10 FF2 - 11 HF2 - 12 SEL - 13 EN1 - 14 EN2 -15 BD15 - 16 BD14 - 17 BD13 - 18 BD12 - 19 BD11 - 20 HI-8582CJI & HI-8582CJT 46 - N/C 45 - CWSTR 44 - ENTX 43 - V+ 42 - TXBOUT 41 - TXAOUT 40 - V39 - FFT 38 - HET 37 - TX/R 36 - PL2 35 - PL1 34 - BD00 52 - Pin Cerquad J-lead (See page 1 for additional pin configuration) ORDERING INFORMATION HI - 8582 xx x - xx No dash number 35 Kohm -10 0 10 Kohm 25 Kohm I T -40°C TO +85°C -55°C TO +125°C I T NO NO CJ PQ 52 PIN CERQUAD J LEAD SOLDER 52 PIN PLASTIC QUAD FLAT PACK (PQFP) SOLDER 8582 8583 37.5 Ohms 10 Ohms 0 27.5 Ohms HOLT INTEGRATED CIRCUITS 14 HI-8582 PACKAGE DIMENSIONS inches (millimeters) 52-PIN J-LEAD CERQUAD Package Type: 52U 7 8 1 52 47 .788 (20.0) MAX. SQ. .720 ± .010 (18.29 ± .25) .750 ± .007 (19.05 ± .18) .040 ± .005 (1.02 ± .013) .019 ± .002 (.483 ± .051) .050 TYP. (1.27) .190 MAX. (4.826) 52-PIN PLASTIC QUAD FLAT PACK (PQFP) Package Type: 52PQS .0256 BSC (0.65 BSC) .520 ± .010 (13.2 ± .25) SQ. .394 ± .004 SQ. (10.00 ± .10) .012 ± .003 (.30 ± .08) .035 ± .006 (.88 ± .15) .063 ± .032 (1.6 ± .175) Typ. .008 (0.20) Min. .009 ± .003R (.225 ± .075R) See Detail A .092 ± .004 (2.32 ± .12) .079 ± .002 (2.00 ± .05) .009 R typ (0.23 R typ) 0° ≤ Θ ≤ 7° DETAIL A HOLT INTEGRATED CIRCUITS 15