HI-8685

HI-8685, HI-8686 September 2006 ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 16-Bit Parallel Data PIN CONFIGURATIONS (Top View) DATARDY D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 Vcc GAPCLK TESTA TESTB RESET RINB (-10) RINA (-10) ERROR PARITY ENB READ D0 D1 D2 D3 DESCRIPTION The HI-8685 and HI-8686 are system components for interfacing incoming ARINC 429 signals to 16-bit parallel data using proven +5V analog/digital CMOS technology. Both products incorporate the digital logic and analog line receiver circuitry in a single device. The receivers on the HI-8685 and the HI-8686 connect directly to the ARINC 429 Bus and translate the incoming signals to normal CMOS levels. Internal comparator levels are set just below the standard 6.5 volt minimum data threshold and just above the standard 2.5 volt maximum null threshold. The -10 version of the HI-8685 allows the incorporation of an external 10KW resistance in series with each ARINC input for lightning protection without affecting ARINC level detection. Both products offer high speed 16-bit parallel bus interface, a 32-bit buffer, and error detection for word length and parity. A reset pin is also provided for power-on initialization. HI-8685PSI 23 HI-8685PST 22 & 21 HI-8685PSI-10 HI-8685PST-10 20 19 18 17 16 15 FEATURES ! Automatic conversion of serial ARINC 429, 575 & 561 data to 16-bit parallel data HI-8685 28-Pin Plastic SOIC - WB Package 29 - DATARDY 27 - GAPCLK ! ! ! ! ! ! ! Error detection - word length and parity Reset input for power-on initialization On-chip line receiver Input hysteresis of at least 2 volts Test lnputs bypass analog inputs Simplified lightning protection with the ability to add 10 Kohm external series resistors SOIC, TQFP and PLCC N/C - 1 D12 - 2 D11 - 3 D10 - 4 D9 - 5 D8 - 6 D7 - 7 D6 - 8 28 - Vcc High speed parallel 16-bit data bus 25 - TESTB 26 - TESTA 32 - D13 31 - D14 30 - D15 24 - RESET 23 - RINB-10 22 - RINB 21 - RINA 20 - RINA-10 19 - ERROR 18 - PARITY ENB 17 - N/C HI-8686PQI HI-8686PQT ! Small, surface mount, plastic package options: ! Military processing available D4 - 10 D3 - 12 D2 - 13 D1 - 14 D0 - 15 APPLICATIONS ! Avionics data communication ! Serial to parallel conversion ! Parallel to serial conversion HI-8686 32-Pin PlasticTQFP Package (See page 8 for additional pin configurations) (Ds8685 Rev. L) HOLT INTEGRATED CIRCUITS www.holtic.com READ - 16 GND - 11 D5 - 9 09/06 HI-8685, HI-8686 PIN DESCRIPTIONS SIGNAL DATA RDY D0 to D15 GND READ PARITY ENB ERROR FUNCTION OUTPUT OUTPUT POWER INPUT INPUT OUTPUT DESCRIPTION Receiver data ready flag. A high level indicates data is available in the receive buffer. Flag goes low when the first 16-bit byte is read. 16-bit parallel data bus (tri-state) 0V Read strobe. A low level transfers receive buffer data to the data bus Parity Enable - A high level activates odd parity checking which replaces the 32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged Error Flag. A high level indicates a bit count error (number of ARINC bits was less than or greater than 32) and/or a parity error if parity detection was enabled (PARITY ENB high) Positive direct ARINC serial data input (both RINA and RINA-10 on HI-8686) Negative direct ARINC serial data input (both RINB and RINB-10 on HI-8686) Internal logic states are initialized with a low level Used in conjunction with the TESTB input to bypass the built-in analog line receiver circuitry Used in conjunction with the TESTA input to bypass the built-in analog line receiver circuitry Gap Clock. Determines the minimum time required between ARINC words for detection. The minimum word gap time is between 16 and 17 clock cycles of this signal. +5V ±5% supply RINA/RINA-10 RINB/RINB-10 RESET TESTA TESTB GAPCLK INPUT INPUT INPUT INPUT INPUT INPUT Vcc POWER FUNCTIONAL DESCRIPTION The HI-8685 and HI-8686 are serial to 16-bit parallel converters. The incoming data stream is serially shifted into an input register, checked for errors, and then transferred in parallel to a 32-bit receive buffer. The receive data can be accessed using two 16-bit parallel read operations while the next serial data steam is being received. RECEIVER INPUTS The block diagram for both the HI-8685 and HI-8685-10 products is found in Figure 1. Both have built-in receivers eliminating the need for additional external ARINC level detection circuitry. The only difference between the two products is the amount of internal resistance in series with each ARINC input. HI-8685 ARINC INPUTS (RINA & RINB) translation, the buffered inputs drive a differential amplifier. The differential signal is compared to levels derived from a divider between VCC and GND. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. A valid ARINC One/Zero input sets a latch and a Null input resets the latch. HI-8685-10 ARINC INPUTS (RINA-10 & RINB-10) Since any added external series resistance will affect the voltage translation, the HI-8685-10 product has only 25KW of the 35KW series resistance required for proper ARINC 429 level detection. The remaining 10KW required is available to the user for incorporation in external circuitry such as for lightning protection. HI-8686 ARINC INPUTS Internal 35KW resistors are in series with both the RINA and RINB ARINC 429 inputs. They connect to level translators whose resistance to GND is typically 10KW. After level The HI-8686 has both sets of ARINC inputs, RINA/RINA-10 and RINB/RINB-10 available to the user. HOLT INTEGRATED CIRCUITS 2 HI-8685, HI-8686 PARITY ENB CLK PARITY DETECT 10KW 25KW ESD PROTECTION & LINE RECEIVER RXA ERROR DETECT ERROR RINA RINB RINA-10 RINB-10 TESTA TESTB RXB CLOCK & DATA DETECT BIT 32 BIT 32 DATA 32-BIT SHIFT REG. 32 32-BIT RECEIVE 32 BUFFER 32-BIT TO 16-BIT 16 MUX 10KW 25KW D0 - D15 BIT COUNT GAP DETECT BYTE COUNT DATA RDY GAPCLK RESET READ Figure 1. Block Diagram FUNCTIONAL DESCRIPTION (cont.) PROTOCOL DETECTION The ARINC clock and One/Zero data that are derived from the digital outputs of the built-in line receiver is illustrated in Figure 3. The resulting steam of digital data is shifted into a 32-bit input register. The ARINC clock and One/Zero data can also be created from the TESTA and TESTB inputs as shown in Figure 4. When either test input is high, the built-in analog line driver is disabled. For ARINC 561 operation, the TESTA and TESTB digital input data streams must be derived from the ARINC 561 data, clock and sync with external logic. DATABUS TYPE 429 BIT PERIOD (µs) 10 MINIMUM GAP (µs) 45 GAP CLOCK MHz 0.75 1.0 1.5 0.1 0.1 0.2 GAP DETECTION TIME (µs) 21.3 - 22.7 16 - 17 10.7 - 11.3 160 - 170 160 - 170 80 - 85 GAP DETECTION The end of a data word is detected by an internal counter that times out when a data One or Zero is not received for a period equal to 16 cycles of the GAPCLK signal. The gap detection time may vary between 16 and 17 cycles of the GAPCLK signal since the incoming data and GAPCLK are not usually synchronous inputs. The required frequency of GAPCLK is a function of the mininum gap time specified for the type of ARINC data being received. Table 1 indicates typical frequencies that may be used for the various data rates normally encountered. 429 575 561 69 - 133 69 - 133 69 - 133 310 - 599 310 - 599 103 - 200 Table 1 - Typical Gap Detection Times HOLT INTEGRATED CIRCUITS 3 HI-8685, HI-8686 FUNCTIONAL DESCRIPTION (cont.) ERROR CHECKING Once a word gap is detected, the data word in the input register is transferred to the receive buffer and checked for errors. When parity detection is enabled (PARITY ENB high), the received word is checked for odd parity. If there is a parity error, the 32nd bit of the received data word is set high. If parity checking is disabled (PARITY ENB low) the 32nd bit of the data word is always the 32nd ARINC bit received. The ERROR flag output is set high upon receipt of a word gap and the number of bits received since the previous word gap is less than or greater than 32. The ERROR flag is reset low when the next valid ARINC word is written into the receive buffer or when RESET is pulsed low. READING RECEIVE BUFFER When the data word is transferred to the receive buffer, the DATA RDY pin goes high. The data word can then be read in two 16-bit bytes by pulsing the READ input low as indicated in Figure 5. The first read cycle resets DATARDY low and increments an internal counter to the second 16-bit byte. The relationship between each bit of an ARINC word received and each bit of the two 16-bit data bus bytes is specified in Figure 2. When a new ARINC word is received it always overwrites the receive buffer. If the first byte of the previous word has not been read, then previous data is lost and the receive buffer will contain the new ARINC word. However, if the DATARDY pin goes high between the reading of the first and second bytes, the first byte is no longer valid because the corresponding second byte has been overwritten by the new ARINC word. Also, the next read will be of the first byte of the new ARINC word since the internal byte counter is always reset to the first byte when new data is transferred to the receive buffer. Read 1st 2nd Byte Byte 1 Byte 2 Data Bus Bits D0 - D15 D0 - D15 ARINC Bits ARINC 1 - ARINC 16 ARINC 17 - ARINC 32 FIGURE 2. ORDER OF RECEIVED DATA RESET A low on the RESET input sets a flip-flop which initializes the internal logic. When RESET goes high, the internal logic remains in the initialized state until the first word gap is detected preventing reception of a partial word. TEST MODE The built-in differential line receiver can be disabled allowing the data and clock detection circuitry to be driven directly with digital signals. The logical OR function of the TESTA and TESTB is defined in Truth Table 1. The two inputs can be used for testing the receiver logic and for inputting ARINC 429 type data derived from another source / protocol. See Figure 4 for typical test input timing. The device should always be initialized with RESET immediately after entering the test mode to clear a partial word that may have been received since the last word gap. Otherwise, an ERROR condition may occur and the first 32 bits of data on the test inputs may not be properly received. Also, when entering the test mode, both TESTA and TESTB should be set high and held in that state for at least one word gap period (17 gap clocks) after RESET goes high. When exiting the test mode, both test inputs should be held low and the device initialized with RESET. TRUTH TABLE 1. RINA (-10) -1.50V to +1.50V -3.25V to -6.50V +3.25V to +6.50V X X X X = don't care HOLT INTEGRATED CIRCUITS 4 RINB (-10) -1.50V to +1.50V +3.25V to +6.50V -3.25V to -6.50V X X X TESTA 0 0 0 0 1 1 TESTB 0 0 0 1 0 1 RXA 0 0 1 0 1 0 RXB 0 1 0 1 0 0 HI-8685, HI-8686 TIMING DIAGRAMS 28 ARINC Data Bits 29 30 31 32 Word Gap 4 Bit Periods Min. 1 2 +10V 0V -10V VDIFF RINA - RINB DERIVED DATA DERIVED CLOCK FIGURE 3 - RECEIVER INPUT TIMING FOR ARINC 429 28 ARINC Data Bits 29 30 31 32 Word Gap 4 Bit Periods Min. 1 2 +5V 0V +5V 0V TESTA TESTB DERIVED DATA DERIVED CLOCK FIGURE 4 - TEST INPUT TIMING FOR ARINC 429 DERIVED DATA 32nd ARINC bit tDRDY tRDYCLR DATA RDY tRDPW READ tRD D0 - D15 VALID 1st 16-bits tRR 2nd 16-bits tFD VALID FIGURE 5 - RECEIVER PARALLEL DATABUS TIMING HOLT INTEGRATED CIRCUITS 5 HI-8685, HI-8686 ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND Supply voltages VCC ....................................................... +7.0V Voltage on inputs RINA (-10) to RINB (-10) ......... +29V to - 29V All other input pins..................-0.3 to Vcc +0.3 DC current per input pin ....................... +10mA Power dissipation at 25°C plastic 28-pin SO..... 1.8W, derate 14.1mW/°C plastic 28-pin PLCC .2.3W, derate 18.2mW/°C plastic 32-pin SO......1.6W, derate 15.4mW/°C Solder Temperature Leads ............................. +280°C for 10 sec Package body ..................................+220°C Storage Temperature ............. -65°C to +150°C Supply Voltages VCC ...................................................+5V ± 5% Temperature Range Industrial Screening .............. -40°C to +85°C Hi-Temp Screening .............. -55°C to +125°C Military Screening..................-55°C to +125°C Junction Temperature, Tj ................... £+175°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. RECOMMENDED OPERATING CONDITIONS DC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ARINC Bus Inputs (RINA, RINB, RINA-10 & RINB-10) Differential input voltage one or zero null common mode Input resistance RINA (-10) to RINB(-10) RINA (-10) or RINB(-10) to GND or VCC Input capacitance (Guaranteed but not tested) differential to GND to VCC VDIN VNIN VCOM RDIFF RSUP CDIFF CG CH differential voltage " " "" with respect to GND supplies floating "" "' RINA (-10) to RINB (-10) 6.5 30 19 10.0 13.0 2.75 5.0 75 40 20 20 20 volts volts volts Kohm Kohm pF pF pF Digital Inputs (RESET, GAPCLK, READ & PARITY ENB) Input voltage high low Input current source sink Input capacitance VIH VIL IIH IIL CI VIN = 5.0V VIN = 0.0V 2.0 0.0 -1.0 VCC 0.8 1.0 8.0 volts volts µA µA pF HOLT INTEGRATED CIRCUITS 6 HI-8685, HI-8686 DC ELECTRICAL CHARACTERISTICS (cont.) Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS Digital Inputs (TESTA & TESTB) Input voltage high low Input current source sink Input capacitance Outputs (D0 to D15, ERROR & DATA RDY) Output voltage high low Output tri-state current (D0 - D15 only) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VIH VIL IIH IIL CI VIN = 5.0V VIN = 0.0V 2.4 0.0 -1.0 - 110 - VCC 0.8 8.0 volts volts µA µA pF VOH VOL IIH IIL IOH = -1.0 mA IOL = 1.6 mA VOH = 5.0V VOL = 0.0V 2.7 -1.0 - - 0.4 1.0 15 volts volts µA µA pF Output capacitance Operating Supply Current VCC CO ICC VIN = 0.0V, outputs open - - 6.5 mA AC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS READ pulse width Data delay from READ READ to data floating READ to DATA RDY clear READ pulse to next READ pulse GAPCLK frequency 32nd ARINC bit to DATA RDY SYMBOL tRDPW tRD tFD tRDYCLR tRR fGC tDRDY TEST CONDITIONS MIN 50 TYP MAX UNITS ns 40 20 35 ns ns ns ns 25 1 16 17 MHz clocks HOLT INTEGRATED CIRCUITS 7 HI-8685, HI-8686 ADDITIONAL HI-8685 PIN CONFIGURATION (See page 1 for additional pin configurations) DATA RDY GAPCLK 27 4 3 2 1 28 D12 D11 D10 D9 D8 D7 D6 TESTA 26 25 D13 D14 D15 VCC 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TESTB RESET RINB (RINB-10) RINA (RINA-10) ERROR PARITY ENB READ HI-8685PJI HI-8685PJT & HI-8685PJI-10 HI-8685PJT-10 24 23 22 21 20 19 GND D5 D4 D3 D2 D1 HI-8685 28-Pin Plastic PLCC ORDERING INFORMATION HI - 8685xx x x - xx PART NUMBER INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY No dash number -10 PART NUMBER 35 Kohm 25 Kohm LEAD FINISH D0 0 10 Kohm Blank F PART NUMBER Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I T PART NUMBER -40°C TO +85°C -55°C TO +125°C PACKAGE DESCRIPTION I T NO NO BUILT-IN LINE RECV’R 8685PJ 8685PS Legend: WB 28 PIN PLASTIC PLCC 28 PIN PLASTIC SOIC - WB - Wide Body YES YES For HI-8686PQ please see next page HOLT INTEGRATED CIRCUITS 8 HI-8685, HI-8686 ORDERING INFORMATION HI - 8686PQ x x PART NUMBER LEAD FINISH Blank F PART NUMBER Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I T PART NUMBER -40°C TO +85°C -55°C TO +125°C PACKAGE DESCRIPTION I T NO NO BUILT-IN LINE RECV’R EXT. 10KW REQUIRED 8686PQ Legend: WB 32 PIN PLASTIC TQFP - Wide Body YES OPTIONAL (1) (1): RINA/B and RINA-10/B-10 are both available For HI-8685 please see previous page HOLT INTEGRATED CIRCUITS 9 HI-8685, HI-8686 PACKAGE DIMENSIONS inches (millimeters) 28-PIN PLASTIC PLCC Package Type: 28J PIN NO. 1 IDENT .045 x 45° .026 ± .003 x 30° (.660 ± .076 x 30°) .050 ± .005 (1.27 ± .127) .029 ± .003 (.737 ± .076) .490 ± .005 (12.446 ± .127) SQ. .454 ± .002 (11.532 ± .051) SQ. .017 ±.004 (.432 ±.102) .152 ± .002 (3.861 ± .051) SEE DETAIL A .010 ± .0003 (.256 ± .0076) .015 ± .002 (.381 ± .051) DETAIL A .020 MIN (.508 MIN) .420 ± .010 (10.668 ± .254) .020 MIN (.508 MIN) .035 R TYP (.889 R) 28-PIN PLASTIC SMALL OUTLINE (SOIC) - WB (Wide Body) Package Type: 28HW .7055 ± .0045 (17.920 ± .114) .0105 ± .0015 (.2667 ± .0381) .4065 ± .0125 (10.325 ± .318) .295 ± .004 (7.493 ± .102) SEE DETAIL A .018 TYP (.457) .095 ± .005 (2.413 ± .127) 0° to 8° .050 TYP (1.27) .033 ± .017 DETAIL A (.838 ± .432) .0075 ± .0035 (.191 ± .089) HOLT INTEGRATED CIRCUITS 10 HI-8685, HI-8686 PACKAGE DIMENSIONS inches (millimeters) 32 PIN PLASTIC THIN QUAD FLAT PACK (TQFP) Package Type: 32PTQS .00057 ± .00022 (0.0145 ± .0055) .0315 BSC (0.80 BSC) .0148 ± .0030 (0.375 ± .075) .0236 ± .0059 (0.60 ± .15) .3543 BSC SQ. (9.00 BSC) .2755 BSC SQ. (7.00 BSC) .0394 ± .002 (1.0 ± .05) See Detail A .047 MAX. (1.20 MAX.) .0039 ± .002 (0.10 ± .05) .0031 R MIN. (0.08 R MIN.) .0055R ± .0024 (0.14R ± .06) 0° £ Q £ 7° Detail A HOLT INTEGRATED CIRCUITS 11