HI-8787PQT

HI-8787, HI-8788 September 2006 ARINC INTERFACE DEVICES 16 bit parallel data converted to 429 & 561 serial data out PIN CONFIGURATION DESCRIPTION The HI-8787 and HI-8788 are system components for interfacing 16 bit parallel data to an ARINC 429 bus. They combine logic and line driver on one chip. The HI-8787 has an output resistance of 37.5 ohms, and the HI-8788 has output resistance of 10 ohms to facilitate external lightning protection circuitry. The technology is analog/digital CMOS. Both products offer high speed data bus transactions into a buffer register. After loading 2 each 16-bit words, data is automatically transferred and transmitted. The data rate is equal to the clock rate. Parity can be enabled in the 32nd bit. Reset is used to initialize the logic upon startup. Word gaps are sent automatically. The part requires +/- 10 volt supplies in addition to a 5 volt supply. 28 - 561 SYNC D4 - 1 N/C - 2 D5 - 3 D6 - 4 D7 - 5 D8 - 6 D9 - 7 D10 - 8 25 - 561 DATA 27 - VCC 32 - D3 31 - D2 30 - D1 29 - D0 26 - V+ 24 - TXBOUT HI-8787PQI HI-8787PQT HI-8788PQI & HI-8788PQT 23 - TXAOUT 22 - V21 - PARITY ENB 20 - XMT RDY 19 - XMIT CLK 18 - RESET 17 - WRITE D12 - 10 D13 - 13 A0 - 12 D14 - 14 D15 - 15 FEATURES 32-Pin Plastic PQFP package l l l l l Automatically converts 16 bit parallel data to ARINC 429 or 561 serial data High speed data bus interface On-chip line driver Available in small TQFP package Military processing options (DS8787 Rev.H) HOLT INTEGRATED CIRCUITS www.holtic.com SLP1.5 - 16 GND - 11 D11 - 9 09/06 HI-8787, HI-8788 PIN DESCRIPTIONS PIN 28 1, 3-10,13-15, 29-32 11 12 16 17 18 19 20 21 22 23 24 25 26 27 SYMBOL 561 SYNC Dn GND A0 SLP1.5 WRITE RESET XMIT CLK XMT RDY PARITY ENB VTXAOUT TXBOUT 561 DATA V+ VCC FUNCTION digital output digital inputs power supply digital input digital input digital input digital input digital input digital output digital input power supply analog output analog output digital output power supply power supply DESCRIPTION ARINC 561 Sync signal Parallel 16 bit bus input Ground Load address, A0=1 for 1st data load, A0=0 for 2nd data load Selects the slope of the line driver. High=1.5us Write strobe. Loads data on rising edge. Registers and sequencing logic initialized when low Clock input for the transmitter Goes high if the buffer register is empty When high the 32nd bit output is odd parity -10 volt rail Line driver output - A side Line driver output - B side Serial output for ARINC 561 data +10 volt rail +5 volt rail, “one” level out of line driver, inverted for “zero” FUNCTIONAL DESCRIPTION The HI-8787 is a parallel to serial converter, which when loaded with two 16 bit parallel words, outputs the data as a 32 bit serial word. Timing circuitry inserts a 4 bit gap at the end of each 32 bit word. An input buffer register allows load operations to take place while the previously loaded word is being transmitted. If the PARITY ENB pin is high, the 32nd bit will be a parity bit, inserted so as to make the 32 bit word have odd parity. If the PARITY ENB pin is low, the 32nd bit will be the D15 bit of the 2nd word loaded. Outputs are provided for both ARINC 429 (TXAOUT and TXBOUT pins) and ARINC 561 (561 DATA and 561 SYNC pins) type data. A low signal applied to the RESET pin resets the HI-8787’s internal logic so that spurious transmission does not take place during power-up. The registers are cleared so that a continuous gap will be transmitted until the first word is loaded into the transmitter. The XMIT CLK frequency is the same as the data rate. Input data can be loaded when the XMT RDY signal is high, which indicates the input buffer register is empty. The first 16 bit word is loaded with the A0 input high. The second word is loaded with A0 in the low state. Once A0 is set low, it must not go high until after the second byte is loaded. Each data word is loaded into the input buffer register by a low pulse on the WRITE input. After the second word has been loaded, the XMT RDY output goes low. The contents of the input buffer register are transferred to the output register during the fourth bit period of the gap. If the fourth gap bit period of the previous word has already been transmitted, the contents of the input buffer register will be transferred to the output shift register during the first bit period after the second data load, and the XMT RDY output goes high. After the output shift register is loaded, the data is shifted out to the output logic in the order shown in figure 2. The 561 SYNC output pulses low when the XMIT CLK is low during the 8th bit of the ARINC transmission. HOLT INTEGRATED CIRCUITS 2 HI-8787, HI-8788 XMIT CLK XMT RDY WRITE status & control logic SLP1.5 TXAOUT A0 line driver word gap counter TXBOUT DATA BUS 16 to 32 bit mux 16 32 32 bit buffer register 32 32 bit shift register bit counter 561 SYNC 561 DATA output logic PARITY ENB Figure 1. Block Diagram FUNCTIONAL DESCRIPTION (Cont.) The HI-8787 and HI-8788 have an on-chip line driver designed to directly drive the ARINC 429 bus. The two ARINC outputs (TXAOUT and TXBOUT) provide a differential voltage to produce a +10 volt One, a -10 volt Zero, and a 0 volt Null. The slope of the ARINC outputs is controlled by the SLP1.5 pin. If SLP1.5 is high, the output rise and fall time is nominally 1.5µs. If SLP1.5 is set low, the rise and fall times are 10µs. The HI-8787 has 37.5 ohms in series with each line driver output. The HI-8788 has 10.0 ohms in series. The HI-8788 is for applications where external series resistance is needed, typically for lightning protection devices. A0 1 0 Load Word 1 Word 2 Data Bus D0 - D15 D0 - D15 ARINC Bits ARINC 1 - ARINC 16 ARINC 17 - ARINC 32 Figure 2. Order of transmitted data POWER SUPPLY SEQUENCING The power supplies must be controlled to prevent large currents during supply turn-on and turn-off. The required sequence is V+ followed by VDD, always ensuring that V+ is the most positive supply. The V- supply is not critical and can be asserted at any time. TRANSMITTER OPERATION DATA BUS WORD 1 VALID WORD 2 VALID tSET WRITE tHLD tWPW A0 t WPD tASW tASW XMT RDY tAH t XD HOLT INTEGRATED CIRCUITS 3 HI-8787, HI-8788 DATA TRANSMISSION - EXAMPLE PATTERN GAP 32 33 34 35 36 1 2 3 4 31 32 33 GAP 34 35 36 1 2 XMIT CLK WRITE XMT RDY ARINC 429 DATA (TXAOUT-TXBOUT) 561 DATA 561 SYNC 561 SYNC LINE DRIVER OUTPUTS XMT CLK t phlx t plhx t plhx t phlx t rx 90% 10% 90% 10% t rx DIFFERENTIAL VOLTAGE TXAOUT - TXBOUT 10% 10V 0V -10V t fx t fx HOLT INTEGRATED CIRCUITS 4 HI-8787, HI-8787, HI-8788 ABSOLUTE MAXIMUM RATINGS Voltages referenced to Ground Supply voltages V+.................................................12.5V V-.................................................-12.5V VCC.................................................. 7V DC current per input pin................ +10ma Power dissipation at 25° plastic DIL............1.0W, derate 10mW/°C ceramic DIL..........0.5W, derate 7mW/°C Solder Temperature ........275°C for 10 sec Storage Temperature........-65°C to +150°C RECOMMENDED OPERATING CONDITIONS Supply Voltages V+.......................................+10V... ±5% V-........................................ -10V... ±5% VCC....................................... 5V... ±5% Temperature Range Industrial Screening.........-40°C to +85°C Hi-Temp Screening........-55°C to +125°C Military Screening..........-55°C to +125°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. DC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VSS = 0V, V+ = 10V, V- = -10V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER Operating Voltage Operating Voltage Operating Voltage Min. Input Voltage Max. Input Voltage Min. Input Current Max. Input Current Min. Output Voltage Max. Output Voltage (HI) (LO) (HI) (LO) (HI) (LO) SYMBOL VCC V+ VVIH VIL IIH IIL VOH VIH CONDITION MIN 4.75 9.5 -9.5 2.0 TYP 5 10 -10 1.4 1.4 MAX 5.25 10.5 10.5 UNITS V V V V 0.7 280 V µA µA V VIH = 4.9V VIL = 0.1V IOUT = -1.6mA IOUT = 1.6mA -1 2.7 0.4 V Line Driver Output Levels (Ref. To GND) ONE NULL ZERO Line Driver Output Levels (Differential TXAOUT - TXBOUT) ONE NULL ZERO Minimum Short Circuit Sink or Source Current Operating Current Drain Operating Current Drain (V+) Operating Current Drain (V-) Input Capacitance IOUT ICC IDD IEE CIN no load, VCC = 5.0V “ “ momentary magnitude f = 100khz f = 100khz f = 100khz Not tested -20 9.0 -0.5 -11.0 80 0.8 6 -6 20 2.8 20 10.0 0 -10.0 11.0 0.5 -9.0 V V V mA mA mA mA pF no load, VCC = 5.0V “ 4.5 -0.25 -5.5 5.0 0 -5.0 5.5 0.25 -4.5 V V V HOLT INTEGRATED CIRCUITS 5 HI-8787, HI-8788 AC ELECTRICAL CHARACTERISTICS VCC = 5.0V, V+ = 10V, V- = -10V, VSS = 0V, TA =Operating Temperature Range (unless otherwise specified). PARAMETER DATA BUS TIMING Setup Data Bus to WRITE Hold WRITE to Data Bus Hold A0 to WRITE Pulse width WRITE Delay between WRITE Setup A0 to WRITE Delay last WRITE to XMT RDY LINE DRIVER TIMING Line Driver propagation delay Output high to low Output low to high Line Driver transition times Output high to low Output low to high Output high to low Output low to high SYMBOL tSET tHLD tAH tWPW tWPD tASW tXD TEST CONDITIONS MIN 20 30 0 40 40 20 80 TYP MAX UNITS ns ns ns 1 CLK ns ns ns ns No load tphlx tplhx 500 500 ns ns t fx t rx t fx t rx SLP1.5 = logic 1 SLP1.5 = logic 1 SLP1.5 = logic 0 SLP1.5 = logic 0 1.0 1.0 5 5 1.5 1.5 10 10 2.0 2.0 15 15 µs µs µs µs ORDERING INFORMATION HI - 87xx xx x x PART NUMBER LEAD FINISH Blank F PART NUMBER Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I T PART NUMBER -40°C TO +85°C -55°C TO +125°C PACKAGE DESCRIPTION I T NO NO PQ PART NUMBER 52 PIN PLASTIC QUAD FLAT PACK (PQFP) OUTPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY 8787 8788 37.5 Ohms 10 Ohms 0 27.5 Ohms HOLT INTEGRATED CIRCUITS 6 HI-8787, HI-8788 PACKAGE DIMENSIONS inches (millimeters) 32 PIN PLASTIC THIN QUAD FLAT PACK (PQFP) Package Type: 32PTQS .00057 ± .00022 (0.0145 ± .0055) .0315 BSC (0.80 BSC) .0148 ± .0030 (0.375 ± .075) .0236 ± .0059 (0.60 ± .15) .3543 BSC SQ. (9.00 BSC) .2755 BSC SQ. (7.00 BSC) .0394 ± .002 (1.0 ± .05) See Detail A .047 MAX. (1.20 MAX.) .0039 ± .002 (0.10 ± .05) .0031 R MIN. (0.08 R MIN.) .0055R ± .0024 (0.14R ± .06) 0° £ Q £ 7° Detail A H OLT INTEGRATED CIRCUITS 7