H5TC1G63BFR

1Gb DDR3L SDRAM 1Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC1G43BFR-xxA H5TC1G83BFR-xxA H5TC1G63BFR-xxA *Hynix Semiconductor reserves the right to change products or specifications without notice Rev. 0.1 / Nov. 2009 1 Revision History Revision No. 0.1 History Initial Release Draft Date Nov. 2009 Remark Preliminary Rev. 0.1 / Nov. 2009 2 Description The H5TC1G43BFR-xxA, H5TC1G83BFR-xxA and H5TC1G63BFR-xxA are a 1Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.) Hynix 1Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10 supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC • Auto Self Refresh supported • JEDEC standard 78ball FBGA(x4/x8) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • 8 bit pre-fetch * This product in compliance with the RoHS directive. Rev. 0.1 / Nov. 2009 3 ORDERING INFORMATION Part No. H5TC1G43BFR-*xxA H5TC1G83BFR-*xxA H5TC1G63BFR-*xxA Configuration 256M x 4 128M x 8 64M x 16 Package 78ball FBGA 96ball FBGA * xx means Speed Bin Grade OPERATING FREQUENCY Speed Grade (Marking) -G7 -H9 Frequency [MHz] CL5 CL6 O O CL7 O O CL8 O O O O CL9 CL10 CL11 Remark (CL-tRCD-tRP) DDR3-1066 7-7-7 DDR3-1333 9-9-9 Rev. 0.1 / Nov. 2009 4 Package Ballout/Mechanical Dimension x4 Package Ball out (Top view): 78ball FBGA Package (no support balls) 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 NF VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS NF RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 7 NF DM DQ1 VDD NF CK CK A10/AP NC A12/BC A1 A11 A14 8 VSS VSSQ DQ3 VSS NF VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N 4 5 6 7 Note: NF(No Function) - This is applied to balls only used in x4 configuration. 123 A B C D E F G H J K L M N 789 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 0.1 / Nov. 2009 5 x8 Package Ball out (Top view): 78ball FBGA Package (no support balls) 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 7 NU/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP NC A12/BC A1 A11 NC 8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N 4 5 6 7 123 A B C D E F G H J K L M N 789 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 0.1 / Nov. 2009 6 x16 Package Ball out (Top view): 96ball FBGA Package (no support balls) 1 A B C D E F G H J K L M N P R T VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 7 DQU4 DQSU DQSU DQU0 DML DQL1 VDD DQL7 CK CK A10/AP A15 A12/BC A1 A11 NC 8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N P R T 4 5 6 7 1 A B C D E F G H J K L M N P R T 2 3 7 8 9 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 0.1 / Nov. 2009 7 Pin Functional Description Symbol CK, CK Type Input Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during powerdown. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8 configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL, DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Address Inputs: Provide the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below). The address inputs also provide the op-code during Mode Register Set commands. Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. 8 CKE, (CKE0), (CKE1) Input CS, (CS0), (CS1), (CS2), (CS3) Input ODT, (ODT0), (ODT1) Input RAS. CAS. WE DM, (DMU), (DML) Input Input BA0 - BA2 Input A0 - A15 Input A10 / AP Input A12 / BC Input Rev. 0.1 / Nov. 2009 Symbol Type Function Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. Data Input/ Output: Bi-directional data bus. Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1. No Connect: No internal electrical connection is present. No Function RESET Input DQ DQU, DQL, DQS, DQS, DQSU, DQSU, DQSL, DQSL Input / Output Input / Output TDQS, TDQS Output NC NF VDDQ VSSQ VDD VSS VREFDQ VREFCA ZQ Supply Supply Supply Supply Supply Supply Supply DQ Power Supply: 1.5 V +/- 0.075 V DQ Ground Power Supply: 1.5 V +/- 0.075 V Ground Reference voltage for DQ Reference voltage for CA Reference Pin for ZQ calibration Note: Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination. Rev. 0.1 / Nov. 2009 9 ROW AND COLUMN ADDRESS TABLE 1Gb Configuration # of Banks Bank Address Auto precharge BL switch on the fly Row Address Column Address Page size 1 256Mb x 4 8 BA0 - BA2 A10/AP A12/BC A0 - A13 A0 - A9,A11 1 KB 128Mb x 8 8 BA0 - BA2 A10/AP A12/BC A0 - A13 A0 - A9 1 KB 64Mb x 16 8 BA0 - BA2 A10/AP A12/BC A0 - A12 A0 - A9 2 KB Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG ÷ 8 where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits Rev. 0.1 / Nov. 2009 10 Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 Units V V V oC Notes 1,3 1,3 1 1, 2 VIN, VOUT Voltage on any pin relative to Vss TSTG Notes: Storage Temperature 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. DRAM Component Operating Temperature Range Temperature Range Symbol TOPER Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability Parameter Normal Operating Temperature Range Extended Temperature Range (Optional) Rating 0 to 85 85 to 95 Units oC oC Notes 1,2 1,3 b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Rev. 0.1 / Nov. 2009 11 AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions - DDR3L (1.35V) operation Symbol VDD VDDQ Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long period of time (e.g 1 sec) 2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications 3. Under these supply voltages, the device operates to this DDR3L specification 4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (See figure 0) Parameter Supply Voltage Supply Voltage for Output Rating Min. 1.283 1.283 Typ. 1.35 1.35 Max. 1.45 1.45 Units V V Notes 1,2,3,4 1,2,3,4 Recommended DC Operating Conditions - DDR3 (1.5V) operation Symbol VDD VDDQ Notes: 1. If maximum limit is exceeded, input levels shall be governed by DDR3L specifications 2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation (See figure 0) Parameter Supply Voltage Supply Voltage for Output Rating Min. 1.425 1.425 Typ. 1.5 1.5 Max. 1.575 1.575 Units V V Notes 1,2,3 1,2,3 Rev. 0.1 / Nov. 2009 12 Ta CK,CK# Tb Tc Td Te Tf Tg Th Ti Tj Tk VDD, VDDQ (DDR3) VDD, VDDQ (DDR3L) Tmin = 10ns Tmin = 10ns tCKSRX Tmin = 200us T = 500us RESET# CKE Tmin = 10ns tDLLK tIS tXPR MRS tMRD MRS tMRD MRS tMRD MRS tMOD ZQCL tZQinit 1) VALID COMMAND READ 1) VALID BA READ tIS MR2 MR3 MR1 MR0 VALID tIS ODT READ Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW VALID RTT NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands. TIME BREAK DON’T CARE Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3 Rev. 0.1 / Nov. 2009 13 IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. • IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. • For IDD and IDDQ measurements, the following definitions apply: • • • • • • • ”0” and “LOW” is defined as VIN = VIHAC(max). “MID_LEVEL” is defined as inputs are VREF = VDD/2. Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1. Basic IDD and IDDQ Measurement Conditions are described in Table 2. Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10. IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH} • • • Rev. 0.1 / Nov. 2009 14 IDD IDDQ (optional) VDD RESET CK/CK CKE CS RAS, CAS, WE A, BA ODT ZQ VDDQ DDR3L SDRAM DQS, DQS DQ, DM, TDQS, TDQS RTT = 25 Ohm VDDQ/2 VSS VSSQ Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above] Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Simulation Correction Channel IO Power Number Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev. 0.1 / Nov. 2009 15 Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol DDR3-1066 7-7-7 1.875 7 7 27 20 7 1KB page size 2KB page size 1KB page size 2KB page size 20 27 4 6 48 59 86 160 187 DDR3-1333 9-9-9 1.5 9 9 33 24 9 20 30 4 5 60 74 107 200 234 Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK tCK CL nRCD nRC nRAS nRP nFAW nRRD nRFC -512Mb nRFC-1 Gb nRFC- 2 Gb nRFC- 4 Gb nRFC- 8 Gb Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol Description Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT IDD0 and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between IDD1 ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4. Rev. 0.1 / Nov. 2009 16 Symbol Precharge Standby Current Description CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2NT Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6; Pattern Details: see Table 6. IDDQ2NT Precharge Standby ODT IDDQ Current (optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2P0 Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2P1 Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current IDD2Q CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD3N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Rev. 0.1 / Nov. 2009 17 Symbol Active Power-Down Current Description IDD3P CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 IDDQ4R Operating Burst Read IDDQ Current (optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, IDD4R Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7. Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, IDD4W Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8. Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com- IDD5B mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9. Self-Refresh Current: Normal Temperature Range TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6 CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Rev. 0.1 / Nov. 2009 18 Symbol Description Self-Refresh Current: Extended Temperature Range TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): ExtendIDD6ET ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Auto Self-Refresh Current TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6TC CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a)f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according IDD7 to Table 10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10. a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B Rev. 0.1 / Nov. 2009 19 Table 3 - IDD0 Measurement-Loop Patterna) Command Sub-Loop Cycle Number A[15:11] BA[2:0] A[9:7] A[6:3] CK, CK A[2:0] 0 0 0 0 0 0 0 0 A[10] ODT RAS CKE CAS WE 0 0 1,2 3,4 ... nRAS ... 1*nRC+0 1*nRC+1, 2 ACT D, D D, D PRE ACT D, D D, D PRE CS Datab) 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F F - repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary Static High toggling 1*nRC+3, 4 ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary repeat pattern 1...4 until 2*nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 0.1 / Nov. 2009 20 Table 4 - IDD1 Measurement-Loop Patterna) Command Sub-Loop Cycle Number A[15:11] BA[2:0] A[9:7] A[6:3] CK, CK A[2:0] 0 0 0 0 0 0 0 0 0 0 A[10] ODT RAS CKE CAS WE 0 0 1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC+1,2 ACT D, D D, D RD PRE ACT D, D D, D RD PRE CS Datab) 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F F F 00000000 00110011 - repeat pattern 1...4 until nRCD - 1, truncate if necessary repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary Static High toggling 1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL. Rev. 0.1 / Nov. 2009 21 Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) Command Sub-Loop Cycle Number A[15:11] BA[2:0] A[9:7] A[6:3] CK, CK A[2:0] 0 0 0 0 A[10] ODT RAS CKE CAS WE 0 0 1 2 3 D D D D CS Datab) 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F - Static High toggling 1 2 3 4 5 6 7 4-7 8-11 12-15 16-19 20-23 24-17 28-31 repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna) Command Sub-Loop Cycle Number A[15:11] BA[2:0] A[9:7] A[6:3] CK, CK A[2:0] 0 0 0 0 A[10] ODT RAS CKE CAS WE 0 0 1 2 3 D D D D CS Datab) 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F - Static High toggling 1 2 3 4 5 6 7 4-7 8-11 12-15 16-19 20-23 24-17 28-31 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 0.1 / Nov. 2009 22 Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna) Command Sub-Loop Cycle Number A[15:11] BA[2:0] A[9:7] A[6:3] CK, CK A[2:0] 0 0 0 0 0 0 A[10] ODT RAS CKE CAS WE 0 0 1 2,3 4 5 RD D D,D RD D D,D CS Datab) 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F 00000000 00110011 - Static High toggling 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. Rev. 0.1 / Nov. 2009 23 Table 8 - IDD4W Measurement-Loop Patterna) Command Sub-Loop Cycle Number A[15:11] BA[2:0] A[9:7] A[6:3] CK, CK A[2:0] 0 0 0 0 0 0 A[10] ODT RAS CKE CAS WE 0 0 1 2,3 4 5 WR D D,D WR D D,D CS Datab) 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F 00000000 00110011 - Static High toggling 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. Table 9 - IDD5B Measurement-Loop Patterna) Command Sub-Loop Cycle Number A[15:11] BA[2:0] A[9:7] A[6:3] CK, CK A[2:0] 0 0 0 A[10] ODT RAS CAS CKE WE 0 1 0 1.2 3,4 5...8 REF D, D D, D CS Datab) 0 1 1 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 F - repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. Static High toggling 9...12 13...16 17...20 21...24 25...28 29...32 2 33...nRFC-1 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 0.1 / Nov. 2009 24 Table 10 - IDD7 Measurement-Loop Patterna) ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 Command Sub-Loop Cycle Number A[15:11] BA[2:0] A[9:7] A[6:3] CK, CK A[2:0] A[10] ODT RAS CAS CKE 0 0 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+ 2 2*nFAW+2*nRRD 2*nFAW+3*nRRD 2*nFAW+4*nRRD 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 3*nFAW+4*nRRD 1 2 3 4 5 6 7 8 Static High toggling 9 10 11 12 13 14 15 16 17 18 19 ACT 0 0 1 1 0 0 00 0 0 0 0 RDA 0 1 0 1 0 0 00 1 0 0 0 D 1 0 0 0 0 0 00 0 0 0 0 repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 F 0 RDA 0 1 0 1 0 1 00 1 0 F 0 D 1 0 0 0 0 1 00 0 0 F 0 repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 1, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 F 0 Assert and repeat above D Command until 2* nFAW - 1, if necessary ACT 0 0 1 1 0 0 00 0 0 F 0 RDA 0 1 0 1 0 0 00 1 0 F 0 D 1 0 0 0 0 0 00 0 0 F 0 Repeat above D Command until 2* nFAW + nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 0 0 RDA 0 1 0 1 0 1 00 1 0 0 0 D 1 0 0 0 0 1 00 0 0 0 0 Repeat above D Command until 2* nFAW + 2* nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 0 0 Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 0 0 Assert and repeat above D Command until 4* nFAW - 1, if necessary WE CS Datab) 00000000 00110011 - - 00110011 00000000 - - - a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. Rev. 0.1 / Nov. 2009 25 IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. IDD Specification Speed Grade Bin Symbol DDR3 - 1066 7-7-7 Max. 75 85 10 20 50 55 50 35 55 115 115 175 10 12 12 170 DDR3 - 1333 9-9-9 Max. 80 90 10 20 55 60 55 40 60 130 130 180 10 12 12 190 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x4/x8 x4/x8 x4/x8 x4/x8 x4/x8 x4/x8 x4/x8 x4/x8 x4/x8 x4/x8 x4/x8 x4/x8 x4/x8,1 x4/x8,2 x4/x8,3 x4/x8 Unit Notes IDD0 IDD01 IDD2P0 IDD2P1 IDD2N IDD2NT IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 Notes: 1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85oC. 2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95oC. 3. Applicable for MR2 settings A6=1 and A7=0. IDD6TC is measured at 95oC Rev. 0.1 / Nov. 2009 26 Input/Output Capacitance Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance, CK and CK Symbol DDR3L-800 Min 1.5 0.8 0 0 0.75 -0.5 -0.5 -0.5 Max 2.5 1.6 0.15 0.20 1.3 0.3 0.5 0.3 3 DDR3L-1066 Min 1.5 0.8 0 0 0.75 -0.5 -0.5 -0.5 Max 2.5 1.6 0.15 0.20 1.3 0.3 0.5 0.3 3 DDR3L-1333 Min 1.5 0.8 0 0 0.75 -0.4 -0.4 -0.5 Max 2.3 1.4 0.15 0.15 1.3 0.2 0.4 0.3 3 Units Notes CIO CCK pF pF pF pF pF pF pF pF pF 1,2,3 2,3 2,3,4 2,3,5 2,3,6 2,3,7,8 2,3,9,10 2,3,11 2,3,12 Input capacitance delta CDCK CK and CK Input capacitance delta, DQS CDDQS and DQS Input capacitance CI (All other input-only pins) Input capacitance delta CDI_CTRL (All CTRL input-only pins) Input capacitance delta CDI_ADD_CM (All ADD/CMD input-only pins) D Input/output capacitance delta CDIO (DQ, DM, DQS, DQS) Input/output capacitance of ZQ CZQ pin Notes: 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS. 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V(cf.CIO & CI=1.35V), VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK. 5. Absolute value of CIO(DQS)-CIO(DQS). 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTR applies to ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS)) 12. Maximum external load capacitance an ZQ pin: 5 pF. Rev. 0.1 / Nov. 2009 27 Standard Speed Bins DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3L-800 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 31. Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CWL = 5 CWL = 5 Supported CL Settings Supported CWL Settings Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) 2.5 6 5 min 15 15 15 52.5 37.5 DDR3-800E 6-6-6 max 20 — — — 9 * tREFI Reserved 3.3 ns ns ns ns ns ns ns nCK nCK 1, 2, 3, 4 1, 2, 3 Unit Notes Rev. 0.1 / Nov. 2009 28 DDR3L-1066 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 31. Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CL = 7 CL = 8 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 min 13.125 13.125 13.125 50.625 37.5 Reserved Reserved 2.5 Reserved Reserved 1.875 Reserved 1.875 6, 7, 8 5, 6 < 2.5 < 2.5 3.3 DDR3-1066 7-7-7 max 20 — — — 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2, 3, 4, 5 4 1, 2, 3, 5 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 Unit Note tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) Supported CL Settings Supported CWL Settings nCK nCK Rev. 0.1 / Nov. 2009 29 DDR3L-1333 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 31. Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6, 7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 5, 6 CWL = 7 CWL = 5, 6 CL = 10 CWL = 7 min 13.5 (13.125)8 13.5 (13.125)8 13.5 (13.125)8 49.5 (49.125)8 36 Reserved Reserved 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.875 Reserved Reserved 1.5 Reserved 1.5 Reserved 6, 8, (7), 9, (10) 5, 6, 7