IC-GFQFN24

iC-GF TRANSCEIVER Rev C1, Page 1/26 FEATURES o IO-Link compliant slave transceiver o Dual channel switches, configurable for high-side, low-side and push-pull operation with tristate function o Configuration via pins or SPI interface o Switches are current limited o Switches, iC supply and feedback channel are protected against reverse polarity o Output current of up to 150 mA per channel o Parallel connection of both channels possible o The channels can be inverted for antivalent output o Sensor communication request function (IO-Link wake-up) o Wide supply voltage range of 9 to 30 V o Sensor parametrisation via a feedback channel (up to 30 V) o Switching converters and linear regulators for 3.3/5 V voltage generation o Error detection with hysteresis with excess temperature, overload and undervoltage o Driver shut-down on all errors o Error signalling at two open-collector outputs APPLICATIONS o o o o o IO-Link slaves I/O sensor interface Digital sensors Light barriers Proximity switches PACKAGES QFN24 4 mm x 4 mm BLOCK DIAGRAM VCC VCC3 CVCC 1uF CVCC3 1uF VCC3 NUVD/MISO Driver NOVL/NDIAG Undervoltage VCC ..5 0 m A VCC3 VBR VCC VH CVH 1uF LVH 22uH VHL CVBR 1uF VBR 1 RSET 6.8k VCC3 Channel 1 QCF G1/NCS INV1/ESPI IN1/T X VCC3 ISET T o ff O v. L o a d Lin. Regulator DC/DC Converter Bias VBO VBO -500 -10 -0.3 -50 Referenced to lowest voltage of VN, VBO, VBR, QP1, QN1, QP2, QN2, CFI, VH, VHL Referenced to highest voltage of VN, VBO, VBR, QP1, QN1, QP2, QN2, CFI, VH, VHL 5 2 500 10 7 10 36 -36 -400 400 Referenced to lowest voltage of VN, VBO, VBR, QP1, QN1, QP2, QN2, VH, VHL Referenced to highest voltage of VN, VBO, VBR, QP1, QN1, QP2, QN2, VH, VHL 36 -36 -4 -0.3 -4 -0.3 -5 -0.3 -4 HBM, 100 pF discharged through 1.5 kΩ -40 -40 4 7 4 7 20 7 4 2 150 150 V V mA V V mA µF V V mA V V mA V mA mA V mA V V mA mA V V mA V mA V mA V mA kV °C °C Unit G002 I(VBO) G003 VBR Current in VBO Voltage at VBR G004 I(VBR) G005 Cl(VBR) G006 V(VH) Current in VBR Capacitive load at VBR Voltage at VH G007 I(VH) G008 V(VHL) Current in VH Voltage at VHL G009 I(VHL) G010 V(VN) G011 I(VN) G012 V() G013 I() G014 V() Current in VHL Voltage at GND vs. VN Current in VN Voltage at VCC, VCC3 Current in VCC, VCC3 Voltage at QP1, QN1, QP2, QN2 G015 I() G016 I() G017 V(CFI) Current in QP1, QP2 Current in QN1, QN2 Voltage at CFI G018 I(CFI) G019 V() G020 I() G021 V() G022 I() G023 V(ISET) G024 I(ISET) G025 Vd() G026 Tj G027 Ts Current in CFI Voltage at INV1, QCFG1, QCFG2, IN1, IN2, OEN, CFP Current in INV1, QCFG1, QCFG2, IN1, IN2, OEN, CFP Voltage at NOVL, NUVD, CFO Current in NOVL, NUVD, CFO Voltage at ISET Current in ISET ESD Susceptibility at all pins Junction Temperature Storage Temperature Range All voltages are referenced to ground unless otherwise stated. All currents into the device pins are positive; all currents out of the device pins are negative. iC-GF TRANSCEIVER Rev C1, Page 6/26 THERMAL DATA Operating Conditions: VBO = 9...30 V (referenced to VN), Tj = -40...125 °C, RSET = 6.8 kΩ ±1%, unless otherwise stated Item No. T01 T02 Symbol Ta Rthja Parameter Operating Ambient Temperature Range (extended range on request) Thermal Resistance Chip/Ambient Surface mounted, thermal pad soldered to ca. 2 cm² heat sink Conditions Min. -40 30 Typ. Max. 85 40 °C K/W Unit All voltages are referenced to ground unless otherwise stated. All currents into the device pins are positive; all currents out of the device pins are negative. iC-GF TRANSCEIVER Rev C1, Page 7/26 ELECTRICAL CHARACTERISTICS Operating Conditions: VBO = 9...30 V (referenced to VN), Tj = -40...125 °C, RSET = 6.8 kΩ ±1%, unless otherwise stated Item No. 001 002 003 004 005 006 007 008 009 010 Symbol Parameter Conditions Min. VBO I(VBO) Vs(VBR) VH I(VH) Vc()hi Vc()lo Vc()hi Vc()lo Vc()hi Permissible Supply Voltage Supply Current in VBO Saturation Voltage at VBR referenced to VBO Permissible Voltage at VH Supply Current in VH Clamp Voltage hi at VBO, VBR vs. VN Clamp Voltage lo at VBO, VBR vs. VN Clamp Voltage hi at QN1, QN2 vs. VN Clamp Voltage lo at QP1, QP2 vs. VBO Referenced to VN No load, VH conected to VBR, I(QP1) = I(QP2) = 0, QPx switched on I(VBR) = 20mA I(VBR) = 50mA VH > VHnr VH = 8 V, no load, I(VCC) = I(VCC3) = 0, V(OEN) = hi I() = 10 mA I() = -10 mA I() = 1 mA, VBO > VN I() = -1 mA, VBO > VN 36 36 -36 8.4 1.5 36 -36 9 Typ. 24 Max. 30 4.5 0.8 1 30 3 V mA V V V mA V V V V V Unit Total Device Clamp Voltage hi at VN, VBO, I() = 1 mA VBR, QP1, QN1, QP2, QN1, CFI, VH, VHL vs. lowest voltage of VN, VBO, VBR, QP1, QN1, QP2, QN1, CFI, VH, VHL Clamp Voltage hi at VCC, VCC3, I() = 1 mA ISET, INV1, IN1, IN2, QCFG1, QCFG2, OEN, CFO, CFP, NOVL, NUVD Clamp Voltage lo at VCC, VCC3, I() = -1 mA ISET, INV1, IN1, IN2, QCFG1, QCFG2, OEN, CFO, CFP, NOVL, NUVD Resistance GND to VN RSET = 5.1 kΩ; I() = 100 mA I() = 50 mA I() = 10 mA RSET = 6.8 kΩ, V() = 3 V...VBO RSET = 5.1 kΩ, V() = 4 V...VBO 011 Vc()hi 7 V 012 Vc()lo -0.5 V 013 RGND 3 7 Ω Low-Side Switch QN1, QN2 101 Vs()lo Saturation Voltage lo at QN1, QN2 vs. VN 1.2 0.65 0.3 100 160 1.5 1.5 0.1 140 200 180 260 2.1 1.8 V V V mA mA V V V 102 103 104 105 106 Isc()lo Vol()on Vol()off Vol()hys llk() Short-Circuit Current lo in QN1, QN2 Overload Detection Threshold on QN1, QN2 lo → hi; referenced to GND Overload Detection Threshold off QN1, QN2 hi → lo; referenced to GND Overload Detection Threshold Hysteresis Leakage Current at QN1, QN2 Vol()hys = Vol()on − Vol()off OEN = lo; V(QN1, QN2) = VBO...VBO + 6 V V(QN1, QN2) = 0...VBO V(QN1, QN2) = -6...0 V V(QN1, QN2) = VBO − 36 V...-6 V VBO = 30 V, Cl = 2.2 nF V(ISET) = 0 V, QNx > 3 V QNx activated; V(QNx) = -6 V NEXC = 0 (see Fig. 9) NEXC = 0 (see Fig. 9) Push-pull configuration, QNx activation delay after QPx deactivation (see Fig. 9) 0 0 -70 -200 170 -300 300 1.5 1.2 300 50 50 0 0 45 440 540 3.5 2.8 µA µA µA µA V/µs mA µA mA µs µs 107 108 109 110 111 112 SR() Imax() Ir() Iexc() texc tdead Slew Rate (switch off → on) Maximum Current in QN1, QN2 Reverse Current in QN1, QN2 Excitation Current Excitation Time Dead Time iC-GF TRANSCEIVER Rev C1, Page 8/26 ELECTRICAL CHARACTERISTICS Operating Conditions: VBO = 9...30 V (referenced to VN), Tj = -40...125 °C, RSET = 6.8 kΩ ±1%, unless otherwise stated Item No. Symbol Parameter Conditions Min. RSET = 5.1 kΩ; I() = -100 mA I() = -50 mA I() = -10 mA RSET = 6.8 kΩ, V() = 0...VBO − 3 V RSET = 5.1 kΩ, V() = 0...VBO − 4 V Typ. Max. Unit High-Side Switch QP1, QP2 201 Vs()hi Saturation Voltage hi vs. VBO -1.4 -0.85 -0.35 -230 -325 -2.1 -1.9 0.1 -150 -220 -100 -140 -1.5 -1.4 V V V mA mA V V V 202 203 204 205 206 Isc()hi Vol()on Vol()off Vol()hys llk() Short-Circuit Current hi Overload Detection Threshold on QP1, QP2 hi → lo; referenced to VBO Overload Detection Threshold off QP1, QP2 lo → hi; referenced to VBO Overload Detection Threshold Hysteresis Leakage Current at QP1, QP2 Vol()hys = Vol()off − Vol()on OEN = lo; V(QP1, QP2) = -6...0 V V(QP1, QP2) = 0 V...VBO V(QP1, QP2) > VBO...VN + 30 V VBO = 30 V, Cl = 2.2 nF V(ISET) = 0 V, VBO − QPx > 4 V QPx activated; V(QPx) = VBO...VBO + 6 V NEXC = 0 (see Fig. 9) NEXC = 0 (see Fig. 9) Push-pull configuration, QPx activation delay after QNx deactivation (see Fig. 9) Permanent overload (see Fig. 6) -100 -40 0 -520 -540 1.5 1.2 0 0 100 40 -170 1 -300 3.5 2.8 µA µA µA V/µs mA mA mA µs µs 207 208 209 210 211 212 SR() Imax() Ir() Iexc() texc tdead Slew Rate (switch off → on) Maximum Current in QP1, QP2 Reverse Current in QP1, QP2 Excitation Current Excitation Time Dead Time Short-Circuit/Overload Monitor 301 302 303 304 305 toldly tolcl tdscr tdnscrmax tdnscrmin Time to Overload Message (NOVL 1 → 0, outputs tri-state) 126 35 70 160 50 213 80 90 40 151 µs ms µs µs µs Time to Overload Message Reset No overload (see Fig. 6) (NOVL 0 → 1, outputs active) Time to Communication Request SPI mode, ENSCR = 1, acknowledge QCFGx(1:0) = 01/10/11 Maximum Time for no Communication Request acknowledge Minimum Time for no Communication Request acknowledge Turn-On Threshold VBO Turn-Off Threshold VBO Hysteresis Time to Undervoltage Message (NUVD 1 → 0, switch tri-state) Time to Undervoltage Message Reset (NUVD 0 → 1, switch active) Overtemperature Shutdown (NOVL 1 → 0, switch tri-state) Overtemperature Shutdown Reset Delay (NOVL 0 → 1, switch active) Input Threshold Voltage hi at IN1/TX, IN2/MOSI, OEN, SCLK, NCS Input Threshold Voltage lo at IN1/TX, IN2/MOSI, OEN, SCLK, NCS Referenced to GND Decreasing voltage VBO VBOhys = VBOon − VBOoff Permanent undervoltage at VBR, VCC or VCC3 No undervoltage at VBR, VCC and VCC3 (see Fig. 6) VBO Voltage Monitor 401 402 403 404 405 VBOon VBOoff VBOhys tuvdly tuvcl 8 7.3 200 25 35 50 500 120 80 9 8.5 V V mV µs ms Temperature Monitor 501 502 Toff ton Increasing temperature Tj Temperature Tj < Toff 130 35 50 165 80 °C ms Inputs IN1/TX, IN2/MOSI, INV1/ENSPI, QCFG1/NCS, QCFG2/SCLK, OEN 601 Vt()hi 2 V 602 Vt()lo 0.8 V iC-GF TRANSCEIVER Rev C1, Page 9/26 ELECTRICAL CHARACTERISTICS Operating Conditions: VBO = 9...30 V (referenced to VN), Tj = -40...125 °C, RSET = 6.8 kΩ ±1%, unless otherwise stated Item No. 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 Symbol Vt()hys Ipd() Ipd() Ipd(OEN) Vahi() Vahi()hys Valo() Valo()hys Voc() Ri() tsup() ttrig() tsup() ttrig() tpio Parameter Conditions Min. Hysteresis at IN1/TX, IN2/MOSI, Vt()hys = Vt()hi − Vt()lo OEN, SCLK, NCS Pull-Down Current at IN1/TX, IN2/MOSI Pull-Down Current at OEN Input Threshold hi at QCFG1, QCFG2, INV1 Hysteresis hi at QCFG1, QCFG2, INV1 Input Threshold lo at QCFG1, QCFG2, INV1 Hysteresis lo at QCFG1, QCFG2, INV1 Open Circuit Voltage at QCFG1, QCFG2, INV1 Internal Resistance at QCFG1, QCFG2, INV1 Referenced to VCC3 Referenced to GND V() > 0.4 V 200 10 10 1 52 3 24 3 42 40 40 46.5 85 85 29 64 Typ. 280 168 40 6 69 7 34 7 51 190 190 2.5 6 5 12 2.4 10 Max. mV µA µA µA %VCC3 %VCC3 %VCC3 %VCC3 %VCC3 kΩ kΩ µs µs µs µs µs Unit Pull-Down Current at NCS, SCLK SPI mode, V() > 0.4 V V(OEN) > 0.4 V Permissible Spurious Pulse No activity triggered, DEFAULT mode or SPI Width at IN1/TX, IN2, INV1/ESPI mode with FCFG(1:0) = 10 Required Pulse Width at IN1/TX, Activity triggered, DEFAULT mode or SPI mode IN2, INV1/ESPI with FCFG(1:0) = 10 Permissible Spurious Pulse Width at QCFG1, QCFG2, OEN No activity triggered, DEFAULT mode or SPI mode with FCFG(1:0) = 10 Required Pulse Width at QCFG1, Activity triggered, DEFAULT mode or SPI mode QCFG2, OEN with FCFG(1:0) = 10 Propagation Delay IN1 → QP1, QN1 IN2 → QP2, QN2 Saturation Voltage lo at NOVL, NUVD Saturation Voltage lo at NDIAG INV1 = low or high, DEFAULT mode or SPI mode with FCFG(1:0) = 10 Error Output NOVL/NDIAG, NUVD/MISO 701 702 703 704 705 706 707 708 709 710 711 712 801 802 803 804 805 806 Vs()lo Vs()lo Isc()lo Isc()lo Ilk() Ilk() Vs()hi Vs()lo Isc()hi Isc()lo tr(MISO) tf(MISO) DEFAULT mode, I() = 1.0 mA SPI mode, I() = 1.0 mA 1.2 1.2 -10 -10 0.4 0.4 25 25 10 10 0.4 0.4 -40 90 22 16 59 44 10.5 8.3 1 -300 -40 66 50 11.3 9 74 56 12 10.5 V V mA mA µA µA V V mA mA ns ns %VBR %VBR V V V µA Short Circuit Current lo in NOVL, DEFAULT mode, V() = 0.4 V...VCC NUVD Short Circuit Current lo in NDIAG SPI mode, V() = 0.4 V...VCC Leakage Current in NOVL, NUVD DEFAULT mode, V() = 0 V...VCC, no error Leakage Current in NDIAG SPI mode, V() = 0 V...VCC, no error Saturation Voltage high at MISO SPI mode, I(MISO) = -2 mA, Vs(MISO)hi = VCC3 − V(MISO) Saturation Voltage low at MISO Short Circuit current hi in MISO Short Circuit current lo in MISO Rise Time Fall Time SPI mode, I(MISO) = 2 mA SPI mode, V(MISO) = 0...VCC3 − 0.4 V SPI mode, V(MISO) = 0.4 V...VCC3 SPI mode, Cl(MISO) = 30 pF, 0 → 90%VCC3 SPI mode, 100 → 10%VCC3 VBR < 18 V VBR < 18 V VBR > 18 V VBR > 18 V Vt(CFI)hys = Vt(CFI)hi − Vt(CFI)lo DEFAULT mode: CFP = hi, V(CFI) = 0...VBR − 3 V SPI mode: POL = 1, ENPUD = 1 Feedback Channel CFI to CFO/RX Vt1(CFI)hi Input Threshold 1 hi at CFI Vt1(CFI)lo Input Threshold 1 lo at CFI Vt2(CFI)hi Input Threshold 2 hi at CFI Vt2(CFI)lo Input Threshold 2 lo at CFI Vt()hys Ipu(CFI) Hysteresis at CFI Pull-Up Current at CFI iC-GF TRANSCEIVER Rev C1, Page 10/26 ELECTRICAL CHARACTERISTICS Operating Conditions: VBO = 9...30 V (referenced to VN), Tj = -40...125 °C, RSET = 6.8 kΩ ±1%, unless otherwise stated Item No. 807 808 809 810 811 812 813 814 815 816 817 818 819 820 Symbol Ipd(CFI) tpcf Vs()lo Isc()lo Ilk() Vt(CFP)hi Vt(CFP)lo Parameter Pull-Down Current at CFI Propagation Delay CFI → CFO/RX Short Circuit Current lo in CFO/RX Leakage Current at CFO/RX Input Threshold Voltage hi at CFP Input Threshold Voltage lo at CFP Vt(CFP)hys = Vt(CFP)hi − Vt(CFP)lo V(CFP) = 0.4 V...Vt(CFP)lo V(CFP) > Vt(CFP)hi No activity triggered, DEFAULT mode or SPI mode with FCFI(1:0) = 01 Activity triggered, DEFAULT mode or SPI mode with FCFI(1:0) = 01 No activity triggered Activity triggered V(CFI) = 3 V...VBR, OEN = lo; DEFAULT mode: CFP = lo SPI mode: POL = 0, ENPUD = 1 SPI mode, ENOD = 0, I(RX) = -2 mA, Vs(RX)hi = VCC3 − V(RX) SPI mode, ENOD = 0, I(RX) = 2 mA SPI mode, ENOD = 0, V(RX) = 0...VCC3 − 0.4 V SPI mode, ENOD = 0, V(RX) = 0.4 V...VCC3 SPI mode, ENOD = 0, CL(RX) = 30 pF, 0 → 90%VCC3 SPI mode, ENOD = 0, CL(RX) = 30 pF, 100 → 10%VCC3 LVH = 22 µH, Ri(LVH) < 1.1 Ω, CVH = 1 µF, I(VH) = 0...50 mA R = 170 Ω, I(VH) = 0...10 mA 6.3 6.3 -200 Va(VH) > VHn I(VHL) = -50 mA I(VHL) = -150 mA Vf(VHL) = V(GND) − V(VHL); I(VHL) = -50 mA I(VHL) = -150 mA VHL = lo, V(VHL) = V(VH) -20 70 6.5 7.3 0.5 1.5 0.6 1.7 8.4 1.1 3.0 1.5 2.9 20 6.7 -40 90 22 22 12 20 6 5 Pull-Down Current at CFP Permissible Spurious Pulse Width at CFI Required Pulse Width at CFI 0.8 200 30 10 280 168 40 2.5 Conditions Min. DEFAULT mode: CFP = lo, V(CFI) = 3 V...VBR SPI mode: POL = 0, ENPUD = 1 V(CFO/RX) = 10 ↔ 90% 40 2.4 Typ. Max. 300 10 0.4 1.2 -10 25 10 2 µA µs V mA µA V V mV µA µA µs µs µs µs µA Unit Saturation Voltage lo at CFO/RX Open collector mode, I(CFO/RX) = 1.0 mA Open collector mode, V(CFO/RX) = 0.4 V...VCC Open collector mode, V(CFO/RX) = 0 V...VCC, CFO/RX = off Vt(CFP)hys Hysteresis at CFP Ipd(CFP) tsup(CFI) ttrig(CFI) tsup(CFP) Permissible Spurious Pulse Width at CFP ttrig(CFP) Ipd(CFI)+ llk(QPx) Vs(RX)hi Vs(RX)lo Isc(RX)hi Isc(RX)lo tr(RX) tf(RX) Required Pulse Width at CFP Pull-Down Current at CFI plus leakage current at QPx Saturation Voltage high at RX Saturation Voltage low at RX Short Circuit current hi in RX Short Circuit current lo in RX Rise Time at RX Fall Time at RX 821 822 823 824 825 826 0.4 0.4 V V mA mA ns ns Step Down Converter VHL, VH 901 902 903 904 906 907 VHn VHnr Ia(VHL) Va(VH) Vs(VHL) Vf(VHL) Nominal Voltage at VH Nominal Voltage at VH, LVH replaced by a resistor max. DC Cut-Off Current in VHL Cut-Off Voltage at VH Saturation Voltage at VHL vs. VBR Saturation Voltage at VHL vs. GND Leakage Current at VHL 7.4 8.4 V V mA V V V V V µA % 908 909 Ilk(VHL) η VH Efficiency of VH switching regula- I(VH) = 50 mA, Ri(LVH) < 1.1 Ω, tor V(VBR) = 12...30 V iC-GF TRANSCEIVER Rev C1, Page 11/26 ELECTRICAL CHARACTERISTICS Operating Conditions: VBO = 9...30 V (referenced to VN), Tj = -40...125 °C, RSET = 6.8 kΩ ±1%, unless otherwise stated Item No. A01 A02 A03 A04 A05 A06 B01 B02 B03 B04 B05 B06 Symbol Parameter Conditions Min. VCCn CVCC RiCVCC VCCon VCCoff VCChys VCC3n CVCC3 RiCVCC3 VCC3on VCC3off VCC3hys Nominal Voltage at VCC Required Capacitor at VCC vs. GND Maximum Permissible Internal Resisitance of capacitor at VCC VCC Monitor Threshold hi VCC Monitor Threshold lo Hysteresis Nominal Voltage at VCC3 Required Capacitor at VCC3 vs. GND Maximum Permissible Internal Resisitance of capacitor at VCC3 VCC3 Monitor Threshold hi VCC3 Monitor Threshold lo Hysteresis Decreasing Voltage at VCC3 VCC3hys = VCC3on − VCC3off 89 80 50 0.88 0.571 1.5 1.53 1.12 -0.55 1.24 -0.4 800 200 1.5 1.35 2.5 2.43 1.29 -0.28 Decreasing Voltage at VCC VCChys = VCCon − VCCoff I(VCC3) = -50...0 mA, VH = VHn 89 80 50 3.1 150 1 98 90 500 3.3 3.5 I(VCC) = -50...0 mA, VH = VHn 4.75 150 1 98 90 Typ. 5 Max. 5.25 V nF Ω %VCCn %VCCn mV V nF Ω % VCC3n % VCC3n mV MHz µs MHz MHz V mA Unit Series Regulator VCC Series Regulator VCC3 Oscillator C01 fosss C02 Tosss C03 fos Spread Spectrum Oscillator Fre- Average value from 64 clock cycles quency Single Clock Cycle Periode (spread spectrum oscillator) Fixed Oscillator Frequency Tj = 27 °C Reference and Bias D01 V(ISET) D02 Isc(ISET) D03 rIbeg Voltage at ISET Short Circuit Current in ISET Transmission Ratio for driver output current limitation Tj = 27 °C V(ISET) = 0 V, Tj = 27 °C Imax(QP1) = Imax(QP2) = Imax(QN1) = Imax(QN2) = I(ISET) ∗ rIbeg, RSET = 5.1...20 kΩ iC-GF TRANSCEIVER Rev C1, Page 12/26 OPERATING REQUIREMENTS: SPI Interface Operating Conditions: VBO = 9...30 V (referenced to VN), Tj = -40...125 °C Item No. Symbol Parameter Setup Time: NCS hi → lo before SCLK lo → hi Setup Time: MOSI stable before SCLK lo → hi Hold Time: MOSI stable after SCLK lo → hi Signal Duration SCLK hi Signal Duration SCLK lo Hold Time: NCS lo after SCLK lo → hi Signal Duration NCS hi Propagation Delay: MISO stable after SCLK hi → lo Propagation Delay: MISO high impedance after NCS lo → hi SPI Frequency Conditions Min. 15 20 0 30 30 0 0 0 0 90 25 Max. ns ns ns ns ns ns ns ns ns Unit I001 tsCCL I002 tsDCL I003 thDCL I004 tCLh I005 tCLI I006 thCLC I007 tCSh I008 tpCLD I009 tpCSD I010 f(SPI) 5 MHz tCSh NCS(=QCFG1) tsCCL SCLK (= QCFG2) tCLh tsDCL thDCL tpCLl thCLC MOSI (= IN2) MSB in tristate LSB in MISO (= NUVD) tCSh NCS(=QCFG1) tpCLh tpCLl SCLK (= QCFG2) thCLC MOSI (= IN2) don’t care tpCLD MISO (= NUVD) MSB out tpCLD LSB out tpCSD Figure 1: SPI write cycle (top) and read cycle (bottom) iC-GF TRANSCEIVER Rev C1, Page 13/26 DESCRIPTION OF FUNCTIONS iC-GF has two independent switching channels which enables digital sensors to drive peripheral elements. They are designed to cope with high driver currents. The switches are reverse-polarity protected, feature a free-wheeling circuit for inductive loads and a saturation voltage minimising system. Reverse polarity protection The pins VBO, QPx, QNx, VN and CFI on the line side of the chip are reverse polarity protected. As far as the maximum voltage ratings are not exceeded, no possible supply combination at the line side pins can damage the chip. I(Qx) responds to the free-wheeling circuit activated. The switching channels are designed so that QNx can only sink current and QPx can only source current (no reverse current). Free-wheeling circuit for inductive loads The free-wheeling circuit is always present and does not depend on the current output status. It is activated by voltages higher than 36 V at QNx referenced to VN or lower than -36 V at QPx referenced to VBO. In that case the correspondent channel will switch on without current limitation (see Figure 4). I(Qx) 36V Ipeak Isc()lo VN 4V A B 36V VBO C V(Qx) VBO-36V VN VBO VAR 36V VN+36V V(Qx) Figure 4: Free-wheeling characteristic Dead time In order to avoid current flow between high- and lowside switch in push-pull configuration, a dead time tdead is implemented as shown in Figure 5 (cf. Electrical Characteristics Nos. 112 and 212). ttrig tdead Figure 2: QNx characteristic when active I(Qx) VBO-36V C Isc()hi Ipeak 36V VN B A VBO V(Qx) INx QNx Figure 3: QPx characteristic when active Output characteristics of Q1, Q2 The switching channels are current limited to a value set by the external resistor RSET (cf. Electrical Characteristics No. D03). If pin ISET is short circuited to GND, the current limitation will be set to a maximum value (cf. Electrical Characteristics Nos. 108, 208). The current limitation works only for voltages higher than 4 V at QNx resp. lower than VBO − 4 V at QPx. For smaller output voltages the current limitation is reduced in order to minimise the saturation voltages without increasing the power dissipation. Figures 2 and 3 show the characteristic of the switching channels when activated. Region "A" is the saturation range, where the current limitation is not fully active yet and region "B" is the current limited range. Region "C" cor- QPx Figure 5: Propagation delay Overload detection To protect the device against excessive power dissipation due to high currents the switches are clocked if an overload occurs. If a short circuit is detected, i.e. if the voltage at the switch output overshoots or undershoots Overload Detection Threshold off (cf. Electrical Characteristics Nos. 104 and 204), the switches are shut down for a typical 50 ms (cf. Electrical Characteristics No. 302) and the current flow thus interrupted. The level of power dissipation depends on the current and the time during which this current flows. A current which fails to trigger the overload detection iC-GF TRANSCEIVER Rev C1, Page 14/26 is not critical; high current can also be tolerated for a short period and with low repeat rates. This is particularly important when switching capacitive loads (charge/discharge currents). VBR NUVD NOVL OEN VCC and VCC3. Both undervoltage detectors are filtered against spurious events smaller than 25 µs (cf. Electrical Characteristics No. 404). In case of a valid undervoltage event (longer than 25 µs) both QPx and QNx are unconditionally brought to high impedance for at least 35 ms (cf. Electrical Characteristics No. 405) resp. as long as the duration of the undervoltage situation. Digital filtering at inputs To obtain high noise immunity the pins QCFGx, INV1/ESPI, IN1/TX, IN2, OEN, CFI and CFP have a digital input filter. Figure 5 shows this filter time ttrig for INx (cf. Electrical Characteristics Nos. 613 to 616 and 816 to 819). Feedback channel CFI–CFO iC-GF implements a feedback channel which permits a communication from the line side to the sensor side. High voltage digital signals at CFI are converted into low voltage (open-collector) levels at CFO. Spread spectrum oscillator To reduce the electromagnetic interference generated by the switching converter (pin VHL) a spread spectrum oscillator has been introduced. Here the switch is not triggered by a fixed frequency but by a varying 32 step frequency mix. Generated interference is then distributed across the frequency spectrum with its amplitude reduced at the same time. Configuration mode Leaving pin INV1 unconnected (cf. Table 1) selects SPI mode for configuration. All functions implemented in DEFAULT mode are also available in SPI mode plus some additional functions, available in SPI mode only. Mode Select INV1 MODE L DEFAULT H DEFAULT Z SPI Table 1: Operating mode configuration Qyx tuvcl toldly toldcl Figure 6: Permanent short circuit VBR NUVD NOVL OEN INx Qyx Off Integrator tuvcl toldcl Figure 7: Overload So that this is possible a shared back-end integrator follows the switches for the purpose of overload detection. This integrator is an 8-bit counter which is updated together with the oscillator clock. If an overload is detected on one channel the counter is incremented by 1; an overload on both channels increments the counter by 2. If no overload is apparent the counter is decremented by 1 every 10 clock pulses. A maximum duty cycle – without deactivation of the switches – of 1:10 results if one channel is overloaded. Only when this ratio is exceeded the counter can reach its maximum value, generating an error message at NOVL and deactivating the switches. Undervoltage detection iC-GF features two separate undervoltage detectors: voltage monitoring at VBO and voltage monitoring at iC-GF TRANSCEIVER Rev C1, Page 15/26 DEFAULT MODE Enabling the switches Setting pin OEN to low unconditionally disables all four output switches. Other functions of the chip (like the DC/DC converter or the feedback channel) remain enabled. Configuring the switches The functionality of the switches is determined by the pins QCFG1 and QCFG2. A voltage at QCFGx which is lower than Va()lo (cf. Figure 8) deactivates the relevant high-side switches; with a voltage higher than Va()hi the relevant low-side switches are deactivated. Both high-side and low-side switches are activated, when the pin is left open. Valo()hys CHANNEL 2 IN2 QCFG2 OEN QN2 QP2 X X L off off L Z H on off H Z H off on L H H off off H H H off on L L H off off H L H on off Table 3: Function table Channel 2 (INV1 = H, L) Tables 2 and 3 show the switch configuration for both channels, with respect to the input pins. Feedback channel CFI–CFO configuration The feedback channel CFI–CFO polarity can be configured via pin CFP (see table 4). This pin also sets the pull-up/down current at pin CFI. QPx active Vahi()hys QNx active Va()lo Va()hi V(QCFGx) Figure 8: Levels at QCFG1/QCFG2 for switch configuration CHANNEL 1 IN1 QCFG1 INV1 OEN QN1 QP1 X X X L off off L Z L H on off H Z L H off on L Z H H off on H Z H H on off L H L H off off H H L H off on L H H H off on H H H H off off L L L H off off H L L H on off L L H H on off H L H H off off Table 2: Function table Channel 1 FEEDBACK CHANNEL CFI CFP CFO PULL at CFI pin H H Z UP H L L DOWN L H L UP L L Z DOWN Table 4: Function table Feedback Channel Undervoltage signalling Undervoltage at VBO, VCC or VCC3 is signalled at pin NUVD. A valid undervoltage event is signalled at NUVD for at least 35 ms (cf. Electrical Characteristics No. 405 ) resp. as long as the duration of the undervoltage situation. iC-GF TRANSCEIVER Rev C1, Page 16/26 SPI MODE In SPI mode the iC-GF is configured and operated using the on-chip registers. Additionally there is a status register, where chip events are logged. If any of the status bits is set to high, the low-active open-drain pin NDIAG is activated, e.g. for interrupt generation for micro controllers. The SPI mode is activated when the pin INV1 is left open and the filter time (cf. Electrical Characteristic No. 614) has elapsed. This enables communication with the iC-GF via an SPI protocol using pins MISO, MOSI, SCLK and NCS. Switch enable There are three different ways of enabling/disabling the output switches in SPI mode: pin mode, register mode and mixed mode. In pin mode (TXEN = "11") or register mode (TXEN = "00") the OEN pin acts as a common enable for both switching channels. The OEN register on the other hand enables or disables each switch separately. Switch enable Qx1 OEN pin TXEN(1:0) OEN(1:0) Qx2 0 00/11 XX disabled disabled 1 00/11 01 disabled enabled 1 00/11 10 enabled disabled 1 XX 11 enabled enabled X XX 00 disabled disabled 0 01 0X disabled disabled 0 01 1X enabled disabled 0 10 X0 disabled disabled 0 10 X1 disabled enabled 1 01 01 disabled enabled 1 01 10 enabled disabled 1 10 01 disabled enabled 1 10 10 enabled disabled Table 5: Switch enable, QCFGx = "00" In mixed mode (TXEN = "01" or "10") the OEN pin acts as an enable only for the channel for which the TXEN bit is set to "1". The OEN register enables or disables each switching channel separately. Table 5 summarises these configurations. Switch control Each switch can be operated by the OUTD register or the input pin TX. The register TXEN selects register OUTD or the pin TX for switch control. A "0" in the register TXEN sets the corresponding switch to be controlled by the relevant bit of the register OUTD. TXEN(1:0) x0 x1 0x 1x Adr 0x00; Bit (5:4) Channel 1 controlled by OUTD(0) Channel 1 controlled by TX Channel 2 controlled by OUTD(1) Channel 2 controlled by TX R/W 01 Table 6: Transmit enable OUTD(1:0) x0 x1 0x 1x Adr 0x00; Bit (1:0) R/W 00 Channel 1: push-pull low resp. high/low-side off Channel 1: push-pull high resp. high/low-side on Channel 2: push-pull low resp. high/low-side off Channel 2: push-pull high resp. high/low-side on Table 7: Output data with INV = "00" Switch configuration The configuration of the switches is determined by the registers QCFG1 and QCFG2; either as high-side, lowside, push-pull or high impedance (disabled). QCFG1(1:0) 00 01 10 11 Adr 0x01; Bit (5:4) disabled low-side switch high-side switch push-pull R/W 11 Table 8: Switch configuration Channel 1 QCFG2(1:0) 00 01 10 11 Adr 0x01; Bit (7:6) disabled low-side switch high-side switch push-pull R/W 11 Table 9: Switch configuration Channel 2 INV inverts the corresponding switching channel. INV(1:0) x0 x1 0x 1x Adr 0x03; Bit (5:4) Switching channel 1 not inverted Switching channel 1 inverted Switching channel 2 not inverted Switching channel 2 inverted R/W 00 Table 10: Invert Ouput Table 11 summarises the above configurations for channel 1. iC-GF TRANSCEIVER Rev C1, Page 17/26 CHANNEL 1 TXEN(0) QCFG1(1:0) TX OUTD(0) INV(0) QN1 QP1 0 01 x 0 0 off off 0 01 x 0 1 on off 0 01 x 1 0 on off 0 01 x 1 1 off off 0 10 x 0 0 off off 0 10 x 0 1 off on 0 10 x 1 0 off on 0 10 x 1 1 off off 0 11 x 0 0 on off 0 11 x 0 1 off on 0 11 x 1 0 off on 0 11 x 1 1 on off 1 01 L x 0 off off 1 01 L x 1 on off 1 01 H x 0 on off 1 01 H x 1 off off 1 10 L x 0 off off 1 10 L x 1 off on 1 10 H x 0 off on 1 10 H x 1 off off 1 11 L x 0 on off 1 11 L x 1 off on 1 11 H x 0 off on 1 11 H x 1 on off Table 11: Function table for channel 1 in SPI mode FCFI(1:0) 00 01 10 11 Adr 0x02; Bit (1:0) Filter disabled 4 µs filtering (8 CLKs) 7 µs filtering (14 CLKs) 16 µs filtering (32 CLKs) R/W 01 ister FCFG for pins TX and OEN and register FCFI for pin CFI. Figure 9 shows the filter time ttrig for TX (cf. Electrical Characteristics Nos. 613 to 616 and 816 to 819). Excitation current Using register NEXC an additional current Iexc can be activated for driving capacitive loads. Figure 9 shows the characteristic of one channel with the excitation current enabled (cf. Electrical Characteristics Nos. 110, 111, 210 and 211). NEXC(1:0) x0 x1 0x 1x Adr 0x03; Bit (1:0) Excitation for channel 1 enabled Excitation for channel 1 disabled Excitation for channel 2 enabled Excitation for channel 2 disabled R/W 11 Table 12: CFI filter configuration FCFG(1:0) 00 01 10 11 Adr 0x02; Bit (3:2) Filter disabled TX: 1.5 µs filtering (3 CLKs) OEN: 3 µs filtering (6 CLKs) TX: 4 µs filtering (8 CLKs) OEN: 8 µs filtering (16 CLKs) TX: 7.5 µs filtering (15 CLKs) OEN: 15 µs filtering (30 CLKs) R/W 10 Table 13: TX and OEN filter configuration Digital filtering at inputs The digital input filters can be configured with the reg- Table 14: Excitation current configuration iC-GF TRANSCEIVER Rev C1, Page 18/26 ttrig tdead TX required – by means of register bit ENPUD (cf. Table 17). POL 0 1 Adr 0x01; Bit (2) R/W 0 QNx QPx I(QNX) Iexc() CFI hi → RX hi (ENOD = 0) resp. on (ENOD = 1) Pull-down current (ENPUD = 1, INVPUD = 0) CFI hi → RX lo (ENOD = 0) resp. off (ENOD = 1) Pull-up current (ENPUD = 1, INVPUD = 0) Isc() 0 0 Isc() Table 16: Input polarity ENPUD 0 1 texc Adr 0x01; Bit (3) CFI pull-up/down disabled CFI pull-up/down enabled R/W 1 Iexc() I(QPx) Figure 9: Dynamic characteristic Table 17: Enable pull-up/down The state of the CFI pin (high or low) is mapped independent of POL to the register bit IND (see table 18). Changes at CFI can be logged in the status bit CFED (and signalled at pin NDIAG), if the bit ENCFD is set to high. The CFED bit is cleared after read. IND Adr 0x00; Bit (7) Input Signal at CFI is low Input Signal at CFI is high R Feedback channel CFI–RX configuration In SPI mode RX is a standard CMOS output, which can also be configured as an open-drain output, using the register bit ENOD (cf. Table 15). ENOD 0 1 Adr 0x01; Bit (0) Push-pull output Open-drain output R/W 1 0 1 Table 15: RX configuration ENCFD 0 1 Table 18: CFI status Adr 0x02; Bit (7) CFED Disabled CFED Enabled R/W 0 The polarity of the feedback channel CFI–RX can be configured using register bit POL (cf. Table 16). Pin CFP has no function in SPI mode. The POL bit also controls the pull-up/down current at CFI. The INVPUD bit changes the polarity of the pull-up/down current at CFI independent of the other configurations. The pullup/down current can be disconnected completely – if Table 19: Enable edge detection at CFI Table 20 summarizes the behaviour of the feedback channel CFI in SPI mode. Feedback channel CFI CFI POL INVPUD IND RX (ENOD = 0) RX (ENOD = 1) Current at CFI 0 0 0 0 0 off down 0 0 1 1 on down 1 0 1 0 0 1 on up 1 1 0 1 0 off up 0 0 1 0 0 off up 1 0 1 1 1 on up 0 1 1 0 1 on down 1 1 1 1 0 off down Table 20: Function table of feedback channel CFI in SPI mode (ENPUD = 1) Overload detection In SPI mode the counter decrements of the overload detection can be programmed with the register DUTYC(1:0), resulting in different overload duty cycles at the switching channels. The maximum allowed over- iC-GF TRANSCEIVER Rev C1, Page 19/26 load time cannot be changed (cf. Electrical Characteristics No. 301), only the average value (duty cycle). DUTYC(1:0) 00 01 10 11 Adr 0x03; Bit (3:2) Duty cycle of 1:4 Duty cycle of 1:8 Duty cycle of 1:10 Duty cycle of 1:15 R/W 10 would be a contrasting pulse, forcing the selected line to a state different than the current one (short-circuit). Table 21: Overload detection duty cycle Spread spectrum oscillator In SPI mode the spread spectrum operation can be disabled with the register ENRND. ENRND 0 1 Adr 0x02; Bit (4) Spread spectrum disabled Spread spectrum enabled R/W 1 Figure 10: Communication request pulse generation Table 22: Spread spectrum oscillator Pull-down currents In SPI mode the pins NCS and SCLK do only have a pull-down current. Undervoltage signalling Undervoltage at VBO, VCC or VCC3 is signalled in the status register UVD. A valid undervoltage event is signalled for the duration of the undervoltage situation resp. for at least 35 ms (Electrical Characteristics No. 405). Only during this time, the undervoltage event is signalled in the status register UVD. It will also be signalled at pin NDIAG. Any confirmed undervoltage situation at VCC or VCC3 will reset the configuration register which will also be signalled in the status register INITR; this bit is cleared when read. The SPI interface is not affected by any of the undervoltage events and is still operable, provided that the supply level at VCC is high enough. UVD(1:0) 00 01 10 11 Adr 0x04; Bit (7:6) No undervoltage detected Undervoltage at VCC or VCC3 Undervoltage at VBO Undervoltage at VBO and VCC/VCC3 R 00 SCR2 0 1 Adr 0x02; Bit (5) Communication request in channel 1 Communication request in channel 2 R/W 0 Bit ENSCR enables the communication request function. By default, communication requests are detected at channel 1 (Q1 connected to CFI). For detection at channel 2, the bit SCR2 must be set. As shown in Figure 11, a communication request is acknowledged when its duration is inside a defined window (cf. Electrical Characteristics No. 303). The relevant threshold voltages are given in the Electrical Characteristics Nos. 801, 802, 803 and 804. The example in Table 26 shows channel 1 used for communication request. ENSCR 0 1 Adr 0x02; Bit (6) Communication request disabled Communication request enabled R/W 0 Table 24: Enable communication request Table 25: Communication request channel select Table 23: Undervoltage detection Communication requests The communication request function (IO-Link wakeup) allows interrupt signal generation by means of a well defined short-circuit on one of the switching channels. This requires the relevant switching channel (Q1 or Q2) to be connected to the feedback channel input CFI (see Figure 10). The communication request An acknowledged communication request will be logged in the status bit SCR and signalled at pin NDIAG. The communication request is not affected by the output disabling (neither by pin nor register OEN), but is disabled if the configuration in QCFGx is set to "00". iC-GF TRANSCEIVER Rev C1, Page 20/26 V(QX) Vtx(CFI)lo A tdnscr max tdscr(MIN) tdscr(MAX) tdnscr min BCB A T Sensor Communication request SCR OUTD(1:0) QCFG1(1:0) CFI (70...90 µs pulse) x0 11 High x1 11 Low x0 10 High x1 10 Low x0 01 Low x1 01 High Table 26: Communication request at channel 1, OEN = 1, SCR2 = 0, ENSCR = 1, INVx = 0 V(NDIAG) Figure 11: Communication request timing: A: Communication request ignored B: Uncertainty range C: Communication request acknowledged SPI INTERFACE The SPI interface uses the pins NCS, SCLK, MISO and MOSI. The protocol is shown in Figures 12 and 13. A communication frame consists of one addressing byte and one data byte. Bit 7 of the address byte is used for selecting a read (set to 1) or a write (set to 0) operation. The other bits are used for register addressing. It is possible to transmit several bytes consecutively, NCS SCLK MOSI MISO ADR(6:0) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X if the NCS signal is not reset and SCLK keeps clocking. The address is internally incremented after each transmitted byte. Once the address has reaches the last register (0x04), the following 3 increments will read and write dummy data. After that addressing will start again at 0x00. The required timing for the SPI signals during a communication is shown in Figure 1. Polarity 0, Phase 0 High Impedance Figure 12: SPI write data NCS SCLK MOSI MISO High Impedance ADDRESS(6:0) Polarity 0, Phase 0 don't care n n-1 n-2 n-3 n-4 n-5 5 4 3 2 1 0 X High Impedance Figure 13: SPI read data iC-GF TRANSCEIVER Rev C1, Page 21/26 REGISTERS Configuration overview The configuration bytes are readable and writeable, with the exception of the IND bit (adr 0x00). The diagnostic register is read only. After reading, the bits CFED, INITRAM and WUD are reset. The bits OVT, OVL(1:0) and UVD(1:0) are set to high during the respective error condition and stay high for least 35 ms after the condition has been removed (Electrical Characteristics Nos. 302, 405). Tables 27, 28 and 29 show an overview of the registers, accessible in SPI mode. Register Address Bits Default Description 0x03 3:2 10 Duty cycle configuration for overload detection DUTY ENCFD 0x02 7 0 Enable logging of changes at CFI ENOD 0x01 0 1 Enable Open-Drain output at RX pin ENPUD 0x01 3 1 Enable pull-up/down current at CFI pin ENRND 0x02 4 1 Enable spread spectrum oscillator ENSCR 0x02 6 0 Enable communication requests FCFG 0x02 3:2 10 Filter configuration for TX and OEN FCFI 0x02 1:0 01 Filter configuration for CFI IND 0x00 7 R/O CFI status (independent of POL), r/o INV 0x03 5:4 00 Switching channel inversion INVPUD 0x01 1 0 Invert pull-up/down configuration at CFI NEXC 0x03 1:0 11 Enable excitation current for capacitive loads OEN 0x00 3:2 11 Switching channel enable OUTD 0x00 1:0 00 Output data for the switching channels POL 0x01 2 0 Polarity inversion at CFI QCFG1 0x01 5:4 11 Switching channel 1 configuration QCFG2 0x01 7:6 11 Switching channel 2 configuration TXEN 0x00 5:4 01 Channel control select (register or pin) SCR2 0x02 5 0 Communication request channel selection Table 27: Overview of the configuration registers Register Address Bits Description INITR 0x04 0 Register reset SCR 0x04 1 Communication request acknowledged CFED 0x04 2 Change detection at CFI OVT 0x04 3 Overtemperature OVL(0) 0x04 4 Overload Channel 1 OVL(1) 0x04 5 Overload Channel 2 UVD(0) 0x04 6 Undervoltage VCC resp. VCC3 0x04 7 Undervoltage VBO UVD(1) Table 28: Overview of the diagnostic register (read only) OVERVIEW Adr 0x00 0x01 0x02 0x03 0x04 UVD(1:0) Bit 7 IND Bit 6 Bit 5 Bit 4 TXEN(1:0) Bit 3 OEN(1:0) ENPUD Bit 2 POL Bit 1 INVPUD Bit 0 OUTD(1:0) ENOD FCFI(1:0) NEXC(1:0) QCFG2(1:0) ENCFD ENSCR QCFG1(1:0) SCR2 ENRND INV(1:0) OVL(1:0) FCFG(1:0) DUTY(1:0) OVT CFED SCR INITR Table 29: Register layout iC-GF TRANSCEIVER Rev C1, Page 22/26 APPLICATION NOTES Setup for medium and small currents at VCC/VCC3 For medium output currents at VCC/VCC3 the inductor of the switching converter may as well be replaced by a resistor (see Fig. 14), resulting though in a considerably less efficiency (power dissipation!) and an elevated noise level at VH and thus at VCC/VCC3. CVH 1uF ..10mA VCC3 VCC VH VHR 170 VHL CVBR 1uF VBR VCC VCC3 CVCC 1uF CVCC3 1uF VCC3 NUVD/MISO NOVL/NDIAG Status Output VCC VBR Undervoltage 1 VCC3 Toff Overload RSET 8.2K VCC3 CEM1 100pF ISET Channel 1 QCFG1/NCS INV1/ESPI IN1/TX Input Interface VCC3 VCC3 Lin. Regulator DC/DC Converter VBO Bias VBO < VN CVBO 100nF VBO SENSOR CEM2 100pF Figure 14: LVH replaced by a resistor For small output currents the switching converter can be bypassed completely (see Fig. 15). CVBR 1uF ..50mA VCC3 VCC VH VHL Channel 2 QCFG2/SCLK IN2/MOSI OEN Figure 16: SPI Mode in extremely noisy environments Output protection Figures 17 to 20 show some common configurations with different wire counts and the respective additional protective circuitry against transients on the transmission line; suggested values as follows: CQx: CCFI: CVBO: TVSx: 1 nF 1 nF 100 nF TVS diodes (eg. Vishay GSOT36C) Lin. Regulator DC/DC Converter VBO Bias VBO < VN CVBO 100nF VBO Figure 15: Switching converter bypassed In extremely noisy environments, additional blocking capacitors (CEM1, CEM2) can be used to ensure SPI mode (see Fig. 16). iC-GF TRANSCEIVER Rev C1, Page 23/26 CVBR 1μF VBR CVBR 1μF VBR VBO VBO < VN CVBO 100nF HS1 TVS1 VBO VBO < VN VBO CVBO TVS1 100nF VBO QP1 Q1 QN1 TVS2 CQ1 1nF HS1 QP1 Q1 QN1 CQ1 1nF TVS2 LS1 Line Output HS2 LS1 LINE QP2 Line Output HS2 LINE QP2 LS2 QN2 LS2 QN2 TVS3 CFI CFI TVS3 VN VN CFI CCFI 1nF VN TVS4 VN iC-GF iC-GF Figure 17: Three-wire interface with feedback (parallel operated channels optional) Figure 19: Four-wire interface with separate feedback (parallel operated channels optional) CVBR 1μF VBR CVBR 1μF VBR VBO VBO < VN CVBO 100nF TVS1 TVS1 VBO VBO VBO < VN CVBO 100nF VBO HS1 QP1 Q1 QN1 CQ1 1nF TVS2 QN1 CQ1 1nF HS1 QP1 TVS2 Q1 LS1 Line Output HS2 LINE Line Output QP2 Q2 QN2 CQ2 1nF TVS3 LS1 LINE HS2 TVS3 QP2 Q2 QN2 CQ2 1nF LS2 LS2 CFI TVS5 CFI CFI CCFI 1nF VN TVS4 VN iC-GF TVS4 VN VN iC-GF Figure 18: Four-wire interface with feedback at channel 2 Figure 20: Five-wire interface iC-GF DEMO BOARD J1 4 JP3 J1 7 IN2_MOSI J1 1 QCFG2_SCLK J1 8 QCFG1_NCS J1 9 NUVD_MISO J1 2 J1 10 VCC CVCC 1μF VCC TRANSCEIVER VCC3 CVCC3 1μF VH 1μF 22μF LVH VHL U1 iC-GF 23 22 VCC3 VCC VCC3 9 NUVD 8 NOVL Toff VBO 18 Bias CVBO 100nF QP1 QP1 17 Control Logic LS1 Line Output Configuration Registers QP2 13 QN2 14 SPI Interface LS2 CQN2 470pF 10 CFO VBR CFI CFI 12 CCFI 1nF CQP2 470pF QN2 PJSD36W D5 HS2 QP2 QN1 16 CQN1 470pF CQP1 470pF QN1 PJSD36W D6 VBO < VN VBO PJSD36W D8 Overload 1 ISET VCC3 4 QCFG1 VCC3 2 INV1 3 IN1 Channel 1 HS1 Lin. Regulator DC/DC Converter Status Output Undervoltage VCC VBR 21 VH 20 VHL 19 VBR CVBR 1μF CVH VCC3 D1 RD D2 RD R1 1.5kΩ R2 1.5kΩ JP1 JP2 NUVD NUVD_MISO NOVL NOVVL_NDIAG 1 VBO RSET ISET CEM1 100pF 8.2kΩ QCFG1 QCFG1_NCS QP1 PJSD36W D7 JP_Q1 QN1 3 INV1 INV1_ESPI 2 JP4 1 Input Interface VCC3 5 QCFG2 6 IN2 7 OEN Channel 2 CEM2 100pF IN1 IN1_TX iC-GF comes with a demo board for test purposes. Figures 21 and 22 show both the schematic and the component side of the demo board. QP2 JP_Q2 QN2 PJSD36W D4 CFI Figure 21: Schematic of the demo board =1 VN Feedback Comparator 11 CFP 24 GND SUB EPAD JP5 VN optional Feedback Output QCFG2 QCFG2_SCLK IN2 IN2_MOSI OEN OEN CFO CFO_RX CFP CFP iC-GF VN 15 PJSD36W D3 GND D9 PJSD36W VN Rev C1, Page 24/26 iC-GF TRANSCEIVER Rev C1, Page 25/26 Figure 22: Demo board (component side) iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by email. Copying – even as an excerpt – is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. iC-GF TRANSCEIVER Rev C1, Page 26/26 ORDERING INFORMATION Type iC-GF Evaluation Board Package QFN24 4 mm x 4 mm (RoHS compliant) Order Designation iC-GF QFN24 iC-GF EVAL GF1D For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com Appointed local distributors: http://www.ichaus.com/sales_partners