TW3DEVAL

iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 1/24 FEATURES o o o o o o o o o o o o o o Fully differential 3-channel signal conditioning PGS inputs for differential and single-ended signals Overall gain of -3 to 57 dB, adjustable in steps of 0.08 dB Output referred offset range of ±1.2 V, adjustable in steps of 2 mV Signal bandwidth to 1 MHz and in/out latency below 1 µs Selectable automatic gain and offset control for encoder applications On-chip or off-chip temperature sensing Temperature drift compensation for gain and offset via programmable look-up-tables Short-circuit-proof outputs: 1 Vpp to 100 Ω, 2 Vpp to 1 kΩ I2 C interface to restore device setup from serial EEPROM Bidirectional 1-wire interface for direct RAM and EEPROM access Optical setup link via 1-wire interface operating a photo receiver Single 3.0 V to 5.5 V supply Operating temperature range of -40 to +125 °C APPLICATIONS o Programmable general purpose sensor interface o Optical position sensors o Magnetic position sensors o Incremental position sensors o Linear scales PACKAGES QFN32 BLOCK DIAGRAM Copyright © 2009 iC-Haus http://www.ichaus.com iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 2/24 DESCRIPTION The general purpose sensor signal conditioner iCTW3 provides highly accurate non contact trimming of three independent sine/cosine sensor signals. The differential output signals can be calibrated to 1 Vpp or to 2 Vpp, alternatively. The internal or an external temperature sensor linked to the chip can influence the gain and offset correction by arbitrary temperature-dependent compensation parameters sourced from a look-up table. For encoder applications an automatic gain and offset control compensates sensor offset voltages and stabilizes the output signal level. The direct connection of sine/cosine encoders, MR sensor bridges or photosensor arrays is possible and supported by a selectable input impedance. iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 3/24 PACKAGES PIN CONFIGURATION QFN32 5 mm x 5 mm PIN FUNCTIONS No. Name Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PINZ NINZ TESTEN CLK NZO ZO GNDB VDDB NBO BO GND SCL SDA VDD GNDA n.c. AO NAO VDDA 1W NERR NRST NSTORE* n.c. NINA PINA KELVIN GNDIN VDDIN PINB NINB VC Signal Input Z+ Signal Input ZTest Mode Enable Input External Clock Input Signal Output ZSignal Output Z+ Driver Ground +3...+5.5 V Driver Supply Voltage Signal Output BSignal Output B+ Digital Ground I2C Interface, clock line I2C interface, data line +3...+5.5 V Digital Supply Voltage Driver Ground not connected Signal Output A+ Signal Output A+3...+5.5 V Driver Supply Voltage 1-Wire Interface, bidirectional port Error Message Output, active low External Reset Input, active low Coefficient Store Input, active low not connected Signal Input ASignal Input A+ External Temperature Sensor Input Input Ground +3...+5.5 V Input Supply Voltage Signal Input B+ Signal Input B1.21 V Reference Voltage Output, Reference Voltage Input Thermal Pad 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 TW3 code... ... 9 10 11 12 13 14 15 16 21 20 19 18 17 TP TP** Notes: *) Pin NSTORE should be wired to VDD. **) The Thermal Pad of the QFN package (bottom side) is to be connected to a ground plane on the PCB which must have GND potential. iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 4/24 ABSOLUTE MAXIMUM RATINGS These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item No. Symbol Parameter Conditions Min. Voltage at VDD, VDDA, VDDB, VDDIN referenced to GND, GNDA, GNDB, GNDIN Voltage applied to any other pin Voltage Difference VDDA, VDDB vs. VDD Voltage Difference VDDIN vs. VDD Voltage Difference GNDA, GNDB vs. GND Voltage Difference GNDIN vs. GND ESD Susceptibility Of Signal Outputs: AO, NAO, BO, NBO, ZO, NZO ESD Susceptibility (remaining pins) Junction Temperature Storage Temperature HBM, 100 pF discharged through 1.5 kΩ HBM, 100 pF discharged through 1.5 kΩ -40 -40 referenced to GND -0.3 -0.3 Max. 6.0 VDD + 0.5 0.5 0.5 0.5 0.5 2 2 150 150 V V V V V V kV kV °C °C Unit G001 VDDx() G002 V() G003 V() G004 V() G005 V() G006 V() G007 Vd G008 Vd G009 Tj G010 Ts THERMAL DATA Item No. T01 T02 Symbol Ta Rthja Parameter Operating Ambient Temperature Range Thermal Resistance Chip To Ambient surface mounted to PCB according to JEDEC 51 Conditions Min. -40 40 Typ. Max. 125 °C K/W Unit All voltages are referenced to ground unless otherwise stated. All currents into the device pins are positive; all currents out of the device pins are negative. iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 5/24 ELECTRICAL CHARACTERISTICS Operating conditions: VDD, VDDA, VDDB, VDDIN = 3.0...5.5 V, Tj = -40...125 °C, reference point GND unless otherwise stated Item No. 001 002 003 004 101 102 103 104 105 106 107 108 Symbol Parameter Conditions Min. VDDx I(VDDx) Vc()hi Vc()lo Vin()sig Vin()os Iin() Rpu() fg CMRR PSRR en Permissible Supply Voltage at VDD, VDDA, VDDB, VDDIN Total Supply Current Clamp-Voltage hi at all pins Clamp-Voltage lo at all pins Permissible Input Voltage Range Input Offset Voltage Input Current Input Pull-Up Resistor -3 dB Bandwidth Common Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Noise ENSIGAB = 0, ENSIGZ = 0 ENSIGAB = 1, ENSIGZ = 1 PGA gain of 36 dB fc < 1 MHz fc < 1 kHz fc < 1 MHz fc < 1 kHz f = 1 kHz f = 100 Hz f = 0.1 to 10 Hz -35 2.0 1.2 40 60 40 60 20 n 25 n 2µ 0.08 2 -50 ± 10 1.7 0.9 -50 19 10 224 245 1.10 0 -0.1 1.21 1.35 2.21 1 3.0 2.6 1.5 3.3 0.8 1.0 -3 700 V V µA V V V V V V µA mV 50 150 2.5 VDDx = 3.3 V VDDx = 5.5 V Vc()hi = V() - VDD; I() = 10 mA I() = -10 mA 0.3 -1.2 1.4 ±5 3.0 Typ. Max. 5.5 15 25 1.4 -0.3 VDD 1.2 V ±15 35 3 V mA mA V V V mV nA MΩ MHz dB dB dB dB √ V/√Hz V/√Hz V/ Hz dB mV °C °C V V nA Unit Total Device Analog Signal Inputs PINA, NINA, PINB, NINB, PINZ, NINZ 109 110 201 202 203 204 205 ∆DGAIN ∆DOFFS Tor Tacc Vin()low Iin() T()lo Dynamic Gain Step Width Dynamic Offset Step Width Int. Temperature Sensor Operat- after calibration of ADC; ing Range Device-To-Device Temp. Sensor Variation Temperature Input Voltage Input Current at KELVIN Lo-Temperature ADC Reading, via Register CELSIUS(7:0) Hi-Temperature ADC Reading, via Register CELSIUS(7:0) after calibration of ADC, Tj = -40 °C to 125 °C CELSIUS(7:0) = 10 CELSIUS(7:0) = 245 V(KELVIN) = 0 .. VDD after calibration of ADC; XCELSIUS = 0, internal sensor: Tj = -40 °C XCELSIUS = 1, ext. sensor: V(KELVIN) = 1.7 V after calibration of ADC; XCELSIUS = 0, internal sensor: Tj = 125 °C XCELSIUS = 1, ext. sensor: V(KELVIN) = 0.9 V VEXT = 0; CL = 100 nF, I() = 0 mA Temperature Sensor and Analog Input KELVIN 206 T()hi Reference Voltage Input/Output VC 301 302 303 401 402 403 404 405 406 Vout(VC) Vin(VC) Iin(VC) VDDon VDDoff Vt()hi Vt()lo Ipu() Vpu() Reference Voltage Output Permissible Input Voltage Range VEXT = 1 at VC Input Current at VC Turn-On Threshold (power-on release) VEXT = 1 increasing voltage at VDD Power-On Reset and Input NRST Turn-Off Threshold (power-down decreasing voltage at VDD reset) Input Threshold Voltage hi Input Threshold Voltage lo Input Pull-Up Current Input Pull-Up Voltage VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % V() = 0...VDD - 1 V Vpu() = VDD - V(), I() = -3 µA iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 6/24 ELECTRICAL CHARACTERISTICS Operating conditions: VDD, VDDA, VDDB, VDDIN = 3.0...5.5 V, Tj = -40...125 °C, reference point GND unless otherwise stated Item No. Symbol Parameter Conditions Min. VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % V() = 1 V...VDD I() = 3 µA TEST_CLK = 1, measured at NERR; CLKDIV = 0 (low active) CLKDIV = 1 3 700 2 4 4 1.5 3.3 0.8 1.0 Typ. Max. V V V V µA mV MHz MHz MHz Unit Oscillator CLK, TESTEN 501 Vt()hi Input Threshold Voltage hi 502 503 504 505 Vt()lo Ipd() Vpd() fosc Input Threshold Voltage lo Input Pull-Down Current Input Pull-Down Voltage Oscillator Frequency 506 fin() Permissible External Clock Frequency at CLK Saturation Voltage lo Short-Circuit Current lo Input Pull-Up Current Input Pull-Up Voltage Rise and Fall Time (10/90%) Input Threshold Voltage hi Input Threshold Voltage lo V() = 0...VDD - 1 V Vpu() = VDD - V(), I() = -3 µA VDD = 3.3 V, CL = 10 pF VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % I() = 1 mA V() = 1V...VDD V() = 0...VDD - 1 V Vpu() = VDD - V(), I() = -3 µA VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % CLKDIV = 0 100 1.5 3.3 3 1.5 3.3 I() = 1 mA 2 1-Wire Interface 1W 601 602 603 604 605 606 607 Vs()lo Isc()lo Ipu() Vpu() tr(), tf() Vt()hi Vt()lo 300 -3 700 32 mV mA µA mV ns V V 0.8 1.0 400 -3 700 V V mV mA µA mV V V 0.8 1.0 V V kHz 20 80 400 400 3 -2.5 ms ms mV mV mA mA I2C Interface SDA, SCL 701 702 703 704 705 706 707 708 Vs()lo Isc()lo Ipu() Vpu() Vt()hi Vt()lo fclk() tbusy()cfg Saturation Voltage lo Short-Circuit Current lo Pull-Up Current Input Pull-Up Voltage Input Threshold Voltage hi at SDA Input Threshold Voltage lo at SDA Write/Read Clock Frequency at SCL Duration Of Startup Configuration CLKDIV = 0, 2 LUT blocks CLKDIV = 0, 16 LUT blocks Saturation Voltage lo Saturation Voltage hi Short-Circuit Current lo Short-Circuit Current hi I() = 1 mA Vs()hi = VDD - V(); I() = -1 mA Digital Output NERR 901 902 903 904 Vs()lo Vs()hi Isc()lo Isc()hi iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 7/24 ELECTRICAL CHARACTERISTICS Operating conditions: VDD, VDDA, VDDB, VDDIN = 3.0...5.5 V, Tj = -40...125 °C, reference point GND unless otherwise stated Item No. B01 B02 B03 B04 B05 B06 B07 B08 B09 Symbol Parameter Conditions Min. Vpk()max Vdc() ∆Vout() Isc()lo Isc()hi Isc() SR()hi, lo tS dbVlin Permissible Output Amplitude Output DC Voltage Output Voltage Load Dependency Short-Circuit Current lo Short-Circuit Current hi Output Current Limitation hi/lo Slew Rate hi/lo Settling Time Output Linearity I() = 0...5 mA pin shorten to VDD/2 pin shorten to VDD/2 V() = 0...VDD CL() = 5 nF CL() = 50 pF CL() = 5 nF, to 0.1% of final value 100 kHz sine and diff. 1 Vpp output voltage; RL() > 1 kΩ RL() = 120 Ω no sustained oscillation 80 60 100 3 4 1 12 -50 40 VDD = 3 V, RL = 50 Ω vs. VDD/2 VDD / 2 50 50 -12 50 mV mA mA mA V / µs V / µs µs dB dB nF Typ. Max. 550 mV Unit Line Driver Outputs AO, NAO, BO, NBO, ZO, NZO B10 CLmax Maximum Capacitive Output Load iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 8/24 PROGRAMMING Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 9 Automatic Compensation . . . . . . . . . . . . . . . . . Page 18 VEXT: Target voltage select DYNAMIC: Automatic compensation control FREQ: Automatic adaption frequency GENTLE: Automatic compensation update rate Temperature Sensing . . . . . . . . . . . . . . . . . . . . . Page 19 XCELSIUS: Temperature sensor select FCELSIUS: Fine temperature offset value CCELSIUS: Coarse temperature offset value CELSIUS: Current temperature value Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20 ERR_SIG: Signal unconnected alarm ERR_TEMP: Temperature alarm ERR_EE: EEPROM error condition Temperature Compensation . . . . . . . . . . . . . . Page 21 TEMP: Temperature compensation control Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 22 PD_CELSIUS: Power down control for internal temperature sensor TEST_CLK: Internal test clock oscillator control CLKDIV: Internal clock divider select Typical Applications . . . . . . . . . . . . . . . . . . . . . . Page 23 I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 11 CHECKSUM: EEPROM Checksum 1-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 12 A/B Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 14 SINGLEIN: Single ended input functionality ENSIGAB: Input signal error detection control CGAINA/B: Coarse gain select for channel A/B COFSA/B: Coarse offset select for channel A/B DGAINA/B: Dynamic gain on channel A/B DOFSA/B: Dynamic offset on channel A/B OGAIN: Output amplifier gain select on channel A/B FILTER: Signal path filter select PDA/B: Power down control for channel A/B Z Signal Path (Index) . . . . . . . . . . . . . . . . . . . . . . Page 16 SINGLEZ: Single ended input functionality for index channel Z MODEZ: Channel Z output mode select BYPASSZ: Channel Z comparator bypass control GAINZ: Gain select for channel Z OFSZ: Offset select for channel Z OGAINZ: Output amplifier gain select on channel Z ENSIGZ: Input signal error detection control on channel Z PDZ: Power down control for channel Z POLARITYZ: Channel Z polarity select iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 9/24 REGISTER MAP Adr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 CELSIUS[7:0] TEST_ADC* TEST_VGA* VC[1:0]* TEST_PGA* GAINZ[2] GAINZ[1:0] CGAINB[2:0] COFSA[7:0] COFSB[7:0] DGAINA[7:0] DGAINB[7:0] DOFSA[7:0] DOFSB[7:0] CLKSLOW* Internal Checksum(7:0) VTEST1* VTEST0* PD_BG* TEST_BG* CLKDIV TEST_CLK PD_CELSIUS OGAIN[1:0] VEXT ERR_SIG EN_NSTORE* Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Configuration Registers ROM Device ID[7:0] SINGLEIN OGAINZ[1:0] ERR_EE FREQ[1:0] MODEZ TALARM[2:0] FILTER[1:0] CCELSIUS[3:0] OFSZ[5:0] CGAINA[2:0] PDZ GENTLE BYPASSZ DYNAMIC SINGLEINZ ENSIGZ PDB FCELSIUS[3:0] TEMP POLARITYZ ENSIGAB PDA XCELSIUS ERR_TEMP Internal State Machine Registers 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE INTERNAL USE Peripheral Registers 0x40 0x41 0x42 EE_ERR CELSIUSRAW[7:0] CHANNEL XERR_OUT OFS_P 1OUTPUT OFS_N 1INPUT GAIN_P XSTORE GAIN_N SIG_VALID iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 10/24 REGISTER MAP Adr 0x43 Bit 7 Bit 6 Bit 5 EE_IRQ Bit 4 Bit 3 Bit 2 1INPUT_IRQ Bit 1 XSTORE_IRQ Bit 0 Notes Only the configuration registers are user programmable. *) Bits marked by an asterisk are solely intended for IC test and must be kept on zero for normal operation. Table 4: Register layout iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 11/24 I2C INTERFACE Startup An external I2 C 1-kbit EEPROM (e.g. 24xx01 family) is used to store configuration parameters permanently. On power-up and after reset is released iC-TW3 accesses the external EEPROM and reads its device configuration according to Table 6. EEPROM Checksum The checksum at address 0x0F contains the 8-bit sum of registers 0x01 to 0x0E plus the 8-bit sum of all LUT bytes up to and including the final block with its breakpoint set to 255. On startup iC-TW3 calculates the expected checksum and compares it with the value stored at EEPROM address 0x0F. If computed and stored address match normal operation begins. Otherwise, iC-TW3 asserts an error condition and pin NERR is pulled low. It is the user’s responsibility to store the correct checksum in the EEPROM during production programming. CHECKSUM(7:0) Code ... Adr 0x0F; Bit 7:0 R/W therefore equivalent to accessing memory location 128 via the 1-wire interface (see page 12). EEPROM Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F EEPROM Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B . . . 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F Description Config. 1 Config. 2 Config. 3 Config. 4 Temp. Sensing Config. Index Coarse Gain COFSA COFSB DGAINA DGAINB DOFSA DOFSB Test 1 CHECKSUM Description Breakpoint 0 GAINA GAINB OFSA OFSB OFSZ Breakpoint 1 (255) GAINA GAINB OFSA OFSB OFSZ . . . Breakpoint 255 GAINA GAINB OFSA OFSB OFSZ Corresponding Configuration Register 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F LUT Block Number 0 0 0 0 0 0 1 1 1 1 1 1 . . . 15 15 15 15 15 15 Function Checksum of EEPROM contents Table 5: Checksum EEPROM Register Map The 14 bytes of device configuration data are followed by a minimum of 2 to a maximum of 16 lock-up-table blocks (LUT). The LUT block size is 6 bytes each and the final block is indicated by its breakpoint value of 255. Thus, a minimum of 28 bytes are read with 2 active LUT blocks and 112 bytes are read with 16 active LUT blocks during the configuration phase. Note that the checksum is only calculated up and including the last LUT block. The last LUT block ist indicated by a breakpoint value of 255. Further descriptions on LUTs are given in section "Temperature Compensation" on page 21. Note that the EEPROM address space maps to the 1-wire address 128. Accessing EEPROM address 0 is Table 6: EEPROM register map iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 12/24 1-WIRE INTERFACE The 1-wire interface provides read and write access to the register bank and to the external EEPROM. When read access is not required an infrared phototransistor can be directly connected to the pin in order to build a cost effective wireless write-only port for in-field or production programming. The communication bit stream is pulse-width modulated (PWM) as shown in Figure 1. A zero-bit is encoded as a short high followed by a long low. A one-bit is encoded as a long high followed by a short low. The modulated signal is independent of the receiver or the transmitted clock frequency. Since iC-TW3 uses a free-running oscillator it is important to implement a robust, frequency insensitive protocol. 1- wire timing idle start 1 0 delay idle tlong tlong tshort tshort tlong tshort tdelay tidle Figure 1: Pulse width modulation bit stream Parameter tstart tlong tshort tdelay tidle Description Low time start condition (Master only) Unit time long (Master and iC-TW3) Unit time short (Master and iC-TW3) Delay on register read (iC-TW3 only) Interface idle before next access Access was write to external EEPROM Access was not write to external EEPROM min 1 ms tshort + 10 µs 35 µs 35 µs 8 ms 3 ms max 400 µs tlong - 10 µs Table 7: 1-Wire interface timing iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 13/24 Addressing The EEPROM address 0x00 maps to the 1-wire address 128. Accessing EEPROM address 0 is therefore equivalent to accessing memory location 128 through the 1-wire interface. All other 1-wire addresses are thus determined by adding 128 to the EEPROM address of interest. Write Sequence Figure 2 describes the write sequence of the 1-wire interface. On an idle wire, a write sequence is initiated 1-Wire Write Access Idle, wire is high by generating a start condition followed by the write command (000) and by the address and register data. Read Sequence A read sequence is depicted in Figure 3. After the start condition the read command (001) is followed by the register address. The master then releases the wire and iC-TW3 begins to pull low while internally accessing the data. When the data is ready it is produced while following the same PWM rules valid for the master. 3-bit command word 000 = write 001 = read Wire not driven Wire driven by master Filler bit, value 0 idle start 000 address(7:0) 0 data(7:0) idle To initiate communication pull low for at least tstart 8-bit register address: 0 to 127: internal registers 128 to 255: external EEPROM Wait at least for tidle before new access Figure 2: Register write sequence 1-Wire Read Access Idle, wire is high 3 bit command word 000 = write 001 = read Wire not driven Master releases driver Wire driven by master iC-TW3 starts returning data (first bit is dummy) Wire driven by iC-TW3 idle start 001 address(7:0) delay X data(7:0) idle To initiate communication pull low for at least tstart 8-bit register address: 0 to 127: internal registers 128 to 255: external EEPROM iC-TW3 drives low until data is ready Wait at least for tidle before new access Figure 3: Register read sequence iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 14/24 A/B SIGNAL PATH iC-TW3 incorporates two analog gain paths called channel A and B, respectively. Gain and offset of both paths are independently controlled and temperature compensated. Figure 4 depicts a diagram of a single signal path, Table 8 below summarizes gain and offset characteristics. VDD ENSIGAB COFSA/B(5:0) FILTER(1:0) PINA/PINB NINA/NINB SINGLEIN VDD/2 + AO/BO output - Input + + FOFSA/B(7:0) dynamic NAO/NBO CGAINA/B(2:0) FGAINA/B(7:0) OGAIN(1:0) Figure 4: The A/B signal path Input Amplifier Gain range Gain step Offset range input referred Offset step input referred 0..36 dB 6.0 dB 1.24 V gaininput 40 mV gaininput Dynamic Amplifier -2..18.4 dB 0.08 dB 0.25 V gaininput 2 mV gaininput Output Amplifier -3 dB, 0 dB, 6 dB Composite -5..60 dB 1.49 V gaininput gaininput = 10 gain_of _input _amplifier _in_dB 20 Table 8: Overview of gain and offset characteristics Single ended signals Single ended input functionality is provided by connecting the negative input terminal (pins NINA and NINB) to an internally generated voltage of VDD /2. This is enabled by setting the control bit SINGLEIN to 1. Alternatively, an externally generated reference voltage may be applied to the negative input terminals. SINGLEIN Code 0 1 Adr 0x01; Bit 5 Function A and B inputs are differential (default) A and B inputs are single ended R/W or damaged sensor connections. Any input terminal left unconnected is pulled to VDD and triggers a sensor error condition err_sig. ENSIGAB Code 0 1 Adr 0x03; Bit 0 Function Pull-up resistors disconnected and error reporting disabled (default) Pull-up resistors and error reporting active on A/B inputs R/W Table 10: Input signal error detection control Gain and offset Registers CGAINA(2:0) and CGAINB(2:0) are used to set the coarse gain. Coarse gain is static and it is not changed by the temperature or automatic compensation algorithm. The highest legal value for CGAINA(2:0) and CGAINB(2:0) is 6. Equivalently registers COFSA(5:0) and COFSB(5:0) are used to control the static off- Table 9: Single ended input functionality Input error detection Weak input pull-up resistors are enabled by setting control bit ENSIGAB to 1. The resistors are at minimum 2.0 MΩ. When driving the input with a high impedance source it might be necessary to disable the pull-up resistors to avoid excessive signal distortion. The pull-up resistors are used to sense floating iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 15/24 set of the input signal. Note that COFSA(5:0) and COFSB(5:0) are in 2’s complement format and their value range is limited from -31 to +31. CGAINA(2:0) CGAINB(2:0) Code 0x00 0x01 ... 0x06 Adr 0x07; Bit 2:0 Adr 0x07; Bit 5:3 R/W R/W gain = cgain x 6 dB 0 dB (default) 6 dB 36 dB enabled the values of FGAINA/B and FOFSA/B are equal to the register values in DGAINA/B(7:0) and DOFSA/B(7:0). Refer to chapter "Temperature Compensation" on page 21 for a detailed explanation of fine gain and fine offset calculations. DGAINA/B(7:0) and DOFSA/B(7:0) can be programmed to a fixed value or it is automatically updated when dynamic adaption is enabled. Output driver The output amplifier is capable of driving a 100 Ω differential load and is stable with capacitive loads of up to 100 nF. Control register OGAIN(1:0) is used to select the output amplifier gain. A gain of -3 dB is useful to accommodate input signals larger than 1 V and gain of +6 dB will provide a 1 Vpp single-ended output. Note that the selected output amplifier gain will influence the automatic gain compensation. Refer to section "Automatic Compensation" on page 18 for details. OGAIN(1:0) Code 0x00 0x01 0x02 0x03 Adr 0x01; Bit 7:6 Function 0 dB (default) reserved +6 dB -3 dB R/W Table 11: Coarse gain select for channel A/B COFSA(7:0) COFSB(7:0) Code 2’K 0xE1 ... 0xFF 0x00 0x01 ... 0x1F Adr 0x08; Bit 7:0 Adr 0x09; Bit 7:0 Code 5:0, and decimal 0x21, -31 ... 0x3F, -1 0x00, 0 0x01, +1 ... 0x1F, +31 1240 mV -1240 mV -40 mV 0 mV (default) 40 mV R/W R/W offset = cofs x 40 mV Table 12: Coarse offset select for channel A/B DGAINA(7:0) Adr 0x0A; Bit 7:0 R/W R/W Table 15: Output amplifier gain on channel A/B A programmable 1st -order low-pass filter can be enabled to limit the path bandwidth. The filter cut-off frequency can be set via the FILTER(1:0) register. FILTER(1:0) Adr 0x04; Bit 4:3 Function 1 MHz (default) 500 kHz 200 kHz reserved R/W DGAINB(7:0) Adr 0x0B; Bit 7:0 gain = dgain x 0.08 dB - 2 dB Code 0x00 ... 0x19 0x1A ... 0xFF 18.4 dB 0 dB 0.08 dB -2 dB (default) Code 0x00 0x01 0x02 0x03 Table 13: Dynamic gain select for channel A/B DOFSA(7:0) DOFSB(7:0) Code 0x81 ... 0xFF 0x00 0x01 ... 0x7F Adr 0x0C; Bit 7:0 Adr 0x0D; Bit 7:0 offset = cofs x 2 mV -254 mV -2 mV 0 mV (default) 2 mV 254 mV R/W R/W Table 16: Signal path filter In order to save power the complete signal path can be disabled using the control bits PDA and PDB respectively. When disabled the outputs are high impedance. The dynamic adaption should be disabled when either channel A or B is disabled. PDA Adr 0x04; Bit 0 Adr 0x04; Bit 1 Function Channel A/B is enabled (default) Channel A/B is powered down R/W R/W Table 14: Dynamic offset select for channel A/B Value FGAINA/B and FOFSA/B are fine gain and offset control respectively. They are calculated dynamically according to the temperature compensation algorithm. In case temperature compensation is not PDB Code 0 1 Table 17: Power down control on channel A/B iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 16/24 Z SIGNAL PATH (INDEX) A third analog path is used for index signal processing frequently found in encoder applications. Refer to Figure 5 for an overview. An input amplifier with a gain range of 0 to 36 dB is used to amplify the index signal to an intermediate level. The input amplifier employs output referred offset correction. This is used to eliminate inherent amplifier offset as well as sensor offset. Additionally, the same offset correction is used to skew the comparator shift point to a desired level. The offset correction is temperature compensated with a LUT. VDD ENSIGZ OFSZ(5:0) BYPASSZ PINZ NINZ SINGLEINZ VDD/2 + + POLARITYZ + 1Vpp + output ZO NZO GAINZ(2:0) MODEZ OGAINZ(1:0) Figure 5: The Z signal path Input Amplifier Gain range Gain step Offset Range (input referred* Offset step input referred 0..36 dB 6 dB 1.86 V gaininput 60 mV gaininput Output Amplifier -3 dB, 0 dB, 6 dB 1.86 V gaininput Composite -3..42 dB *: gaininput = 10 gain_of _input _amplifier _in_dB 20 Table 18: Gain and offset characteristics for channel Z A single ended input referenced to VDD /2 is provided by setting bit SINGLEINZ of register 0x02. Alternatively, pin NINZ can be biased with an external voltage. SINGLEINZ Code 0 1 Adr 0x02; Bit 1 Function channel Z input is differential (default) channel Z is single ended BYPASSZ Adr 0x02; Bit 2 Function Comparator is enabled (default) Comparator is bypassed R/W R/W MODEZ Code 0 1 Adr 0x02; Bit 3 Function 1 Vpp out (default) Rail-to-rail output (requires OGAINZ(1:0) set to 0x2) R/W Table 20: Channel Z output mode select Table 19: Single ended input functionality A zero-crossing comparator generates a 1.0 Vpeak-peak output signal or a rail-to-rail signal depending on control bit MODEZ. The comparator can be bypassed which allows using the Z Path as a regular amplifier path. Bypassing can be toggled via bit BYPASSZ of register 0x02. Code 0 1 Table 21: Channel Z comparator bypass iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 17/24 Gain and offset Gain and offset selections on channel Z are made available by providing control bits GAINZ(2:0) and OFSZ(5:0). Note that the maximum value for gain on channel Z is 6 which corresponds to a total gain of 36 dB. OGAINZ(1:0) Code 0x00 0x01 0x02 0x03 Adr 0x02; Bit 5:4 R/W Function 0 dB (default) reserved +6 dB -3 dB Table 24: Output amplifier gain on channel Z GAINZ(2:0) is split up amongst register 0x06 which holds the MSB and register 0x07 holding the other two bits. OFSZ(5:0) is the correction value to the output of the input amplifier and is interpreted as 2’s complement. The input referred offset is therefore gain dependent. Input error detection Pull-up resistor and error detection on channel Z can be controlled by bit ENSIGZ of register 0x03, disabling of the complete Z path can be achieved by setting bit PDZ of register 0x04 to 1. For more detailed information on pull-up and power control refer to section "A/B PATH" on page 14 as the behaviour of index path and signal path equal regarding these matters. ENSIGZ Code 0 GAINZ(2:0) Code 0x00 0x01 ... 0x06 36 dB Adr 0x06; Bit 7 Adr 0x07; Bit 1:0 gain = gainz x 6 dB 0 dB (default) 6 dB PDZ Code 0 1 R/W 1 Adr 0x03; Bit 1 Function Pull-up resistors disconnected and error reporting disabled (default) Pull-up resistors and error reporting active on inZ R/W The output gain on channel Z can be set via control bits OGAINZ(1:0). For more details again refer to section "A/B PATH" on page 14. Table 25: Input signal error detection control Adr 0x04; Bit 2 Function Channel Z is enabled (default) Channel Z is powered down R/W Table 22: Gain select for channel Z Table 26: Power-down control on channel Z OFSZ(5:0) Code 2’K 0x21 ... 0x3F 0x00 0x01 ... 0x1F Adr 0x06; Bit 5:0 Decimal -31 ... -1 0 +1 ... +31 R/W offset = cofs x 60 mV -1860 mV -60 mV 0 mV (default) 60 mV 1860 mV POLARITYZ Code 0 1 Adr 0x02; Bit 0 Function Channel Z has normal polarity (default) Channel Z has inverted polarity R/W Polarity of channel Z Furthermore, the polarity on channel Z can be inverted by setting or not setting bit POLARITYZ. Table 23: Offset select for channel Z Table 27: Channel Z polarity select iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 18/24 AUTOMATIC COMPENSATION Automatic gain and offset correction is available for dual sensor bridges that are 90° out of phase. These types of sensors are used for encoder applications. Automatic compensation removes any sensor offset and sets the gain to achieve a fixed output voltage. The target output voltage depends on the output gain OGAIN(1:0) as well as on the control bit VEXT. When using an external reference voltage, the appropriate voltage must be applied to pin VC. VEXT Code 0 1 Adr 0x02; Bit 7 Function Internally generated 1 V or 2 V is used as output target voltage, depending on register OGAIN(1:0). Voltage applied to pin VC defines target output voltage (see Table 29). R/W FREQ(1:0) Code 00 01 10 11 Adr 0x01; Bit 4:3 Function no tracking limit (default) 200 kHz 20 kHz 2 kHz R/W DYNAMIC Code 0 1 Adr 0x01; Bit 1 Function Automatic function is disabled Automatic function is enabled R/W Table 30: Automatic compensation enable Note that setting FREQ(1:0) to other values than 0 does not affect the signal bandwidth of the amplifier. It merely limits the rate of automatic adaption. Table 28: Target voltage selection Target Output Voltage Vppdiff 1V 2V 1V 2.21 V - V(VC) (2.21 V - VC) x 2 2.21 V - VC Table 31: Automatic compensation adaption rate OGAIN(1:0) Output Gain 00 01 10 11 00 01 10 11 0 dB reserved 6 dB -3 dB 0 dB reserved 6 dB -3 dB VEXT 0 0 0 0 1 1 1 1 In normal operation the compensation algorithm will adjust both gain and offset simultaneously in order to achieve fast convergence. If control bit GENTLE of register 0x01 is set, gain and offset registers are updated alternately. This reduces output jumpiness at the expense of slower convergence. GENTLE Code 0 1 Adr 0x01; Bit 2 Function Gain and offset are updated simultaneously Gain and offset are updated alternately R/W Table 29: Target output voltages Automatic compensation is enabled by setting control bit DYNAMIC of register 0x01 to 1. If enabled, it will constantly alter register DOFSA/B and DGAINA/B to maintain zero offset and the target output amplitude. Control bits FREQ(1:0) of register 0x01 are used to limit the tracking rate. If the input frequency increases above the limit tracking will stop. Normally, it is not required to limit the tracking frequency although it can be useful for certain bandwidth limited sensors. Table 32: Automatic compensation sequence control Automatic compensation can be used in conjunction with temperature compensation. Automatic compensation will then remove any residual offset or gain mismatch not corrected by the temperature correction algorithm. iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 19/24 TEMPERATURE SENSING iC-TW3 contains an on-chip temperature sensor. Optionally, an external sensor can be used by setting bit XCELSIUS of register 0x02 to 1. An external temperature sensor is useful for remote temperature sensing or in situations where the internal sensor does not provide adequate accuracy. Also, device self-heating due to heavy output loads can have an impact on the internal sensor readings. Connect the external temperature sensor with its analog output to pin KELVIN. CCELSIUS(3:0) Code 1111 ... 1001 1000 0000 0001 ... 0111 Adr 0x05; Bit 3:0 R/W Bit 3 is sign, bits 2:0 are magnitude of correction most negative correction ... least negative correction no correction no correction (default) least positive correction ... most positive correction Table 34: Coarse offset correction XCELSIUS Code 0 1 Adr 0x02; Bit 6 Function Select internal temperature sensor (default) Select external temperature sensor R/W FCELSIUS(3:0) Adr 0x05; Bit 7:4 R/W Value added to ADC reading is FCELSIUS(3:0) - 8 Code 0000 0001 ... 1111 -8 (default) -7 ... 7 Table 33: Temperature sensor select Table 35: Fine offset correction An ADC converts the analog temperature signal into an 8-bit digital word. In case the on-chip sensor is used the 8-bit value spans a temperature range of -50 °C to 150 °C. It is recommended to calibrate the ADC using register 0x05 even when using an external temperature sensor. CELSIUS(7:0) Data 0x00 Adr 0x12; Bit 7:0 R Function Current temperature ADC value that is used for compensation calculations. Value of this register is 0x40 + FCELSIUS(3:0) - 8 0xFF Table 36: Temperature data Calibrating the temperature ADC The raw ADC value can be accessed through register 0x40. A ±2 increment hysteresis is applied to the ADC value to remove conversion noise and the offset register 0x05 is added. The final value is stored in register 0x12 and is used for temperature compensation. Temperature alarm The iC-TW3 features a built-in temperature alarm system. An alarm threshold can be specified by the user via the TALARM(2:0) bits in register 0x03. A temperature alarm is asserted once the temperature value generated by the ADC is above the defined threshold. The alarm is indicated by the ERR_TEMP bit set to 1 as well as by pin NERR going low. TALARM(2:0) Code 000 001 ... 110 111 Adr 0x03; Bit 4:2 R/W To achieve best temperature accuracy it is required to calibrate the ADC by correctly programming register 0x05. At any known ambient temperature the register 0x05 is programmed such to read the expected ADC value. As an example, consider the product assembly floor with an ambient temperature of 20 °C. Due to device variation the ADC value read before calibration can be anything between 0 °C to 40 °C. Register 0x05 is now used to tune the ADC output value to the correct binary representation of 20 °C. tempthreshold = (TALARM(2:0) x 16) + 144 144 (default) 160 ... 240 Alarm disabled Table 37: Temperature alarm threshold iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 20/24 ERROR CONDITIONS iC-TW3 maintains three status bits reporting system error conditions. These bits are ERR_EE, ERR_TEMP and ERR_SIG of register 0x03. If any error condition is triggered, i.e. indicated by any of these bits being set to 1, this will also assert pin NERR pulling it low. ERR_EE Code 0 1 Adr 0x03; Bit 5 Error message No error since the last reset One of the following error conditions has occurred since the last reset: 1. EEPROM checksum error* 2. EEPROM read error 3. EEPROM write error This error message can not be disabled and its bit status is maintained until the device is reset. *) A permanent logic zero read at SDA does not lead to a checksum error. R ERR_TEMP Code 0 1 Notes Adr 0x03; Bit 6 Error message ADC reading is below value defined in register TALARM(2:0) ADC reading is above value defined in register TALARM(2:0) This error is not latched. Disabling temperature monitoring is possible by setting TALARM(2:0) to ’111’. R Table 39: Temperature alarm ERR_SIG Code 0 1 Notes Adr 0x03; Bit 7 Error message All input terminals are connected An input terminal is left unconnected This error is not latched. To enable this alarm ENSIGAB or ENSIGZ must be set 1. R Notes Table 38: EEPROM data error Table 40: Signal unconnected alarm iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 21/24 TEMPERATURE COMPENSATION Temperature compensation is enabled by setting control bit TEMP of register 0x01. A piece-wise linear interpolation of values stored in a look-up-table (LUT) is employed to calculate the gain and offset for a given temperature. Figure 6 shows a sample configuration with seven breakpoints. TEMP Code 0 1 Adr 0x01; Bit 0 Function Temperature compensation is disabled (default) Temperature compensation is enabled R/W Table 41: Temperature compensation enable gain/ofs ofsZ ofsB ofsA gainB gainA ADC value bp0 0 bp1 bp2 bp3 bp4 bp5 bp6 255 Figure 6: LUT with seven breakpoints There can be a minimum of two up to a maximum of 16 temperature breakpoints within the LUT. Each breakpoint has five interpolation values associated to it namely GAINA, GAINB, OFSA, OFSB and OFSZ. For more details on the layout of the LUT refer to section "EEPROM" on page 11. Breakpoints can be placed freely across the temperature axis except for the first and the last breakpoint. The first breakpoint must be located at ADC value 0 (which roughly corresponds to -50 °C when using the internal sensor), the last breakpoint must be located at ADC value 255 (150 °C with the internal sensor). The LUT is stored in the off-chip EEPROM from memory location 0x10 onward. Note that the EEPROM address space maps to the 1-wire address 128. Accessing EEPROM address 0 is therefore equivalent to accessing memory location 128 through the 1-wire interface. The breakpoint entry with a value of 255 marks the last valid LUT entry. All addresses thereafter including their data will be ignored. Temperature dependent gain and offset is determined by performing linear interpolation between breakpoints. Temperature dependent gain and offset are TGAINA/B and TOFSA/B respectively. Fine gain FGAINA/B and fine offset FOFSA/B (see figure 4 on page 14) are calculated as follows: fgain = tgain + dgain fofs = tofs + dofs Whereas TGAIN and TOFS are the temperature dependent values calculated using the LUT and DGAIN and DOFS are registers updated either manually or by the automatic compensation function. iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 22/24 EEPROM address 1-wire address 16 16 + 128 = 144 22 22 + 128 = 150 28 28 + 128 = 156 0 gainA gainB ofsA ofsB ofsZ 1 gainA gainB ofsA ofsB ofsZ 255 gainA gainB ofsA ofsB ofsZ 3 breakpoint look-up table EEPROM address 1-wire address 16 16 + 128 = 144 22 22 + 128 = 150 106 106 + 128 = 234 0 gainA gainB ofsA ofsB ofsZ 1 gainA gainB ofsA ofsB ofsZ 255 gainA gainB ofsA ofsB ofsZ 16 breakpoint look-up table Figure 7: Temperature LUT memory map TEST MODES The iC-TW3 posses two registers 0x0E and 0x10 which provide access to basic testing functionality. The PD_CELSIUS bit allows powering off the internal temperature sensor. If powered down, the temperature sensor output value can be forced to a desired value by writing to register 0x40. The user can then test the compensation circuit without cycling the device temperature. PD_CELSIUS Code 0 1 Adr 0x0E; Bit 0 R/W TEST_CLK Code 0 1 Adr 0x0E; Bit 1 Function Clock is not driven on any pin (default) Clock is driven on pin NERR R/W Table 43: Internal clock oscillator CLKDIV Code 1 0 Adr 0x0E; Bit 2 Function fsystem = fosc (default) fsystem = fosc / 2 R/W Function Temperature sensor enabled (default) Temperature sensor disabled Table 44: Internal clock divider selection Table 42: Temperature sensor power control iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 23/24 TYPICAL APPLICATIONS A typical application is shown in figure 8. Three differential MR sensor bridges are connected to the iC+3...5.5V TW3. A, B and Z outputs are driving 120Ω terminated transmission lines. +3...5.5V VDDIN/A/B 0.1μF VDD GND 0.1μF GNDIN/A/B PINA termination 120 Ω AO NAO R Sensor Bridge 0 NINA BO PINB Sensor Bridge 1 NBO ZO NZO VDD R NINB PINZ Index Sensor R SCL NINZ SDA 10k SCL SDA 24xx01 iC-TW3 Figure 8: Typical application MR Sensors EEPROM iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by email. Copying – even as an excerpt – is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. iC-TW3 SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER Rev B1, Page 24/24 ORDERING INFORMATION Type iC-TW3 Evaluation board Package 32 pin QFN, 5 mm x 5 mm Order Designation iC-TW3 QFN32 TW3D EVAL For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com Appointed local distributors: http://www.ichaus.com/sales_partners