X76F641XEG-2.0

This X76F641 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. ICmic TM IC MICROSYSTEMS 64K X76F641 Secure Serial Flash DESCRIPTION 8Kx8 + 32x8 FEATURES •64-bit Password Security —Five 64-bit Passwords for Read, Program and Reset •8192 Byte+32 Byte Password Protected Arrays —Seperate Read Passwords —Seperate Write Passwords —Reset Password •Programmable Passwords •Retry Counter Register —Allows 8 tries before clearing of both arrays —Password Protected Reset •32-bit Response to Reset (RST Input) •32 byte Sector Program •400kHz Clock Rate •2 wire Serial Interface •Low Power CMOS —2.0 to 5.5V operation —Standby current Less than 1µA —Active current less than 3 mA •High Reliability Endurance: —100,000 Write Cycles •Data Retention: 100 years •Available in: —8 lead EIAJ SOIC —SmartCard Module The X76F641 is a Password Access Security Supervisor, containing one 65536-bit Secure Serial Flash array and one 256-bit Secure Serial Flash array. Access to each memory array is controlled by five 64-bit passwords each. These passwords protect read and write operations of the memory array. A separate RESET password is used to reset the passwords and clear the memory arrays in the event the read and write passwords are lost. The X76F641 features a serial interface and software protocol allowing operation on a popular two wire bus. The bus signals are a clock Input (SCL) and a bidirectional data input and output (SDA). The X76F641 also features a synchronous response to reset providing an automatic output of a hard-wired 32-bit data stream conforming to the industry standard for memory cards. The X76F641 utilizes Xicor’s proprietary Direct Write providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. TM cell, Functional Diagram SCL SDA INTERFACE LOGIC DATA TRANSFER ARRAY ACCESS ENABLE 8K BYTE SerialFlash ARRAY ARRAY 0 (PASSWORD PROTECTED) PASSWORD ARRAY AND PASSWORD VERIFICATION LOGIC RST RESET RESPONSE REGISTER 32 BYTE SerialFlash ARRAY ARRAY 1 (PASSWORD PROTECTED) RETRY COUNTER 7025 FM 01 ∧Xicor, Inc. 1994, 1995, 1996 Patents Pending 9900-5004.5 3/9/99 EP 1 Characteristics subject to change without notice X76F641 PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a true three state serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In all other cases, this pin is in a high impedance state. PIN NAMES Symbol SDA SCL RST Vcc Vss NC Description Serial Data Input/Output Serial Clock Input Reset Input Supply Voltage Ground No Connect Reset (RST) RST is a device reset pin. When RST is pulsed high the PIN CONFIGURATION X76F641 will output 32 bits of fixed data which conforms to the standard for “synchronous response to reset”. part The must not be in a write cycle for the response to reset to occur. See Figure 11. If there is power interrupted durEIAJ SOIC ing the Response to Reset, the response to reset will be aborted and the part will return to the standby state. The VSS VCC 1 8 response to reset is "mask programmable" only! NC 2 3 4 7 6 5 RST SCL NC VCC RST SCL Smart Card DEVICE OPERATION There are two primary modes of operation for the X76F641; Protected READ and protected WRITE. Protected operations must be performed with one of four 8-byte passwords. SDA NC GND NC SDA The basic method of communication for the device is generating a start condition, then transmitting a comNC NC mand, followed by the correct password. All parts will be shipped from the factory with all passwords equal to ‘0’. 7025 FM 02 The user must perform ACK Polling to determine the validity of the password, before starting a data transfer After each transaction is completed, the X76F641 will (see Acknowledge Polling.) Only after the correct passreset and enter into a standby mode. This will also be the word is accepted and a ACK polling has been performed, response if an unsuccessful attempt is made to access a can the data transfer occur. protected array. To ensure the correct communication, RST must remain LOW under all conditions except when running a “Response to Reset sequence”. Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device. If the X76F641 is in a nonvolatile write cycle a “no A CK” (SDA=High) response will be issued in response to loading of the command byte. If a stop is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. The basic sequence is illustrated in Figure 1. 2 X76F641 Figure 1. X76F641 Device Operation LOAD COMMAND BYTE Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X76F641 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. A start may be issued to terminate the input of a control byte or the input data to be written. This will reset the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are inhibited while a write is in progress. Stop Condition LOAD 8-BYTE PASSWORD VERIFY PASSWORD ACCEPTANCE BY USE OF PASSWORD ACK POLLING LOAD 2 BYTE ADDRESS READ/WRITE DATA BYTES All communications must be terminated by a stop condition. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. As with starts, stops are inhibited when outputting data and while a write is in progress. Acknowledge 7025 FM 03 Twc OR DATA ACK POLLING Retry Counter The X76F641 contains a retry counter. The retry counter allows 8 accesses with an invalid password before any action is taken. The counter will increment with any combination of incorrect passwords. If the retry counter overflows, all memory areas are cleared and the device is The X76F641 will respond with an acknowledge after locked by preventing any read or write array password recognition of a start condition and its slave address. If matches. The passwords are unaffected. If a correct both the device and a write condition have been selected, the X76F641 will respond with an acknowledge password is received prior to retry counter overflow, the after the receipt of each subsequent eight-bit word. retry counter is reset and access is granted. In order to reset the operation of a locked up device, a special reset Reset Device Command command must be used with a RESET password. The reset device command is used to clear the retry counter and reactivate the device. When the reset device Device Protocol The X76F641 supports a bidirectional bus oriented proto- command is used prior to the retry counter overflow, the retry col. The protocol defines any device that sends data onto counter is reset and no arrays or passwords are the bus as a transmitter and the receiving device as aaffected. If the retry counter has overflowed, all memory areas are cleared and all commands are blocked and the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master willretry counter is disabled. Issuing a valid reset device command (with reset password) to the device resets and always initiate data transfers and provide the clock for re-enables the retry counter and re-enables the other both transmit and receive operations. Therefore, the commands. Again, the passwords are not affected. X76F641 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 2 and Figure 3. 3 Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Reset Password Command A reset password command will clear both arrays and set all passwords to all zero. X76F641 Figure 2. Data Validity SCL SDA Data Stable Data Change 7025 FM 04 Figure 3. Definition of Start and Stop Conditions SCL SDA Start Condition Stop Condition 7025 FM 05 Table 1. X76F641 Instruction Set 1st Byte after Start 1000 0000 1000 1000 1001 0000 1001 1000 1010 0000 1010 1000 1011 0000 1011 1000 1100 0000 1110 0000 1110 1000 1111 0000 1st Byte after Password High Address High Address High Address High Address 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 not used not used not used All the rest 2nd Byte after Password Low address Low address Low address Low address 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 not used not used not used Command Description Read (Array 0) Read (Array 1) Sector Write (Array 0) Sector Write (Array 1) Change Read 0 Password Change Read 1 Password Change Write 0 Password Change Write 1 Password Change Reset Password Reset Password Command Reset Device Command ACK Polling command (Ends Password operation) Reserved Password used Read 0 Read 1 Write 0 Write 1 Read 0 Read 1 Write 0 Write 1 Reset Reset Reset None 7025 FM T04 Notes:Illegal command codes will be disregarded. The part will respond with a “no-A to the illegal byte and then return to the standby mode. CK” All write/read operations require a password. 4 X76F641 PROGRAM OPERATIONS Sector Programming The sector program mode requires issuing the 8-bit write command followed by the password, password Ack command, the address and then the data bytes transferred as illustrated in figure 4. Up to 32 bytes may be transferred. After the last byte to be transferred is acknowledged a stop condition is issued which starts the nonvolatile write cycle. Figure 4. Sector Programming START COMMAND Write Password 7 Write Password 0 SDA S ACK ACK ACK ACK W ait tWC OR Repeated ACK Polling Command If ACK, Then Password Matches START ACK POLLING COMMAND A15 A14 A13 A12 A11 A10 Data 0 S ACK ACK NACK ACK ACK S ACK ACK Wait tWC Data ACK Polling A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ... Data 31 STOP 7025 FM 07 5 X76F641 requires the master to perform an ACK polling with the ACK Polling Once a stop condition is issued to indicate the end of the specific code of F0h. As with regular Acknowledge polling the user can either time out for 10ms, and then issue the ACK host’s write sequence, the X76F641 initiates the internal polling once, or continuously loop as described in nonvolatile write cycle. In order to take advantage of the the flow. typical 5ms write cycle, ACK polling can begin immediately. This involves issuing the start condition followed by the new command code of 8 bits (1st byte of Password ACK Polling Sequence the protocol.) If the X76F641 is still busy with the non PASSWORD LOAD volatile write operation, it will issue a “no-A CK” in COMPLETED response. If the nonvolatile write operation has completed, ENTER ACK POLLING an “ACK” will be returned and the host can then proceed with the rest of the protocol. ISSUE START Data ACK Polling Sequence WRITE SEQUENCE COMPLETED ENTER ACK POLLING ISSUE PASSWORD ACK COMMAND ISSUE START ACK RETURNED? ISSUE NEW COMMAND CODE YES PROCEED ACK RETURNED? YES PROCEED 7025 FM 08 NO NO 7025 FM 09 If the password that was inserted was correct, then an “ACK” will be returned once the nonvolatile cycle is over, in response to the ACK polling cycle immediately following it. If the password that was inserted was incorrect, then a “no A CK” will be returned even if the nonvolatile cycle is After the password sequence, there is always a nonvolatile over. Therefore, the user cannot be certain that the passwrite cycle. This is done to discourage random word is incorrect until the 10ms write cycle time has guesses of the password if the device is being tampered elapsed. with. In order to continue the transaction, the X76F641 6 X76F641 Figure 5. Acknowledge Polling SCL 8th clk. of 8th pwd. byte ‘ACK’ clk 8th clk ‘ACK’ clk SDA ‘ACK’ START condition 8th bit ACK or no ACK 7025 FM 10 READ OPERATIONS Sequential Read Read operations are initiated in the same manner as write The host can read sequentially within an array after the password acceptance sequence. The data output is operations but with a different command code. sequential, with the data from address n followed by the data from n+1. The address counter for read operations Random Read The master issues the start condition and a Read instruc- increments all address bits, allowing the entire memory tion and password, performs a Password Ack Polling, then array contents to be serially read during one operation. At issues the word address. Once the password has been the end of the address space (address 1FFFh for array 0, acknowledged and first byte has been read, another start 1Fh for array 1), the counter “rolls over” to address 0 and the X76F641 continues to output data for each acknowl- edge can be issued followed by a new 8-bit address. Random reads are allowed, but only the low order 8 bits can received. Refer to figure 7 for the address, acknowledge change. This limits random reads to a 256 byte block. edge and data transfer sequence. An acknowledge must follow each 8-bit data transfer. After the last bit has been Therefore, with a single password cycle only a 256 byte block of array 0 may be accessed randomly. To randomly read, a stop condition is generated without a preceding access another block of array 0, a stop must be issued fol- acknowledge. lowed by a new command/address/password sequence. A random read of the array 1 can access all locations without another password command sequence. Figure 6. Random Read START Read Password 7 Read Password 0 COMMAND SDA S ACK ACK ACK ACK START W ait tWC OR Repeated ACK Polling Command If ACK, then Password Matches START A15 A14 A13 A12 A11 A10 STOP S ACK Data Y 7025 FM 11 ACK POLLING COMMAND A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 S ACK ACK NACK ACK Data X S 7 A7 A6 A5 A4 A3 A2 A1 A0 X76F641 Figure 7. Sequential Read START Read Password 7 Read Password 0 Wait tWC OR Repeated ACK Polling Command COMMAND SDA S ACK ACK ACK ACK If ACK, then Password Matches START A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ACK POLLING COMMAND ACK STOP S ACK ACK ACK Data 0 Data X 7025 FM 12 S NACK PASSWORDS After this time, it cannot be determined if the password has been loaded correctly, without trying the new passThe sequence in Figure 8 shows how to change (proword. To determine if the new password has been loaded gram) the passwords. The programming of passwords is correctly the data ACK polling command is issued immedone twice prior to the nonvolatile write cycle in order to diately following the stop bit. If it returns an ACK, then the verify that the new password is consistent. After the eight two passes of the new password entry do not match. If it bytes are entered in the second pass, a comparison returns a "no ACK" then the passwords match and a high takes place. A mismatch will cause the part to reset and voltage cycle is in progress. The high voltage cycle is enter into the standby mode. complete when a subsequent data ACK command Data ACK polling can be used to determine if a password returns an "ACK". has been loaded correctly, however the data ACK command must be issued less than 2ms after the stop bit. There is no way to read any of the passwords. Figure 8. Change Passwords START COMMAND Old Password 7 Old Password 0 W ait tWC OR Repeated ACK Polling Command SDA S ACK ACK ACK ACK ACK START If ACK, then Password Matches ACK POLLING COMMAND Two bytes of “0” ACK ACK S NACK ACK STOP ACK Data ACK Polling If immediate ACK, then New Password error If immediate NACK, followed by ACK after ~5ms then New Password OK 7025 FM 13 New Password 0 New Password 7 Password 0 ACK New Password 7 S ACK ACK ACK 8 ACK X76F641 Figure 9. Reset Password Wait tWC OR Repeated ACK Polling Command If ACK, then Device reset START ACK POLLING COMMAND STOP S ACK 7025 FM 14 START Reset Password COMMAND Reset Password 7 Reset Password 0 SDA S ACK ACK ACK ACK NACK S Figure 10. Reset Device Wait tWC OR Repeated ACK Polling Command If ACK, then Device reset START ACK POLLING COMMAND STOP S ACK 7025 FM 15 START Reset Device COMMAND Reset Password 7 Reset Password 0 SDA S ACK ACK ACK ACK NACK S is pulsed HIGH and the CLK is within the RST pulse (meet the tNOL spec.) in the middle of an ISO transaction, The ISO Response to reset is controlled by the RST and it will output the 32 bit sequence again (starting at bit 0). CLK pins. When RST is pulsed high during a clock pulse, Otherwise, this aborts the ISO operation and the part the device will output 32 bits of data, one bit per clock, returns to standby state. If the RST is pulsed HIGH and the and it resets to the standby state. This conforms to the CLK is outside the RST pulse (in the middle of an ISO standard for “synchronous response to reset”. part The ISO transaction), this aborts the ISO operation and the must not be in a write cycle for the response to reset to part returns to standby state. occur. If there is power interrupted during the Response to After initiating a nonvolatile write cycle the RST pin must Reset, the response to reset will be aborted and the part not be pulsed until the nonvolatile write cycle is complete. will return to the standby state. A Response to Reset is not If not, the ISO response will not be activated. If the RST available during a nonvolatile write cycle. RESPONSE TO RESET (DEFAULT = 19 41 AA 55) 9 X76F641 Figure 11. Response to RESET (RST) RST SCK SO 10 LSB Byte 0 11 0 00 1 0000 010 01010101 10101010 MSB 3 MSB LSB 0 1 MSB LSB 2 MSB LSB ABSOLUTE MAXIMUM RATINGS* Temperature under Bias ...................... –65°C to +135°C Storage Temperature ........................... –65°C to +150°C Voltage on any Pin with Respect to VSS..................................... . –1V to +7V D.C. Output Current .................................................. 5mA Lead Temperature (Soldering, 10 seconds) ................................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Commercial Extended Min. 0° C –20° C Max. +70° C +85° C 7025 FM T05 Supply Voltage X76F641 X76F641 – 2.0 Limits 4.5V to 5.5V 2.0V to 3.6V 7025 FM T06 10 X76F641 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol ICC1 Parameter VCC Supply Current (Read) VCC Supply Current (Write) VCC Supply Current (Standby) VCC Supply Current (Standby) Input Leakage Current Output Leakage Current Min. Limits Max. 1 Units mA Test Conditions fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA = Open RST = VSS fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA = Open RST = VSS VIL = VCC x 0.1, VIH = VCC x 0.9 = 400 KHz, fSDA = 400 KHz VSDA = VSCC = VCC Other = GND or VCC–0.3V VIN = VSS to VCC VOUT = VSS to VCC VCC = 5.5V VCC = 5.5V VCC = 2.0V VCC = 2.0V IOL = 3mA 7002 FM T07 ICC2 (3) ISB1 (1) ISB2 (1) ILI ILO VIL1 (2) 3 mA 50 1 10 10 –0.5 VCC x 0.3 µA µA µA µA V V V V V fSCL Input LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage VIH1 (2) VIL2 (2) VIH2 (2) VOL VCC x 0.7VCC + 0.5 –0.5 VCC x 0.1 VCC x 0.9VCC + 0.5 0.4 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol COUT CIN (3) (3) Test Output Capacitance (SDA) Input Capacitance (RST, SCL) Max. 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V 7002 FM T08 NOTES: (1) Must perform a stop command after a read command prior to measurement (2) VIL min. and VIH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT 5V 1533Ο OUTPUT 100pF OUTPUT 100pF 7025 FM 17 A.C. TEST CONDITIONS Input Pulse Levels 3V 1.3KΟ VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 100pF 7002 FM T09 Input Rise and Fall Times Input and Output Timing Level Output Load 11 X76F641 AC CHARACTERISTICS AC Specifications (Over the recommended operating conditions) Symbol fSCL tIN (1) tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR tF fSCL_RST tSR tNOL tRST tSU:RST tLOW_RST tHIGH_RST tRDV tCDV tDHZ Notes:1. Notes:2. (1) Parameter SCL Clock Frequency Pulse width of spikes which must be suppressed by the input filter SCL LOW to SDA Data Out Valid Time the bus must be free before a new transmit can start Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time SDA and SCL Rise Time SDA and SCL Fall Time SCL Clock Frequency during Response to Reset Device Select to RST active RST to SCL Non-Overlap RST High Time Response to Reset Setup Time Clock LOW during Response to Reset Clock HIGH during Response to Reset RST LOW to SDA Valid During Response to Reset CLK LOW to SDA Valid During Response to Reset Device Deselect to SDA high impedance Min 0 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 20 + 0.1 x Cb (2) 20 + 0.1 x Cb (2) Typ Max 400 Units KHz ns 100 0.3 0.9 ∝s ∝s ∝s ∝s ∝s ∝s ns ∝s ∝s 300 300 300 400 ns ns ns kHz ns ns ∝s ∝s ∝s ∝s 500 500 500 ns ns ns 200 500 2.25 1.25 1.25 1.25 0 0 0 Typical values are for TA = 25˚C and VCC = 5.0V Cb = Total Capacitance of one bus line in pf. 7025 FM T14 12 X76F641 RESET AC SPECIFICATIONS Power Up Timing Symbol tPUR (1) tPUW (1) Notes:1. (2) Parameter Time from Power Up to Read Time from Power Up to Write Min. Typ Max. 1 5 Units mS mS 7025 FM T11 Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 2. Typical values are for TA = 25˚C and VCC = 5.0V Nonvolatile Write Cycle Timing Symbol tWC (1) Notes:1. Parameter W rite Cycle Time Min. Typ.(1) 5 Max. 10 Units mS 7025 FM T12 tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. TIMING DIAGRAMS Bus Timing tR SCL tSU:STA tHD:STA SDA IN tAA SDA OUT 7025 FM 18 tF tSU:DAT tHIGH tLOW tHD:DAT tSU:STO tDH tBUF Write Cycle Timing SCL SDA 8th bit of last byte ACK tWC Stop Condition Start Condition 7025 FM 19 13 X76F641 RST Timing Diagram – Response to a Synchronous Reset RST tRST tNOL tNOL 1st clk pulse tHIGH_RST 2nd clk pulse CLK tRDV I/O tSU:RST DATA BIT (1) tCDV tLOW_RST DATA BIT (2) 3rd clk pulse RST CLK I/O DATA BIT (N) DATA BIT (N+1) (N+2) 7025 FM 21 GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS 100 80 60 40 20 Pull Up Resistance in KΟ RMAX V CCMAX R = 1.8KΟ I MIN = -------------------------OLMIN RMIN 40 60 80 100 20 Bus capacitance in pF t R R ---------------MAX = C BUS tR = maximum allowable SDA rise time 7025 FM 22 14 X76F641 8-LEAD PLASTIC, 0.200” WIDE SMALL OUTLINE GULLWING PACKAGE TYP “A” (EIAJ SOIC) 0.020 (.508) 0.012 (.305) .213 (5.41) .205 (5.21) PIN 1 ID .330 (8.38) .300 (7.62) .050 (1.27) BSC .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) 0 8 REF .010 (.254) .007 (.178) .035 (.889) .020 (.508) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 7025 FM 24 15 X76F641 8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X 8 CONTACT MODULE 11.4 6 CONTACT MODULE 8 0.15 0.2 1 . 59 12.6 90° 1 1.215 1.3 1.3 2.54 2.54 35mm TAPE 35mm TAPE 1.422 REJECT PUNCH POSITION 35 23.02 8.82 NOTE: ALL MEASUREMENTS IN MILLIMETERS 16 4.75 X76F641 ORDERING INFORMATION X76F641 Device P T G –V VCC Limits Blank = 5V ±10% 2.0 = 2.0V to 3.6V G=RoHS Compliant Lead Free package Blank = Standard package. Non lead free Temperature Range Blank = Commercial = 0° to +70°C C E = Extended = –20° to +85° C C Package A = 8-Lead SOIC (EIAJ) H = Die in Waffle Packs W = Die in Wafer Form X = Smart Card Module LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detec- tion and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life sup- port device or system, or to affect its safety or effectiveness. 17