IS61C3216-10T

IS61C3216 IS61C3216 32K x 16 HIGH-SPEED CMOS STATIC RAM DESCRIPTION The I CSI IS61C3216 is a high-speed, 512K static RAM organized as 32,768 words by 16 bits. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields fast access times with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61C3216 is packaged in the JEDEC standard 44-pin 400mil SOJ and 44-pin 400mil TSOP-2. FEATURES • High-speed access time: 10, 12, 15, and 20 ns • CMOS low power operation — 450 mW (typical) operating — 250 µW (typical) standby • TTL compatible interface levels • Single 5V ± 10% power supply • I/O compatible with 3.3V device • Fully static operation: no clock or refresh required • Three state outputs • Industrial temperature available • Available in 44-pin 400mil SOJ package and 44-pin TSOP-2 1 2 3 4 5 6 7 FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K x 16 MEMORY ARRAY 8 9 VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O 10 11 12 CE OE WE UB LB CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. SR008-0B 1 IS61C3216 PIN CONFIGURATIONS 44-Pin SOJ NC A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC 44-Pin TSOP-2 NC A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC PIN DESCRIPTIONS A0-A14 I/O0-I/O15 CE OE WE Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input LB UB NC Vcc GND Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground TRUTH TABLE Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O0-I/O7 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O8-I/O15 High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current ISB1, ISB2 ICC ICC Write ICC 2 Integrated Circuit Solution Inc. SR008-0B IS61C3216 ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TSTG PT IOUT Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –0.5 to +7.0 –65 to +150 1.5 20 Unit V V °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1 2 3 4 5 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C Speed -10, -12 -15, -20 -12 -15, -20 VCC 5V ± 5% 5V ± 10% 5V ± 5% 5V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) GND < VIN < VCC GND < VOUT < VCC, Outputs Disabled Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 — 2.2 –0.5 –2 –2 Max. — 0.4 VCC + 0.5 0.8 2 2 Unit V V V V µA µA 6 7 8 Input Leakage Output Leakage Notes: 1. VIL (min.) = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB1 Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE > VIH , f = 0 VCC = Max., CE > VCC – 0.2V, VIN > VCC – 0.2V, or VIN < 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. -10 -12 Min. Max. Min. Max. — — — — — — 300 — 40 — 5 — — — — — — — 270 300 40 45 5 10 -15 Min. Max. — — — — — — 250 270 40 45 5 10 -20 Min. Max. Unit — — — — — — 230 250 40 45 5 10 mA mA 9 10 11 12 ISB2 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. SR008-0B 3 IS61C3216 CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) -10 Min. Max. 10 — 3 — — 0 0 0 4 — 0 5 — 10 — 10 5 5 — 5 — 5 5 — -12 Min. Max. 12 — 3 — — 0 0 0 4 — 0 5 — 12 — 12 5 6 — 6 — 6 6 — -15 Min. Max. 15 — 3 — — 0 0 0 4 — 0 5 — 15 — 15 7 7 — 7 — 7 7 — -20 Min. Max. 20 — 3 — — — 0 0 4 — — 5 — 20 — 20 8 8 — 8 — 8 8 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE tLZOE(2) tHZCE(2 tLZCE tBA tHZB tLZB (2) OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b 480 Ω 5V 5V 480 Ω AC TEST LOADS OUTPUT 30 pF Including jig and scope OUTPUT 255 Ω 5 pF Including jig and scope 255 Ω Figure 1a. 4 Figure 1b. Integrated Circuit Solution Inc. SR008-0B IS61C3216 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) tRC 1 2 ADDRESS tAA tOHA tOHA DATA VALID DOUT PREVIOUS DATA VALID 3 4 READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA 5 6 7 tHZCE tHZB DATA VALID OE tDOE tHZOE CE tLZCE tLZOE tACE LB, UB tBA tLZB 8 9 10 11 12 DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Circuit Solution Inc. SR008-0B 5 IS61C3216 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End (2) -10 Min. Max. 10 9 9 1 0 9 7 5 0 — 1 — — — — — — — — — 5 — -12 Min. Max. 12 10 10 1 0 10 8 6 0 — 1 — — — — — — — — — 6 — -15 Min. Max. 15 11 11 1 0 11 10 7 0 — 1 — — — — — — — — — 7 — -20 Min. Max. 20 12 12 1 0 12 11 8 0 — 1 — — — — — — — — — 8 — Unit ns ns ns ns ns ns ns ns ns ns ns tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE tLZWE(2) WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 6 Integrated Circuit Solution Inc. SR008-0B IS61C3216 AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) 1 tWC ADDRESS tSCE tHA 2 tPWB CE 3 4 5 tSD tHD LB, UB tAW tPWE WE tSA WRITE (1) 6 UNDEFINED DIN tHZWE tLZWE UNDEFINED HIGH-Z HIGH-Z DOUT 7 8 9 10 11 12 Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). Integrated Circuit Solution Inc. SR008-0B 7 IS61C3216 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 10 12 15 20 IS61C3216-10T IS61C3216-10K IS61C3216-12T IS61C3216-12K IS61C3216-15T IS61C3216-15K IS61C3216-20T IS61C3216-20K Package 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 12 15 20 IS61C3216-12TI IS61C3216-12KI IS61C3216-15TI IS61C3216-15KI IS61C3216-20TI IS61C3216-20KI Package 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 8 Integrated Circuit Solution Inc. SR008-0B