IS61C512-15N

IS61C512 IS61C512 64K x 8 HIGH-SPEED CMOS STATIC RAM DESCRIPTION The ICSI IS61C512 is a very high-speed, low power, 65,536 word by 8-bit CMOS static RAMs. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 1 mW (typical) with CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C512 is available in 32-pin 300mil DIP, SOJ and 8*20mm TSOP-1 packages. FEATURES • • • • • • • • Pin compatible with 128K x 8 devices High-speed access time: 15, 20, 25, 35 ns Low active power: 500 mW (typical) Low standby power — 250 µW (typical) CMOS standby Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications Fully static operation: no clock or refresh required TTL compatible inputs and outputs Single 5V (±10%) power supply FUNCTIONAL BLOCK DIAGRAM A0-A15 DECODER 512 X 1024 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE1 CE2 OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. SR011-0B 1 IS61C512 PIN CONFIGURATION 32-Pin DIP and SOJ NC NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 PIN CONFIGURATION 32-Pin TSOP-1 A11 A9 A8 A13 WE CE2 A15 VCC NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN DESCRIPTIONS A0-A15 CE1 CE2 OE WE I/O0-I/O7 Vcc GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output Power Ground TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –10 to +85 –65 to +150 1.5 20 Unit V °C °C W mA 2 Integrated Circuit Solution Inc. SR011-0B IS61C512 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage (1) Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 — 2.2 –0.3 Max. — 0.4 VCC + 0.5 0.8 2 2 Unit V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, Outputs Disabled –2 –2 Notes: 1. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC1 ICC2 ISB1 Parameter Vcc Operating Supply Current Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = 0 Com. Ind. -15 ns Min. Max. — — — — — — 70 — 125 — 25 — -20 ns Min. Max. — — — — — — 70 90 115 135 25 30 -25 ns Min. Max. — — — — — — 70 90 105 125 25 30 -35 ns Min. Max. — — — — — — 70 90 90 115 25 30 Unit mA mA mA VCC = Max., Com. IOUT = 0 mA, f = fMAX Ind. VCC = Max., VIN = VIH or VIL CE1 ≥ VIH or CE2 ≤ VIL, f = 0 Com. Ind. ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., Com. CE1 ≥ VCC – 0.2V, Ind. CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 — — 750 — — — 750 1 — — 750 1 — — 750 1 µA mA Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. Integrated Circuit Solution Inc. SR011-0B 3 IS61C512 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1 Access Time CE2 Access Time OE Access Time (2) (2) -15 ns Min. Max. 15 — 3 — — — 0 0 2 2 0 0 — — 15 — 15 15 7 — 6 — — 8 — 12 -20 ns Min. Max. 20 — 3 — — — 0 0 3 3 0 0 — — 20 — 20 20 8 — 9 — — 9 — 18 Min. 25 — 3 — — — 0 0 3 3 0 0 — -25 ns Max. — 25 — 25 25 9 — 10 — — 10 — 20 -35 ns Min. Max. 35 — 3 — — — 0 0 3 3 0 0 — — 35 — 35 35 12 — 12 — — 12 — 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE1 tACE2 tDOE tLZOE OE to Low-Z Output OE to High-Z Output tHZOE tLZCE1(2) CE1 to Low-Z Output tLZCE2 tHZCE tPU (3) (2) CE2 to Low-Z Output CE1 or CE2 to High-Z Output CE1 or CE2 to Power-Up CE1 or CE2 to Power-Down (2) tPD(3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b AC TEST LOADS 1213 Ω 3.3V 3.3V 1213 Ω OUTPUT 100 pF Including jig and scope 1378 Ω OUTPUT 5 pF Including jig and scope 1378 Ω Figure 1a. 4 Figure 1b. Integrated Circuit Solution Inc. SR011-0B IS61C512 AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE1 tLZOE tACE1/tACE2 CE2 tLZCE1/tLZCE2 tHZCE DATA VALID HIGH-Z DOUT HIGH-Z tPU tPD 50% 50% ICC SUPPLY CURRENT ISB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. Integrated Circuit Solution Inc. SR011-0B 5 IS61C512 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End (2) -15 ns Min. Max. 15 12 12 12 0 0 10 8 0 — 2 — — — — — — — — — 7 — -20 ns Min. Max. 20 15 15 15 0 0 12 10 0 — 2 — — — — — — — — — 10 — Min. 25 20 20 20 0 0 15 12 0 — 2 -25 ns Max. — — — — — — — — — 12 — -35 ns Min. Max. 35 30 30 30 0 0 20 15 0 — 2 — — — — — — — — — 8 — Unit ns ns ns ns ns ns ns ns ns ns ns tWC tSCE1 tSCE2 tAW tHA tSA tPWE(4) tSD tHD tHZWE WE LOW to High-Z Output tLZWE(2) WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ADDRESS tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID 6 Integrated Circuit Solution Inc. SR011-0B IS61C512 WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2) tWC ADDRESS tSA tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE WE tHZWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE = HIGH. Integrated Circuit Solution Inc. SR011-0B 7 IS61C512 ORDERING INFORMATION: IS61C512 Commercial Range: 0°C to + 70°C Speed (ns) Order Part No. 15 15 15 20 20 20 25 25 25 35 35 35 IS61C512-15J IS61C512-15N IS61C512-15T IS61C512-20J IS61C512-20N IS61C512-20T IS61C512-25J IS61C512-25N IS61C512-25T IS61C512-35J IS61C512-35N IS61C512-35T Package 300mil SOJ 300mil DIP 8*20mm TSOP-1 300mil SOJ 300mil DIP 8*20mm TSOP-1 300mil SOJ 300mil DIP 8*20mm TSOP-1 300mil SOJ 300mil DIP 8*20mm TSOP-1 ORDERING INFORMATION: IS61C512 Industrial Range: –40°C to + 85°C Speed (ns) Order Part No. 15 15 15 20 20 20 25 25 25 35 35 35 IS61C512-15JI IS61C512-15NI IS61C512-15TI IS61C512-20JI IS61C512-20NI IS61C512-20TI IS61C512-25JI IS61C512-25NI IS61C512-25TI IS61C512-35JI IS61C512-35NI IS61C512-35TI Package 300mil SOJ 300mil DIP 8*20mm TSOP-1 300mil SOJ 300mil DIP 8*20mm TSOP-1 300mil SOJ 300mil DIP 8*20mm TSOP-1 300mil SOJ 300mil DIP 8*20mm TSOP-1 Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 8 Integrated Circuit Solution Inc. SR011-0B