IS61C64AH-15J

IS61C64AH 8K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 15, 20, 25 ns • Automatic power-down when chip is deselected • CMOS low power operation — 450 mW (typical) operating — 250 µW (typical) standby • TTL compatible interface levels • Single 5V power supply • Fully static operation: no clock or refresh required • Three state outputs • Two Chip Enables (CE1 and CE2) for simple memory expansion DESCRIPTION The I CSI IS61C64AH is a very high-speed, low power, 8192-word by 8-bit static RAM. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 15 ns with low power consumption. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) with CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C64AH is packaged in the JEDEC standard 28-pin, 300mil SOJ and 330mil SOP. FUNCTIONAL BLOCK DIAGRAM A0-A12 DECODER 256 X 256 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE2 CE1 OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. SR001-B 1 IS61C64AH PIN CONFIGURATION 28-Pin SOJ and SOP NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 PIN DESCRIPTIONS A0-A12 CE1 CE2 OE WE I/O0-I/O7 Vcc GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output Power Ground TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –55 to +125 –65 to +150 1.0 20 Unit V °C °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial(1) Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% Notes: 1. Industrial supplement specification available upon request. 2 Integrated Circuit Solution Inc. SR001-B IS61C64AH DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, Outputs Disabled Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 — 2.2 –0.5 –2 –2 Max. — 0.4 VCC + 0.5 0.8 2 2 Unit V V V V µA µA 1 2 3 4 Note: 1. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB1 Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE1 ≥ VIH or CE2 ≥ VIL, f = 0 VCC = Max., CE1 ≥ VCC – 0.2V, CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 -15 ns Min. Max. — — 135 20 -20 ns Min. Max. — — 120 20 -25 ns Min. Max. — — 110 20 Unit mA mA 5 6 7 ISB2 CMOS Standby Current (CMOS Inputs) — 6 — 6 — 6 mA 8 9 10 Conditions VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance 11 12 Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. Integrated Circuit Solution Inc. SR001-B 3 IS61C64AH READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1 Access Time CE2 Access Time OE Access Time (2) (2) -15 ns Min. Max. 15 — 3 — — — 0 — 3 3 — 0 — — 15 — 15 15 7 — 6 — — 8 — 15 -20 ns Min. Max. 20 — 3 — — — 0 — 3 3 — 0 — — 20 — 20 20 7 — 7 — — 10 — 20 -25 ns Min. Max. 25 — 3 — — — 0 — 3 3 — 0 — — 25 — 25 25 9 — 9 — — 12 — 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE1 tACE2 tDOE tLZOE OE to Low-Z Output OE to High-Z Output tHZOE tLZCE1(2) CE1 to Low-Z Output tLZCE2 tHZCE tPU (3) (2) CE2 to Low-Z Output CE1 or CE2 to High-Z Output CE1 or CE2 to Power-Up CE1 or CE2 to Power-Down (2) tPD(3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 Ω 5V 5V 480 Ω OUTPUT 30 pF Including jig and scope 255 Ω OUTPUT 5 pF Including jig and scope 255 Ω Figure 1. Figure 2. 4 Integrated Circuit Solution Inc. SR001-B IS61C64AH AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS 1 2 t OHA DATA VALID t AA t OHA DOUT PREVIOUS DATA VALID 3 4 READ CYCLE NO. 2(1,3) t RC ADDRESS 5 t OHA t AA OE 6 7 8 t DOE CE1 t HZOE t LZOE CE2 t LZCE1 t LZCE2 DOUT HIGH-Z t ACE1 t ACE2 DATA VALID t HZCE1 t HZCE2 9 10 11 12 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. Integrated Circuit Solution Inc. SR001-B 5 IS61C64AH WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End (2) -12 ns Min. Max. 12 10 10 10 0 0 8 8 0 — 0 — — — — — — — — — 6 — -15 ns Min. Max. 15 12 12 12 0 0 10 9 0 — 0 — — — — — — — — — 8 — Min. 20 17 17 15 0 0 12 10 0 — 0 -20 ns Max. — — — — — — — — — 10 — -25 ns Min. Max. 25 22 22 20 0 0 15 12 0 — 0 — — — — — — — — — 12 — Unit ns ns ns ns ns ns ns ns ns ns ns tWC tSCE1 tSCE2 tAW tHA tSA tPWE(4) tSD tHD tHZWE WE LOW to High-Z Output tLZWE(2) WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC ADDRESS VALID ADDRESS t SA CE1 t SCE1 t SCE2 t HA CE2 WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID 6 Integrated Circuit Solution Inc. SR001-B IS61C64AH AC WAVEFORMS WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS 1 t HA 2 3 OE CE1 CE2 WE LOW HIGH t AW t PWE1 t SA t HZWE DATA UNDEFINED HIGH-Z 4 t LZWE DOUT 5 t HD t SD DIN DATAIN VALID 6 7 t HA WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE CE1 LOW LOW HIGH 8 9 CE2 t AW t PWE2 WE 10 t LZWE t SD t HD t SA DOUT DATA UNDEFINED t HZWE HIGH-Z 11 12 DIN DATAIN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE = VIH. Integrated Circuit Solution Inc. SR001-B 7 IS61C64AH ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 15 20 25 Order Part No. IS61C64AH-15J IS61C64AH-15U IS61C64AH-20J IS61C64AH-20U IS61C64AH-25J IS61C64AH-25U Package 300mil SOJ 330mil SOP 300mil SOJ 330mil SOP 300mil SOJ 330mil SOP Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 8 Integrated Circuit Solution Inc. SR001-B