IS61LV5128-8KI

IS61LV5128 FEATURES 512K x 8 HIGH-SPEED CMOS STATIC RAM • High-speed access times: — 8, 10, 12 and 15 ns • High-preformance, lower-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh reguired • TTL compatible inputs and outputs • Single 3.3V + 10% power supply • Packages available: — 36-pin 400mil SOJ — 44-pin TSOP-2 524,288-word by 8-bit COMS static RAM. The IS61LV5128 is fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher preformance and low power consumotion devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) with CMOS input levels. The IS61LV5128 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV5128 is available in 36-pin, 400mil SOJ and 44-pin TSOP-2 package. DESCRIPTION The 1+51 IS61LV5128 is a very high-speed, low power, FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K X 8 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc. Integrated Circuit Solution, Inc. SR027-0C 1 IS61LV5128 PIN CONFIGURATION 36-Pin SOJ A0 A1 A2 A3 A4 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A14 A13 A12 A11 A10 NC PIN CONFIGURATION 44-Pin TSOP-2 NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC PIN DESCRIPTIONS A0-A18 CE OE WE I/O0-I/O7 Vcc GND NC Address Inputs Chip Enable Input Output Enable Input Write Enable Input Input/Output Power Ground No Connection TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN Vcc Current ISB, ISB ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PD Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation Value Unit –0.5 to Vcc + 0.5 V –55 to +125 °C –65 to +150 °C 1.0 W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Circuit Solution, Inc. SR027-0C IS61LV5128 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V + 10% 3.3V + 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage  Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 — 2.0 –0.3 Max. — 0.4 VCC + 0.3 0.8 1 5 1 5 Unit V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. Com. Ind. –1 –5 –1 –5 Notes: 1. VIL = –3.0V for pulse width less than 10 ns. 2. The Vcc operating range for 8 ns is 3.3V +10%, -5%. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ISB Parameter Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE ≥ VIH , f = 0 VCC = Max., CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. -8 ns Min. Max. — — — — — — 300 310 55 65 10 15 -10 ns Min. Max. — — — — — — 280 290 55 65 10 15 -12 ns Min. Max. — — — — — — 260 270 55 65 10 15 -15 ns Min. Max. — — — — — — 240 250 55 65 10 15 Unit mA mA ISB mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. Integrated Circuit Solution, Inc. SR027-0C 3 IS61LV5128 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time  Min. 8 — 3 — — 0 0 0 3 -8 Max. — 8 — 8 4 4 — 4 — -10 Min. Max. 10 — 3 — — — 0 0 3 — 10 — 10 5 5 — 5 — -12 Min. Max. 12 — 3 — — — 0 0 3 — 12 — 12 6 6 — 6 — -15 Min. Max. 15 — 3 — — 0 0 0 3 — 15 — 15 7 6 — 6 — Unit ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE tLZOE  OE to High-Z Output OE to Low-Z Output CE to High-Z Output tHZCE tLZCE  CE to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 Notes: 1. The Vcc operating range for 8 ns is 3.3V +10%, -5%. AC TEST LOADS 319 Ω 3.3V 3.3V 319 Ω OUTPUT 30 pF Including jig and scope 353 Ω OUTPUT 5 pF Including jig and scope 353 Ω Figure 1. 4 Figure 2. Integrated Circuit Solution, Inc. SR027-0C IS61LV5128 AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t DOE CE t HZOE t LZOE t ACE t LZCE t HZCE DATA VALID DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Circuit Solution, Inc. SR027-0C 5 IS61LV5128 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End  -8 Min. Max. 8 7 7 0 0 7 4.5 0 — 3 — — — — — — — — 4 — -10 Min. Max. 10 8 8 0 0 8 5 0 — 3 — — — — — — — — 5 — -12 Min. Max. 12 9 9 0 0 9 6 0 — 3 — — — — — — — — 6 — -15 Min. Max. 15 10 10 0 0 10 7 0 — 3 — — — — — — — — 7 — Unit ns ns ns ns ns ns ns ns ns ns tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE  WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. AC WAVEFORMS WRITE CYCLE NO. 1 (1,2 )(CE Controlled, OE is HIGH or LOW) t WC ADDRESS VALID ADDRESS t SA CE t SCE t HA WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID 6 Integrated Circuit Solution, Inc. SR027-0C IS61LV5128 WRITE CYCLE NO. 2 (1,2)(WE Controlled, OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE CE LOW t HA LOW t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. Integrated Circuit Solution, Inc. SR027-0C 7 IS61LV5128 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 8 10 12 15 Order Part No. IS61LV5128-8T IS61LV5128-8K IS61LV5128-10T IS61LV5128-10K IS61LV5128-12T IS61LV5128-12K IS61LV5128-15T IS61LV5128-15K Package 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 8 10 12 15 Order Part No. IS61LV5128-8TI IS61LV5128-8KI IS61LV5128-10TI IS61LV5128-10KI IS61LV5128-12TI IS61LV5128-12KI IS61LV5128-15TI IS61LV5128-15KI Package 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 Integrated Circuit Solution, Inc. BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 8 Integrated Circuit Solution, Inc. SR027-0C