IS62LV1024L-70H

IS62LV1024L IS62LV1024L/LL IS62LV1024LL 128K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM .EATURES • Access times of 45, 55, and 70 ns • Low active power: 60 mW (typical) • Low standby power: 15 µW (typical) CMOS standby • Low data retention voltage: 2V (min.) • Available in Low Power (-L) and Ultra Low Power (-LL) • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • TTL compatible inputs and outputs • Single 2.7V to 3.6V power supply DESCRIPTION The 1+51 IS62LV1024L and IS62LV1024LL are low power and low Vcc,131,072-word by 8-bit CMOS static RAMs. They are fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62LV1024L and IS62LV1024LL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1, 450mil SOP and 48-pin 6*8mm T.-BGA. .UNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 512 X 2048 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE1 CE2 OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 1 IS62LV1024L/LL PIN CON.IGURATION 32-Pin SOP NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN CON.IGURATION 32-Pin 8x20mm TSOP-1 and 8x13.4mm TSOP-1 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 48-Pin 6x8mm T.-BGA PIN DESCRIPTIONS A0-A16 Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground CE1 CE2 OE WE I/O0-I/O7 NC Vcc GND 1 A B C D E F G H A0 I/O5 I/O6 GND Vcc I/O7 I/O8 A9 2 A1 A2 3 CE2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O1 I/O2 Vcc GND NC OE A10 CE1 A11 NC A16 A12 A15 A13 I/O3 I/O4 A14 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 2.7V to 3.6V 2.7V to 3.6V 2 Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 IS62LV1024L/LL TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB, ISB ISB, ISB ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.5 –0.3 to +4.6 –40 to +85 –65 to +150 0.7 Unit V V °C °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit p. p. Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 2.1 mA Min. 2.2 — 2.2 –0.3 –1 –1 Max. — 0.4 VCC + 0.3 0.4 1 1 Unit V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC Notes: 1. VIL = –3.0V for pulse width less than 10 ns. Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 3 IS62LV1024L/LL IS62LV1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. -45L ns Min. Max. — — — — — — 40 45 0.3 0.4 50 75 -55L ns Min. Max. — — — — — — 35 40 0.3 0.4 50 75 -70L ns Min. Max. — — — — — — 30 35 0.3 0.4 50 75 Unit mA mA VCC = Max., Com. VIN = VIH or VIL, CE1 ≥ VIH Ind. or CE2 ≤ VIL, f = 0 VCC = Max., f = 0 Com. CE1 ≥ VCC – 0.2V, Ind. CE2 ≤ 0.2V, or VIN ≥ VCC – 0.2V, VIN ≤ 0.2V ISB µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. IS62LV1024LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. -45LL ns Min. Max. — — — — — — 40 45 0.2 0.3 5 10 -55LL ns Min. Max. — — — — — — 35 40 0.2 0.3 5 10 -70LL ns Min. Max. — — — — — — 30 35 0.2 0.3 5 10 Unit mA mA VCC = Max., Com. VIN = VIH or VIL, CE1 ≥ VIH Ind. or CE2 ≤ VIL, f = 0 VCC = Max., f = 0 Com. CE1 ≥ VCC – 0.2V, Ind. CE2 ≤ 0.2V, or VIN ≥ VCC – 0.2V, VIN ≤ 0.2V ISB µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 IS62LV1024L/LL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -45 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1 Access Time CE2 Access Time OE Access Time   -55 Min. 55 — 10 — — — 5 0 7 7 0 Max. — 55 — 55 55 25 — 20 — — 20 Min. 70 — 10 — — — 5 0 10 10 0 -70 Max. — 70 — 70 70 35 — 25 — — 25 Unit ns ns ns ns ns ns ns ns ns ns ns Min. 45 — 10 — — — 0 0 5 5 0 Max. — 45 — 45 45 20 — 15 — — 15 tRC tAA tOHA tACE tACE tDOE tLZOE tHZOE tLZCE tHZCE OE to Low-Z Output OE to High-Z Output CE2 to Low-Z Output CE1 or CE2 to High-Z Output tLZCE  CE1 to Low-Z Output   Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in .igure 1. 2. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and .all Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.5V See .igures 1 AC TEST LOADS 1 TTL OUTPUT 100 pF Including jig and scope .igure 1. Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 1 TTL OUTPUT 5 pF Including jig and scope .igure 2. 5 IS62LV1024L/LL AC WAVE.ORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE1 tACE1/tACE2 tLZOE CE2 tLZCE1/ tLZCE2 HIGH-Z tHZCE DATA VALID DOUT Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. 6 Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 IS62LV1024L/LL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power) -45 Symbol Parameter Write Cycle Time CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time " -55 Min. 55 50 50 50 0 0 40 25 0 — 5 Max. — — — — — — — — — 20 — Min. 70 60 60 60 0 0 55 30 0 0 5 -70 Max. — — — — — — — — — 25 — Unit ns ns ns ns ns ns ns ns ns ns ns Min. 45 35 35 35 0 0 35 25 0 — 5 Max. — — — — — — — — — 15 — tWC tSCE tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE   WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in .igure 1. 2. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVE.ORMS WRITE CYCLE NO. 1 (9- Controlled)(1,2) tWC ADDRESS tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE(4) tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 7 IS62LV1024L/LL WRITE CYCLE NO. 2 (+-, CE2 Controlled)(1,2) tWC ADDRESS tSA tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE(4) WE tHZWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Vcc for Data Retention Data Retention Current Test Condition See Data Retention Waveform Vcc = 2.0V, CE1 ≥ Vcc – 0.2V Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) Min. 2.0 — — — — 0 Max. 3.6 30 5 50 10 — — Unit V µA µA µA µA ns ns VDR IDR tSDR tRDR Data Retention Setup Time Recovery Time See Data Retention Waveform See Data Retention Waveform tRC DATA RETENTION WAVE.ORM (+- Controlled) tSDR VCC Data Retention Mode tRDR 3.0V 2.2V VDR CE1 ≥ VCC - 0.2V CE1 GND 8 Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 IS62LV1024L/LL DATA RETENTION WAVE.ORM (CE2 Controlled) Data Retention Mode VCC tSDR tRDR 3.0V CE2 2.2V VDR 0.4V GND CE2 ≤ 0.2V IS62LV1024L ORDERING IN.ORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 45 IS62LV1024L-45Q IS62LV1024L-45T IS62LV1024L-45H IS62LV1024L-45B IS62LV1024L-55Q IS62LV1024L-55T IS62LV1024L-55H IS62LV1024L-55B IS62LV1024L-70Q IS62LV1024L-70T IS62LV1024L-70H IS62LV1024L-70B Package 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA IS62LV1024L ORDERING IN.ORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 45 IS62LV1024L-45QI IS62LV1024L-45TI IS62LV1024L-45HI IS62LV1024L-45BI IS62LV1024L-55QI IS62LV1024L-55TI IS62LV1024L-55HI IS62LV1024L-55BI IS62LV1024L-70QI IS62LV1024L-70TI IS62LV1024L-70HI IS62LV1024L-70BI Package 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 55 55 70 70 Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 9 IS62LV1024L/LL IS62LV1024LL ORDERING IN.ORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 45 IS62LV1024LL-45Q IS62LV1024LL-45T IS62LV1024LL-45H IS62LV1024LL-45B IS62LV1024LL-55Q IS62LV1024LL-55T IS62LV1024LL-55H IS62LV1024LL-55B IS62LV1024LL-70Q IS62LV1024LL-70T IS62LV1024LL-70H IS62LV1024LL-70B Package 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA IS62LV1024LL ORDERING IN.ORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 45 IS62LV1024LL-45QI IS62LV1024LL-45TI IS62LV1024LL-45HI IS62LV1024LL-45BI IS62LV1024LL-55QI IS62LV1024LL-55TI IS62LV1024LL-55HI IS62LV1024LL-55BI IS62LV1024LL-70QI IS62LV1024LL-70TI IS62LV1024LL-70HI IS62LV1024LL-70BI Package 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm T.-BGA 55 55 70 70 HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 .ax: 886-3-5783000 Integrated Circuit Solution Inc. BRANCH O..ICE: 7., NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 .AX: 886-2-26962252 http://www.icsi.com.tw 10 Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001