M2006-02A

Integrated Circuit Systems, Inc. Product Data Sheet M2006-02A VCSO BASED FEC CLOCK PLL PIN ASSIGNMENT (9 x 9 mm SMT) FIN_SEL1 GND NC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19 GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication ratios are pin-selected from pre-programming look-up tables. FEATURES ◆ Reduced intrinsic output jitter and improved power supply noise rejection compared to M2006-02 ◆ Low phase jitter of 0.25 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz) ◆ Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including: • 255/238 (OTU1) Mapping and 238/255 De-mapping • 255/237 (OTU2) Mapping and 237/255 De-mapping • 255/236 (OTU3) Mapping and 236/255 De-mapping 28 29 30 31 32 33 34 35 36 M2006-02A (Top View) 18 17 16 15 14 13 12 11 10 P0_SEL P1_SEL nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND Figure 1: Pin Assignment ◆ Input reference and VCSO frequencies up to 700MHz, supports loop timing modes (Specify VCSO frequency at time of order) ◆ Supports active switching between inverse-FEC and non-FEC clock ratios (same VCSO center frequency) ◆ Ideal for complex ratio FEC ratio translation and for use with an unstable reference (i.e., similar to the M2006-12A - and pin-compatible - but without the Hitless Switching and Phase Build-out functions) ◆ Single 3.3V power supply ◆ Small 9 x 9 mm SMT (surface mount) package Example I/O Clock Combinations Using M2006-02A-622.0800 PLL Ratio 1/1 237/255 (inverse FEC) Input Clock (MHz) 622.08, 155.52, 77.76, or 19.44 669.3266, 167.3316, 83.6658, or 20.9165 Output Clock (MHz) 622.08 or 155.52 Table 1: Example I/O Clock Combinations Using M2006-02A-622.0800 Using M2006-02A-669.3266 PLL Ratio 237/255 (FEC rate) 1/1 Input Clock (MHz) 622.08, 155.52, 77.76, or 19.44 669.3266, 167.3316, 83.6658, or 20.9165 Output Clock (MHz) 669.3266 or 167.3316 Table 2: Example I/O Clock Combinations Using M2006-02A-669.3266 SIMPLIFIED BLOCK DIAGRAM Loop Filter M2006-02A DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL 4 2 0 Rfec Div 1 Mfec Div Mfin Div (1, 4, 8, or 32) GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN 1 2 3 4 5 6 7 8 9 VCSO P0 Div (1 or 4) FOUT0 nFOUT0 FEC_SEL3:0 FIN_SEL1:0 Mfec / Rfec Divider LUT Mfin Divider LUT P0_SEL P1 Div (1 or 4) FOUT1 nFOUT1 P1_SEL Figure 2: Simplified Block Diagram M2006-02A Datasheet Rev 1.0 M2006-02A VCSO Based FEC Clock PLL Revised 28Jul2004 ● Integrated Circuit Systems, Inc. Networking & Communications ● w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M2006-02A VCSO BASED FEC CLOCK PLL Product Data Sheet DETAILED BLOCK DIAGRAM RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP OP_OUT RPOST nOP_OUT nVC VC External Loop Filter Components M2006-02 A MUX OP_IN Phase Detector nOP_IN DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL RIN 0 Rfec Divider RIN Loop Filter Amplifier 1 Phase Locked Loop (PLL) SAW Delay Line Phase Shifter VCSO Mfec Divider Mfin Divider P0 Divider FOUT0 nFOUT0 FEC_SEL3:0 4 Mfec / Rfec Divider LUT Mfin Divider LUT P = 1 ( P0_SEL = 0 ) or 4 ( P0_SEL = 1 ) FIN_SEL1:0 2 P1 Divider P = 1 ( P1_SEL = 0 ) or 4 ( P1_SEL = 1 ) FOUT1 nFOUT1 P0_SEL P1_SEL Figure 3: Detailed Block Diagram PIN DESCRIPTIONS Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12, 13 15, 16 17 18 20 21 22 23 24 25 27 28 29 30 31 32 34, 35, 36 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC FOUT1, nFOUT1 FOUT0, nFOUT0 P1_SEL P0_SEL nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 NC FIN_SEL1 FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 DNC I/O Configuration Description Ground Input Output Input Power Output Input Input Input Input No internal terminator Internal pull-down resistor1 Internal pull-UP resistor1 Internal pull-down resistor1 Internal pull-down resistor1 Internal pull-UP resistor1 Internal pull-down resistor 1 Power supply ground connections. External loop filter connections. See Figure 4. Power supply connection, connect to +3.3V. Clock output pairs. Differential LVPECL. P Divider controls. LVCMOS/LVTTL. (For P0_SEL, P1_SEL, see Table 6 on pg. 3. Reference clock input pair 1. Differential LVPECL or LVDS. Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. Reference clock input pair 0. Differential LVPECL or LVDS. No internal connection. Input clock frequency selection. LVCMOS/LVTTL. (For FIN_SEL1:0, see Table 4 on pg. 3. FEC PLL divider ratio selection. LVCMOS/ LVTTL. (For FEC_SEL3:0, see Table 5 on pg. 3.) Internal nodes. Connection to these pins can cause erratic device operation. Table 3: Pin Descriptions Input Internal pull-down resistor1 Internal pull-UP resistor1 Do Not Connect. Input M2006-02A Datasheet Rev 1.0 Integrated Circuit Systems, Inc. ● 2 of 8 Networking & Communications ● Revised 28Jul2004 w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M2006-02A VCSO BASED FEC CLOCK PLL Product Data Sheet Post-PLL Dividers The M2006-02A also features two post-PLL dividers, one for each output pair. The “P1” divider is for FOUT1 and nFOUT1; the “P0” divider is for FOUT0 and nFOUT0. Each divides the VCSO frequency to produce one of two output frequencies (1/4 or 1/1 of the VCSO frequency). The P1_SEL and P0_SEL pins each select the value for their corresponding divider. M2006-02A-622.0800 PLL DIVIDER LOOK-UP TABLES Mfin Divider Look-Up Table (LUT) The FIN_SEL1:0 pins select the feedback divider value “Mfin” (for Frequency Input). FIN_SEL1:0 Mfin Value 1* 4 8 32 M2006-02A-622.0800 1 1 0 0 1 0 1 0 Sample Ref. Freq. (MHz) † 622.08 155.52 77.76 19.44 P1_SEL, P0_SEL P Value 4 1 Table 4: Mfin Divider Look-Up Table (LUT) Note *: Do not use with FEC_SEL3:0=1100 or 1101 or an excessive phase detector frequency will result. Note †: Example with M2006-02A-622.0800 and “Non-FEC ratio” selection made from Table 5 (FEC_SEL2=1). 1 0 Sample Output Frequency (MHz) 155.52 622.08 Table 6: P Divider Selector, Values, and Frequencies FEC PLL Ratio Dividers Look-up Table (LUT) The FEC_SEL3:0 pins select the FEC feedback and reference divider values Mfec and Rfec. FEC_SEL3:0 Mfec Rfec1 FUNCTIONAL DESCRIPTION The M2006-02A is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW filter provides low jitter signal performance and controls the output frequency of the VCSO (Voltage Controlled SAW Oscillator). Configurable FEC feedback and reference dividers (the “Mfec Divider” and “Rfec Divider”) provide the multiplication ratios necessary to accomodate clock translation for both forward and inverse Forward Error Correction. In addition, a configurable feedback divider (labeled “Mfin Divider”) provides the broader division options needed to accomodate various reference clock frequencies. For example, the M2006-02A-622.0800 (see “Ordering Information” on pg. 8) has a 622.08MHz VCSO frequency: Description Inverse FEC ratio Inverse FEC ratio, equivalent to 237/255 Inverse FEC ratio, equivalent to 238/255 Inverse FEC ratio Non-FEC ratio, complements 0001 or 1001 2 Non-FEC ratio, complements 0010 or 1010 2 Non-FEC ratio, complements 0011 or 1011 2 FEC ratio (OTU3) FEC ratio, equivalent to 255/237 (OTU2) FEC ratio, equivalent to 255/238 (OTU1) FEC ratio Non-FEC ratio 3 Do not use these two settings with FIN_SEL1:0=11 Non-FEC ratio 3 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 236 79 14 239 236 79 14 239 255 85 15 255 1 2 4 8 255 85 15 255 79 14 239 236 79 14 239 1 2 4 8 0100 0101 0110 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 236 Non-FEC ratio, complements 0000 or 1000 2 • The inverse FEC PLL ratios (at top of Table 5) enable the M2006-02A-622.0800 to accept “base” input reference frequencies of: 663.7255, 666.5143, 669.3266, 672.1627, and 622.08MHz. The Mfin feedback divider enables the actual input reference clock to be the “base” input frequency divided by 1, 4, 8, or 32. Therefore, for the base input frequency of 622.08MHz, the actual input reference clock frequencies can be: 622.08, 155.52, 77.76, and 19.44MHz. (See Table 4 on pg. 3.) Table 5: FEC PLL Ratio Dividers Look-up Table (LUT) Note 1: The phase detector frequency (Fpd, which is calculated as Fref/Rfec) should be above 1.5 MHz to prevent spurs on the output clock. To ensure the PLL remains locked when using a recovered clock (such as in loop timing mode), the phase detector frequency should ideally be about 20MHz, or at least less than 50 MHz. Note 2: These table selections use the same or similar Mfec divider values as the complementary selections noted. This allows the use of the same loop filter component values and yields the same PLL loop bandwidth and damping factor values for complementary selections. Complementary selections can be actively switched in a given application. Note 3: In non-FEC applications, these settings can be used to optimize phase detector frequency or to actively change PLL loop bandwidth. • M2006-02A Datasheet Rev 1.0 Integrated Circuit Systems, Inc. ● 3 of 8 Networking & Communications ● Revised 28Jul2004 w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. The PLL The PLL uses a phase detector and configurable dividers to synchronize the output of the VCSO with selected reference clock. The “Mfin Divider” and “Mfec Divider” divide the VCSO frequency, feeding the result into the phase detector. The selected input reference clock is divided by the “Rfec Divider”. The result is fed into the other input of the phase detector. The phase detector compares its two inputs. It then outputs pulses to the loop filter as needed to increase or decrease the VCSO frequency and thereby match and lock the divider output’s frequency and phase to those of the input reference clock. Due to the narrow tuning range of the VCSO (+200ppm), appropriate selection of all of the following are required for the PLL be able to lock: VCSO center frequency, input frequency, and divider selections. Maintaining PLL Lock: M2006-02A VCSO BASED FEC CLOCK PLL Product Data Sheet Relationship Among Frequencies and Dividers The VCSO center frequency must be specified at time of order. The relationship between the VCSO (Fvcso) frequency, the Mfin divider, the Mfec divider, the Rfec divider, and the input reference frequency (Fin) is: M fec Fvcso = Fin × Mfin × ------------Rfec As an example, for the M2006-02A-622.0800, the non-FEC and inverse-FEC PLL ratios in Table 5 enable use with these corresponding input reference frequencies: VCSO Clock Frequency (MHz) 622.08 M2006-02A-622.0800 ÷ FEC Ratio 1 /1 238 / 255 237 / 255 236 / 255 Base Input Ref. = Frequency (MHz) 1 622.0800 666.5143 669.3266 672.1627 M2006-02A-622.0800 Table 7: Example FEC PLL Rations and Input Reference Frequencies Note 1: Input reference clock (“Fin”) can be the base frequency shown divided by “Mfin” (as shown in Table 4 on pg. 3). The narrow tuning range of the VCSO requires that the input reference frequency must remain suitable for the current look-up table selection. For example, when switching between “Inverse FEC ratio” and “Non-FEC ratio” look-up table selections (see Table 5 on pg. 3), the input reference frequency must change accordingly in order for the PLL to lock. An out-of-lock condition due to an inappropriate configuration will typically result in the VCSO operating at its lower or upper frequency rail, which is approximately 200ppm above or below the nominal VCSO center frequency. Outputs The M2006-02A provides a total of two differential LVPECL output pairs: FOUT1 and FOUT0. Because each output pair has its own P divider, the FOUT1 pair and the FOUT0 can output the two different frequencies at the same time. For example, FOUT1 can output 155.52MHz while FOUT0 outputs 622.08MHz. Any unused output should be left unconnected (floating) in the system application. This will minimize output switching current and therefore minimize noise modulation of the VCSO. M2006-02A Datasheet Rev 1.0 Integrated Circuit Systems, Inc. ● 4 of 8 Networking & Communications ● Revised 28Jul2004 w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. External Loop Filter To provide stable PLL operation, and thereby a low jitter output clock, the M2006-02A requires the use of an external loop filter. This is provided via the provided filter pins (see Figure 4). Due to the differential signal path design, the implementation requires two identical complementary RC filters as shown here. RLOOP CLOOP RPOST M2006-02A VCSO BASED FEC CLOCK PLL Product Data Sheet PLL bandwidth is affected by loop filter component values, “Mfec” and “Mfin” values, and the “PLL Loop Constants” listed in AC Characteristics on pg. 7. The various “Non-FEC ratio” settings can be used to actively change PLL loop bandwidth in a given application. See “FEC PLL Ratio Dividers Look-up Table (LUT)” on pg. 3. See Example External Loop Filter Component Values table. PLL Simulator Tool Available CPOST CPOST RLOOP OP_IN 4 9 CLOOP OP_OUT 8 5 RPOST nOP_OUT nVC 6 7 nOP_IN VC A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application. Go to the SAW PLL Simulator Software web page at www.icst.com/products/calculators/m2000filterSWdesc.htm Figure 4: External Loop Filter Example External Loop Filter Component Values1 VCSO Parameters: KVCO = 800kHz/V, RIN = 50kΩ, VCSO Bandwidth = 700kHz. Device Configuration (MHz) Example External Loop Filter Component Values pins Nominal Performance Using These Values FRef FVCSO (MHz) FIN_SEL1:0 FEC_ SEL3:0 pins R loop 11.5kΩ C loop 2.2µF R post 34kΩ C post 470pF PLL Loop Bandwidth 1kHz Damping Passband Factor Peaking (dB) 6.0 0.05 19.44 77.76 155.52 622.08 167.3317 669.3266 155.52 622.08 622.08 00 01 10 11 10 11 1100 1110 1111 0110 0001 1001 5.11kΩ 113.0kΩ 28.0kΩ 121.0kΩ 30.1kΩ 4.7µF 0.22µF 1.0µF 0.22µF 1.0µF 6.0 6.0 6.3 6.0 6.5 0.06 0.06 0.05 0.05 0.05 669.3266 10 11 Table 8: Example External Loop Filter Component Values Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com. ABSOLUTE MAXIMUM RATINGS1 Symbol Parameter Rating Unit VI VO VCC TS Inputs Outputs Power Supply Voltage Storage Temperature -0.5 to VCC +0.5 -0.5 to VCC +0.5 4.6 V V V oC -45 to +100 Table 9: Absolute Maximum Ratings Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. M2006-02A Datasheet Rev 1.0 Integrated Circuit Systems, Inc. ● 5 of 8 Networking & Communications ● Revised 28Jul2004 w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M2006-02A VCSO BASED FEC CLOCK PLL Product Data Sheet RECOMMENDED CONDITIONS OF OPERATION Symbol Parameter Min 3.135 Typ 3.3 Max 3.465 Unit VCC TA Positive Supply Voltage Ambient Operating Temperature Commercial Industrial V o o 0 -40 +70 +85 C C Table 10: Recommended Conditions of Operation ELECTRICAL SPECIFICATIONS DC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50Ω to VCC - 2V Symbol Parameter Min 3.135 Typ 3.3 175 Max 3.465 225 Unit Conditions Power Supply VCC ICC All Differential Inputs Differential Inputs with Pull-down Differential Inputs with Pull-up All LVCMOS / LVTTL Inputs LVCMOS / LVTTL Inputs with Pull-down LVCMOS / LVTTL Inputs with Pull-up Differential Outputs VP-P VCMR CIN IIH IIL IIH IIL Rpullup VIH VIL CIN IIH IIL IIH IIL Rpullup VOH VOL VP-P Positive Supply Voltage Power Supply Current Peak to Peak Input Voltage Common Mode Input Input Capacitance Input High Current (Pull-down) Input Low Current (Pull-down) Input High Current (Pull-up) Input Low Current (Pull-up) Internal Pull-up Resistance Input High Voltage Input Low Voltage Input Capacitance Input High Current (Pull-down) Input Low Current (Pull-down) Input High Current (Pull-up) Input Low Current (Pull-up) Internal Pull-up Resistance Output High Voltage Output Low Voltage Peak to Peak Output Voltage 1 FOUT0, nFOUT0, FOUT1, nFOUT1 FEC_SEL3, FEC_SEL2, FEC_SEL1, FEC_SEL0 REF_SEL, FIN_SEL1, FIN_SEL0, P1_SEL, P0_SEL REF_SEL, FIN_SEL1, FIN_SEL0, FEC_SEL3, FEC_SEL2, FEC_SEL1, FEC_SEL0, P1_SEL, P0_SEL nDIF_REF0, nDIF_REF1 DIF_REF0, DIF_REF1 DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 V mA V 0.15 0.5 Vcc - .85 V 4 150 pF µA µA kΩ VCC = VIN = 3.456V -5 50 5 Rpulldown Internal Pull-down Resistance -150 µA µA kΩ VIN = 0 to 3.456V 50 2 Vcc + 0.3 V 0.8 4 150 -0.3 V pF µA µA kΩ VCC = VIN = 3.456V -5 50 Rpulldown Internal Pull-down Resistance -150 5 50 Vcc - 1.4 Vcc - 2.0 0.4 µA µA kΩ VCC = 3.456V VIN = 0 V Vcc - 1.0 V Vcc - 1.7 V 0.85 V Note 1: Single-ended measurement. See Figure 5, Output Rise and Fall Time, on pg. 7. Table 11: DC Characteristics M2006-02A Datasheet Rev 1.0 Integrated Circuit Systems, Inc. ● 6 of 8 Networking & Communications ● Revised 28Jul2004 w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M2006-02A VCSO BASED FEC CLOCK PLL Product Data Sheet ELECTRICAL SPECIFICATIONS (CONTINUED) AC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50Ω to VCC - 2V Symbol Parameter Min DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 FOUT0, nFOUT0, FOUT1, nFOUT1 Commercial Industrial 10 Typ Max 700 Unit Test Conditions Input Frequency Range Output Frequency FIN Input Frequency MHz FFOUT APR Output Frequency Range VCSO Pull-Range VCO Gain Internal Loop Resistor Single Side Band Phase Noise @622.08MHz Jitter (rms) @622.08MHz Output Duty Cycle FOUT0, nFOUT0, FOUT1, nFOUT1 2 100 700 MHz ppm ppm kHz/V kΩ kHz dBc/Hz Fin=19.44 MHz dBc/Hz Mfin=32, Mfec=1, Rfec=1 dBc/Hz ps rms ps rms % % ps ps 20% to 80% 20% to 80% ±120 ±50 ±200 ±150 800 50 700 PLL Loop Constants 1 KVCO RIN Φn BWVCSO VCSO Bandwidth 1kHz Offset 10kHz Offset 100kHz Offset 12kHz to 20MHz 50kHz to 80MHz P0, P1 = 1 P0, P1 = 4 Phase Noise and Jitter J(t) tPW tR tF -73 -103 -126 0.25 0.25 40 45 200 200 50 50 450 450 0.5 0.5 60 55 500 500 Output Rise Time 2 Output Fall Time 2 FOUT0, nFOUT0, FOUT1, nFOUT1 Table 12: AC Characteristics Note 1: Parameters needed for PLL Simulator software; see Table 8, Example External Loop Filter Component Values, on pg. 5. Note 2: See Parameter Measurement Information on pg. 7. PARAMETER MEASUREMENT INFORMATION Output Rise and Fall Time Output Duty Cycle nFOUT FOUT VP-P Clock Output 20% tR 20% tF odc = tPW tPERIOD tPW (Output Pulse Width) tPERIOD 80% 80% Figure 5: Output Rise and Fall Time Figure 6: Output Duty Cycle M2006-02A Datasheet Rev 1.0 Integrated Circuit Systems, Inc. ● 7 of 8 Networking & Communications ● Revised 28Jul2004 w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. Product Data Sheet M2006-02A VCSO BASED FEC CLOCK PLL DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER Mechanical Dimensions: Refer to the SAW PLL application notes web page at www.icst.com/products/appnotes/SawPllAppNotes.htm for application notes, including recommended PCB footprint, solder mask, and furnace profile. Figure 7: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier ORDERING INFORMATION Part Numbering Scheme Part Number: Device Number Temperature “ - ” = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) VCSO Frequency (MHz) See Table 13, right. Consult ICS for other frequencies. Standard VCSO Output Frequencies (MHz)* Consult ICS for the availablity of other VCSO frequencies M2006- 02A - xxx.xxxx 622.0800 625.0000 627.3296 644.5313 666.5143 669.1281 669.3120 669.3266 669.6429 670.8386 672.1600 690.5692 Figure 8: Part Numbering Scheme Table 13: Standard VCSO Output Frequencies (MHz) Note *: Fout can equal Fvcso divided by: 1 or 4 Consult ICS for the availability of other PLL frequencies. Example Part Numbers PLL Frequency (MHz) 622.08 625.00 669.3266 669.6429 Temperature commercial industrial commercial industrial commercial industrial commercial industrial Order Part Number M2006-02A - 622.0800 M2006-02AI622.0800 M2006-02A - 625.0000 M2006-02AI625.0000 M2006-02A - 669.3266 M2006-02AI669.3266 M2006-02A - 669.6429 M2006-02AI669.6429 Table 14: Example Part Numbers While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M2006-02A Datasheet Rev 1.0 Integrated Circuit Systems, Inc. ● 8 of 8 Networking & Communications ● Revised 28Jul2004 w w w. i c s t . c o m ● tel (508) 852-5400