MX29LV033MTI-70R

PRELIMINARY MX29LV033M 32M-BIT SINGLE VOLTAGE 3V ONLY UNIFORM SECTOR FLASH MEMORY FEATURES GENERAL FEATURES • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Configuration - 4,194,304 x 8 byte structure • Sector structure - 64KB x 64 • Sector Protection/Chip Unprotect - Provides sector group protect function to prevent program or erase operation in the protected sector group - Provides chip unprotect function to allow code changes - Provides temporary sector group unprotect function for code changes in previously protected sector groups • Secured Silicon Sector - Provides a 256-byte OTP area for permanent, secure identification - Can be programmed and locked at factory or by customer • Latch-up protected to 250mA from -1V to VCC + 1V • Low VCC write inhibit is equal to or less than 1.5V • Compatible with JEDEC standard - Pin-out and software compatible to single power supply Flash PERFORMANCE • High Performance - Fast access time: 70R/90ns - Page read time: 25ns - Sector erase time: 0.5s (typ.) - Effective write buffer byte programming time: 11us - 8 byte page read buffer - 32 byte write buffer: reduces programming time for multiple-byte updates • Low Power Consumption - Active read current: 18mA(typ.) - Active write current: 50mA(typ.) - Standby current: 20uA(typ.) • Minimum 100,000 erase/program cycle • 20-year data retention SOFTWARE FEATURES • Support Common Flash Interface (CFI) - Flash device parameters stored on the device and provide the host system to access. • Program Suspend/Program Resume - Suspend program operation to read other sectors • Erase Suspend/Erase Resume - Suspends sector erase operation to read or program other sectors • Status Reply - Data# polling & Toggle bits provide detection of program and erase operation completion HARDWARE FEATURES • Ready/Busy (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode • ACC input - ACC (high voltage) accelerates programming time for higher throughput during system PACKAGE • 40-pin TSOP GENERAL DESCRIPTION The MX29LV033M is a 32-mega bit Flash memory organized as 4M bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory. The MX29LV033M is packaged in 40-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LV033M offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV033M has separate chip enable (CE#) and P/N:PM1143 REV. 0.02, MAR. 23, 2005 1 MX29LV033M output enable (OE#) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV033M uses a command register to manage this functionality. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29LV033M uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V. fication of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASE The MX29LV033M is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# . MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29LV033M electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set. AUTOMATIC PROGRAMMING The MX29LV033M is byte/page programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA# polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 50 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and veri- P/N:PM1143 REV. 0.02, MAR. 23, 2005 2 MX29LV033M PIN CONFIGURATION 40 TSOP A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# ACC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS A20 A19 A10 Q7 Q6 Q5 Q4 VCC VCC A21 Q3 Q2 Q1 Q0 OE# VSS CE# A0 LOGIC SYMBOL 22 A0-A21 Q0-Q7 8 MX29LV033M CE# OE# WE# RESET# ACC RY/BY# PIN DESCRIPTION SYMBOL A0~A21 Q0~Q7 CE# WE# OE# RESET# RY/BY# VCC ACC VSS NC PIN NAME Address Input 8 Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Hardware Reset Pin, Active Low Read/Busy Output +3.3V single power supply Hardware Acceleration Pin Device Ground Pin Not Connected Internally P/N:PM1143 REV. 0.02, MAR. 23, 2005 3 MX29LV033M BLOCK DIAGRAM CE# OE# WE# RESET# WRITE CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE X-DECODER STATE FLASH ARRAY ARRAY REGISTER ADDRESS LATCH A0-A21 AND BUFFER SENSE AMPLIFIER Y-DECODER Y-PASS GATE SOURCE HV COMMAND DATA DECODER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q7 I/O BUFFER P/N:PM1143 REV. 0.02, MAR. 23, 2005 4 MX29LV033M SECTOR (GROUP) STRUCTURE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8-bit Address Range (in hexadecimal) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF 200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF P/N:PM1143 REV. 0.02, MAR. 23, 2005 5 MX29LV033M Sector SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A18 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A17 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8-bit Address Range (in hexadecimal) 260000-26FFFF 270000-27FFFF 280000-28FFFF 290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3FFFFF P/N:PM1143 REV. 0.02, MAR. 23, 2005 6 MX29LV033M MX29LV033M Sector Group Protection Address Table Sector Group SA0-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA63 A21-A17 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 P/N:PM1143 REV. 0.02, MAR. 23, 2005 7 MX29LV033M Table 1. BUS OPERATION (1) Operation Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset Sector Group Protect (Note 2) CE# L L L VCC ±0.3V L X L OE# L H H X H X H WE# H L L X H X L RESET# H H H VCC±0.3V H L VID ACC X X VHH H X X X Address AIN AIN AIN X X X Sector Addresses, A6=L,A3=L, A2=L, A1=H,A0=L Chip unprotect (Note 2) L H L VID X Sector Addresses, A6=H, A3=L, A2=L, A1=H, A0=L Temporary Sector Group Unprotect X X X VID X AIN (Note 3) (Note 3) Q0~Q7 DOUT (Note 3) (Note 3) High-Z High-Z High-Z (Note 3) Legend: L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0 ± 0.5V, VHH=12.0 ± 0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN, DOUT=Data OUT Notes: 1. Address are A21:A0. Sector addresses are A21:A16. 2. The sector group protect and chip unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Chip Unprotect" section. 3. DIN or DOUT as required by command sequence, Data# polling or sector protect algorithm (see Figure 15). P/N:PM1143 REV. 0.02, MAR. 23, 2005 8 MX29LV033M Table 2. AUTOSELECT CODES (High Voltage Method) A21 Description CE# OE# WE# to A15 Manufacturer ID 29LV033M A14 to A10 X VID A9 A8 to A7 X L A6 A5 to A4 X A3 to A2 L L L L H H H L H L H L C2h 7Eh 1Ch 00h 01h (protected), 00h (unprotected) 90h A1 A0 Q7 to Q0 L L H X Cycle 1 Cycle 2 Cycle 3 L L H SA X VID X L X L L H X X VID X L X H H L Sector Protection Verification Secured Silicon Sector Indicator Bit (Q7) L L H X X VID X L X L H H (factory locked), 10h (not factory locked) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. P/N:PM1143 REV. 0.02, MAR. 23, 2005 9 MX29LV033M REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the Automatic Select command sequence, the device enters the Automatic Select mode. The system can then read Automatic Select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. PAGE MODE READ The MX29LV033M offers "fast page mode read" function. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 bytes. The appropriate page is selected by the higher address bits A-1~A1. This is an asynchronous operation; the microprocessor supplies the specific word location. The system performance could be enhanced by initiating 1 normal read and 7 fast page read. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses. WRITE BUFFER Write Buffer Programming allows the system to write a maximum of 32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See "Write Buffer" for more information. ACCELERATED PROGRAM OPERATION The device offers accelerated program operations through the ACC function. This is one of two functions provided by the ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. WRITING COMMANDS/COMMAND QUENCES SE- To program data to the device or erase sectors of memory, the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. Table indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands P/N:PM1143 REV. 0.02, MAR. 23, 2005 10 MX29LV033M STANDBY MODE When using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at VCC ± 0.3V. If CE# and RESET# are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, VCC active current (ICC2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data. but not within VSS±0.3V, the standby current will be greater. The RESET# pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 3 for the timing diagram. AUTOMATIC SLEEP MODE The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when address remain stable for tACC+30ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. SECTOR GROUP PROTECT OPERATION The MX29LV033M features hardware sector group protection. This feature will disable both program and erase operations for these sector group protected. In this device, a sector group consists of four adjacent sectors which are protected or unprotected at the same time. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE#, (suggest VID = 12V) A6 = VIL and CE# = VIL. (see Table 2) Programming of the protection circuitry begins on the falling edge of the WE# pulse and is terminated on the rising edge. Please refer to sector group protect algorithm and waveform. MX29LV033M also provides another method. Which requires VID on the RESET# only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE# and OE# at VIL and WE# at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes. (Read Silicon ID) OUTPUT DISABLE With the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. RESET# OPERATION The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL P/N:PM1143 REV. 0.02, MAR. 23, 2005 11 MX29LV033M It is also possible to determine if the group is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector. the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. MX29LV033M provides hardware method to access the silicon ID read operation. Which method requires VID on A9 pin, VIL on CE#, OE#, A6, and A1 pins. Which apply VIL on A0 pin, the device will output MXIC's manufacture code. Which apply VIH on A0 pin, the device will output MX29LV033M device code. CHIP UNPROTECT OPERATION The MX29LV033M also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. To activate this mode, the programming equipment must force VID on control pin OE# and address pin A9. The CE# pins must be set at VIL. Pins A6 must be set to VIH. (see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotect mechanism begins on the falling edge of the WE# pulse and is terminated on the rising edge. MX29LV033M also provides another method. Which requires VID on the RESET# only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. It is also possible to determine if the chip is unprotect in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs (Q0-Q7) for an unprotect sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed. VERIFY SECTOR GROUP PROTECT STATUS OPERATION MX29LV033M provides hardware method for sector group protect status verify. Which method requires VID on A9 pin, VIH on WE# and A1 pins, VIL on CE#, OE#, A6, and A0 pins, and sector address on A16 to A21 pins. Which the identified sector is protected, the device will output 01H. Which the identified sector is not protect, the device will output 00H. DATA PROTECTION The MX29LV033M is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. TEMPORARY SECTOR GROUP UNPROTECT OPERATION This feature allows temporary unprotect of previously protected sector to change data in-system. The Temporary Sector Unprotect mode is activated by setting the RESET# pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased as unprotect sector. Once VID is remove from the RESET# pin, all the previously protected sectors are protected again. SECURED SILICON SECTOR The MX29LV033M features a OTP memory region where the system may access through a command sequence to create a permanent part identification as so called Electronic Serial Number (ESN) in the device. Once this region is programmed, any further modification on the region is impossible. The secured silicon sector is a 256 bytes in length, and uses a Secured Silicon Sector Indi- SILICON ID READ OPERATION Flash memories are intended for use in applications where P/N:PM1143 REV. 0.02, MAR. 23, 2005 12 MX29LV033M cator Bit (Q7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevent duplication of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. The MX29LV033M offers the device with Secured Silicon Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory , and has the Secured Silicon Sector Indicator Bit permanently set to a "1". The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to utilize that sector in any form they prefer. The customer-lockable version has the secured sector Indicator Bit permanently set to a "0". Therefore, the Secured Silicon Sector Indicator Bit prevents customer, lockable device from being used to replace devices that are factory locked. The system access the Secured Silicon Sector through a command sequence (refer to "Enter Secured Silicon/ Exit Secured Silicon Sector command Sequence). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the address normally occupied by the first sector SA0. Once entry the Secured Silicon Sector the operation of boot sectors is disabled but the operation of main sectors is as normally. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending command to sector SA0. Secured Silicon Sector address range 000000h-00000Fh 000010h-0000FFh ESN Unavailable Determined by Customer ESN factory locked Customer lockable way. A factory locked device has an 16-byte random ESN at address 000000h-00000Fh. CUSTOMER LOCKABLE:Secured Silicon Sector NOT Programmed or Protected At the Factory As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 256 bytes Secured Silicon Sector. Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotected the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. The Secured Silicon Sector area can be protected using one of the following procedures: Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 15, except that RESET# may be at either VIH or VID. This allows insystem protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that method is only applicable to the Secured Silicon Sector. Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then alternate method of sector protection described in the :Sector Group Protection and Unprotect" section. Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. LOW VCC WRITE INHIBIT When VCC is less than VLKO the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional write when VCC is greater than VLKO. FACTORY LOCKED:Secured Silicon Sector Programmed and Protected At the Factory In device with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any P/N:PM1143 REV. 0.02, MAR. 23, 2005 13 MX29LV033M WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns (typical) on CE# or WE# will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one. POWER-UP SEQUENCE The MX29LV033M powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. POWER-UP WRITE INHIBIT If WE#=CE#=VIL and OE#=VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. POWER SUPPLY DE COUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND. P/N:PM1143 REV. 0.02, MAR. 23, 2005 14 MX29LV033M SOFTWARE COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 3 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device (when applicable). All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data are latched on rising edge of WE# or CE#, whichever happens first. TABLE 3. MX29LV033M COMMAND DEFINITIONS First Bus Command Bus Cycle Second Bus Third Bus Cycle Cycle Fourth Bus Cycle Data Fifth Bus Cycle Sixth Bus Cycle Cycles Addr Data Addr Read (Note 5) Reset (Note 6) Automatic Select (Note 7) Manufacturer ID 4 XXX AA XXX 1 1 RA XXX RD F0 Data Addr Data Addr Addr Data Addr Data 55 XXX 90 X00 C2H Device ID (Note 8) Secured Sector Factory Protect Sector Group Protect Verify (Note 9) Enter Secured Silicon Sector Exit Secured Silicon Sector Program Write to Buffer (Note 10) Program Buffer to Flash Write to Buffer Abort Reset (Note 11) Chip Erase Sector Erase Program/Erase Suspend (Note 12) Program/Erase Resume (Note 13) CFI Query (Note 14) 4 XXX AA XXX 55 XXX 90 X01 7E X0E 1Ch X0F 00 4 XXX AA XXX 55 XXX 90 X03 4 XXX AA XXX 55 XXX 90 (SA)X02 00/01 3 XXX AA XXX 55 XXX 88 4 XXX AA XXX 55 XXX 90 XXX 00 4 6 1 3 XXX XXX SA XXX AA AA 29 AA XXX XXX 55 55 XXX A0 SA 25 PA SA PD BC PA PD WBL PD XXX 55 XXX F0 6 6 1 XXX XXX XXX AA AA B0 XXX XXX 55 55 XXX 80 XXX 80 XXX XXX AA AA XXX 55 XXX 55 XXX 10 SA 30 1 XXX 30 1 AA 98 P/N:PM1143 REV. 0.02, MAR. 23, 2005 15 MX29LV033M Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse, whichever happen later. DDI=Data of device identifier C2H for manufacture code PD=Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse. SA=Address of the sector to be erase or verified (in autoselect mode). Address bits A21-A12 uniquely select any sector. WBL=Write Buffer Location. Address must be within the same write buffer page as PA. BC=Byte Count. Number of write buffer locations to load minus 1. Notes: 1. See Table 1 for descriptions of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or automatic select data, all bus cycles are write operation. 4. Address bits are don't care for unlock and command cycles, except when PA or SA is required. 5. No unlock or command cycles required when device is in read mode. 6. The Reset command is required to return to the read mode when the device is in the automatic select mode or if Q5 goes high. 7. The fourth cycle of the automatic select command sequence is a read cycle. 8. The device ID must be read in three cycles. 9. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 10. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 11. Command sequence resets device for next command after aborted write-to-buffer operation. 12. The system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in the erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode. 14. Command is valid when device is ready to read array data or when device is in automatic select mode. P/N:PM1143 REV. 0.02, MAR. 23, 2005 16 MX29LV033M READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if Q5 goes high, or while in the automatic select mode. See the "Reset Command" section, next. array data (also applies during Erase Suspend). SILICON ID READ COMMAND SEQUENCE The SILICON ID READ command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 2 shows the address and data requirements. This method is an alternative to that shown in Table 1, which is intended for PROM programmers and requires VID on address bit A9. The SILICON ID READ command sequence is initiated by writing two unlock cycles, followed by the SILICON ID READ command. The device then enters the SILICON ID READ mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table for valid sector addresses. The system must write the reset command to exit the automatic select mode and return to reading array data. RESET COMMAND Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset command must be written to return to reading array data (also applies to SILICON ID READ during Erase Suspend). If Q5 goes high during a program or erase operation, writing the reset command returns the device to reading BYTE PROGRAM COMMAND SEQUENCE The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 3 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/ BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming op- P/N:PM1143 REV. 0.02, MAR. 23, 2005 17 MX29LV033M eration. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. Q7, Q6, Q5, and Q1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: • Load a value that is greater than the page buffer size during the Number of Locations to Program step. • Write to an address in a sector different than the one specified during the Write-Buffer-Load command. • Write an Address/Data pair to a different write-bufferpage than the one selected by the Starting Address during the write buffer data loading stage of the operation. • Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by Q1 = 1, Q7 = DATA# (for the last address location loaded), Q6 = toggle, and Q5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using WriteBuffer-Programming features in Unlock Bypass mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX-4. All subsequent address/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any P/N:PM1143 REV. 0.02, MAR. 23, 2005 18 MX29LV033M non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15us maximum (5 us typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. See Write Operation Status for more information. AUTOMATIC CHIP/SECTOR ERASE COMMAND The device does not require the system to preprogram prior to erase. The Automatic Erase algorithm automatically pre-program and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 3 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Automatic Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using Q7, Q6, Q2, or RY/BY#. See "Write Operation Status" for information on these status bits. When the Automatic Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 10 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 9 for timing diagrams. SETUP AUTOMATIC CHIP/SECTOR ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H, or the sector erase command 30H. The MX29LV033M contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code. A read cycle with A1=VIL,A0=VIH retrieves the device code. P/N:PM1143 REV. 0.02, MAR. 23, 2005 19 MX29LV033M SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE# or CE#, whichever happens later , while the command (data) is latched on the rising edge of WE# or CE#, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE# or CE#, whichever happens later. Each successive sector load cycle started by the falling edge of WE# or CE#, whichever happens later must begin within 50us from the rising edge of the preceding WE# or CE#, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode. device requires a maximum 20us to suspend the sector erase operation. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Erase Resume, program data to, or read data from any sector not selected for erasure. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended blocks. ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. ERASE SUSPEND This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is issued during the sector erase operation, the P/N:PM1143 REV. 0.02, MAR. 23, 2005 20 MX29LV033M QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29LV033M is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table 4. The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Read ID mode; however, it is ignored otherwise. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or read ID mode. The command is valid only when the device is in the CFI mode. Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Address h Address h (x16) (x8) 10 20 11 22 12 24 13 26 14 28 15 2A 16 2C 17 2E 18 30 19 32 1A 34 Data h 51 52 59 02 00 40 00 00 00 00 00 Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code (none) Address for secondary algorithm extended query table (none) Table 4-2. CFI Mode: System Interface Data Values Description VCC supply, minimum (2.7V) VCC supply, maximum (3.6V) VPP supply, minimum (none) VPP supply, maximum (none) Typical timeout for single word/byte write (2N us) Typical timeout for maximum size buffer write (2N us) Typical timeout for individual block erase (2N ms) Typical timeout for full chip erase (2N ms) Maximum timeout for single word/byte write times (2N X Typ) Maximum timeout for maximum size buffer write times (2N X Typ) Maximum timeout for individual block erase times (2N X Typ) Maximum timeout for full chip erase times (not supported) P/N:PM1143 Address h Address h (x16) (x8) 1B 36 1C 38 1D 3A 1E 3C 1F 3E 20 40 21 42 22 44 23 46 24 48 25 4A 26 4C Data h 27 36 00 00 07 07 0A 00 01 05 04 00 REV. 0.02, MAR. 23, 2005 21 MX29LV033M Table 4-3. CFI Mode: Device Geometry Data Values Description Device size (2n bytes) Flash device interface code Maximum number of bytes in multi-byte write = 2n Number of erase block regions Erase block region 1 information [2E,2D] = # of blocks in region -1 [30, 2F] = size in multiples of 256-bytes Address h Address h (x16) (x8) 27 4E 28 50 29 52 2A 54 2B 56 2C 58 2D 5A 2E 5C 2F 5E 30 60 31 62 32 64 33 66 34 68 35 6A 36 6C 37 6E 38 70 39 72 3A 74 3B 76 3C 78 Data h 16 00 00 05 00 01 3F 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 Erase Block Region 2 Information (refer to CFI publication 100) Erase Block Region 3 Information (refer to CFI publication 100) Erase Block Region 4 Information (refer to CFI publication 100) P/N:PM1143 REV. 0.02, MAR. 23, 2005 22 MX29LV033M Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Query-unique ASCII string "PRI" Address h Address h (x16) (x8) 40 80 41 82 42 84 43 86 44 88 45 8A 46 8C 47 8E 48 90 49 92 4A 94 4B 96 4C 98 4D 9A 4E 4F 9C 9E Data h 50 52 49 31 33 01 02 04 01 04 00 00 01 B5 C5 00 Major version number, ASCII Minor version number, ASCII Address sensitive unlock (0=required, 1= not required) Erase suspend (2= to read and write) Sector protect (N= # of sectors/group) Temporary sector unprotect (1=supported) Sector protect/unprotect scheme Simultaneous R/W operation (0=not supported) Burst mode type (0=not supported) Page mode type (1= 8 bye page) ACC (Acceleration) Supply Minimum 00h=Not Supported, D7-D4: Volt, D3-D0:100mV ACC (Acceleration) Supply Maximum 00h=Not Supported, D7-D4: Volt, D3-D0:100mV Top/Bottom Boot Sector Flag 00h=Uniform Device without WP# support 02h=Bottom Boot Device, 03h=Top Boot Device 04h=uniform sectors bottom WP# protect, 05h=uniform sectors top WP# protect Program Suspend 00h=Not Supported, 01h=Supported 50 A0 01 P/N:PM1143 REV. 0.02, MAR. 23, 2005 23 MX29LV033M WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY#. Table 5 and the following subsections describe the functions of these bits. Q7, RY/BY#, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 5. Write Operation Status Status Byte Program in Auto Program Algorithm Auto Erase Algorithm Erase Suspend Read Erase Suspended Mode (Erase Suspended Sector) Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program Program-Suspended Read Program Suspend Write-to-Buffer (Program-Suspended Sector) Program-Suspended Read (Non-Program-Suspended Sector) Busy Abort Q7# Q7# Toggle Toggle 0 0 N/A N/A N/A N/A 0 1 0 0 Data 1 Q7# Toggle 0 N/A N/A N/A 0 1 Invalid (not allowed) Data Q7 Q7# 0 1 Q6 Toggle Toggle No Toggle Data Data Data Data Data 1 Q5 0 0 0 Q3 N/A 1 N/A Q2 No Toggle Toggle Toggle N/A N/A 0 1 Q1 0 RY/BY# 0 Notes: 1. Q5 switches to "1" when an Byte Program, Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on Q5 for more information. 2. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. Q1 switches to "1" when the device has aborted the write-to-buffer operation. P/N:PM1143 REV. 0.02, MAR. 23, 2005 24 MX29LV033M Q7: Data# Polling The Data# Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming during Erase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program address to read valid status information on Q7. If a program address falls within a protected sector, Data# Polling on Q7 is active for approximately 1 us, then the device returns to reading array data. During the Automatic Erase algorithm, Data# Polling produces a "0" on Q7. When the Automatic Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on Q7. This is analogous to the complement/true datum output described for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement," or "0". The system must provide an address within any of the sectors selected for erasure to read valid status information on Q7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output Enable (OE#) is asserted low. happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles for 100us and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 5 shows the outputs for Toggle Bit I on Q6. Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# or CE#, whichever happens first pulse in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# or CE#, whichever P/N:PM1143 REV. 0.02, MAR. 23, 2005 25 MX29LV033M parison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 5 to compare outputs for Q2 and Q6. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. The Q5 failure condition may appear if the system tries to program a to a "1" location that is previously programmed to "0". Only an erase operation can change a "0" back to a "1". Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, Q5 produces a "1". Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Q3:Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data# Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If Q3 is low ("0"), the device will accept addi- Q5:Program/Erase Timing Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this condition. P/N:PM1143 REV. 0.02, MAR. 23, 2005 26 MX29LV033M tional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. If the time between additional erase commands from the system can be less than 50us, the system need not to monitor Q3. Q1: Write-to-Buffer Abort Q1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions Q1 produces a "1". The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer section for more details. RY/BY#:READY/BUSY OUTPUT The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC . If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. P/N:PM1143 REV. 0.02, MAR. 23, 2005 27 MX29LV033M ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC Ambient Temperature with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20ns. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RATINGS Commercial (C) Devices Ambient Temperature (TA ). . . . . . . . . . . . 0° C to +70° C Industrial (I) Devices Ambient Temperature (TA ). . . . . . . . . . -40° C to +85° C VCC Supply Voltages VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V VCC for regulated voltage range. . . . . . +3.0 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. P/N:PM1143 REV. 0.02, MAR. 23, 2005 28 MX29LV033M DC CHARACTERISTICS TA=-40° C to 85° C, VCC=2.7V~3.6V (TA= 0° C to 70° C, VCC=3.0V~3.6V for 70R) Parameter Description I LI I LIT I LO Input Load Current (Note 1) A9 Input Leakage Current Output Leakage Current Test Conditions VIN = VSS to VCC , VCC = VCC max VCC=VCC max; A9 = 12.5V VOUT = VSS to VCC , VCC= VCC max ICC1 VCC Active Read Current (Notes 2,3) ICC2 VCC Intra-Page Read Current (Notes 2,3) ICC3 VCC Active Write Current (Notes 2,3) ICC4 VCC Standby Current (Note 2) ICC5 VCC Reset Current (Note 2) ICC6 Automatic Sleep Mode (Notes 2,4) VIL VIH VHH VID VOL VOH2 VLKO Low VCC Lock-Out Voltage (Note 5) Notes: 1. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC = 3.0V. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. 5. Not 100% tested. P/N:PM1143 REV. 0.02, MAR. 23, 2005 Min. Typ. Max. ±1.0 35 ±1.0 Unit uA uA uA mA mA mA mA mA mA uA uA uA V V V V V V V CE#= VIL, OE# = VIH CE#= VIL , OE# = VIH WE#=VIL 10 MHz 5 MHz 1 MHz 10 MHz 40 MHz 35 18 5 5 10 50 20 20 20 -0.5 0.7xVCC 50 25 20 20 40 60 50 50 50 0.8 VCC+0.5 CE#= VIL , OE# = VIH CE#,RESET#=VCC±0.3V RESET#=VSS±0.3V VIL = V SS ± 0.3 V, VIH = VCC ± 0.3 V, Input Low Voltage Input High Voltage Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage IOL= 4.0mA,VCC=VCC min VCC = 3.0 V ± 10% VCC = 2.7V ~ 3.6V 11.5 11.5 12.0 12.0 12.5 12.5 0.45 VOH1 Output High Voltage IOH=-2.0mA,VCC=VCC min 0.85VCC IOH=-100uA,VCC=VCC min VCC-0.4 2.3 2.5 V 29 MX29LV033M SWITCHING TEST CIRCUITS TEST SPECIFICATIONS Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels All Speeds 1 TTL gate 30 5 0.0-3.0 1.5 1.5 Unit pF ns V V V DEVICE UNDER TEST 2.7K ohm 3.3V CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State(High Z) OUTPUTS SWITCHING TEST WAVEFORMS 3.0V 1.5V Measurement Level 1.5V OUTPUT 0.0V INPUT P/N:PM1143 REV. 0.02, MAR. 23, 2005 30 MX29LV033M AC CHARACTERISTICS Read-Only Operations TA=-40° C to 85° C, VCC=2.7V~3.6V (TA= 0° C to 70° C, VCC=3.0V~3.6V for 70R) Parameter Std. tRC tACC tCE tPACC tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Page Access Time Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Address, CE# or OE#, whichever Occurs First Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling Min Min 35 10 ns ns CE#, OE#=VIL OE#=VIL Test Setup Min Max Max Max Max Max Max Min Speed Options 70R 70 70 70 25 35 16 16 0 90 90 90 90 25 35 Unit ns ns ns ns ns ns ns ns Notes: 1. Not 100% tested. 2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE for test specifications. P/N:PM1143 REV. 0.02, MAR. 23, 2005 31 MX29LV033M Figure 1. READ TIMING WAVEFORMS tRC VIH Addresses VIL ADD Valid tCE VIH CE# VIL tRH tRH VIH WE# VIL VIH VIL tOH tOEH tOE tDF OE# tACC Outputs VOH VOL VIH HIGH Z DATA Valid HIGH Z RESET# VIL RY/BY# 0V Figure 2. PAGE READ TIMING WAVEFORMS A2~A21 Same Page A0~A2 tACC CE# tPACC tPACC tPACC tPACC tPACC tPACC tPACC OE# Output Qa Qb Qc Qd Qe Qf Qg Qh P/N:PM1143 REV. 0.02, MAR. 23, 2005 32 MX29LV033M AC CHARACTERISTICS Parameter tREADY1 tREADY2 tRP tRH tRB tRPD Description RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) RESET# Pulse Width (NOT During Automatic Algorithms) RESET# High Time Before Read (See Note) RY/BY# Recovery Time(to CE#, OE# go low) RESET# Low to Standby Mode MIN MIN MIN MIN 500 50 0 20 ns ns ns us MAX 500 ns Test Setup All Speed Options Unit MAX 20 us Note:Not 100% tested Figure 3. RESET# TIMING WAVEFORM RY/BY# CE#, OE# tRH RESET# tRP tReady2 Reset Timing NOT during Automatic Algorithms tReady1 RY/BY# tRB CE#, OE# RESET# tRP Reset Timing during Automatic Algorithms P/N:PM1143 REV. 0.02, MAR. 23, 2005 33 MX29LV033M AC CHARACTERISTICS Erase and Program Operations TA=-40° C to 85° C, VCC=2.7V~3.6V (TA= 0° C to 70° C, VCC=3.0V~3.6V for 70R) Parameter Std. tWC tAS tASO tAH tAHT tDS tDH tCEPH tOEPH tGHWL tGHEL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time CE# High During Toggle Bit Polling Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) Read Recovery Time Before Write CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Notes 2,3) Single Word/Byte Program Operation (Notes 2,5) Accelerated Single Word/Byte Programming Operation (Notes 2,5) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay VHH Rise and Fall Time (Note 1) Program Valid Before Status Polling (Note 6) Speed Options 70R 90 70 90 0 15 45 0 35 0 20 20 0 0 0 0 35 30 240 60 54 0.5 50 0 70 250 4 90 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us us us sec us ns ns ns us Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Min Min Min Min Max tWHWH1 tWHWH2 tVCS tRB tBUSY tVHH tPOLL Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-16 words/1-32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. P/N:PM1143 REV. 0.02, MAR. 23, 2005 34 MX29LV033M ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC PROGRAM TIMING WAVEFORMS Program Command Sequence(last two cycle) tWC tAS Read Status Data (last two cycle) Address XXXh PA tAH PA PA CE# tCH OE# tWP tWHWH1 WE# tCS tDS tDH tWPH A0h Data PD Status DOUT tBUSY tRB RY/BY# tVCS VCC Note : 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address Figure 5. ACCELERATED PROGRAM TIMING DIAGRAM VHH ACC VIL or VIH VIL or VIH tVHH tVHH P/N:PM1143 REV. 0.02, MAR. 23, 2005 35 MX29LV033M Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Increment Address Data Poll from system No Verify Word Ok ? YES No Last Address ? YES Auto Program Completed P/N:PM1143 REV. 0.02, MAR. 23, 2005 36 MX29LV033M Figure 7. WRITE BUFFER PROGRAMMING ALGORITHM FLOWCHART Write "Write to Buffer" command and Sector Address Write number of addresses to program minus 1(WC) and Sector Address Part of "Write to Buffer" Command Sequence Write first address/data Yes WC = 0 ? No Yes Write to a different sector address Abort Write to Buffer Operation ? No (Note 1) Write next address/data pair Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. WC = WC - 1 Write program buffer to flash sector address Read Q7~Q0 at Last Loaded Address Yes Q7 = Data ? No No No Q1 = 1 ? Q5 = 1 ? Yes Yes Read Q7~Q0 with address = Last Loaded Address Notes: 1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. Q7 may change simultaneously with Q5. Therefore, Q7 should be verified. 3. If this flowchart location was reached because Q5= "1" then the device FAILED. If this flowchart location was reached because Q1="1", then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If Q1=1, write the Write-Buffer-Programming-Abort-Reset command. If Q5=1, write the Reset command. 4. See Table 3 for command sequences required for write buffer programming. (Note 2) Q7 = Data ? Yes No (Note 3) FAIL or ABORT PASS P/N:PM1143 REV. 0.02, MAR. 23, 2005 37 MX29LV033M Figure 8. PROGRAM SUSPEND/RESUME FLOWCHART Program Operation or Write-to-Buffer Sequence in Progress Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations Write address/data XXXh/B0h Wait 15us Read data as required Autoselect and Secured Sector read operations are also allowed Data cannot be read from erase-or program-suspended sectors No Done reading ? Yes Write address/data XXXh/30h Write Program Resume Command Sequence Device reverts to operation prior to Program Suspend P/N:PM1143 REV. 0.02, MAR. 23, 2005 38 MX29LV033M Figure 9. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM Erase Command Sequence(last two cycle) tWC tAS Read Status Data Address 2AAh SA 555h for chip erase tAH VA VA CE# tCH OE# tWP tWHWH2 WE# tCS tDS tDH tWPH 55h Data 30h 10 for Chip Erase In Progress Complete tBUSY tRB RY/BY# tVCS VCC Note : 1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1143 REV. 0.02, MAR. 23, 2005 39 MX29LV033M Figure 10. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data Poll from system YES No DATA = FFh ? YES Auto Erase Completed P/N:PM1143 REV. 0.02, MAR. 23, 2005 40 MX29LV033M Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Last Sector to Erase ? NO YES Data Poll from System NO Data=FFh? YES Auto Sector Erase Completed P/N:PM1143 REV. 0.02, MAR. 23, 2005 41 MX29LV033M Figure 12. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H NO Toggle Bit checking Q6 not toggled YES Read Array or Program ERASE SUSPEND Reading or Programming End YES Write Data 30H NO ERASE RESUME Continue Erase Another Erase Suspend ? YES NO P/N:PM1143 REV. 0.02, MAR. 23, 2005 42 MX29LV033M AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations TA=-40° C to 85° C, VCC=2.7V~3.6V (TA= 0° C to 70° C, VCC=3.0V~3.6V for 70R) Parameter Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Write Buffer Program Operation (Notes 2,3) Single Byte Program Operation tWHWH1 (Notes 2,5) Accelerated Single Byte Programming Operation (Notes 2,5) tWHWH2 tRH tPOLL Sector Erase Operation (Note 2) RESET HIGH Time Before Write (Note 1) Program Valid Before Status Polling (Note 6) Typ Min Max 0.5 50 4 sec ns us Typ 54 us Min Min Min Min Typ Typ 0 0 35 25 240 60 ns ns ns ns us us Min Min Min Min Min Min Speed Options 70R 70 0 45 35 0 0 90 90 Unit ns ns ns ns ns ns Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-32 bytes programmed. 4. Effective write buffer specification is based upon a 32-byte write buffer operation. 5. Byte programming specification is based upon a single byte programming operation not utilizing the write buffer. 6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. P/N:PM1143 REV. 0.02, MAR. 23, 2005 43 MX29LV033M Figure 13. CE# CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Address tWC tWH tAS tAH PA WE# tGHEL OE# tCP tWHWH1 or 2 CE# tWS tDS tDH tCPH tBUSY Q7 Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase DOUT RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence. P/N:PM1143 REV. 0.02, MAR. 23, 2005 44 MX29LV033M SECTOR GROUP PROTECT/CHIP UNPROTECT Figure 14. Sector Group Protect / Chip Unprotect Waveform (RESET# Control) VID VIH RESET# SA, A6 A1, A0 Valid* Valid* Valid* Sector Group Protect or Chip Unprotect Data 1us Verify 40h Status 60h 60h Sector Group Protect:150us Chip Unprotect:15ms CE# WE# OE# Note: For sector group protect A6=0, A1=1, A0=0. For chip unprotect A6=1, A1=1, A0=0 P/N:PM1143 REV. 0.02, MAR. 23, 2005 45 MX29LV033M Figure 15. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH RESET#=VID START START PLSCNT=1 Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT=1 RESET#=VID RESET#=VID Wait 1us Wait 1us Temporary Sector Unprotect Mode No First Write Cycle=60h? Yes Set up sector address No Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 First Write Cycle=60h? Yes No Temporary Sector Unprotect Mode All sectors protected? Yes Set up first sector address Wait 150us Verify Sector Protect: Write 40h to sector address with A6=0, A1=1, A0=0 Increment PLSCNT Read from sector address with A6=0, A1=1, A0=0 No Reset PLSCNT=1 Sector Unprotect: Write 60h to sector address with A6=1, A1=1, A0=0 Wait 15 ms Increment PLSCNT No PLSCNT=25? Data=01h? Verify Sector Unprotect: Write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=1, A1=1, A0=0 Yes Device failed Yes No Protect another sector? Yes No PLSCNT=1000? Reset PLSCNT=1 Data=00h? Sector Protect Algorithm No Remove VID from RESET# Yes Device failed Write reset command Last sector verified? No Yes Sector Protect complete Chip Unprotect Algorithm Yes Remove VID from RESET# Write reset command Sector Unprotect complete P/N:PM1143 REV. 0.02, MAR. 23, 2005 46 MX29LV033M AC CHARACTERISTICS Parameter tVLHT tWPP1 tOESP Description Voltage transition time Write pulse width for sector group protect OE# setup time to WE# active Test Setup Min. Min. Min. All Speed Options 4 100 4 Unit us ns us Figure 16. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE# Control) A1 A6 12V 3V A9 tVLHT Verify 12V 3V OE# tVLHT tWPP 1 tVLHT WE# tOESP CE# Data tOE 01H F0H A21-A16 Sector Address P/N:PM1143 REV. 0.02, MAR. 23, 2005 47 MX29LV033M Figure 17. SECTOR GROUP PROTECTION ALGORITHM (A9, OE# Control) START Set Up Sector Addr PLSCNT=1 OE#=VID, A9=VID, CE#=VIL A6=VIL Activate WE# Pulse Time Out 150us Set WE#=VIH, CE#=OE#=VIL A9 should remain VID . No Read from Sector Addr=SA, A1=1 PLSCNT=32? No Data=01H? Yes Device Failed Protect Another Sector? Yes Remove VID from A9 Write Reset Command Sector Protection Complete P/N:PM1143 REV. 0.02, MAR. 23, 2005 48 MX29LV033M Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control) A1 12V 3V A9 tVLHT A6 Verify 12V 3V OE# tVLHT tWPP 2 tVLHT WE# tOESP CE# Data tOE 00H F0H P/N:PM1143 REV. 0.02, MAR. 23, 2005 49 MX29LV033M Figure 19. CHIP UNPROTECT FLOWCHART (A9, OE# Control) START Protect All Sectors PLSCNT=1 Set OE#=A9=VID CE#=VIL, A6=1 Activate WE# Pulse Time Out 15ms Increment PLSCNT Set OE#=CE#=VIL A9=VID, A1=1 Set Up First Sector Addr Read Data from Device No Increment Sector Addr Data=00H? No PLSCNT=1000? Yes No Yes Device Failed All sectors have been verified? Yes Remove VID from A9 Write Reset Command Chip Unprotect Complete * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1143 REV. 0.02, MAR. 23, 2005 50 MX29LV033M AC CHARACTERISTICS Parameter tVIDR tRSP tRRB Description VID Rise and Fall Time (see Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Group Unprotect Test Setup Min Min Min 500 4 4 ns us us All Speed Options Unit Figure 20. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS 12V RESET# 0 or 3V VIL or VIH tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRSP tRRB RY/BY# P/N:PM1143 REV. 0.02, MAR. 23, 2005 51 MX29LV033M Figure 21. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART Start RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH Temporary Sector Unprotect Completed(Note 2) Notes : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V 2. All previously protected sectors are protected again. P/N:PM1143 REV. 0.02, MAR. 23, 2005 52 MX29LV033M Figure 22. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART START Enter Secured Silicon Sector Wait 1us First Wait Cycle Data=60h Second Wait Cycle Data=60h A6=0, A1=1, A0=0 Wait 300us No Data = 01h ? Yes Device Failed Write Reset Command Secured Sector Protect Complete P/N:PM1143 REV. 0.02, MAR. 23, 2005 53 MX29LV033M Figure 23. SILICON ID READ TIMING WAVEFORM VCC 3V VID VIH VIL VIH VIL tACC VIH VIL tACC tACC tACC ADD A9 ADD A0 A1 A2 VIH VIL ADD VIH VIL CE# VIH VIL tCE WE# VIH VIL OE# VIH VIL tOE tDF tOH tOH tOH tOH VIH DATA Q0-Q15 VIL DATA OUT Manufacturer ID DATA OUT Device ID Cycle 1 DATA OUT Device ID Cycle 2 DATA OUT Device ID Cycle 3 P/N:PM1143 REV. 0.02, MAR. 23, 2005 54 MX29LV033M WRITE OPERATION STATUS Figure 24. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE VA VA CE# tCH tOE OE# tOEH tDF WE# tOH Q7 Q0-Q6 tBUSY Status Data Complement True Valid Data High Z Status Data Status Data True Valid Data High Z RY/BY# Note : VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle. P/N:PM1143 REV. 0.02, MAR. 23, 2005 55 MX29LV033M Figure 25. DATA# POLLING ALGORITHM Start Read Q7~Q0 Add.=VA(1) Q7 = Data ? Yes No No Q5 = 1 ? Yes Read Q7~Q0 Add.=VA Q7 = Data ? (2) No FAIL Yes Pass Notes: 1.VA=valid address for programming. 2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1143 REV. 0.02, MAR. 23, 2005 56 MX29LV033M Figure 26. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE VA VA VA CE# tCH tOE OE# tOEH tDF WE# tDH tOH Q6/Q2 Valid Status Valid Status (first read) Valid Status (second read) Valid Data (stops toggling) Valid Data RY/BY# Note : VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. P/N:PM1143 REV. 0.02, MAR. 23, 2005 57 MX29LV033M Figure 27. TOGGLE BIT ALGORITHM START Read Q7~Q0 Read Q7~Q0 (Note 1) Toggle Bit Q6 =Toggle? YES NO NO Q5=1? YES Read Q7~Q0 Twice (Note 1,2) Toggle Bit Q6= Toggle? YES Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes : 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1143 REV. 0.02, MAR. 23, 2005 58 MX29LV033M Figure 28. Q6 versus Q2 Enter Embedded Erasing Erase Suspend Erase Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Erase Complete WE# Q6 Q2 Note : The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended P/N:PM1143 REV. 0.02, MAR. 23, 2005 59 MX29LV033M ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Chip Erase Time Total Write Buffer Program Time (Note 4) Total Accelerated Effective Write Buffer Program Time (Note 4) Chip Program Time 31.5 sec Typ (Note 1) 0.5 32 240 200 Max (Note 2) 3.5 64 Unit sec sec us us Notes: 1. Typical program and erase times assume the following conditions: 25° C, 3.0 V VCC. Programming specifications assume checkerboard data pattern. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Byte programming specification is based upon a single byte programming operation not utilizing the write buffer. 4. For 1-32 bytes programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-byte basis for a 32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 3 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCH-UP CHARACTERISTICS MIN. Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 13.5V VCC + 1.0V +100mA DATA RETENTION Parameter Minimum Pattern Data Retention Time Min 20 Unit Years P/N:PM1143 REV. 0.02, MAR. 23, 2005 60 MX29LV033M TSOP PIN AND BGA PACKAGE CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Set VIN=0 VOUT=0 VIN=0 TSOP CSP TSOP CSP TSOP CSP Notes: 1. Sampled, not 100% tested. 2. Test conditions TA=25° C, f=1.0MHz TYP 6 4.2 8.5 5.4 7.5 3.9 MAX 7.5 5.0 12 6.5 9 4.7 UNIT pF pF pF pF pF pF P/N:PM1143 REV. 0.02, MAR. 23, 2005 61 MX29LV033M ORDERING INFORMATION PLASTIC PACKAGE PART NO. MX29LV033MTC-70R MX29LV033MTI-70R MX29LV033MTC-90 MX29LV033MTI-90 MX29LV033MTC-90G MX29LV033MTI-90G ACCESS TIME (ns) 70 70 90 90 90 90 Ball Pitch/ Ball size 40 Pin TSOP 40 Pin TSOP 40 Pin TSOP 40 Pin TSOP 40 Pin TSOP 40 Pin TSOP Pb-free Pb-free PACKAGE Remark P/N:PM1143 REV. 0.02, MAR. 23, 2005 62 MX29LV033M PACKAGE INFORMATION P/N:PM1143 REV. 0.02, MAR. 23, 2005 63 MX29LV033M REVISION HISTORY Revision No. Description 0.01 1. To modified CFI parameter 2. To added 70ns speed grade information 0.02 1. Changed title from "Advanced Information" to "Preliminary" Page Date P22,23 DEC/08/2004 P1,28,29,31, P34,43,62 P1 MAR/23/2005 P/N:PM1143 REV. 0.02, MAR. 23, 2005 64 M X29LV033M MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.