49FCT805PYGSOGBLANK

IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE FAST CMOS BUFFER/CLOCK DRIVER IDT49FCT805/A FEATURES: • • • • • • • • • • • 0.5 MICRON CMOS Technology Guaranteed low skew < 700ps (max.) Low duty cycle distortion < 1ns (max.) Low CMOS power levels TTL compatible inputs and outputs Rail-to-rail output voltage swing High drive: -24mA IOH, +64mA IOL Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output Available in SSOP and SOIC packages DESCRIPTION: The 49FCT805 is a non-inverting buffer/clock driver built using advanced dual metal CMOS technology. Each bank consists of two banks of drivers. Each bank drives five output buffers from a standard TTL compatible input. These devices feature a “heart-beat” monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The 49FCT805 offers low capacitance inputs and hysteresis. Rail-to-rail output swing improves noise margin and allows easy interface with CMOS inputs. FUNCTIONAL BLOCK DIAGRAM OE A IN A 5 OA 1 -OA 5 IN B 5 OB 1 -OB 5 OE B MON The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE 1 c 2006 Integrated Device Technology, Inc. MAY 2010 DSC-5836/5 IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION VCCA OA1 OA2 OA3 GNDA OA4 OA5 NC (1) ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max –0.5 to +7 –0.5 to VCC+0.5 –65 to +150 –60 to +60 Unit V V °C mA 1 2 3 4 5 6 7 8 9 10 SOIC/ SSOP TOP VIEW 20 19 18 17 16 15 14 13 12 11 VCC OB1 OB2 OB3 GNDB OB4 OB5 MON OEB INB VTERM(2) VTERM(3) TSTG IOUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Input and VCC terminals. 3. Output and I/O terminals. OEA INA CAPACITANCE (TA = +25OC, f = 1.0MHz) Symbol CIN C OUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. 6 8 Unit pF pF NOTE: 1. This parameter is measured at characterization but not tested. NOTE: 1. Pin 8 is not internally connected on devices with a "K" prefix in the date code. On older devices, pin 8 is internally connected to GND. To insure compatibility with all products, pin 8 should be connected to GND at the board level. PIN DESCRIPTION Pin Names OEA, OEB INA, INB OAn, OBn MON Clock Inputs Clock Outputs Monitor Output Description 3-State Output Enable Inputs (Active LOW) FUNCTION TABLE (1) Inputs OEA, OEB L L H H NOTE: 1. H = HIGH L = LOW Z = High-Impedance Outputs INA, INB L H L H OAn, OBn L H Z Z MON L H L H 2 IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C, VCC = 5V ± 5% Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VOH Clamp Diode Voltage Short Circuit Current Output HIGH Voltage VCC = Min., IIN = –18mA VCC = Max., VO = GND(3) VCC = 3V, VIN = VLC or VHC VCC = Min. VIN = VIH or VIL VCC = 3V, VIN = VLC or VHC VOL VH ICC Output LOW Voltage Input Hysteresis for all inputs Quiescent Power Supply Current VCC = Min. VIN = VIH or VIL — VCC = Max., VIN = GND or VCC IOH = –32µA IOH = –300µA IOH = –15mA IOH = –24mA IOL = 300µA IOL = 300mA IOL = 64mA Parameter Input HIGH Level (Input pins) Input LOW Level (Input and I/O pins) Input HIGH Current Input LOW Current Off State (Hi-Z) Output Current Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VI = 5.5V VI = GND VO = VCC VO = GND Min. 2 — — — — — — –60 VHC VHC 3.6 2.4 — — — — — Typ.(2) — — — — — — –0.7 –120 VCC VCC 4.3 3.8 GND GND 0.3 200 5 Max. — 0.8 ±1 ±1 ±1 ±1 –1.2 — — — — — VLC VLC 0.55 — 500 mV µA V V V mA Unit V V µA µA µA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 3 IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OEA = OEB = GND 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. Outputs Open fO = 10MHz 50% Duty Cycle OEA = OEB = VCC Mon. Output Toggling VCC = Max. Outputs Open fO = 2.5MHz 50% Duty Cycle OEA = OEB = GND Eleven Outputs Toggling NOTES: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at VCC = 5V, +25°C ambient. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. Test Conditions(1) Min. — Typ.(2) 1 0.15 Max. 2.5 0.2 Unit mA mA/MHz VIN = VCC VIN = GND — VIN = VCC VIN = GND VIN = 3.4V VIN = GND VIN = VCC VIN = GND VIN = 3.4V VIN = GND — 1.5 2.5 — 2 3.8 — 4.1 6 (5) mA — 5.1 8.5 (5) 4 IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) FCT805 Symbol tPLH tPHL tR tF tSK(O) tSK(P) tSK(PP) Parameter Propagation Delay INA to OAn, INB to OBn Output Rise Time Output Fall Time Output skew: skew between outputs of all banks of same package (inputs tied together) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) Part-to-part skew: skew between outputs of different packages at same power supply voltage, tPZL tPZH tPLZ tPHZ temperature, package type and speed grade Output Enable Time OEA to OAn, OEB to OBn Output Disable Time OEA to OAn, OEB to OBn 1.5 1.5 8 7 1.5 1.5 8 7 ns ns Conditions(2) CL = 50pF RL = 500Ω Min. 1.5 — — — — — Max. 5.6 1.5 1.5 0.7 1 1.5 Min. 1.5 — — — — — FCT805A Max. 5.3 1.5 1.5 0.7 1 1.5 Unit ns ns ns ns ns ns NOTES: 1. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 2. See test circuits and waveforms. 5 IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC 7V 500 Pulse Generator V IN D.U.T. 50pF RT 5 00 CL V OUT SWITCH POSITION Test Disable LOW Enable LOW Disable HIGH Enable HIGH Switch Closed GND DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Circuits for All Outputs 3V 1.5V INPUT tP LH t PHL V OH 2.0V OUTPUT tR tF O UTPUT 2 tPLH2 3V 1.5V INPUT tPLH t PHL V OH 1.5V OUTPUT tSK (p) = t PHL - t PLH V OL INPUT tPLH1 t PHL1 3V 1.5V 0V V OH PACKAGE 1 OUTPUT ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH 3.5V SW ITCH CLO SED 3V 1.5V INPUT t PLH 1 t PLH 1 0V V OH 1.5V 0V 1.5V V OL OUTPUT 1 tSK (o) tSK (o) V OL V OH 1.5V V OL tPHL2 or 0.8V Package Delay tSK (o) = t PLH2 - tPLH1 t PHL2 - tPHL1 0V Output Skew Pulse Skew - tSK(P) 1.5V VO L tSK (pp) tSK(pp) V OH 1.5V VO L t PLH 2 tSK (pp) = tPLH2 - t PLH1 or DISABLE 3V 1.5V 0V t PLZ PACKAGE 2 OUTPUT t PHL2 t PH L2 - t PHL1 1.5V t PHZ 1.5V 0V 3.5V 0.3V V OL tP ZH SW ITCH O PEN 0.3V V OH 0V Part-to-Part Skew - tSK(PP) NOTE: 1. Package 1 and Package 2 are same device type and speed grade. Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 6 IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT49FCT XXXX Device Type X Package X Process Blank I SO SOG PY PYG 805 805A Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Small Outline IC SOIC - Green Shrink Small Outline Package SSOP - Green Fast CMOS Buffer/Clock Driver CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 7 for Tech Support: clockhelp@idt.com