70T9169PF

HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM .eatures x x PRELIMINARY IDT70T9169/59L x x x x True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial:7.5/9/12ns (max.) – Industrial: 9ns (max.) Low-power operation – IDT70T9169/59L Active: 225mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic x x x x Full synchronous operation on both ports – 4.0ns setup to clock and 0.5ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 12ns cycle time, 83MHz operation in Pipelined output mode LVTTL- compatible, single 2.5V (±100mV) power supply Industrial temperature range (–40°C to +85°C) is available for 66MHz Available in a 100-pin Thin Quad Flatpack (TQFP) and 100pin fine pitch Ball Grid Array (fpBGA) packages. .unctional Block Diagram R/WL OEL CE0L CE1L R/WR OER CE0R CE1R 1 0 0/1 1 0 0/1 FT/PIPEL 0/1 1 0 0 1 0/1 FT/PIPER I/O0L - I/O8L I/O0R - I/O8R I/O Control I/O Control A13L(1) A0L CLKL ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A13R(1) A0R CLKR ADSR CNTENR CNTRSTR 5654 drw 01 NOTE: 1. A 13 is a NC for IDT70T9159. JULY 2002 1 ©2002 Integrated Device Technology, Inc. D SC-5654/1 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Description The IDT70T9169/59 is a high-speed 16/8K x 9 bit synchronous DualPort RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T9169/59 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 225mW of power. Pin Configurations(1,2,3,4) 06/21/02 Index NC NC A7L A8L A9L A10L A11L A12L A13L(1) NC NC NC VDD NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL FT/PIPEL NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 NC NC A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL Vss Vss ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R NC 70T9169/59PF PN100-1(5) 100-Pin TQFP Top View(6) 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A7R A8R A9R A10R A11R A12R A13R(1) NC NC NC Vss NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER Vss NC . 5654 drw 02 NOTES: 1. A13 is a NC for IDT70T9159. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. Vss I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L Vss I/O1L I/O0L VDD Vss I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R NC NC 2 6.42 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Configurations (con't.)(1,2,3,4) 70T9169/59BF BF100(5) 100-Pin fpBGA Top View(6) A2 A3 A4 A5 A6 A7 A8 A9 A10 06/21/02 A1 A6R B1 A9R B2 A12R B3 NC B4 VSS B5 VSS B6 NC B7 R/WR B8 VSS B9 NC B10 A4R C1 A5R C2 A8R C3 A10R C4 NC C5 NC C6 NC C7 OER C8 NC C9 I/O6R C10 A3R D1 NC D2 NC D3 A7R D4 NC D5 CE0R CE1R PL/FTR I/O7R I/O3R D6 D7 D8 D9 D10 A0R E1 CLKR E2 A1R E3 CNTENR F3 A2R E4 A11R A13R(1) CNTRSTR I/O8R E5 E6 E7 E8 I/O5R I/O1R E9 E10 VSS F1 ADS R F2 A1L F4 ADSL F5 VSS F6 I/O4R F7 I/O2R F8 I/O0R F9 VDD F10 VSS G1 CNTENL H1 CLKL G2 A0L G3 A3L G4 VDD G5 VSS G6 VDD G7 I/O2L G8 I/O1L G9 I/O0L G10 NC H2 A5L H3 A12L H4 H5 NC R/WL H6 NC H7 I/O4L H8 VSS H9 I/O3L H10 , A2L J1 A4L J2 A9L J3 A13L(1) J4 J5 NC NC K5 CE1L J6 J7 NC OEL K7 I/O7L J8 I/O6L J9 I/O5L J10 NC K1 A7L K2 A10L K3 NC K4 NC K6 VSS K8 CNTRSTL VSS K9 I/O8L K10 A6L A8L A11L NC VDD VDD CE0L PL/FTL NC 5654 drw 03 NOTES: 1. A 13 is a NC for IDT70T9159. 2. All V DD pins must be connected to power supply. 3. All V SS pins must be connected to ground supply. 4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.42 3 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/WL OEL A0L - A13L(1) I/O0L - I/O8L CLKL ADSL CNTENL CNTRSTL FT/PIPEL Right Port CE0R, CE1R R/WR OER A0R - A13R(1) I/O0R - I/O8R CLKR ADSR CNTENR CNTRSTR FT/PIPER VDD VSS NOTE: 1. A13 is a NC for IDT70T9159. Names Chip Enables Read/Write Enable Output Enable Address Data Input/Output Clock Address Strobe Counter Enable Counter Reset Flow-Through/Pipeline Power (2.5V) Ground (0V) 5654 tbl 01 Truth Table I—Read/Write and Enable Control(1,2,3) OE X X X L H CLK ↑ ↑ ↑ ↑ X CE0 H X L L L CE 1 X L H H H R/W X X L H X I/O0-8 High-Z High-Z DATAIN DATAOUT High-Z Mode Deselected —Power Down Deselected —Power Down Write Read Outputs Disabled 5654 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 4 6.42 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Truth Table II—Address Counter Control(1,2) External Address An X X X Previous Internal Address X An An + 1 X Internal Address Used An An + 1 An + 1 A0 CLK ↑ ↑ ↑ ↑ ADS L(4) H H X CNTEN X L(5) H X CNTRST H H H L (4) I/O(3) DI/O (n) DI/O (n+1) DI/O (n+1) DI/O(0) External Address Used MODE Counter Enabled —Internal Address generation External Addre ss Blocked— Counter disab led (An + 1 reused) Counter Reset to Address 0 5654 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/ W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0 and CE1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1. Recommended Operating Temperature and Supply Voltage Grade Commercial Industrial Ambient Temperature(1) 0OC to +70OC -40OC to +85OC GND 0V 0V VDD 2.5V + 100mV 2.5V + 100mV 5654 tbl 04 Recommended DC Operating Conditions Sym bol V DD V SS V IH V IL Parameter Sup p ly Vo ltag e G ro und Inp ut Hig h Vo ltag e Inp ut Lo w Vo ltag e Min. 2.4 0 1.7 -0.3 (1) Typ. 2.5 0 ____ Max. 2.6 0 V DD+ 0.3V (2) 0.7 Unit V V V V 5654 tbl 05 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. ____ NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDD +0.3V. Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +3.6 Unit V Capacitance(1) Symbol CIN Parameter Input Capacitance (3) (TA = +25°C, f = 1.0MHz) Conditions(2) VIN = 3dV V OUT = 3dV Max. 9 10 Unit pF pF 5654 tbl 07 TBIAS TSTG IOUT -55 to +125 -65 to +150 50 o C C COUT Output Capacitance o mA 5654 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V. NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references C I/O. 6.42 5 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (VDD = 2.5V ± 100mV) 70T9169/59L Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage VDD = 2.6V, VIN = 0V to VDD CE = VIH o r CE1 = VIL, VOUT = 0V to VDD IOL = + 2mA IOH = -2mA Test Conditions Min. ___ Max. 5 5 0.4 ___ Unit µA µA V V 5654 tbl 08 ___ ___ 2.0 NOTE: 1. At Vcc < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV) 70T9169/59L7 Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) Test Condition CEL and CER= VIL, Outputs Disabled, f = fMAX(1) CEL = CER = VIH f = fMAX(1) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) Both Ports CEL and CER >VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) Version COM'L IND COM'L IND COM'L IND COM'L IND L L L L L L L L L L ____ ____ 70T9169/59L9 Com'l & Ind Typ.(4) 75 75 20 20 47 47 0.1 0.1 47 47 Max. 175 220 50 70 100 190 3.0 3.0 100 190 70T9169/59L12 Com'l Only Typ.(4) 70 ____ Typ.(4) 80 ____ Max. 200 ____ Max. 150 ____ Unit mA ISB1 20 ____ 60 ____ 20 ____ 40 ____ mA ISB2 50 ____ 115 ____ 45 ____ 85 ____ mA ISB3 0.1 ____ 3.0 ____ 0.1 ____ 3.0 ____ mA ISB4 COM'L CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) IND VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) 50 115 45 ____ 85 ____ mA 5654 tbl 09 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS" at input levels of GND to 2.5V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 75mA (Typ). 5. CEX = V IL means CE 0X = V IL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6 6.42 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 2.5V 2ns Max. 1.25V 1.25V Figures 1 and 2 5654 tbl 10 50Ω DATAOUT 50Ω 1.25V 10pF / 5pF* (Tester) , 5654 drw 04 *(For tCKLZ, t CKHZ, t OLZ, Figure 1. AC Output Test load. and tOHZ ). ∆ tCD (Typical, ns) ∆ Capacitance (pF) from AC Test Load 5654 drw 06 Figure 2. Typical Output Derating (Lumped Capacitive Load). 6.42 7 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C) 70T9169/59L7 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSB tHB tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Clock Cycle Time (Flow-Through)(2) Clock Cycle Time (Pipelined) (2) (2) 70T9169/59L9 Com'l & Ind Min. 25 15 12 12 6 6 ____ 70T9169/59L12 Com'l Only Min. 30 20 12 12 8 8 ____ Parameter Min. 22 12 7.5 7.5 5 5 ____ Max. ____ ____ Max. ____ ____ Max. ____ ____ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock High Time (Flow-Through) ____ ____ ____ ____ ____ ____ ____ ____ ____ Clock Low Time (Flow-Through)(2) Clock High Time (Pipelined) Clock Low Time (Pipelined) Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time Byte Enable Setup Time Byte Enable Hold Time R/ W S etup Time R/ W Hold Time Input Data Setup Time Input Data Hold Time ADS S etup Time ADS Hold Time CNTEN S etup Time CNTEN Hold Time CNTRST S etup Time CNTRST Hold Time Output Enable to Data Valid Output Enable to Output Low-Z (1) (1) (2) (2) ____ ____ ____ 3 3 ____ ____ 3 3 ____ ____ 3 3 ____ ____ ____ ____ ____ 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 7.5 ____ 9 ____ 12 ____ 2 1 ____ ____ 2 1 ____ ____ 2 1 ____ ____ Output Enable to Output High-Z 7 18 7.5 ____ 7 20 9 ____ 7 25 12 ____ Clock to Data Valid (Flow-Through)(2) Clock to Data Valid (Pipelined) (2) Data Output Hold After Clock High Clock High to Output High-Z(1) Clock High to Output Low-Z (1) 2 2 2 2 2 2 2 2 2 9 ____ 9 ____ 9 ____ Port-to-Port Delay tCWDD tCCS Write Port Clock High to Read Data Delay Clock-to-Clock Setup Time ____ 28 10 ____ 35 15 ____ 40 15 ns ns ____ ____ ____ 5654 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, t CD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL. 8 6.42 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for .low-Through Output (FT/PIPE"X" = VIL)(3,6) tCYC1 tCH1 CLK CE0 tSC CE1 tHC tSC tHC tCL1 R/W tSW tSA tHW tHA An + 1 tCD1 tDC Qn tCKLZ(1) Qn + 1 tOHZ (1) ADDRESS (5) An An + 2 An + 3 tCKHZ (1) Qn + 2 tOLZ (1) DATAOUT tDC OE (2) tOE 5654 drw 07 Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,6) tCYC2 tCH2 CLK CE0 tSC CE1 tHC tSC (4) tCL2 tHC R/W tSW tHW tSA tHA An + 1 (1 Latency) tCD2 Qn tCKLZ (1) ADDRESS (5) An An + 2 tDC Qn + 1 An + 3 DATAOUT Qn + 2 (1) (6) tOHZ tOLZ (1) OE (2) tOE 5654 drw 08 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = V IL following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. "X" here denotes Left or Right port. The diagram is with respect to that port. 6.42 9 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of a Bank Select Pipelined Read(1,2) tCH2 CLK tSA ADDRESS(B1) tSC tHA A0 tHC tSC tCD2 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 A4 A5 A6 Q0 tDC tHC tCD2 tCKHZ Q1 tDC (3) tCYC2 tCL2 A1 A2 A3 A4 A5 A6 CE0(B1) tCD2 Q3 tCKLZ (3) tCKHZ (3) tSC CE0(B2) tSC tHC tHC tCD2 DATAOUT(B2) tCKLZ (3) tCKHZ (3) Q2 tCD2 tCKLZ (3) 5654 drw 09 Q4 Timing Waveform of Write with Port-to-Port .low-Through Read(4,5,7) CLK "A" tSW R/W "A" tSA ADDRESS "A" tHA NO MATCH tHW MATCH tSD DATAIN "A" tHD VALID tCCS CLK "B" (6) tCD1 R/W "B" tSW tSA ADDRESS "B" tHW tHA NO MATCH MATCH tCWDD DATAOUT "B" tDC (6) tCD1 VALID VALID tDC 5654 drw 10 NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70T9169/59 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS (B2) in this situation. 2. OE and ADS = VIL; CE 1(B1), CE1(B2) , R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD . If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. t CWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A". 10 6.42 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW ADDRESS (4) An tSA tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 DATAIN (2) tCD2 Qn READ tCKHZ (1) tCKLZ (1) tCD2 Qn + 3 DATAOUT NOP(5) WRITE READ 5654 drw 11 Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCH2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW tCYC2 tCL2 ADDRESS (4) An tSA tHA An +1 An + 2 tSD tHD An + 3 An + 4 An + 5 DATAIN (2) tCD2 Qn tOHZ(1) Dn + 2 Dn + 3 tCKLZ(1) tCD2 Qn + 4 DATAOUT OE READ WRITE READ 5654 drw 12 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE 0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 11 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of .low-Through Read-to-Write-to-Read (OE = VIL)(3) tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tSW tHW R/W tSW tHW tHC ADDRESS (4) An tSA tHA An +1 An + 2 An + 2 tSD tHD An + 3 An + 4 DATAIN (2) Dn + 2 tCD1 Qn tDC READ tCD1 Qn + 1 tCKHZ (5) NOP (1) tCD1 Qn + 3 tCKLZ WRITE (1) tCD1 DATAOUT tDC READ 5654 drw 13 Timing Waveform of .low-Through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W ADDRESS (4) tSW tHW An tSA tHA An +1 An + 2 tSD tHD Dn + 2 (2) An + 3 An + 4 An + 5 DATAIN tCD1 Qn tOHZ OE READ (1) Dn + 3 tDC tOE tCD1 (1) tCD1 Qn + 4 tDC DATAOUT tCKLZ WRITE READ 5654 drw 14 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. CE0 and ADS = VIL; CE1, CNTEN , and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 12 6.42 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2 An tSAD tHAD ADS tSAD tHAD CNTEN tCD2 DATAOUT Qx - 1(2) Qx tDC READ EXTERNAL ADDRESS READ WITH COUNTER Qn tSCN tHCN Qn + 1 Qn + 2(2) Qn + 3 COUNTER HOLD READ WITH COUNTER 5654 drw 15 Timing Waveform of .low-Through Read with Address Counter Advance(1) tCH1 CLK tSA ADDRESS tHA tCYC1 tCL1 An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 5654 drw 16 Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 NOTES: 1. CE 0 and OE = VIL, CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 6.42 13 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (.low-Through or Pipelined Outputs)(1) tCH2 CLK tSA ADDRESS tHA An tCYC2 tCL2 INTERNAL(3) ADDRESS tSAD tHAD ADS An(7) An + 1 An + 2 An + 3 An + 4 CNTEN tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 5654 drw 17 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCH2 CLK tSA tHA ADDRESS(4) INTERNAL(3) ADDRESS R/W ADS CNTEN tSRST tHRST CNTRST DATAIN DATAOUT(5) COUNTER(6) RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 tSD tHD D0 Q0 READ ADDRESS n Q1 READ ADDRESS n+1 5654 drw 18 tCYC2 tCL2 An Ax(6) tSW tHW An + 1 An + 2 0 1 An An + 1 Qn . NOTES: 1. CE0 and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0 = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written to during this cycle. 14 6.42 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges A .unctional Description The IDT70T9169/59 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. CE0 = VIH or CE1 = VIL for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70T9169/59's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required to get valid data on the outputs. Depth and Width Expansion The IDT70T9169/59 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70T9169/59 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 18-bit or wider applications. A14/A13(1) IDT70T9169/59 CE0 CE1 VDD IDT70T9169/59 CE 0 CE 1 VDD Control Inputs Control Inputs IDT70T9169/59 CE1 CE0 IDT70T9169/59 CE1 CE0 CNTRST CLK ADS CNTEN R/W OE Control Inputs Control Inputs 5654 drw 19 Figure 4. Depth and Width Expansion with IDT70T9169/59 NOTE: 1. A14 is for IDT70T9169, A13 is for IDT70T9159. 6.42 15 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 99 Speed A Package A Process/ Temperature Range Blank I(1) PF BF Commercial (0°C to +70°C) Industrial (-40°C to +85°C) 100-pin TQFP (PN100-1) 100-pin fpBGA (BF100) 7 9 12 L Commercial Only Commercial & Industrial Speed in nanoseconds Commercial Only Low Power .. 70T9169 144K (16K x 9-Bit) 2.5V Synchronous Dual-Port RAM 70T9159 72K (8K x 9-Bit) 2.5V Synchronous Dual-Port RAM 5654 drw 20 NOTE: 1. Contact your local sales office for Industrial temp range for other speeds, packages and powers. Datasheet Document History 07/08/02: Initial Public Release CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-611 6 fax: 408-492-8674 www.idt.com 16 6.42 for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.