79RC32435

IDTTM InterpriseTM Integrated Communications Processor 79RC32435 Device Overview The 79RC32435 is a member of the IDT™ Interprise™ family of PCI integrated communications processors. It incorporates a high performance CPU core and a number of on-chip peripherals. The integrated processor is designed to transfer information from I/O modules to main memory with minimal CPU intervention, using a highly sophisticated direct memory access (DMA) engine. All data transfers through the RC32435 are achieved by writing data from an on-chip I/O peripheral to main memory and then out to another I/O module. Features x 32-bit CPU Core – MIPS32 instruction set – Cache Sizes: 8KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches – 16 dual-entry JTLB with variable page sizes – 3-entry instruction TLB – 3-entry data TLB – Max issue rate of one 32x16 multiply per clock – Max issue rate of one 32x32 multiply every other clock – CPU control with start, stop, and single stepping – Software breakpoints support – Hardware breakpoints on virtual addresses – ICE Interface that is compatible with v2.5 of the EJTAG Specification PCI Interface – 32-bit PCI revision 2.2 compliant – Supports host or satellite operation in both master and target modes – Support for synchronous and asynchronous operation – PCI clock supports frequencies from 16 MHz to 66 MHz – PCI arbiter in Host mode: supports 6 external masters, fixed priority or round robin arbitration – I2O “like” PCI Messaging Unit x Ethernet Interface – 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant – Supports MII or RMII PHY interface – Supports 64 entry hash table based multicast address filtering – 512 byte transmit and receive FIFOs – Supports flow control functions outlined in IEEE Std. 802.3x1997 x DDR Memory Controller – Supports up to 256MB of DDR SDRAM – 1 chip select supporting 4 internal DDR banks – Supports a 16-bit wide data port using x8 or x16 bit wide DDR SDRAM devices – Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR SDRAM devices – Data bus multiplexing support allows interfacing to standard DDR DIMMs and SODIMMs – Automatic refresh generation x Block Diagram MII/RMII I2C Bus MIPS-32 CPU Core ICE EJTAG D. Cache PMBus Interrupt Controller : : 1 Ethernet 10/100 Interface MMU I. Cache 3 Counter Timers IPBusTM I2C Controller NVRAM Controller DMA Controller DDR (16-bit) DDR Controllers Arbiter Memory & I/O Controller Bus/System Integrity Monitor 1 UART (16550) GPIO Interface SPI Controller PCI Master/Target Interface PCI Arbiter (Host Mode) Memory & Peripheral Bus (8-bit) Serial Channel GPIO Pins SPI Bus PCI Bus IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 of 53  2005 Integrated Device Technology, Inc. January 19, 2006 DSC 6214 IDT 79RC32435 Non-Volatile RAM – Provides 512-bits of non-volatile storage – Eliminates need for external boot configuration vector – Stores initial PCI configuration register values when PCI configured to operate in satellite mode with suspended CPU execution – Authorization unit ensures only authorized software will operate on the system x Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 8-bit data bus, 26-bit address bus, 4 chip selects, control for external data bus buffers Automatic byte gathering and scattering – Flexible protocol configuration parameters: programmable number of wait states (0 to 63), programmable postread/postwrite delay (0 to 31), supports external wait state generation, supports Intel and Motorola style peripherals – Write protect capability per chip select – Programmable bus transaction timer generates warm reset when counter expires – Supports up to 64 MB of memory per chip select x DMA Controller – 6 DMA channels: two channels for PCI (PCI to Memory and Memory to PCI), two channels for the Ethernet interface, and two channels for memory to memory DMA operations – Provides flexible descriptor based operation – Supports unaligned transfers (i.e., source or destination address may be on any byte boundary) with arbitrary byte length x Universal Asynchronous Receiver Transmitter (UART) – Compatible with the 16550 and 16450 UARTs – 16-byte transmit and receive buffers – Programmable baud rate generator derived from the system clock – Fully programmable serial characteristics: – 5, 6, 7, or 8 bit characters – Even, odd or no parity bit generation and detection – 1, 1-1/2 or 2 stop bit generation – Line break generation and detection – False start bit detection – Internal loopback mode x I2C-Bus – Supports standard 100 Kbps mode as well as 400 Kbps fast mode – Supports 7-bit and 10-bit addressing – Supports four modes: master transmitter, master receiver, slave transmitter, slave receiver x Additional General Purpose Peripherals – Interrupt controller – System integrity functions – General purpose I/O controller – Serial peripheral interface (SPI) x Counter/Timers – Three general purpose 32-bit counter timers – Timers may be cascaded – Selectable counter/timer clock source x JTAG Interface – Compatible with IEEE Std. 1149.1 - 1990 x Core CPU Execution Core The 32-bit CPU core is 100% compatible with the MIPS32 instruction set architecture (ISA). Specifically, this device features the 4Kc CPU core developed by MIPS Technologies Inc. (www.mips.com). This core issues a single instruction per cycle, includes a five stage pipeline and is optimized for applications that require integer arithmetic. The CPU core includes 8 KB instruction and 8 KB data caches. Both caches are 4-way set associative and can be locked on a per line basis, which allows the programmer control over this precious on-chip memory resource. The core also features a memory management unit (MMU). The CPU core also incorporates an enhanced joint test access group (EJTAG) interface that is used to interface to in-circuit emulator tools, providing access to internal registers and enabling the part to be controlled externally, simplifying the system debug process. The use of this core allows IDT's customers to leverage the broad range of software and development tools available for the MIPS architecture, including operating systems, compilers, and in-circuit emulators. PCI Interface The PCI interface on the RC32435 is compatible with version 2.2 of the PCI specification. An on-chip arbiter supports up to six external bus masters, supporting both fixed priority and rotating priority arbitration schemes. The part can support both satellite and host PCI configurations, enabling the RC32435 to act as a slave controller for a PCI add-in card application or as the primary PCI controller in the system. The PCI interface can be operated synchronously or asynchronously to the other I/O interfaces on the RC32435 device. Ethernet Interface The RC32435 has one Ethernet Channel supporting 10Mbps and 100Mbps speeds to provide a standard media independent interface (MII or RMII), allowing a wide range of external devices to be connected efficiently. Double Data Rate Memory Controller The RC32435 incorporates a high performance double data rate (DDR) memory controller which supports x16 memory configurations up to 256MB. This module provides all of the signals required to interface to discrete memory devices, including a chip select, differential clocking outputs and data strobes. 2 of 53 January 19, 2006 IDT 79RC32435 I/ Controller Memory and I/O Controller The RC32435 uses a dedicated local memory/IO controller including a de-multiplexed 8-bit data and 26-bit address bus. It includes all of the signals required to interface directly to a maximum of four Intel or Motorola-style external peripherals. DMA Controller The DMA controller consists of 6 independent DMA channels, all of which operate in exactly the same manner. The DMA controller off-loads the CPU core from moving data among the on-chip interfaces, external peripherals, and memory. The controller supports scatter/gather DMA with no alignment restrictions, making it appropriate for communications and graphics systems. UART Interface The RC32435 contains a serial channel (UART) that is compatible with the industry standard 16550 UART. I2C Interface The standard I2C interface allows the RC32435 to connect to a number of standard external peripherals for a more complete system solution. The RC32435 supports both master and slave operations. General General Purpose I/O Controller The RC32435 has 14 general purpose input/output pins. Each pin may be used as an active high or active low level interrupt or nonmaskable interrupt input, and each signal may be used as a bit input or output port. System Integrity Functions The RC32435 contains a programmable watchdog timer that generates a non-maskable interrupt (NMI) when the counter expires and also contains an address space monitor that reports errors in response to accesses to undecoded address regions. Thermal Considerations The RC32435 is guaranteed in an ambient temperature range of 0° to +70° C for commercial temperature devices and - 40° to +85° for industrial temperature devices. Revision History Revision Histor y January 19, 2006: Initial publication. 3 of 53 January 19, 2006 IDT 79RC32435 Pin Description Table The following table lists the functions of the pins provided on the RC32435. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description Memory and Peripheral Bus BDIRN O External Buffer Direction. Controls the direction of the external data bus buffer for the memory and peripheral bus. If the RC32435 memory and peripheral bus is connected to the A side of a transceiver, such as an IDT74FCT245, then this pin may be directly connected to the direction control (e.g., BDIR) pin of the transceiver. External Buffer Enable. This signal provides an output enable control for an external buffer on the memory and peripheral data bus. Write Enables. This signal is the memory and peripheral bus write enable signal. Chip Selects. These signals are used to select an external device on the memory and peripheral bus. Address Bus. 22-bit memory and peripheral bus address bus. MADDR[25:22] are available as GPIO alternate functions. Data Bus. 8-bit memory and peripheral data bus. During a cold reset, these pins function as inputs that are used to load the boot configuration vector. Output Enable. This signal is asserted when data should be driven by an external device on the memory and peripheral bus. Read Write. This signal indicates whether the transaction on the memory and peripheral bus is a read transaction or a write transaction. A high level indicates a read from an external device. A low level indicates a write to an external device. Wait or Transfer Acknowledge. When configured as wait, this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle. When configured as a transfer acknowledge, this signal is asserted during a transaction to signal the completion of the transaction. BOEN WEN CSN[3:0] MADDR[21:0] MDATA[7:0] OEN RWN O O O O I/O O O WAITACKN I DDR Bus DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE O O O O DDR Address Bus. 14-bit multiplexed DDR address bus. This bus is used to transfer the addresses to the DDR devices. DDR Bank Address. These signals are used to transfer the bank address to the DDRs. DDR Column Address Strobe. This signal is asserted during DDR transactions. DDR Clock Enable. The DDR clock enable signal is asserted during normal DDR operation. This signal is negated following a cold reset or during a power down operation. DDR Negative DDR clock. This signal is the negative clock of the differential DDR clock pair. Table 1 Pin Description (Part 1 of 6) DDRCKN O 4 of 53 January 19, 2006 IDT 79RC32435 Signal DDRCKP DDRCSN DDRDATA[15:0] DDRDM[1:0] Type O O I/O O Name/Description DDR Positive DDR clock. This signal is the positive clock of the differential DDR clock pair. DDR Chip Selects. This active low signal is used to select DDR device(s) on the DDR bus. DDR Data Bus. 16-bit DDR data bus is used to transfer data between the RC32435 and the DDR devices. Data is transferred on both edges of the clock. DDR Data Write Enables. Byte data write enables are used to enable specific byte lanes during DDR writes. DDRDM[0] corresponds to DDRDATA[7:0] DDRDM[1] corresponds to DDRDATA[15:8] DDR Data Strobes. DDR byte data strobes are used to clock data between DDR devices and the RC32435. These strobes are inputs during DDR reads and outputs during DDR writes. DDRDQS[0] corresponds to DDRDATA[7:0] DDRDQS[1] corresponds to DDRDATA[15:8] DDR Row Address Strobe. The DDR row address strobe is asserted during DDR transactions. DDR Voltage Reference. SSTL_2 DDR voltage reference is generated by an external source. DDR Write Enable. DDR write enable is asserted during DDR write transactions. DDRDQS[1:0] I/O DDRRASN DDRVREF DDRWEN PCI Bus PCIAD[31:0] O I O I/O PCI Multiplexed Address/Data Bus. Address is driven by a bus master during initial PCIFRAMEN assertion. Data is then driven by the bus master during writes or by the bus target during reads. PCI Multiplexed Command/Byte Enable Bus. PCI commands are driven by the bus master during the initial PCIFRAMEN assertion. Byte enable signals are driven by the bus master during subsequent data phase(s). PCI Clock. Clock used for all PCI bus transactions. PCI Device Select. This signal is driven by a bus target to indicate that the target has decoded the address as one of its own address spaces. PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus transaction. Negation indicates the last data. PCI Bus Grant. In PCI host mode with internal arbiter: The assertion of these signals indicates to the agent that the internal RC32435 arbiter has granted the agent access to the PCI bus. In PCI host mode with external arbiter: PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32435 that access to the PCI bus has been granted. PCIGNTN[3:1]: unused and driven high. In PCI satellite mode: PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the RC32435 that access to the PCI bus has been granted. PCIGNTN[3:1]: unused and driven high. PCI Initiator Ready. Driven by the bus master to indicate that the current datum can complete. Table 1 Pin Description (Part 2 of 6) PCICBEN[3:0] I/O PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] I I/O I/O I/O PCIIRDYN I/O 5 of 53 January 19, 2006 IDT 79RC32435 Signal PCILOCKN PCIPAR Type I/O I/O Name/Description PCI Lock. This signal is asserted by an external bus master to indicate that an exclusive operation is occurring. PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during address and write Data phases. Driven by the bus target during the read data phase. PCI Parity Error. If a parity error is detected, this signal is asserted by the receiving bus agent 2 clocks after the data is received. PCI Bus Request. In PCI host mode with internal arbiter: These signals are inputs whose assertion indicates to the internal RC32435 arbiter that an agent desires ownership of the PCI bus. In PCI host mode with external arbiter: PCIREQN[0]: asserted by the RC32435 to request ownership of the PCI bus. PCIREQN[3:1]: unused and driven high. In PCI satellite mode: PCIREQN[0]: this signal is asserted by the RC32435 to request use of the PCI bus. PCIREQN[1]: function changes to PCIIDSEL and is used as a chip select during configuration read and write transactions. PCIREQN[3:2]: unused and driven high. PCI Reset. In host mode, this signal is asserted by the RC32435 to generate a PCI reset. In satellite mode, assertion of this signal initiates a warm reset. PCI System Error. This signal is driven by an agent to indicate an address parity error, data parity error during a special cycle command, or any other system error. Requires an external pull-up. PCI Stop. Driven by the bus target to terminate the current bus transaction. For example, to indicate a retry. PCI Target Ready. Driven by the bus target to indicate that the current data can complete. PCIPERRN PCIREQN[3:0] I/O I/O PCIRSTN PCISERRN I/O I/O PCISTOPN PCITRDYN I/O I/O General Purpose Input/Output GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0SOUT Alternate function: UART channel 0 serial output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0SINP Alternate function: UART channel 0 serial input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0RTSN Alternate function: UART channel 0 request to send. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0CTSN Alternate function: UART channel 0 clear to send. Table 1 Pin Description (Part 3 of 6) GPIO[1] I/O GPIO[2] I/O GPIO[3] I/O 6 of 53 January 19, 2006 IDT 79RC32435 Signal GPIO[4] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[22] Alternate function: Memory and peripheral bus address. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[23] Alternate function: Memory and peripheral bus address. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[24] Alternate function: Memory and peripheral bus address. The value of this pin may be used as a counter timer clock input (see Counter Timer Clock Select Register in Chapter 14, Counter/Timers, of the RC32435 User Manual). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[25] Alternate function: Memory and peripheral bus address. The value of this pin may be used as a counter timer clock input (see Counter Timer Clock Select Register in Chapter 14, Counter/Timers, of the RC32435 User Manual). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: CPU Alternate function: CPU or DMA debug output pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIREQN[4] Alternate function: PCI Request 4. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIGNTN[4] Alternate function: PCI Grant 4. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIREQN[5] Alternate function: PCI Request 5. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIGNTN[5] Alternate function: PCI Grant 5. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIMUINTN Alternate function: PCI Messaging unit interrupt output. GPIO[5] I/O GPIO[6] I/O GPIO[7] I/O GPIO[8] I/O GPIO[9] I/O GPIO[10] I/O GPIO[11] I/O GPIO[12] I/O GPIO[13] I/O SPI Interface SCK I/O Serial Clock. This signal is used as the serial clock output. This pin may be used as a bit input/output port. Table 1 Pin Description (Part 4 of 6) 7 of 53 January 19, 2006 IDT 79RC32435 Signal SDI SDO I C Bus Interface SCL SDA Ethernet Interfaces MIICL MIICRS MIIRXCLK I I I Ethernet MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected. Ethernet MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle. Ethernet MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data. This pin also functions as the RMII REF_CLK input. Ethernet MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY. This pin also functions as the RMII RXD[1:0] input. Ethernet MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus. This pin also functions as the RMII CRS_DV input. Ethernet MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the MII receive data bus. This pin also functions as the RMII RX_ER input. Ethernet MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data. Ethernet MII Transmit Data. This nibble wide data bus contains the data to be transmitted. This pin also functions as the RMII TXD[1:0] output. Ethernet MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission. This pin also functions as the RMII TX_EN output. Ethernet MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols which are not valid data or delimiters. MII Management Data Clock. This signal is used as a timing reference for transmission of data on the management interface. MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the ethernet PHY. I/O I/O I2C Clock. I2C-bus clock. I2C Data Bus. I2C-bus data bus. 2 Type I/O I/O Name/Description Serial Data Input. This signal is used to shift in serial data. This pin may be used as a bit input/output port. Serial Data Output. This signal is used shift out serial data. MIIRXD[3:0] I MIIRXDV I MIIRXER I MIITXCLK MIITXD[3:0] I O MIITXENP O MIITXER O MIIMDC MIIMDIO EJTAG / JTAG JTAG_TMS O I/O I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. When using the EJTAG debug interface, this pin should be left disconnected (since there is an internal pull-up) or driven high. Table 1 Pin Description (Part 5 of 6) 8 of 53 January 19, 2006 IDT 79RC32435 Signal EJTAG_TMS Type I Name/Description EJTAG Mode. The value on this signal controls the test mode select of the EJTAG Controller. When using the JTAG boundary scan, this pin should be left disconnected (since there is an internal pull-up) or driven high. JTAG Reset. This active low signal asynchronously resets the boundary scan logic, JTAG TAP Controller, and the EJTAG Debug TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board 3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high. JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic, JTAG Controller, or the EJTAG Controller. JTAG_TCK is independent of the system and the processor clock with a nominal 50% duty cycle. JTAG Data Output. This is the serial data shifted out from the boundary scan logic, JTAG Controller, or the EJTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Data Input. This is the serial data input to the boundary scan logic, JTAG Controller, or the EJTAG Controller. JTAG_TRST_N I JTAG_TCK I JTAG_TDO O JTAG_TDI System CLK I I Master Clock. This is the master clock input. The processor frequency is a multiple of this clock frequency. This clock is used as the system clock for all memory and peripheral bus operations. Load External Boot Configuration Vector. When this pin is asserted (i.e., high) the boot configuration vector is loaded from an externally supplied value during a cold reset. When this pin is negated, the boot configuration vector is taken from the NVRAM located on-chip. External Clock. This clock is used for all memory and peripheral bus operations. Cold Reset. The assertion of this signal initiates a cold reset. This causes the processor state to be initialized, boot configuration to be loaded, and the internal PLL to lock onto the master clock (CLK). Reset. The assertion of this bidirectional signal initiates a warm reset. This signal is asserted by the RC32435 during a warm reset. Table 1 Pin Description (Part 6 of 6) EXTBCV I EXTCLK COLDRSTN O I RSTN I/O 9 of 53 January 19, 2006 IDT 79RC32435 Pin Characteristics Note: Some input pads of the RC32435 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs (such as WAITACKN) which, if left floating, could adversely affect the RC32435’s operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Memory and Peripheral Bus Pin Name BDIRN BOEN WEN CSN[3:0] MADDR[21:0] MDATA[7:0] OEN RWN WAITACKN DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE DDRCKN DDRCKP DDRCSN DDRDATA[15:0] DDRDM[1:0] DDRDQS[1:0] DDRRASN DDRVREF DDRWEN PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[3:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN GPIO[8:0] GPIO[13:9] Type O O O O I/O I/O O O I O O O O O O O I/O O I/O O I O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL SSTL_2 SSTL_2 SSTL_2 SSTL_2 / LVCMOS SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 Analog SSTL_2 PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI LVTTL PCI I/O Type High Drive High Drive High Drive High Drive High Drive High Drive High Drive High Drive STI Internal Resistor Notes1 pull-up DDR Bus PCI Bus Interface pull-up on board pull-up on board pull-up on board pull-up on board Open Collector pull-up on board pull-down on board pull-up on board pull-up on board pull-up on board pull-up pull-up on board General Purpose I/O High Drive Table 2 Pin Characteristics (Part 1 of 2) 10 of 53 January 19, 2006 IDT 79RC32435 Function Serial Peripheral Interface I2C-Bus Interface Ethernet Interfaces Pin Name SCK SDI SDO SCL SDA MIICL MIICRS MIIRXCLK MIIRXD[3:0] MIIRXDV MIIRXER MIITXCLK MIITXD[3:0] MIITXENP MIITXER MIIMDC MIIMDIO JTAG_TMS EJTAG_TMS JTAG_TRST_N JTAG_TCK JTAG_TDO JTAG_TDI CLK EXTBCV EXTCLK COLDRSTN RSTN Type I/O I/O I/O I/O I/O I I I I I I I O O O O I/O I I I I O I I I O I I/O Buffer LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL I/O Type High Drive High Drive High Drive Low Drive/STI Low Drive/STI STI STI STI STI STI STI STI Low Drive Low Drive Low Drive Low Drive Low Drive STI STI STI STI Low Drive STI STI STI High Drive STI Low Drive / STI Internal Resistor pull-up pull-up pull-up Notes1 pull-up on board pull-up on board pull-up on board pull-up on board2 pull-up on board2 pull-down pull-down pull-up pull-up pull-down pull-down pull-up EJTAG / JTAG pull-up pull-up pull-up pull-up pull-up pull-up pull-down System pull-up pull-up on board Table 2 Pin Characteristics (Part 2 of 2) 1. External pull-up required in most system applications. Some applications may require additional pull-ups not identified in this table. a 2.2K pull-up resistor for I2C pins. 2. Use 11 of 53 January 19, 2006 IDT 79RC32435 Boot Configuration Vector The encoding of the boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. The value of the boot configuration vector read in by the RC32435 during a cold reset may be determined by reading the Boot Configuration Vector (BCV) Register. Signal MADDR[3:0] Name/Description CPU Pipeline Clock Multiplier. This field specifies the value by which the PLL multiplies the master clock input (CLK) to obtain the processor clock frequency (PCLK). For master clock input frequency constraints, refer to Table 3.2 in the RC32435 User Manual. 0x0 - PLL Bypass 0x1 - Multiply by 3 0x2 - Multiply by 4 0x3 - Multiply by 5 - Reserved 0x4 - Multiply by 5 0x5 - Multiply by 6 - Reserved 0x6 - Multiply by 6 0x7 - Multiply by 8 0x8 - Multiply by 10 0x9 through 0xF - Reserved External Clock Divider. This field specifies the value by which the IPBus clock (ICLK), which is always 1/2 PCLK, is divided in order to generate the external clock output on the EXTCLK pin. 0x0 - Divide by 1 0x1 - Divide by 2 0x2 - Divide by 4 0x3 - reserved Endian. This bit specifies the endianness. 0x0 - little endian 0x1 - big endian Reset Mode. This bit specifies the length of time the RSTN signal is driven. 0x0 - Normal reset: RSTN driven for minimum of 4000 clock cycles. If the internal boot configuration vector is selected, the expiration of an 18-bit counter operating at the master clock input (CLK) frequency is used as the PLL stabilization delay. 0x1 - Reserved PCI Mode. This bit controls the operating mode of the PCI bus interface. The initial value of the EN bit in the PCIC register is determined by the PCI mode. 0x0 - Disabled (EN initial value is zero) 0x1 - PCI satellite mode with PCI target not ready (EN initial value is one) 0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one) 0x3 - PCI host mode with external arbiter (EN initial value is zero) 0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm (EN initial value is zero) 0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm (EN initial value is zero) 0x6 - reserved 0x7 - reserved Table 3 Boot Configuration Encoding (Part 1 of 2) MADDR[5:4] MADDR[6] MADDR[7] MADDR[10:8] 12 of 53 January 19, 2006 IDT 79RC32435 Signal MADDR[11] Name/Description Disable Watchdog Timer. When this bit is set, the watchdog timer is disabled following a cold reset. 0x0 - Watchdog timer enabled 0x1 - Watchdog timer disabled Reserved. These pins must be driven low during boot configuration. Reserved. Must be set to zero. Table 3 Boot Configuration Encoding (Part 2 of 2) MADDR[13:12] MADDR[15:14] 13 of 53 January 19, 2006 IDT 79RC32435 RC32435 Logic Diagram — RC32435 CLK COLDRSTN RSTN EXTCLK EXTBCV BDIRN BOEN WEN CSN[3:0] MADDR[21:0] MDATA[7:0] OEN RWN WAITACKN System Signals 4 22 8 Memory and Peripheral Bus Ethernet MIIMDC MIIMDIO MIICL MIICRS MIIRXCLK MIIRXD[3:0] MIIRXDV MIIRXER MIITXCLK MIITXD[3:0] MIITXENP MIITXER 14 2 4 4 16 2 2 EJTAG / JTAG Signals JTAG_TRST_N JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS EJTAG_TMS DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE DDRCKN DDRCKP DDRCSN DDRDATA[15:0] DDRDM[1:0] DDRDQS[1:0] DDRRASN DDRVREF DDRWEN DDR Bus RC32435 32 4 General Purpose I/O GPIO[13:0] 14 4 SPI SDO SCK SDI 4 PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[3:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN PCI Bus I2C-Bus SDA SCL VccCore VccI/O Vss VccPLL VssPLL Power/Ground Figure 1 Logic Diagram 14 of 53 January 19, 2006 IDT 79RC32435 AC Timing Definitions Below are examples of the AC timing characteristics used throughout this document. Tlow Tper clock Tdo Output signal 1 Tzd Output signal 2 Tsu Input Signal 1 Tpw Signal 1 Signal 2 Signal 3 Tskew Thld Tdz Tdo Tjitter Trise Tfall Thigh Figure 2 AC Timing Definitions Waveform Symbol Tper Tlow Thigh Trise Tfall Tjitter Tdo Tzd Tdz Tsu Thld Tpw Tslew X(clock) Tskew Clock period. Clock low. Amount of time the clock is low in one clock period. Definition Clock high. Amount of time the clock is high in one clock period. Rise time. Low to high transition time. Fall time. High to low transition time. Jitter. Amount of time the reference clock (or signal) edge can vary on either the rising or falling edges. Data out. Amount of time after the reference clock edge that the output will become valid. The minimum time represents the data output hold. The maximum time represents the earliest time the designer can use the data. Z state to data valid. Amount of time after the reference clock edge that the tri-stated output takes to become valid. Data valid to Z state. Amount of time after the reference clock edge that the valid output takes to become tri-stated. Input set-up. Amount of time before the reference clock edge that the input must be valid. Input hold. Amount of time after the reference clock edge that the input must remain valid. Pulse width. Amount of time the input or output is active for asynchronous signals. Slew rate. The rise or fall rate for a signal to go from a high to low, or low to high. Timing value. This notation represents a value of ‘X’ multiplied by the clock time period of the specified clock. Using 5(CLK) as an example: X = 5 and the oscillator clock (CLK) = 25MHz, then the timing value is 200. Skew. The amount of time two signal edges deviate from one another. Table 4 AC Timing Definitions 15 of 53 January 19, 2006 IDT 79RC32435 System Clock Parameters (Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 15 and 16.) 266MHz Min 200 3.8 none 100 7.5 none 25 8.0 40 — — Max 266 5.0 133 10.0 125 40.0 60 3.0 0.1 300MHz Min 200 3.3 100 6.7 25 8.0 40 — — Max 300 5.0 150 10.0 125 40.0 60 3.0 0.1 350MHz Min 200 2.85 100 5.7 25 8.0 40 — — Max 350 5.0 175 10.0 125 40.0 60 3.0 0.1 400MHz Min 200 2.5 100 5.0 25 8.0 40 — — Max 400 5.0 200 10.0 125 40.0 60 3.0 0.1 Timing Diagram Reference See Figure 3. Parameter PCLK1 ICLK2,3,4 CLK5 Symbol Frequency Tper Frequency Tper Frequency Tper_5a Thigh_5a, Tlow_5a Trise_5a, Tfall_5a Tjitter_5a Reference Edge none Units MHz ns MHz ns MHz ns % of Tper_5a ns ns Table 5 Clock Parameters 1. The CPU pipeline clock (PCLK) speed is selected during cold reset by the boot configuration vector (see Table 3). Refer to Chapter 3, Clocking and Initialization, in the RC32435 User Reference Manual for the allowable frequency ranges of CLK and PCLK. 2. ICLK is the internal IPBus clock. It is always equal to PCLK divided by 2. This clock cannot be sampled externally. (MIIxRXCLK and MIIxTXCLK) frequency must be equal to or less than 1/2 ICLK (MIIxRXCLK and MIIxTXCLK VOUT > 0 Conditions VOL = 0.4V VOH = 1.5V VOL = 0.4V VOH = 1.5V — — VOL = 0.5V VOH = 1.76V — — — — — — — — — — — — — — 0.5(VccSI/O) - 0.18 VccSI/O + 0.3 — — -32(VccI/O) See Note 1 — — +38(VccI/O) See Note 2 0.3(VccI/O) 5.5 10.5 + 10 + 10 — 16(VccI/O) IOL(AC) Switching +16(VccI/O) +26.7(VOUT) — — VIL VIH Capacitance Leakage CIN -0.3 0.5(VccI/O) — — — — — — — — Inputs I/OLEAK W/O Pull-ups/ downs I/OLEAK WITH Pull-ups/ downs µA µA — — + 80 µA Vcc (max) Table 18 DC Electrical Characteristics Note 1: IOH(AC) max = (98/VCCI/O) * (VOUT - VCCI/O) * (VOUT + 0.4VCCI/O) Note 2: IOL(AC) max = (256/VCCI/O) * VOUT * (VCCI/O - VOUT) 38 of 53 January 19, 2006 IDT 79RC32435 AC Test Conditions Input Reference Voltage 50 Ω RC32435 Output . 50 Ω Test Point Value Parameter Input pulse levels Input rise/fall Input reference level Output reference levels AC test load SSTL I/O 0 to 2.5 0.8 0.5(VccSI/O) 1.25 35 Other I/O 0 to 3.3 1.0 0.5(VccI/O) 1.5 35 Units V ns V V pF Figure 23 AC Test Conditions 39 of 53 January 19, 2006 IDT 79RC32435 Absolute Maximum Ratings Symbol VCCI/O VCCSI/O (DDR) VCCCore VCCPLL VCCAPLL VinI/O VinSI/O Ta Industrial Ta Commercial Ts 1. Parameter I/O supply except for SSTL_22 I/O supply for SSTL_2 Core Supply Voltage PLL supply (digital) PLL supply (analog) I/O Input Voltage except for SSTL_2 I/O Input Voltage for SSTL_2 Ambient Operating Temperature Ambient Operating Temperature Storage Temperature 2 Min1 -0.6 -0.6 -0.6 -0.6 -0.6 -0.6 -0.6 -40 0 -40 Max1 4.0 4.0 2.0 2.0 4.0 VccI/O+ 0.5 VccSI/O+ 0.5 +85 +70 +125 Unit V V V V V V V °C °C °C Table 19 Absolute Maximum Ratings Functional and tested operating conditions are given in Table 15. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. SSTL_2 I/Os are used to connect to DDR SDRAM. 2. 40 of 53 January 19, 2006 IDT 79RC32435 Signal Package Pin-out — 256-BGA Signal Pinout for the RC32435 RC32435 The following table lists the pin numbers, signal names, and number of alternate functions for the RC32435 device. Signal names ending with an “_n” or “n” are active when low. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 Function RWN OEN CSN[2] CSN[0] MADDR[10] MDATA[6] GPIO[7] GPIO[4] MADDR[16] MADDR[13] Vss PLL JTAG_TDI MADDR[9] MADDR[7] MADDR[5] MADDR[2] BOEN RSTN CSN[3] CSN[1] MADDR[11] MDATA[1] MDATA[4] GPIO[5] MADDR[17] MADDR[12] Vcc PLL Vss APLL MADDR[8] MADDR[6] MADDR[3] MADDR[1] EXTCLK 1 1 1 Alt Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 Function MIIRXD[3] MIIRXD[2] MIITXD[0] MIITXD[1] Vcc I/0 Vcc I/0 Vcc I/0 Vcc CORE Vcc CORE Vcc I/0 Vcc DDR Vcc DDR DDRDATA[6] DDRDATA[5] DDRADDR[13] DDRDATA[4] MIITXD[2] MIIRXCLK MIITXD[3] MIITXENP Vcc I/0 Vss Vss Vss Vcc CORE Vss Vss Vcc DDR DDRDATA[9] DDRDATA[8] DDRDM[0] DDRDATA[7] MIIRXDV Alt Pin J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 Function GPIO[3] JTAG_TCK GPIO[2] EJTAG_TMS Vcc CORE Vss Vss Vss Vss Vss Vcc CORE Vcc CORE DDRCKN DDRVREF DDRCKP DDRDQS[0] JTG_TDO SCK Reserved SDO Vcc I/0 Vcc I/0 Vss Vss Vss Vss Vss Vcc DDR DDRCKE DDRADDR[11] DDRADDR[10] DDRADDR[12] SDA 1 Alt 1 Pin N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 Function PCIAD[29] PCIAD[28] PCIAD[30] PCIAD[18] PCIREQN[1] PCIREQN[2] PCIIRDYN PCILOCKN PCIPERRN PCIAD[15] PCIAD[11] PCICBEN[0] DDRADDR[5] DDRADDR[4] DDRADDR[3] DDRBA[0] PCIAD[27] PCIAD[26] GPIO[10] PCIAD[20] PCIREQN[3] PCIREQN[0] PCIFRAMEN PCISTOPN PCISERRN PCIAD[14] PCIAD[10] PCIAD[7] PCIAD[4] DDRADDR[0] DDRADDR[2] DDRCSN PCIAD[25] 1 Alt Table 20 RC32435 Pinout (Part 1 of 2) 41 of 53 January 19, 2006 IDT 79RC32435 Pin C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 Function BDIRN COLDRSTN WEN MDATA[3] MDATA[5] GPIO[6] MADDR[21] MADDR[18] MADDR[14] JTAG_TMS Vcc APLL CLK MADDR[4] MADDR[0] DDRDATA[0] MIIRXD[0] MIICL MIICRS MIIRXD[1] MDATA[7] MDATA[2] MDATA[0] MADDR[20] MADDR[19] MADDR[15] EXTBCV JTAG_TRSTN WAITACKN DDRDATA[2] DDRDATA[3] DDRDATA[1] 1 Alt Pin G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 Function MIITXER MIIRXER MIITXCLK Vcc I/0 Vss Vss Vss Vss Vss Vss Vcc DDR DDRDM[1] DDRDQS[1] DDRDATA[10] DDRDATA[11] MIIMDIO MIIMDC GPIO[0] GPIO[1] Vcc CORE Vcc CORE Vss Vss Vss Vss Vss Vcc CORE DDRDATA[15] DDRDATA[14] DDRDATA[12] DDRDATA[13] 1 1 Alt Pin L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 SCL GPIO[8] SDI Vcc I/0 Vss Vss Vcc CORE Vss Vss Vss Vcc DDR DDRADDR[9] DDRWEN DDRCASN DDRADDR[8] GPIO[12] PCIAD[31] GPIO[11] GPIO[9] Vcc I/0 Vcc I/0 Vcc I/0 Vcc CORE Vcc CORE Vcc I/0 Vcc DDR Vcc DDR DDRRASN DDRBA[1] DDRADDR[6] DDRADDR[7] 1 1 1 1 Function Alt Pin R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Function PCICBEN[3] PCIAD[23] PCIAD[21] PCIAD[17] PCIRSTN PCICBEN[2] PCITRDYN PCICBEN[1] PCIAD[12] PCIAD[8] PCIAD[5] PCIAD[3] PCIAD[0] PCIGNTN[2] DDRADDR[1] PCIAD[24] GPIO[13] PCIAD[22] PCIAD[19] PCIAD[16] PCICLK PCIGNTN[0] PCIDEVSELN PCIPAR PCIAD[13] PCIAD[9] PCIAD[6] PCIAD[2] PCIAD[1] PCIGNTN[1] PCIGNTN[3] 1 Alt Table 20 RC32435 Pinout (Part 2 of 2) 42 of 53 January 19, 2006 IDT 79RC32435 RC32435 Alternate RC32435 Alternate Signal Functions Pin A7 A8 B8 C7 H3 H4 J1 GPIO GPIO[7] GPIO[4] GPIO[5] GPIO[6] GPIO[0] GPIO[1] GPIO[3] Alternate MADDR[25] MADDR[22] MADDR[23] MADDR[24] U0SOUT U0SINP U0CTSN Pin J3 L3 M1 M3 M4 P3 T2 GPIO GPIO[2] GPIO[8] GPIO[12] GPIO[11] GPIO[9] GPIO[10] GPIO[13] Alternate U0RTSN CPU PCIGNTN[5] PCIREQN[5] PCIREQN[4] PCIGNTN[4] PCIMUINTN Table 21 RC32435 Alternate Signal Functions RC32435 Power RC RC32435 Power Pins Vcc I/O E5 E6 E7 E10 F5 G5 K5 K6 L5 M5 M6 M7 M10 Table 22 RC32435 Power Pins Vcc DDR E11 E12 F12 G12 K12 L12 M11 M12 Vcc Core E8 E9 F9 H5 H6 H12 J5 J11 J12 L8 M8 M9 Vcc PLL B11 Vcc APLL C12 43 of 53 January 19, 2006 IDT 79RC32435 RC32435 Ground RC32435 Ground Pins Vss F6 F7 F8 F10 F11 G6 G7 G8 G9 G10 G11 H7 H8 H9 H10 H11 Table 23 RC32435 Ground Pins Vss J6 J7 J8 J9 J10 K7 K8 K9 K10 K11 L6 L7 L9 L10 L11 Vss PLL A11, B12 Signals RC32435 Signals Listed Alphabetically The following table lists the RC32435 pins in alphabetical order. Signal Name BDIRN BOEN CLK COLDRSTN CSN[0] CSN[1] CSN[2] CSN[3] I/O Type O O I I O O O O Location C2 B1 C13 C3 A4 B4 A3 B3 Signal Category Memory and Peripheral Bus System Memory and Peripheral Bus Table 24 RC32435 Alphabetical Signal List (Part 1 of 7) 44 of 53 January 19, 2006 IDT 79RC32435 Signal Name DDRADDR[0] DDRADDR[1] DDRADDR[2] DDRADDR[3] DDRADDR[4] DDRADDR[5] DDRADDR[6] DDRADDR[7] DDRADDR[8] DDRADDR[9] DDRADDR[10] DDRADDR[11] DDRADDR[12] DDRADDR[13] DDRBA[0] DDRBA[1] DDRCASN DDRCKE DDRCKN DDRCKP DDRCSN DDRDATA[0] DDRDATA[1] DDRDATA[2] DDRDATA[3] DDRDATA[4] DDRDATA[5] DDRDATA[6] DDRDATA[7] DDRDATA[8] DDRDATA[9] DDRDATA[10] DDRDATA[11] DDRDATA[12] DDRDATA[13] DDRDATA[14] I/O Type O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location P14 R16 P15 N15 N14 N13 M15 M16 L16 L13 K15 K14 K16 E15 N16 M14 L15 K13 J13 J15 P16 C16 D16 D14 D15 E16 E14 E13 F16 F14 F13 G15 G16 H15 H16 H14 Signal Category DDR Bus Table 24 RC32435 Alphabetical Signal List (Part 2 of 7) 45 of 53 January 19, 2006 IDT 79RC32435 Signal Name DDRDATA[15] DDRDM[0] DDRDM[1] DDRDQS[0] DDRDQS[1] DDRRASN DDRVREF DDRWEN EJTAG_TMS EXTBCV EXTCLK GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRSTN I/O Type I/O O O I/O I/O O I O I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O I I Location H13 F15 G13 J16 G14 M13 J14 L14 J4 D11 C1 H3 H4 J3 J1 A8 B8 C7 A7 L3 M4 P3 M3 M1 T2 J2 A12 K1 C11 D12 JTAG / EJTAG General Purpose Input/Output JTAG / EJTAG System Signal Category DDR Bus Table 24 RC32435 Alphabetical Signal List (Part 3 of 7) 46 of 53 January 19, 2006 IDT 79RC32435 Signal Name MADDR[0] MADDR[1] MADDR[2] MADDR[3] MADDR[4] MADDR[5] MADDR[6] MADDR[7] MADDR[8] MADDR[9] MADDR[10] MADDR[11] MADDR[12] MADDR[13] MADDR[14] MADDR[15] MADDR[16] MADDR[17] MADDR[18] MADDR[19] MADDR[20] MADDR[21] MDATA[0] MDATA[1] MDATA[2] MDATA[3] MDATA[4] MDATA[5] MDATA[6] MDATA[7] I/O Type O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O Location C15 B16 A16 B15 C14 A15 B14 A14 B13 A13 A5 B5 B10 A10 C10 D10 A9 B9 C9 D9 D8 C8 D7 B6 D6 C5 B7 C6 A6 D5 Signal Category Memory and Peripheral Bus Table 24 RC32435 Alphabetical Signal List (Part 4 of 7) 47 of 53 January 19, 2006 IDT 79RC32435 Signal Name MIICL MIICRS MIIMDC MIIMDIO MIIRXCLK MIIRXD[0] MIIRXD[1] MIIRXD[2] MIIRXD[3] MIIRXDV MIIRXER MIITXCLK MIITXD[0] MIITXD[1] MIITXD[2] MIITXD[3] MIITXENP MIITXER OEN PCIAD[0] PCIAD[1] PCIAD[2] PCIAD[3] PCIAD[4] PCIAD[5] PCIAD[6] PCIAD[7] PCIAD[8] PCIAD[9] PCIAD[10] PCIAD[11] PCIAD[12] PCIAD[13] PCIAD[14] PCIAD[15] PCIAD[16] I/O Type I I O I/O I I I I I I I I O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location D2 D3 H2 H1 F2 D1 D4 E2 E1 G1 G3 G4 E3 E4 F1 F3 F4 G2 A2 R14 T14 T13 R13 P13 R12 T12 P12 R11 T11 P11 N11 R10 T10 P10 N10 T5 Memory and Peripheral Bus PCI Bus Interface Signal Category Ethernet Interface Table 24 RC32435 Alphabetical Signal List (Part 5 of 7) 48 of 53 January 19, 2006 IDT 79RC32435 Signal Name PCIAD[17] PCIAD[18] PCIAD[19] PCIAD[20] PCIAD[21] PCIAD[22] PCIAD[23] PCIAD[24] PCIAD[25] PCIAD[26] PCIAD[27] PCIAD[28] PCIAD[29] PCIAD[30] PCIAD[31] PCIBEN[0] PCIBEN[1] PCIBEN[2] PCIBEN[3] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[0] PCIGNTN[1] PCIGNTN[2] PCIGNTN[3] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[0] PCIREQN[1] PCIREQN[2] PCIREQN[3] PCIRSTN PCISERRN I/O Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location R5 N4 T4 P4 R4 T3 R3 T1 R1 P2 P1 N2 N1 N3 M2 N12 R9 R7 R2 T6 T8 P7 T7 T15 R15 T16 N7 N8 T9 N9 P6 N5 N6 P5 R6 P9 Signal Category PCI Bus Interface Table 24 RC32435 Alphabetical Signal List (Part 6 of 7) 49 of 53 January 19, 2006 IDT 79RC32435 Signal Name PCISTOPN PCITRDYN RSTN RWN SCK SCL SDA SDI SDO Vcc APLL Vcc Core I/O Type I/O I/O I/O O I/O I/O I/O I/O I/O Location P8 R8 B2 A1 K2 L2 L1 L4 K4 C12 E8, E9, F9, H5, H6, H12, J5, J11, J12, L8, M8, M9 E11, E12, F12, G12, K12, L12, M11, M12 E5, E6, E7, E10, F5, G5, K5, K6, L5, M5, M6, M7, M10 B11 F6, F7, F8, F10, F11, G6, G7, G8, G9, G10, G11, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, K7, K8, K9, K10, K11, L6, L7, L9, L10, L11 B12 A11 I O D13 C4 K3, L1, L2 Table 24 RC32435 Alphabetical Signal List (Part 7 of 7) Memory and Peripheral Bus Ground Power Serial Peripheral Interface System Memory and Peripheral Bus Serial Peripheral Interface I2C Signal Category PCI Bus Interface Vcc DDR Vcc I/O Vcc PLL Vss Vss APLL Vss PLL WAITACKN WEN Reserved 50 of 53 January 19, 2006 IDT 79RC32435 Package CABGA RC32435 Package Drawing — 256-pin CABGA 51 of 53 January 19, 2006 IDT 79RC32435 RC32435 Package RC32435 Package Drawing Page — Page Two 52 of 53 January 19, 2006 IDT 79RC32435 Ordering Information 79RCXX Product Type YY Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process Blank I Commercial Temperature (0°C to +70°C Ambient) Industrial Temperature (-40° C to +85° C Ambient) 256-pin CABGA 266 MHz Pipeline Clk 300 MHz Pipeline Clk 350 MHz Pipeline Clk 400 MHz Pipeline Clk Integrated Core Processor BC 266 300 350 400 435 H 79RC32 1.2V +/- 0.1V Core Voltage 32-bit Embedded Microprocessor Valid Valid Combinations 79RC32H435 - 266BC, 300BC, 350BC, 400BC 79RC32H435 - 266BCI, 300BCI, 350BCI 256-pin CABGA package, Commercial Temperature 256-pin CABGA package, Industrial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: rischelp@idt.com phone: 408-284-8208 53 of 53 January 19, 2006