8344AY-01

LOW SKEW, 1-TO-24 DIFFERENTIALTO-LVCMOS/LVTTL FANOUT BUFFER ICS8344-01 GENERAL DESCRIPTION The ICS8344-01 is a low voltage, low skew IC S fanout buffer and a member of the HiPerClockS ™ HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS8344-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most standard differential input levels. The ICS8344-01 is designed to translate any differential signal level to LVCMOS/LVTTL levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock inputs which also facilitate board level testing. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. The outputs are driven low when disabled. The ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS8344-01 ideal for those clock distribution applications demanding well defined performance and repeatability. FEATURES • Twenty-four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Two selectable differential CLKx, nCLKx inputs • CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Output frequency up to 250MHz • Translates any single ended input signal to LVCMOS/LVTTL with resistor bias on nCLK input • Synchronous clock enable • Additive phase jitter RMS: 0.21ps (typical) • Output skew: 200ps (maximum) • Part-to-part skew: 900ps (maximum) • Bank skew: 85ps (maximum) • Propagation delay: 5ns (maximum) • Output supply modes: Core/Output 3.3V/3.3V 2.5V/2.5V 3.3V/2.5V • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM CLK_SEL Pulldown CLK0 Pulldown nCLK0 Pullup CLK1 Pulldown nCLK1 Pullup 0 1 Q0:Q7 PIN ASSIGNMENT 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 48-Lead LQFP 6 31 7mm x 7mm x 1.4mm 7 30 package body 8 29 Y Package 9 28 Top View 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 Q8 Q9 VDDO GND Q10 Q11 Q12 Q13 VDDO GND Q14 Q15 Q8:Q15 Q16:Q23 LE Q Q16 Q17 VDDO GND Q18 Q19 Q20 Q21 VDDO GND Q22 Q23 ICS8344-01 Q7 Q6 VDDO GND Q5 Q4 Q3 Q2 VDDO GND Q1 Q0 CLK_EN Pullup nc OE CLK_EN CLK0 nCLK0 VDD GND CLK1 nCLK1 VDD GND CLK_SEL nD OE Pullup IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 1 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 2, 5, 6 7, 8, 11, 12 3, 9, 28, 34, 39, 45 4, 10, 14,18, 27, 33, 40, 46 13 15, 19 16 17 20 21 22 23 Name Q16, Q17, Q18, Q19 Q20, Q21, Q22, Q23 VDDO GND CLK_SEL VDD nCLK1 CLK1 nCLK0 CLK0 CLK_EN OE Type Output Power Power Input Power Input Input Input Input Input Input Description Q16 thru Q23 outputs. 7Ω typical output impedance. Output supply pins. Connect 3.3V or 2.5V. Power supply ground. Connect to ground. Clock select input. When HIGH, selects CLK1, nCLK inputs, Pulldown When LOW, selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levelss. Positive supply pins. Connect 3.3V or 2.5V. Pullup Pullup Inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pulldown Non-inver ting differential LVPECL clock input. Pulldown Non-inver ting differential LVPECL clock input. Synchronizing control for enabling and disabling clock outputs. Pullup LVCMOS interface levels. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q23. No connect. 24 nc Unused 25, 26, 29, 30 Q0, Q1, Q2, Q3 Output Q0 thru Q7 outputs. 7Ω typical output impedance. 31, 32, 35, 36 Q4, Q5, Q6, Q7 37, 38, 41, 42 Q8, Q9, Q10, Q11 Output Q8 thru Q15 outputs. 7Ω typical output impedance. 43, 44, 47, 48 Q12, Q13, Q14, Q15 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN Parameter Input Capacitance CLK0, nCLK0, CLK1, nCLK1 CLK_SEL, CLK_EN, OE VDDO = 3.465V VDDO = 2.675V 23 16 51 51 7 Test Conditions Minimum Typical Maximum 4 4 Units pF pF pF pF kΩ kΩ Ω CPD RPULLUP RPULLDOWN ROUT Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 2 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Banks 1, 2, 3 Inputs OE 0 1 CLK_EN X 0 Outputs Q0-Q23 Hi-Z Disabled in logic LOW state. NOTE 1 1 (default) 1 (default) Enabled. NOTE 1 NOTE 1: The clock enable and disable function is synchronous to the falling edge of the selected reference clock. TABLE 3B. CLOCK SELECT FUNCTION TABLE Control Input CLK_SEL 0 (default) 1 CLK0, nCLK0 Selected De-selected Clock CLK1, nCLK1 De-selected Selected TABLE 3C. CLOCK INPUT FUNCTION TABLE Inputs OE 1 (default) 1 1 1 1 CLK0, CLK1 0 (default) 1 0 1 Biased; NOTE 1 nCLK0, nCLK1 1 (default) 0 Biased; NOTE 1 Biased; NOTE 1 0 Outputs Q0 thru Q23 LOW HIGH LOW HIGH HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting 1 Biased; NOTE 1 1 LOW Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 8, Figure 1, which discusses Wiring the Differential Input to Accept Single-Ended Levels. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 3 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 95 Units V V mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 95 Units V V mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 95 Units V V mA TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK_SEL, CLK_EN, OE CLK_SEL, CLK_EN, OE CLK_EN, OE CLK_SEL CLK_EN, OE CLK_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0V VDD = VDDO = 3.135V IOH = -36mA VDD = VDDO = 3.135V IOL = 36mA -150 -5 2.7 0.5 Typical Maximum 3.8 0.8 5 150 Units V V µA µA µA µA V V IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 4 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4E. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_SEL, CLK_EN, OE CLK_SEL, CLK_EN, OE CLK_EN, OE CLK_SEL CLK_EN, OE CLK_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0V VDD = 3.135V VDDO = 2.375V IOH = -27mA VDD = 3.135V VDDO = 2.375V IOL = 27mA -150 -5 1.9 Typical Maximum 3.8 0.8 5 150 Units V V µA µA µA µA V Output High Voltage VOL Output Low Voltage 0.4 V TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK_SEL, CLK_EN, OE CLK_SEL, CLK_EN, OE CLK_EN, OE CLK_SEL CLK_EN, OE CLK_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625, VIN = 0V VDD = 2.625, VIN =0V VDD = VDDO = 2.375V IOH = -27mA VDD = VDDO = 2.375V IOL = 27mA -150 -5 1.9 0.4 Typical Maximum 2.9 0.8 5 150 Units V V µA µA µA µA V V IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 5 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4G. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 IIL VPP VCMR Input Low Current CLK0, CLK1 Peak-toPeak Input Voltage Common Mode Input Voltage: NOTE 1, 2 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 0.3 0.9 1.3 2 Minimum Typical Maximum 5 150 Units µA µA µA µA V V NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. TABLE 4H. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 IIL VPP VCMR Input Low Current CLK0, CLK1 Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 0.3 0.9 1.3 2 Minimum Typical Maximum 5 150 Units µA µA µA µA V V NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. TABLE 4I. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 IIL VPP VCMR Input Low Current CLK0, CLK1 Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Test Conditions VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V VDD = 2.625V, VIN = 0V -150 -5 0.3 0.9 1.3 2 Minimum Typical Maximum 5 150 Units µA µA µA µA V V NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 6 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%; VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%; VDD = VDDO = 2.5V ± 5%, TA = 0°C TO 70°C Symbol Parameter fMAX tPD Maximum Output Frequency Propagation Delay, NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Q[0:7] Bank Skew; NOTE 2, 6 Test Conditions f ≤ 200MHz 155.52MHz, Integration Range: 12kHz - 20MHz Minimum Typical Maximum 250 Units MHz ns ps 2.5 0.21 5 t jit 85 Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 30% to 70% 30% to 70% f ≤ 200MHz f = 200MHz 200 200 tCYCLE/2 - 0.25 2.25 tCYCLE/2 2.5 180 100 200 900 800 800 tCYCLE/2 + 0.25 2.75 5 4 ps ps ps ps ps ps ps % ns ns ns t sk(b) Q[8:15] Q[16:23] t sk(o) t sk(pp) tR tF odc tEN tDIS Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise Time; NOTE 5 Output Fall Time; NOTE 5 Output Duty Cycle Output Enable Time; NOTE 5 Output Disable TIme; NOTE 5 f = 10MHz f = 10MHz All parameters measured at 200MHz and VPPtyp unless noted otherwise. NOTE 1: Measured from the differential input crossing point to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions. NOTE 4: Defined as between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 7 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 155.52MHz (12kHz to 20MHz) = 0.21ps typical SSB PHASE NOISE dBc/HZ OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 8 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±5% 1.25V±5% VDD, VDDO Qx SCOPE VDD VDDO SCOPE Qx LVCMOS GND GND LVCMOS -1.65V±5% -1.25V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT VDD VDD, VDDO SCOPE Qx nCLK0, nCLK1 V CLK0, CLK1 PP Cross Points V CMR LVCMOS GND GND -1.25V±5% 2.5V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 Qx V DDO V DDO 2 Qx 2 PART 2 Qy V DDO V DDO 2 t sk(pp) Qy 2 t sk(o) PART-TO-PART SKEW OUTPUT SKEW IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 9 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER nCLK0, nCLK1 CLK0, CLK1 Q0:Q23 V DDO 2 t PW t PERIOD Q0:Q23 t PD odc = t PW t PERIOD x 100% PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% 20% tR 80% 20% tF Clock Outputs OUTPUT RISE/FALL TIME IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 10 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. There should be no trace attached. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 11 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in F igure 2A, t he input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL Zo = 50 Ohm CLK nCLK HiPerClockS Input HiPerClockS Input R1 50 R2 50 FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN IDT HIPERCLOCKS LVHSTL DRIVER BY FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125 3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm CLK nCLK Receiv er FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input R5 100 - 200 R6 100 - 200 R1 84 R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE BY IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 12 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8344-01 is: 1503 IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 13 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L θ ccc 0.45 0° --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7° 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 14 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number 8344AY-01 8344AY-01T 8344AY-01LF 8344AY-01LFT Marking ICS8344AY-01 ICS8344AY-01 ICS8344AY0lL ICS8344AY0lL Package 48 Lead LQFP 48 Lead LQFP 48 lead "Lead-Free" LQFP 48 lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 15 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev B Table 4A 4D 4G 5A Page 4 5 6 7 8-10 1 8 14 1 10 11 14 3A 3 1 1 2 3 7 8 15 2 Description of Change Revised IDD row from 60mA Max. to 95mA Max. Revised IDD row from 60mA Max. to 95mA Max. Revised IDD row from 60mA Max. to 95mA Max. Revised Note 1 and Note 4. Updated Parameter Measurement Figures. Deleted Power Consideration notes. Updated Block Diagram. On April 18, 2001 a typo was corrected in the Ordering Information Table. The correction was ICS8344AY-01 from ICS8344BY-01. Features Section - added lead-free bullet. Added Recommendations for Unused Input and Output Pins. Added Differential Clock Input Interface. Ordering Information Table - added lead-free par t number, marking and note. Updated datasheet format. Output Enable Function Table - updated table. Added Pullup and Pulldown to Block Diagram. Features Section - added Additive Phase Jitter bullet. Pin Characteristics Table - add CPD specs. Function Tables - added default to conditions. AC Characteristics Table - added Additive Phase Jitter row. Added Additive Phase Jitter Plot. Ordering Information Table - removed ICS prefix from par t/order number column. In CIN row, replaced CLK-SEL with CLK_SEL. Date 8/6/01 B 12/13/01 12/18/01 7/24/02 B B B 10/26/06 B 5/10/07 C T3A - T3C 5 8 9/8/08 C T2 9/9/08 IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 16 ICS8344AY-01 REV. C SEPTEMBER 9, 2008 ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA