84329AV-01LFT

ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION The ICS84329-01 is a general purpose, single output high frequency synthesizer. The VCO operates at a frequency range of 200MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of thecrystal frequency divided by 16. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps as small as 125kHz to 1MHz can be achieved using a 16MHz crystal depending on the output dividers. FEATURES • • • • • • • • • • • • Fully integrated PLL, no external loop filter requirements 1 differential 3.3V LVPECL output Crystal oscillator interface Output frequency range: 25MHz to 700MHz VCO range: 200MHz to 700MHz Parallel interface for programming counter and output dividers during power-up Serial 3 wire interface RMS Period jitter: 5.5ps (maximum) Cycle-to-cycle jitter: 35ps (maximum) 3.3V supply voltage 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT M0 M1 M2 M3 M4 M5 M6 M7 M8 N0 N1 VEE TEST VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nP_LOAD VCC XTAL2 XTAL1 nc nc VCCA S_LOAD S_DATA S_CLOCK VCC FOUT nFOUT VEE XTAL1 OSC XTAL2 ÷ 16 PLL PHASE DETECTOR 1 VCO ÷M 0 ÷1 ÷2 ÷4 ÷8 FOUT nFOUT ICS84329-01 28-Lead SOIC 7.5mm x 18.05mm x 2.25mm package body M Package Top View nFOUT FOUT TEST VCC VCC VEE VEE S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 CONFIGURATION INTERFACE LOGIC TEST 25 24 23 22 21 20 19 S_CLOCK S_DATA S_LOAD VCCA nc nc XTAL1 26 27 28 1 18 17 N1 N0 M8 M7 M6 M5 M4 ICS84329-01 16 28-Lead PLCC 15 11.6mm x 11.4mm x 4.1mm 2 14 V Package 3 13 Top View 4 5 XTAL2 12 6 Vcc 7 nP_LOAD 8 M0 9 10 11 M1 M2 M3 84329AM-01 www.idt.com 1 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1. The ICS84329-01 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A series-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency ÷ 16 by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84329-01 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode the nP_LOAD input is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly T2 0 0 0 0 1 1 1 1 S_CLOCK S_DATA S_LOAD nP_LOAD t to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. The TEST output is Mode 000 (shift register out) when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x fVCO = M 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 200 ≤ M ≤ 511. The frequency out is defined as follows: fout = fVCO = fxtal x M N N 16 Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T2:T0. The internal registers T2:T0 determine the state of the TEST output as follows: TEST Output fOUT Shift Register Out fOUT High fOUT PLL Reference Xtal ÷ 16 fOUT M (non 50% Duty M divider) fOUT fOUT fOUT S_CLOCK ÷ N divider fOUT T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 VCO ÷ fOUT LVCMOS Output Frequency < 200MHz Low S_CLOCK ÷ M (non 50% Duty Cycle M divider) fOUT ÷ 4 SERIAL LOADING T2 S T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 t H t S PARALLEL LOADING M0:M8, N0:N1 nP_LOAD t S M, N t H S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS 84329AM-01 www.idt.com 2 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Name M0, M1, M2, M3, M4, M5, M6, M7, M8 N0, N1 VEE TEST VCC nFOUT, FOUT S_CLOCK S_DATA S_LOAD VCCA nc XTAL1, XTAL2 Type Input Input Power Output Power Output Input Input Input Power Unused Input Pullup Pullup Description M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input. LVCMOS / LVTTL interface levels. Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. Negative supply pins. Test output which is used in the serial mode of operation. LVCMOS / LVTTL interface levels. Core supply pins. Differential output for the synthesizer. 3.3V LVPECL interface levels. Clocks the serial data present at S_DATA input into the shift register Pulldown on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. Pulldown LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the M divider. Pulldown LVCMOS / LVTTL interface levels. Analog supply pin. No connect. Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Parallel load input. Determines when data present at M8:M0 is loaded into the M divider, and when data present at N1:N0 sets the N output divider value. nP_LOAD Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF kΩ kΩ 84329AM-01 www.idt.com 3 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 3A. PARALLEL nP_LOAD X L ↑ H H H M X Data Data X X X AND SERIAL MODE FUNCTION TABLE Inputs S_LOAD X X L L ↑ ↓ S_CLOCK X X X ↑ L L X S_DATA X X X Data Data Data X Conditions Reset. M and N bits are all set HIGH. Data on M and N inputs passed directly to M divider and N output divider. TEST mode 000. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divide and N output divide values are latched. Parallel or serial input do not affect shift registers. N X Data Data X X X H X X L NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE VCO Frequency (MHz) 200 201 202 203 • • 509 510 511 M Divider 200 201 202 203 • • 509 510 511 256 M8 0 0 0 0 • • 1 1 1 128 M7 1 1 1 1 • • 1 1 1 64 M6 1 1 1 1 • • 1 1 1 32 M5 0 0 0 0 • • 1 1 1 16 M4 0 0 0 0 • • 1 1 1 8 M3 1 1 1 1 • • 1 1 1 4 M2 0 0 0 0 • • 1 1 1 2 M1 0 0 1 1 • • 0 1 1 1 M0 0 1 0 1 • • 1 0 1 NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N1 0 0 1 1 N0 0 1 0 1 N Divider Value 1 2 4 8 Output Frequency (MHz) Minimum 200 100 50 25 Maximum 700 350 175 87.5 84329AM-01 www.idt.com 4 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5 V -0.5V to VCC + 0.5V 46.2°C/W (0 lfpm) -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol VCC VCCA IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 110 15 Units V V mA mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH Parameter S_LOAD, nP_LOAD, Input High Voltage S_DATA, S_CLOCK, M0:M8, N0:N1 S_LOAD, nP_LOAD, Input Low Voltage S_DATA, S_CLOCK, M0:M8, N0:N1 M0-M8, N0, N1, nP_LOAD Input High Current S_LOAD, S_DATA, S_CLOCK M0-M8, N0, N1, nP_LOAD Input Low Current S_LOAD, S_DATA, S_CLOCK Output High Voltage; NOTE 1 Test Conditions Minimum Typical 2 Maximum VCC + 0.3 Units V VIL -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -150 -5 2.6 0.8 5 150 V µA µA µA µA V IIH IIL VOH Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50Ω to VCC/2. See figure "3.3V Output Load Test Circuit" in the "Parameter Measurement Information" section. 0.5 V TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol VOH V OL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. 84329AM-01 www.idt.com 5 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 10 Test Conditions Minimum Typical Maximum 25 70 7 Units MHz Ω pF Fundamental TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol fIN Parameter XTAL; NOTE 1 Input Frequency XTAL; NOTE 1, 2 Test Conditions Minimum 10 17 Typical Maximum 17 25 Units MHz MHz S_CLOCK 50 MHz NOTE 1: For the cr ystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency range of 200MHz or 700MHz. Using the minimum frequency of 10MHz valid values of M are 320 ≤ M ≤ 511. Using the maximum frequency of 25MHz valid values of M are 128 ≤ M ≤ 448. NOTE 2: For cr ystal frequencies greater than 17MHz, a series tuning capacitor is required for proper operation. For more information, please refer to the Application Information, "Cr ystal Input and Oscillator Interface". TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol FOUT Parameter Output Frequency Period Jitter, RMS; NOTE 1, 2 Cycle-to-Cycle Jitter ; NOTE 1, 2 Output Rise/Fall Time Setup Time Hold Time PLL Lock Time 45 50 fOUT ≥ 65MHz fOUT < 65MHz fOUT ≥ 50MHz fOUT < 50MHz 20% to 80% 300 5 5 10 55 Test Conditions Minimum Typical Maximum 700 5.5 12 35 50 800 Units MHz ps ps ps ps ps ns ns ms % tjit(per) tjit(cc) tR / tF tS tH tL odc Output Duty Cycle See Parameter Measurement Information section. Characterized using a 16MHz XTAL. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: See Applications section. 84329AM-01 www.idt.com 6 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V VCC, VCCA Qx SCOPE nFOUT FOUT t cycle n LVPECL nQx VEE ➤ t jit(cc) = t cycle n – t cycle n+1 1000 Cycles -1.3V ± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER VOH VREF VOL nFOUT FOUT t PW t PERIOD 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements odc = Histogram t PW t PERIOD Reference Point (Trigger Edge) Mean Period (First edge after trigger) PERIOD JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD S_DATA S_CLOCK 80% Clock Outputs 80% VSW I N G 20% tR tF 20% M0:M8 N0:N1 S_LOAD t SET-UP t HOLD t SET-UP nP_LOAD t HOLD t SET-UP OUTPUT RISE/FALL TIME 84329AM-01 SETUP www.idt.com 7 AND HOLD REV. D AUGUST 7, 2010 ➤ ➤ t cycle n+1 ➤ x 100% ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84329-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 Ω r esistor along with a 10 μ F and a .01 μ F bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF VCCA .01μF 10 μF 10 Ω FIGURE 2. POWER SUPPLY FILTERING TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Zo = 50Ω 125Ω 3.3V 125Ω FOUT Zo = 50Ω 50Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o 50Ω FIN Zo = 50Ω FOUT FIN Zo = 50Ω 84Ω 84Ω VCC - 2V RTT RTT = FIGURE 3A. LVPECL OUTPUT TERMINATION FIGURE 3B. LVPECL OUTPUT TERMINATION 84329AM-01 www.idt.com 8 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 14 12 10 Time (pS) 8 6 4 2 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 Output Frequency (MHz) FIGURE 4A. RMS JITTER VS. fOUT (USING A 16MHZ XTAL) 60 50 40 Time (pS) 30 20 10 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 Output Frequency (MHz) FIGURE 4B. CYCLE-TO-CYCLE JITTER VS. fOUT (USING A 16MHZ XTAL) www.idt.com 9 84329AM-01 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER CRYSTAL INPUT AND OSCILLATOR INTERFACE The ICS84329-01 features an internal oscillator that uses an external quartz crystal as the source of its reference frequency. The oscillator is a series resonant, multi-vibrator type design. This design provides better stability and eliminates the need for large on chip capacitors. Though a series resonant crystal is preferred, a parallel resonant crystal can be used. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified. A few hundred ppm translates to KHz inaccuracy. In general computing applications, this level of inaccuracy is irrelevant. If better ppm accuracy is required, an external capacitor can be added to a quartz crystal in series to XTAL1. Figure 5A shows how to interface with a crystal. Figures 5A and 5B show various crystal parameters which are recommended only as guidelines. Figure 5A shows how to interface a capacitor with a parallel resonant crystal. Figure 5B shows the capacitor value needed for the optimum ppm performance over various series resonant crystal frequencies. For IA64/32 platforms which required a Raltron Parallel Resonant Quartz crystal part #AS-16.66-18-SMD-T-M1, a 7pF series capacitor can be used to better the ppm accuracy. ICS84329-01 XTAL2 XTAL1 FIGURE 5A. CRYSTAL INTERFACE NOTE: For crystal frequencies higher than 17MHz, a series tuning capacitor is required for proper operation. FIGURE 5B. Recommended tuning capacitance for various series resonant crystals. 30 Series Capacitor (pf) 25 20 15 10 5 0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 12.000 14.318 16.000 20.000 24.000 10.000 Series Resonant Crystal Frequency (MHz) 84329AM-01 www.idt.com 10 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE The schematic of the ICS84329-01 layout example used in this layout guideline is shown in Figure 6A. The ICS84329-01 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. M3 M2 M1 M0 nPLOAD VCC C3 0.1u 16MHz X1 VCC M3 M2 M1 M0 nP_LOAD VCC XTAL2 11 10 9 8 7 6 5 VCC=3.3V SP = Space (i.e. not intstalled) M[8:0]= 110010000 (400) N[1:0] =01 (Divide by 2) M4 M5 M6 M7 M8 N2 N1 12 13 14 15 16 17 18 84329_01_PLCC RU0 SP M0 M1 RU1 SP M7 RU7 1K M8 RU8 1K N0 RU9 SP N1 RU10 1K nPLoad RU11 SP 19 20 21 22 23 24 25 VCC U1 VEE TEST VCC VEE nFOUT FOUT VCC M4 M5 M6 M7 M8 N0 N1 XTAL1 nc nc VCCA S_LOAD S_DATA S_CLOCK 4 3 2 1 28 27 26 R7 10 VCCA C11 0.01u C16 10u C1 0.1uF VCC Zo = 50 Ohm Fout = 200 MHz C2 0.1u RD6 1K Zo = 50 Ohm RD0 1K RD1 1K RD7 SP RD8 SP RD9 1K RD10 SP R2 50 R1 50 R3 50 FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT 84329AM-01 www.idt.com 11 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. • The differential 50Ω output traces should have the same length. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. • Make sure no other signal traces are routed between the clock trace pair. • The matching termination resistors should be located as close to the receiver input pins as possible. POWER AND GROUNDING Place the decoupling capacitors C1, C2 and C3, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL1) and 25 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. X1 C3 U1 GND VCC PIN 2 PIN 1 C11 C16 VCCA R7 VCCA VIA Signals Traces C1 C2 50 Ohm Traces FIGURE 6B. PCB BOARD LAYOUT FOR ICS84329-01 84329AM-01 www.idt.com 12 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84329-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84329-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.2mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 381.2mW + 30mW = 411.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.411W * 39.7°C/W = 86.3°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8A. THERMAL RESISTANCE θJA FOR 28-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 46.2°C/W 200 60.8°C/W 39.7°C/W 500 53.2°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 8B. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 200 31.1°C/W 500 28.3°C/W 84329AM-01 www.idt.com 13 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 7. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V (V CC_MAX OH_MAX =V CC_MAX – 0.9V -V OH_MAX ) = 0.9V =V – 1.7V • For logic low, VOUT = V (V CC_MAX OL_MAX CC_MAX -V OL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V – (V - 2V))/R ] * (V L OH_MAX CC_MAX CC_MAX -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V L CC_MAX -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 84329AM-01 www.idt.com 14 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 9A. θJAVS. AIR FLOW SOIC TABLE θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 46.2°C/W 200 60.8°C/W 39.7°C/W 500 53.2°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 9B. θJAVS. AIR FLOW PLCC TABLE θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 200 31.1°C/W 500 28.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84329-01 is: 4408 84329AM-01 www.idt.com 15 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - M SUFFIX FOR 28 LEAD SOIC TABLE 10A. PACKAGE DIMENSIONS SYMBOL N A A1 A2 B C D E e H h L α 10.00 0.25 0.40 0° -0.10 2.05 0.33 0.18 17.70 7.40 1.27 BASIC 10.65 0.75 1.27 8° Millimeters MINIMUM 28 2.65 -2.55 0.51 0.32 18.40 7.60 MAXIMUM Reference Document: JEDEC Publication 95, MS-013, MO-119 84329AM-01 www.idt.com 16 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC TABLE 10B. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 4.19 2.29 1.57 0.33 0.19 12.32 11.43 4.85 12.32 11.43 4.85 MINIMUM 28 4.57 3.05 2.11 0.53 0.32 12.57 11.58 5.56 12.57 11.58 5.56 MAXIMUM Reference Document: JEDEC Publication 95, MS-018 84329AM-01 www.idt.com 17 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 11. ORDERING INFORMATION Part/Order Number 84329AM-01 84329AM-01T 84329AM-01LF 84329AM-01LFT 84329AV-01 84329AV-01T 84329AV-01LF 84329AV-01LFT Marking ICS84329AM-01 ICS84329AM-01 ICS84329AM-01LF ICS84329AM-01LF ICS84329AV-01 ICS84329AV-01 ICS84329A01L ICS84329A01L Package 28 Lead SOIC 28 Lead SOIC Lead-Free, 28 Lead SOIC Lead-Free, 28 Lead SOIC 28 Lead PLCC 28 Lead PLCC Lead-Free, 28 Lead PLCC Lead-Free, 28 Lead PLCC Shipping Packaging Tube 1000 Tape & Reel Tube 1000 Tape & Reel Tube 500 Tape & Reel Tube 500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 84329AM-01 www.idt.com 18 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev B Table T6 Page 6 Description of Change Input Frequency Characteristics Table • updated XTAL from 25MHz Max. to 20MHz Max. • added another XTAL row to include Notes 1 and 2 Added Cr ystal Input and Oscillator Interface section. Updated Parallel & Serial Load Operations diagram. Changed VCC and cr ystal descriptions. Updated format. Block Diagram, replaced ÷N with dividers. Changed 20MHz max. limit to 17MHz max. and changed 20MHz min. limit to 17MHz min. Revised Note 2. Cr ystal Input & Oscillator Interface section, added same cr ystal frequency note. Features Section - added lead-free bullet. Corrected Figure 1, Parallel & Serial Load Operations Diagram. Pin Characteristics - changed CIN from 4pF max. to 4pF typical. LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to VCC - 0.9V. Power Considerations - corrected power dissipation to reflect VOH max in Table 4C. Ordering Information Table - added lead-free par t number for ICS84329AM-01, and added lead-free par t number and marking for ICS84329AV-01. Added lead-free note. Ordering Information Table - removed ICS prefix from Par t/Order Number column. Added lead-free marking for 28 lead SOIC package. Added Contact Page. Updated datasheet's header/footer with IDT from ICS. 12/18/02 Date 02/14/02 12 2 B T1 3 1 6 10 1 2 3 5 13 - 14 T11 18 T6 C 4/3/03 T2 T4C D 4/10/07 T11 D 18 20 8/7/10 84329AM-01 www.idt.com 19 REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 Tech Support netcom@idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 84329AM-01 www.idt.com 20 REV. D AUGUST 7, 2010