845252AKILFT

FemtoClock™ Crystal-to-CML Clock Generator ICS845252I DATA SHEET General Description The ICS845252I is a 3.3V/2.5V CML clock generator designed for Ethernet applications. The device HiPerClockS™ synthesizes either a 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz or 312.5MHz clock signal with excellent phase jitter performance. The clock signal is distributed to two low-skew differential CML outputs. The device is suitable for driving the reference clocks of Ethernet PHYs. The device supports 3.3V and 2.5V voltage supply and is packaged in a small, lead-free (RoHS 6) 32-lead VFQFN package. The extended temperature range supports telecommunication, wireless infrastructure and networking end equipment requirements. The device is a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. Features • • • • Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz and 312.5MHz Two differential CML clock output pairs Crystal interface designed for 25MHz, 18pF parallel resonant crystal RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 400fs (typical), 3.3V Offset Noise Power 100Hz.................... -102.4 dBc/Hz 1kHz.................... -119.4 dBc/Hz 10kHz................... -124.8 dBc/Hz 100kHz................... -125.7 dBc/Hz ICS • • • • LVCMOS interface levels for the control inputs Full 3.3V and 2.5V supply voltage Available in lead-free (RoHS 6) 32 VFQFN package -40°C to 85°C ambient operating temperature Block Diagram XTAL_IN OSC XTAL_OUT fREF 0 0 Pin Assignment GND nQ1 Q1 FBSEL nc REF_CLK REF_SEL FBSEL nBYPASS FSEL1:0 nOE Pulldown Pulldown Pulldown Pullup Pulldown, Pulldown Pulldown Phase Detector 1 VCO 490-680 MHz 1 ÷2 (default), ÷4, ÷5, ÷10 Q0 nQ0 nQ0 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 nc nc nc nc nc nc REF_SEL FSEL1 FSEL0 nc VDD nc Q1 nQ1 Q0 VDD nOE nc nc nc nc ÷20, ÷25 (default) 10 11 12 13 14 15 16 XTAL_OUT XTAL_IN VDDA nBYPASS REF_CLK GND nc ICS845252I 32 lead VFQFN 5.0mm x 5.0mm x 0.925mm package body K Package Top View ICS845252AKI REVISION A SEPTEMBER 30, 2009 1 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Table 1. Pin Descriptions Number 1, 2 3, 18 4 5, 6, 7, 8, 9, 16, 17, 19, 23, 24, 25, 30, 31, 32 10 11 12 13, 29 14, 15 20, 21 22 26 27, 28 Name nQ0, Q0 VDD nOE Output Power Input Pulldown Type Description Differential clock output pair. CML interface levels. Core supply pins. Output enable pin. See Table 3E for function. LVCMOS/LVTTL interface levels. Do not connect. Analog supply pin. Pullup Pulldown PLL bypass pin. See Table 3D for function. LVCMOS/LVTTL interface levels. Single-ended reference clock input. LVCMOS/LVTTL interface levels. Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown Pulldown Pulldown Output frequency divider select enable pins. See Table 3C for function. LVCMOS/LVTTL interface levels. PLL reference clock select pin. See Table 3A for function. LVCMOS/LVTTL interface levels. PLL feedback divider select pin. See Table 3B for function. LVCMOS/LVTTL interface levels. Differential clock output pair. CML interface levels. nc VDDA nBYPASS REF_CLK GND XTAL_OUT, XTAL_IN FSEL0, FSEL1 REF_SEL FBSEL nQ1, Q1 Unused Power Input Input Power Input Input Input Input Output NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF kΩ kΩ ICS845252AKI REVISION A SEPTEMBER 30, 2009 2 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Function Tables Table 3A. PLL Reference Clock Select Function Table Input REF_SEL 0 (default) 1 Operation The crystal interface is the selected. The REF_CLK input is the selected. NOTE: REF_SEL is an asynchronous control. Table 3B. PLL Feedback Select Function Table Input FBSEL 0 (default) 1 Operation fVCO = fREF * 25 fVCO = fREF * 20 NOTE: FBSEL is an asynchronous control. Table 3C. Output Divider Select Function Table Input FSEL1 0 (default) 0 1 1 FSEL0 0 (default) 1 0 1 Operation fOUT = fVCO ÷ 2 fOUT = fVCO ÷ 4 fOUT = fVCO ÷ 5 fOUT = fVCO ÷ 10 Output Frequency fOUT with fREF = 25MHz FBSEL = 0 312.5MHz 156.25MHz 125MHz 62.5MHz FBSEL = 1 250MHz 125MHz 100MHz 50MHz NOTE: FSEL[1:0] are asynchronous controls. Table 3D. PLL nBYPASS Function Table Input nBYPASS 0 1 (default) Operation PLL is bypassed. The reference frequency fREF is divided by the selected output divider. AC specifications do not apply in PLL bypass mode. PLL is enabled. The reference frequency fREF is multiplied by the selected feedback divider and then divided by the selected output divider. NOTE: nBYPASS is an asynchronous control. Table 3E. Output Enable Function Table Input nOE 0 (default) 1 Operation Outputs enabled. Outputs disabled (high-impedance). NOTE: nOE is an asynchronous control. ICS845252AKI REVISION A SEPTEMBER 30, 2009 3 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 43.4°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VDD – 0.12 Typical 3.3 3.3 Maximum 3.465 VDD 88 12 Units V V mA mA Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 VDD – 0.11 Typical 2.5 2.5 Maximum 2.625 VDD 84 11 Units V V mA mA ICS845252AKI REVISION A SEPTEMBER 30, 2009 4 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Table 4C. LVCMOS/LVTTL Input DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol VIH Parameter Input High Voltage Test Conditions Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 5 -5 -150 Units V V V V µA µA µA µA VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V or 2.625V, VIN = 0V VIL Input Low Voltage FBSEL, nOE, FSEL[1:0], REF_SEL, REF_CLK nBYPASS FBSEL, nOE, FSEL[1:0], REF_SEL, REF_CLK nBYPASS IIH Input High Current IIL Input Low Current Table 4D. CML DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol VOH VOUT Parameter Output High Voltage Output Voltage Swing Test Conditions Minimum VDD - 0.02 325 650 Typical VDD - 0.01 400 800 Maximum VDD 600 1200 Units V mV mV VDIFF_OUT Differential Output Voltage Swing Table 5. Crystal Characteristics Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Test Conditions Minimum Typical Fundamental 25 50 7 MHz Maximum Units Ω pF ICS845252AKI REVISION A SEPTEMBER 30, 2009 5 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR AC Characteristics Table 6A. AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter Test Conditions FBSEL = 0, FSEL[1:0] = 00 FBSEL = 0, FSEL[1:0] = 01 FBSEL = 0, FSEL[1:0] = 10 fOUT Output Frequency; NOTE 1 FBSEL = 0, FSEL[1:0] = 11 FBSEL = 1, FSEL[1:0] = 00 FBSEL = 1, FSEL[1:0] = 01 FBSEL = 1, FSEL[1:0] = 10 FBSEL = 1, FSEL[1:0] = 11 tsk(o) Output Skew; NOTE 1, 2, 3 RMS Phase Jitter (Random); NOTE 4 Output Rise/Fall Time Output Duty Cycle FSEL = 0, 125MHz, Integration Range: 1.875MHz – 20MHz FSEL = 0, 156.25MHz, Integration Range: 1.875MHz – 20MHz 20% to 80% FBSEL[1:0] ≠ 10 FBSEL[1:0] = 10 300 48 46 400 408 850 52 54 Minimum Typical 312.5 156.25 125 62.5 250 125 100 50 60 Maximum Units MHz MHz MHz MHz MHz MHz MHz MHz ps fs fs ps % % tjit(Ø) tR / tF odc NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: fREF = 25 MHz. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Please refer to the phase noise plots. Table 6B. AC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C Symbol Parameter Test Conditions FBSEL = 0, FSEL[1:0] = 00 FBSEL = 0, FSEL[1:0] = 01 FBSEL = 0, FSEL[1:0] = 10 fOUT Output Frequency; NOTE 1 FBSEL = 0, FSEL[1:0] = 11 FBSEL = 1, FSEL[1:0] = 00 FBSEL = 1, FSEL[1:0] = 01 FBSEL = 1, FSEL[1:0] = 10 FBSEL = 1, FSEL[1:0] = 11 tsk(o) Output Skew; NOTE 1, 2, 3 RMS Phase Jitter (Random); NOTE 4 Output Rise/Fall Time Output Duty Cycle FSEL = 0, 125MHz, Integration Range: 1.875MHz – 20MHz FSEL = 0, 156.25MHz, Integration Range: 1.875MHz – 20MHz 20% to 80% FBSEL[1:0] ≠ 10 FBSEL[1:0] = 10 300 48 46 406 441 850 52 54 Minimum Typical 312.5 156.25 125 62.5 250 125 100 50 60 Maximum Units MHz MHz MHz MHz MHz MHz MHz MHz ps fs fs ps % % tjit(Ø) tR / tF odc For NOTES see Table 6A above. ICS845252AKI REVISION A SEPTEMBER 30, 2009 6 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Typical Phase Noise at 125MHz (3.3V) Noise Power dBc Hz Offset Frequency (Hz) ICS845252AKI REVISION A SEPTEMBER 30, 2009 7 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Typical Phase Noise at 125MHz (2.5V) Noise Power dBc Hz Offset Frequency (Hz) ICS845252AKI REVISION A SEPTEMBER 30, 2009 8 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Parameter Measurement Information 0V Qx SCOPE VDD CML Driver GND 0V Qx SCOPE VDD CML Driver GND Power Supply Power Supply -3.3V ± 5% -2.5V ± 5% 3.3V CML Output Load AC Test Circuit 2.5V CML Output Load AC Test Circuit Phase Noise Plot Noise Power nQx Qx nQy Qy f1 Offset Frequency f2 t sk(o) RMS Jitter = Area Under Offset Frequency Markers RMS Phase Jitter Output Skew nQ0, nQ1 nQ0, nQ1 80% 80% VSW I N G Q0, Q1 t PW t PERIOD Q0, Q1 20% tR tF 20% odc = t PW t PERIOD x 100% Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period ICS845252AKI REVISION A SEPTEMBER 30, 2009 9 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS845252I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V or 2.5V VDD .01µF VDDA .01µF 10µF 10Ω Figure 1. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: CML Outputs All unused CML outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. REF_CLK Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. ICS845252AKI REVISION A SEPTEMBER 30, 2009 10 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Crystal Input Interface The ICS845252I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p Figure 2. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. VDD VDD R1 Ro Rs 50Ω 0.1µf XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface ICS845252AKI REVISION A SEPTEMBER 30, 2009 11 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology. PIN SOLDER EXPOSED HEAT SLUG SOLDER PIN PIN PAD GROUND PLANE THERMAL VIA LAND PATTERN (GROUND PAD) PIN PAD Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS845252AKI REVISION A SEPTEMBER 30, 2009 12 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS845252I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS845252I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V * (88mA + 12mA) = 346.5mW Power (outputs)MAX = 35.76mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 35.76mW = 71.52mW Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 71.52mW = 418.02mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.418W * 43.4°C/W = 103°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 43.4°C/W 1 37.9°C/W 2.5 34.0°C/W ICS845252AKI REVISION A SEPTEMBER 30, 2009 13 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the CML driver output pair. The CML output circuit and termination are shown in Figure 5. VDD RL1 RL2 50 Q nQ Q1 Q2 50 V_output I_load IC Figure 5. CML Driver (without built-in 50Ω pullup) Circuit and Termination To calculate worst case power dissipation into the load, use the following equations: Power dissipation when the output driver is logic LOW: Pd_L = I Load * V Output = (VOUT_MAX /RL) * (VDD_MAX – VOUT_MAX) = (600mV/50Ω) * (3.465V – 600mV) = 34.38mW Power dissipation when the output driver is logic HIGH: Pd_H = I Load * V Output = (0.02V/50Ω) * (3.465V – 0.02V) = 1.38mW Total Power Dissipation per output pair = Pd_H + Pd_L = 35.76mW ICS845252AKI REVISION A SEPTEMBER 30, 2009 14 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Reliability Information Table 8. θJA vs. Air Flow Table for a 32 VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 43.4°C/W 1 37.9°C/W 2.5 34.0°C/W Transistor Count The transistor count for the ICS845252I is: 3064 Package Outline and Package Dimensions Package Outline - K Suffix for VFQFN Packages S eating Plan e Ind ex Area N A1 A3 L N 1 2 E2 (N -1)x e E2 2 (Re f.) (Ref.) (N -1)x e (R ef.) N &N Even e (Ty p.) 2 If N & N To p View Anvil Anvil Singulation Singula tion or OR Sawn Singulation are Even b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C (Ref.) e D2 2 D2 N &N Odd Th er mal Ba se Table 9. Package Dimensions JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9. ICS845252AKI REVISION A SEPTEMBER 30, 2009 15 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR Table 10. Ordering Information Part/Order Number 845252AKILF 845252AKILFT Marking ICS45252AIL ICS45252AIL Package Lead-Free, 32 Lead VFQFN Lead-Free, 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS845252AKI REVISION A SEPTEMBER 30, 2009 16 ©2009 Integrated Device Technology, Inc. ICS845252I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.